EMBEDDED IntelDX2™ PROCESSOR

■ Integrated Floating-Point Unit ■ SL Technology

■ Speed-Multiplying Technology ■ Data Bus Parity Generation and Checking
■ 32-Bit RISC Technology Core ■ Boundary Scan (JTAG)
■ 8-Kbyte Write-Through Cache ■ 3.3-Volt Processor, 50 MHz, 25 MHz CLK
■ Four Internal Write Buffers — 208-Lead Shrink Quad Flat Pack (SQFP)
■ Burst Bus Cycles ■ 5-Volt Processor, 66 MHz, 33 MHz CLK
— 168-Pin Pin Grid Array (PGA)
■ Dynamic Bus Sizing for 8- and 16-bit
Data Bus Devices ■ Binary Compatible with Large Software
Base

64-Bit Interunit Transfer Bus

32-Bit Data Bus Core
Clock CLK
Clock
32-Bit Data Bus
Multiplier
Linear Address 32

PCD
PWT
Base/ Bus Interface A31-A2
Barrel Segmentation 2
Shifter Index Unit Paging Cache Unit 32 Address BE3#- BE0#
Bus Unit 20 Drivers
Register 32 Descriptor
File Registers Physical Write Buffers
Address 8 Kbyte 32
Cache 4 x 32
Limit and Translation
ALU D31-D0
Attribute PLA Lookaside Data Bus
Buffer 32 Transceivers

Bus Control ADS# W/R# D/C# M/IO#

128

PCD PWT RDY# LOCK#

PLOCK# BOFF# A20M#
Displacement Bus BREQ HOLD HLDA
RESET SRESET INTR
32 NMI SMI# SMIACT#
Prefetcher FERR# IGNNE#
Micro- STPCLK#
Instruction Request
Sequencer
32-Byte Code
Burst Bus BRDY# BLAST#
Queue
Code Control
Stream 2x16 Bytes
Floating Control & Instruction Bus Size BS16# BS8#
Protection Decode 24
Point Unit Control
Test Unit
KEN# FLUSH#
Decoded Cache AHOLD EADS#
Floating Control
Point Control Instruction
ROM Path
Register File
Parity DP3-DP0 PCHK#
Generation
and Control
TCK TMS
Boundary TDI TD0
Scan
Control

A3223-01

Figure 1. Embedded IntelDX2™ Processor Block Diagram

© INTEL CORPORATION, 1997 December 1997 Order Number: 272770-002

Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.

The Embedded IntelDX2™ processor may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your
product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Copyright © Intel Corporation, 1997

*Third-party brands and names are the property of their respective owners.
 Contents

EMBEDDED IntelDX2™ PROCESSOR

1.0 INTRODUCTION ........................................................................................................................................ 1

1.1 Features ............................................................................................................................................. 1
1.2 Family Members ................................................................................................................................. 2
2.0 HOW TO USE THIS DOCUMENT ............................................................................................................. 3
3.0 PIN DESCRIPTIONS ................................................................................................................................. 3
3.1 Pin Assignments ................................................................................................................................. 3
3.2 Pin Quick Reference ......................................................................................................................... 16
4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW ............................................................................. 25
4.1 CPUID Instruction ............................................................................................................................. 25
4.1.1 Operation of the CPUID Instruction ....................................................................................... 25
4.2 Identification After Reset .................................................................................................................. 26
4.3 Boundary Scan (JTAG) .................................................................................................................... 26
4.3.1 Device Identification ............................................................................................................... 26
4.3.2 Boundary Scan Register Bits and Bit Order ........................................................................... 27
5.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 28
5.1 Maximum Ratings ............................................................................................................................. 28
5.2 DC Specifications ............................................................................................................................. 28
5.3 AC Specifications ............................................................................................................................. 33
5.4 Capacitive Derating Curves .............................................................................................................. 39
6.0 MECHANICAL DATA .............................................................................................................................. 41
6.1 Package Dimensions ........................................................................................................................ 41
6.2 Package Thermal Specifications ...................................................................................................... 44

FIGURES
Figure 1. Embedded IntelDX2™ Processor Block Diagram ...................................................................... i
Figure 2. Package Diagram for 208-Lead SQFP Embedded IntelDX2™ Processor ................................ 4
Figure 3. Package Diagram for 168-Pin PGA Embedded IntelDX2™ Processor ................................... 10
Figure 4. CLK Waveform ........................................................................................................................ 35
Figure 5. Input Setup and Hold Timing ................................................................................................... 35
Figure 6. Input Setup and Hold Timing ................................................................................................... 36
Figure 7. PCHK# Valid Delay Timing ...................................................................................................... 36
Figure 8. Output Valid Delay Timing ....................................................................................................... 37
Figure 9. Maximum Float Delay Timing .................................................................................................. 37
Figure 10. TCK Waveform ........................................................................................................................ 38
Figure 11. Test Signal Timing Diagram .................................................................................................... 38

iii
Contents

Figure 12. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a Low-to-High Transition, 3.3 V Processor ......................................................................... 39
Figure 13. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a High-to-Low Transition, 3.3 V Processor ......................................................................... 39
Figure 14. Typical Loading Delay versus Load Capacitance under
Worst-Case Conditions for a Low-to-High Transition, 5 V Processor ...................................... 40
Figure 15. Typical Loading Delay versus Load Capacitance under
Worst-Case Conditions for a High-to-Low Transition, 5 V Processor ...................................... 40
Figure 16. 208-Lead SQFP Package Dimensions .................................................................................... 41
Figure 17. Principal Dimensions and Data for 168-Pin Pin Grid Array Package ....................................... 42

TABLES
Table 1. The Embedded IntelDX2™ Processor Family ............................................................................ 2
Table 2. Pinout Differences for 208-Lead SQFP Package ...................................................................... 5
Table 3. Pin Assignment for 208-Lead SQFP Package ........................................................................... 6
Table 4. Pin Cross Reference for 208-Lead SQFP Package ................................................................... 8
Table 5. Pinout Differences for 168-Pin PGA Package ......................................................................... 11
Table 6. Pin Assignment for 168-Pin PGA Package .............................................................................. 12
Table 7. Pin Cross Reference for 168-Pin PGA Package ...................................................................... 14
Table 8. Embedded IntelDX2™ Processor Pin Descriptions ................................................................. 16
Table 9. Output Pins .............................................................................................................................. 23
Table 10. Input/Output Pins ..................................................................................................................... 23
Table 11. Test Pins .................................................................................................................................. 23
Table 12. Input Pins ................................................................................................................................. 24
Table 13. CPUID Instruction Description ................................................................................................. 25
Table 14. Boundary Scan Component Identification Code (3.3 Volt Processor) ..................................... 26
Table 15. Boundary Scan Component Identification Code (5 Volt Processor) ........................................ 27
Table 16. Absolute Maximum Ratings ..................................................................................................... 28
Table 17. Operating Supply Voltages ...................................................................................................... 28
Table 18. 3.3 V DC Specifications ........................................................................................................... 29
Table 19. 3.3 V ICC Values ...................................................................................................................... 30
Table 20. 5 V DC Specifications .............................................................................................................. 31
Table 21. 5 V ICC Values ......................................................................................................................... 32
Table 22. AC Characteristics ................................................................................................................... 33
Table 23. AC Specifications for the Test Access Port ............................................................................. 34
Table 24. 168-Pin Ceramic PGA Package Dimensions ........................................................................... 42
Table 25. Ceramic PGA Package Dimension Symbols ........................................................................... 43
Table 26. Thermal Resistance, θJA (°C/W) ............................................................................................. 44
Table 27. Thermal Resistance, θJC (°C/W) ............................................................................................. 44
Table 28. Maximum Tambient, TA max (°C) ............................................................................................... 44

iv

1.0 INTRODUCTION
The embedded IntelDX2™ processor provides high
performance to 32-bit, embedded applications.
Designed for applications that need a floating-point
unit, the processor is ideal for embedded designs
running DOS*, Microsoft Windows*, OS/2*, or UNIX *
applications written for the Intel architecture.
Projects can be completed quickly by utilizing the
wide range of software tools, utilities, assemblers
and compilers that are available for desktop
computer systems. Also, developers can find
advantages in using existing chipsets and peripheral
components in their embedded designs.
The embedded IntelDX2 processor is binary
compatible with the Intel386™ and earlier Intel
processors. Compared with the Intel386 processor, it
provides faster execution of many commonly-used
instructions. It also provides the benefits of an
integrated, 8-Kbyte, write-through cache for code
and data. Its data bus can operate in burst mode
which provides up to 106-Mbyte-per-second
transfers for cache-line fills and instruction
prefetches.
Intel’s SL technology is incorporated in the
embedded IntelDX2 processor. Utilizing Intel’s
System Management Mode (SMM), it enables
designers to develop energy-efficient systems.
Two component packages are available. A 168-pin
Pin Grid Array (PGA) is available for 5-Volt designs
and a 208-lead Shrink Quad Flat Pack (SQFP) is
available for 3.3-Volt designs.
The processor operates at twice the external-bus
frequency. The 5 V processor operates up to 66
MHz (33-MHz CLK). The 3.3 V processor operates
up to 50 MHz (25-MHz CLK).
1.1 Features
The embedded IntelDX2 processor offers these
features:
• 32-bit RISC-Technology Core — The embedded
IntelDX2 processor performs a complete set of
arithmetic and logical operations on 8-, 16-, and
32-bit data types using a full-width ALU and eight
general purpose registers.
• Single Cycle Execution — Many instructions
execute in a single clock cycle.
* Other brands and names are the property of their
respective owners.
Embedded IntelDX2™ Processor
• Instruction Pipelining — Overlapped instruction
fetching, decoding, address translation and
execution.
• On-Chip Floating-Point Unit — Intel486™
processors support the 32-, 64-, and 80-bit formats
specified in IEEE standard 754. The unit is binary
compatible with the 8087, Intel287™, Intel387™
coprocessors, and Intel OverDrive® processor.
• On-Chip Cache with Cache Consistency
Support — An 8-Kbyte, write-through, internal
cache is used for both data and instructions.
Cache hits provide zero wait-state access times
for data within the cache. Bus activity is tracked to
detect alterations in the memory represented by
the internal cache. The internal cache can be
invalidated or flushed so that an external cache
controller can maintain cache consistency.
• External Cache Control — Write-back and flush
controls for an external cache are provided so the
processor can maintain cache consistency.
• On-Chip Memory Management Unit — Address
management and memory space protection
mechanisms maintain the integrity of memory in a
multitasking and virtual memory environment. Both
memory segmentation and paging are supported.
• Burst Cycles — Burst transfers allow a new
double-word to be read from memory on each bus
clock cycle. This capability is especially useful for
instruction prefetch and for filling the internal
cache.
• Write Buffers — The processor contains four
write buffers to enhance the performance of
consecutive writes to memory. The processor can
continue internal operations after a write to these
buffers, without waiting for the write to be
completed on the external bus.
• Bus Backoff — When another bus master needs
control of the bus during a processor initiated bus
cycle, the embedded IntelDX2 processor floats its
bus signals, then restarts the cycle when the bus
becomes available again.
• Instruction Restart — Programs can continue
execution following an exception generated by an
unsuccessful attempt to access memory. This
feature is important for supporting demand-paged
virtual memory applications.
• Dynamic Bus Sizing — External controllers can
dynamically alter the effective width of the data
bus. Bus widths of 8, 16, or 32 bits can be used.
1
Embedded IntelDX2™ Processor
• Boundary Scan (JTAG) — Boundary Scan
provides in-circuit testing of components on
printed circuit boards. The Intel Boundary Scan
implementation conforms with the IEEE Standard
Test Access Port and Boundary Scan Architecture.
Intel’s SL technology provides these features:
• Intel System Management Mode (SMM) — A
unique Intel architecture operating mode provides
a dedicated special purpose interrupt and address
space that can be used to implement intelligent
power management and other enhanced functions
in a manner that is completely transparent to the
operating system and applications software.
• I/O Restart — An I/O instruction interrupted by a
System Management Interrupt (SMI#) can
automatically be restarted following the execution
of the RSM instruction.
• Stop Clock — The embedded IntelDX2 processor
has a stop clock control mechanism that provides
two low-power states: a Stop Grant state (20–45
mA typical, depending on input clock frequency)
and a Stop Clock state (~100-200 µA typical, with
input clock frequency of 0 MHz).
Table 1. The Embedded IntelDX2™ Processor Family
Supply Voltage
Product Processor
VCC Frequency
SB80486DX2SC50 3.3 V
A80486DX2SA66 5.0 V
2
• Auto HALT Power Down — After the execution of
a HALT instruction, the embedded IntelDX2
processor issues a normal Halt bus cycle and the
clock input to the processor core is automatically
stopped, causing the processor to enter the Auto
HALT Power Down state (20–45 mA typical,
depending on input clock frequency).
• Auto Idle Power Down — This function allows the
processor to reduce the core frequency to the bus
frequency when both the core and bus are idle.
Auto Idle Power Down is software transparent and
does not affect processor performance. Auto Idle
Power Down provides an average power savings
of 10% and is only applicable to clock multiplied
processors.
1.2 Family Members
Table 1 shows the embedded IntelDX2 processors
and briefly describes their characteristics.
Maximum Maximum
External Bus Package
Frequency
50 MHz 25 MHz 208-Lead SQFP
66 MHz 33 MHz 168-Pin PGA

2.0 HOW TO USE THIS DOCUMENT
For a complete set of documentation related to the
embedded IntelDX2 processor, use this document in
conjunction with the following reference documents:
• Embedded Intel486™ Processor Family
Developer’s Manual — Order No. 273021
• Embedded Intel486™ Processor Hardware
Reference Manual — Order No. 273025
• Intel486 Microprocessor Family Programmer’s
Reference Manual — Order No. 240486
• Intel Application Note AP-485 — Intel Processor
Identification with the CPUID Instruction —
Order No. 241618
The information in the reference documents for the
IntelDX2 processor applies to the embedded
IntelDX2 processor. Some of the IntelDX2 processor
information is duplicated in this document to
minimize the dependence on the reference
documents.
Embedded IntelDX2™ Processor
3.0 PIN DESCRIPTIONS
3.1 Pin Assignments
The following figures and tables show the pin assign-
ments of each package type for the embedded
IntelDX2 processor. Tables are provided showing
the pin differences between the embedded IntelDX2
processor and other embedded Intel486 processor
products.
208-Lead SQFP - Quad Flat Pack
• Figure 2, Package Diagram for 208-Lead SQFP
Embedded IntelDX2™ Processor (pg. 4)
• Table 2, Pinout Differences for 208-Lead SQFP
Package (pg. 5)
• Table 3, Pin Assignment for 208-Lead SQFP
Package (pg. 6)
• Table 4, Pin Cross Reference for 208-Lead SQFP
Package (pg. 8)
168-Pin PGA - Pin Grid Array
• Figure 3, Package Diagram for 168-Pin PGA
Embedded IntelDX2™ Processor (pg. 10)
• Table 5, Pinout Differences for 168-Pin PGA
Package (pg. 11)
• Table 6, Pin Assignment for 168-Pin PGA
Package (pg. 12)
• Table 7, Pin Cross Reference for 168-Pin PGA
Package (pg. 14)
3
Embedded IntelDX2™ Processor

RESERVED#
PLOCK#

BLAST#
LOCK#

ADS#

TMS
VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC
VCC
A10

A11

A12

A13
A14

A15
A16

A17

A18
A19
A20

A21
A22
A23
A24
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
TDI
A2

A3
A4
A5

A6
A7
A8

A9
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VSS 1 156 VSS
VCC 2 155 VCC
VCC 3 154 A25
PCHK# 4 153 A26
BRDY# 5 152 A27
BOFF# 6 151 A28
BS16# 7 150 VCC
BS8# 8 149 A29
VCC 9 148 A30
VSS 10 147 A31
INC 11 146 VSS
RDY# 12 145 DP0
KEN# 13 144 D0
VCC 14 143 D1
VSS 15 142 D2
HOLD 16 141 D3
AHOLD 17 140 D4
TCK 18 139 VCC
VCC 19 138 VSS
VCC 20 208-Lead SQFP 137 VCC
VSS 21 136 VCC
VCC 22
Embedded IntelDX2™ Processor 135 VSS
VCC 23 134 VCC
CLK 24 133 VCC
VCC 25 132 VSS
HLDA 26 131 VCC
W/R# 27 130 D5
VSS 28 129 D6
VCC 29 128 VCC
BREQ 30 127 NC
BE0# 31 Top View 126 D7
BE1# 32 125 DP1
BE2# 33 124 D8
BE3# 34 123 D9
VCC 35 122 VSS
VSS 36 121 VCC
M/IO# 37 120 VSS
VCC 38 119 D10
D/C# 39 118 D11
PWT 40 117 D12
PCD 41 116 D13
VCC 42 115 VSS
VSS 43 114 VCC
VCC 44 113 D14
VCC 45 112 D15
EADS# 46 111 VCC
A20M# 47 110 VSS
RESET 48 109 DP2
FLUSH# 49 108 D16
INTR 50 107 VSS
NMI 51 106 VCC
VSS 52 105 VSS
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
SRESET
SMIACT#
VSS
VCC
VSS
VCC
VSS

VCC
VSS
VCC
INC
INC
SMI#
FERR#
NC
TDO
VCC
INC
INC
IGNNE#
STPCLK#
D31
D30
VSS
VCC
D29
D28

D22
D21

NC
VCC
VSS
VCC
D27
D26
D25

DP3
D23
VCC
D24
VSS
VCC

VSS
VCC

VSS
VCC
D20
D19
D18
VCC
D17
VSS

A3227-01

Figure 2. Package Diagram for 208-Lead SQFP Embedded IntelDX2™ Processor

4
 Embedded IntelDX2™ Processor

Table 2. Pinout Differences for 208-Lead SQFP Package

Embedded Embedded Embedded Write-Back
Pin # Intel486™ SX IntelDX2™ Enhanced IntelDX4™
Processor Processor Processor
3 VCC1 VCC VCC5
11 INC2 INC CLKMUL
63 INC INC HITM#
64 INC INC WB/WT#
66 INC FERR# FERR#
70 INC INC CACHE#
71 INC INC INV
72 INC IGNNE# IGNNE#
NOTES:
1. This pin location is for the VCC5 pin on the embedded IntelDX4 processor. For compatibility with 3.3V processors that
have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin should be connected to a VCC trace, not to
the VCC plane.
2. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded IntelDX2 processor. How-
ever, new signals are defined for the location of the INC pins in the embedded IntelDX4 processor. One system design
can accommodate any one of these processors provided the purpose of each INC pin is understood before it is used.

5
Embedded IntelDX2™ Processor

Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 1 of 2)

Pin# Description Pin# Description Pin# Description Pin# Description

1 VSS 53 VSS 105 VSS 157 VSS
2 VCC 54 VCC 106 VCC 158 A24
3 VCC1 55 VSS 107 VSS 159 A23
4 PCHK# 56 VCC 108 D16 160 A22
5 BRDY# 57 VSS 109 DP2 161 A21
6 BOFF# 58 SRESET 110 VSS 162 VCC
7 BS16# 59 SMIACT# 111 VCC 163 VCC
8 BS8# 60 VCC 112 D15 164 A20
9 VCC 61 VSS 113 D14 165 A19
10 VSS 62 VCC 114 VCC 166 A18
11 INC2 63 INC2 115 VSS 167 TMS
12 RDY# 64 INC2 116 D13 168 TDI
13 KEN# 65 SMI# 117 D12 169 VCC
14 VCC 66 FERR# 118 D11 170 VSS
15 VSS 67 NC3 119 D10 171 A17
16 HOLD 68 TDO 120 VSS 172 VCC
17 AHOLD 69 VCC 121 VCC 173 A16
18 TCK 70 INC2 122 VSS 174 A15
19 VCC 71 INC2 123 D9 175 VSS
20 VCC 72 IGNNE# 124 D8 176 VCC
21 VSS 73 STPCLK# 125 DP1 177 A14
22 VCC 74 D31 126 D7 178 A13
23 VCC 75 D30 127 NC3 179 VCC
24 CLK 76 VSS 128 VCC 180 A12
25 VCC 77 VCC 129 D6 181 VSS
26 HLDA 78 D29 130 D5 182 A11
27 W/R# 79 D28 131 VCC 183 VCC
28 VSS 80 VCC 132 VSS 184 VSS
29 VCC 81 VSS 133 VCC 185 VCC
30 BREQ 82 VCC 134 VCC 186 A10
31 BE0# 83 D27 135 VSS 187 A9
32 BE1# 84 D26 136 VCC 188 VCC
33 BE2# 85 D25 137 VCC 189 VSS
34 BE3# 86 VCC 138 VSS 190 A8
35 VCC 87 D24 139 VCC 191 VCC

6
 Embedded IntelDX2™ Processor

Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 2 of 2)

Pin# Description Pin# Description Pin# Description Pin# Description

36 VSS 88 VSS 140 D4 192 A7
37 M/IO# 89 VCC 141 D3 193 A6
38 VCC 90 DP3 142 D2 194 RESERVED#
39 D/C# 91 D23 143 D1 195 A5
40 PWT 92 D22 144 D0 196 A4
41 PCD 93 D21 145 DP0 197 A3
42 VCC 94 VSS 146 VSS 198 VCC
43 VSS 95 VCC 147 A31 199 VSS
44 VCC 96 NC 3 148 A30 200 VCC
45 VCC 97 VSS 149 A29 201 VSS
46 EADS# 98 VCC 150 VCC 202 A2
47 A20M# 99 D20 151 A28 203 ADS#
48 RESET 100 D19 152 A27 204 BLAST#
49 FLUSH# 101 D18 153 A26 205 VCC
50 INTR 102 VCC 154 A25 206 PLOCK#
51 NMI 103 D17 155 VCC 207 LOCK#
52 VSS 104 VSS 156 VSS 208 VSS
NOTES:
1. This pin location is for the VCC5 pin on the embedded IntelDX4 processor. For compatibility with 3.3V processors that have
5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin should be connected to a VCC trace, not to the VCC
plane.
2. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded IntelDX2 processors. How-
ever, signals are defined for the location of the INC pins in the IntelDX4 processor. One system design can accommodate
any one of these processors provided the purpose of each INC pin is understood before it is used.
3. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to VCC, or VSS or to any other
signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors.

7
Embedded IntelDX2™ Processor

Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 1 of 2)

Address Pin # Data Pin # Control Pin # NC INC VCC VSS

A2 202 D0 144 A20M# 47 67 11 2 1
A3 197 D1 143 ADS# 203 96 63 3 10
A4 196 D2 142 AHOLD 17 127 64 9 15
A5 195 D3 141 BE0# 31 70 14 21
A6 193 D4 140 BE1# 32 71 19 28
A7 192 D5 130 BE2# 33 20 36
A8 190 D6 129 BE3# 34 22 43
A9 187 D7 126 BLAST# 204 23 52
A10 186 D8 124 BOFF# 6 25 53
A11 182 D9 123 BRDY# 5 29 55
A12 180 D10 119 BREQ 30 35 57
A13 178 D11 118 BS16# 7 38 61
A14 177 D12 117 BS8# 8 42 76
A15 174 D13 116 CLK 24 44 81
A16 173 D14 113 D/C# 39 45 88
A17 171 D15 112 DP0 145 54 94
A18 166 D16 108 DP1 125 56 97
A19 165 D17 103 DP2 109 60 104
A20 164 D18 101 DP3 90 62 105
A21 161 D19 100 EADS# 46 69 107
A22 160 D20 99 FERR# 66 77 110
A23 159 D21 93 FLUSH# 49 80 115
A24 158 D22 92 HLDA 26 82 120
A25 154 D23 91 HOLD 16 86 122
A26 153 D24 87 IGNNE# 72 89 132
A27 152 D25 85 INTR 50 95 135
A28 151 D26 84 KEN# 13 98 138
A29 149 D27 83 LOCK# 207 102 146
A30 148 D28 79 M/IO# 37 106 156
A31 147 D29 78 NMI 51 111 157
D30 75 PCD 41 114 170
D31 74 PCHK# 4 121 175
PLOCK# 206 128 181
PWT 40 131 184
RDY# 12 133 189
RESERVED# 194
RESET 48
SMI# 65 134 199
SMIACT# 59 136 201

8
 Embedded IntelDX2™ Processor

Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 2 of 2)

Address Pin # Data Pin # Control Pin # NC INC V CC VSS

SRESET 58 137 208
STPCLK# 73 139
TCK 18 150
TDI 168 155
TDO 68 162
TMS 167 163
W/R# 27 169
172
176
179
183
185
188
191
198
200
205

9
Embedded IntelDX2™ Processor

A B C D E F G H J K L M N P Q R S

D20 D19 D11 D9 VSS DP1 VSS VSS VCC VSS VSS VSS D2 D0 A31 A28 A27
1 1

D22 D21 D18 D13 VCC D8 VCC D3 D5 VCC D6 VCC D1 A29 VSS A25 A26
2 2

TCK VSS CLK D17 D10 D15 D12 DP2 D16 D14 D7 D4 DP0 A30 A17 VCC A23
3 3

D23 VSS VCC A19 VSS NC

4 4

DP3 VSS VCC A21 A18 A14

5 5

D24 D25 D27 A24 VCC VSS

6 6

VSS VCC D26 A22 A15 A12

7 7
168-Pin PGA
8
D29 D31 D28 Embedded IntelDX2™ Processor A20 VCC VSS
8

VSS VCC D30 A16 VCC VSS

9 9

INC SMI# SRESET A13 VCC VSS

10 10
Pin Side View
VSS VCC RESERVED# A9 VCC VSS 11
11

INC INC SMIACT# A5 A11 VSS 12

12

INC INC NC A7 A8 A10

13 13

TDI TMS FERR# A2 VCC VSS

14 14

IGNNE# NMI FLUSH# A20M# HOLD KEN# STPCLK# BRDY# BE2# BE0# PWT D/C# LOCK# HLDA BREQ A3 A6
15 15

INTR TDO RESET BS8# VCC RDY# VCC VCC BE1# VCC VCC VCC M/IO# VCC PLOCK# BLAST# A4
16 16

17 AHOLD EADS# BS16# BOFF# VSS BE3# VSS VSS PCD VSS VSS VSS W/R# VSS PCHK# INC ADS# 17

A B C D E F G H J K L M N P Q R S

A3226-01

Figure 3. Package Diagram for 168-Pin PGA Embedded IntelDX2™ Processor

10
 Embedded IntelDX2™ Processor

Table 5. Pinout Differences for 168-Pin PGA Package

Embedded Write-Back Enhanced

Pin # Embedded IntelDX2™ Processor
IntelDX4™ Processor
A10 INC INV
A12 INC HITM#
B12 INC CACHE#
B13 INC WB/WT#
J1 VCC V CC5
R17 INC CLKMUL
S4 NC VOLDET

11
Embedded IntelDX2™ Processor

Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 1 of 2)

Pin # Description Pin # Description Pin # Description

A1 D20 D17 BOFF# P2 A29
A2 D22 E1 VSS P3 A30
A3 TCK E2 VCC P15 HLDA
A4 D23 E3 D10 P16 VCC

A5 DP3 E15 HOLD P17 VSS

A6 D24 E16 VCC Q1 A31

A7 VSS E17 VSS Q2 VSS

A8 D29 F1 DP1 Q3 A17

A9 VSS F2 D8 Q4 A19
1
A10 INC F3 D15 Q5 A21
A11 VSS F15 KEN# Q6 A24
A12 INC1 F16 RDY# Q7 A22
A13 INC1 F17 BE3# Q8 A20
A14 TDI G1 VSS Q9 A16
A15 IGNNE# G2 VCC Q10 A13
A16 INTR G3 D12 Q11 A9
A17 AHOLD G15 STPCLK# Q12 A5
B1 D19 G16 VCC Q13 A7
B2 D21 G17 VSS Q14 A2
B3 VSS H1 VSS Q15 BREQ
B4 VSS H2 D3 Q16 PLOCK#
B5 VSS H3 DP2 Q17 PCHK#
B6 D25 H15 BRDY# R1 A28
B7 VCC H16 VCC R2 A25
B8 D31 H17 VSS R3 VCC

B9 VCC J1 VCC R4 VSS

B10 SMI# J2 D5 R5 A18

B11 VCC J3 D16 R6 VCC

B12 INC1 J15 BE2# R7 A15

B13 INC1 J16 BE1# R8 VCC

B14 TMS J17 PCD R9 VCC

B15 NMI K1 VSS R10 VCC

B16 TDO K2 VCC R11 VCC

12
 Embedded IntelDX2™ Processor

Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 2 of 2)

Pin # Description Pin # Description Pin # Description

B17 EADS# K3 D14 R12 A11
C1 D11 K15 BE0# R13 A8
C2 D18 K16 VCC R14 VCC

C3 CLK K17 VSS R15 A3

C4 VCC L1 VSS R16 BLAST#
C5 VCC L2 D6 R17 INC1
C6 D27 L3 D7 S1 A27
C7 D26 L15 PWT S2 A26
C8 D28 L16 VCC S3 A23
C9 D30 L17 VSS S4 NC2
C10 SRESET M1 VSS S5 A14
C11 RESERVED# M2 VCC S6 VSS

C12 SMIACT# M3 D4 S7 A12

C13 NC2 M15 D/C# S8 VSS

C14 FERR# M16 VCC S9 VSS

C15 FLUSH# M17 VSS S10 VSS

C16 RESET N1 D2 S11 VSS

C17 BS16# N2 D1 S12 VSS

D1 D9 N3 DP0 S13 A10

D2 D13 N15 LOCK# S14 VSS

D3 D17 N16 M/IO# S15 A6

D15 A20M# N17 W/R# S16 A4
D16 BS8# P1 D0 S17 ADS#
NOTES:
1. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded
IntelDX2 processors. However, signals are defined for the location of the INC pins in the IntelDX4
processor. One system design can accommodate any one of these processors provided the pur-
pose of each INC pin is understood before it is used.
2. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to
VCC, or VSS or to any other signal can result in component malfunction or incompatibility with
future steppings of the Intel486 processors.

13
Embedded IntelDX2™ Processor

Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 1 of 2)

Address Pin # Data Pin # Control Pin # NC INC Vcc Vss

A2 Q14 D0 P1 A20M# D15 C13 A10 B7 A7
A3 R15 D1 N2 ADS# S17 S4 A12 B9 A9
A4 S16 D2 N1 AHOLD A17 A13 B11 A11
A5 Q12 D3 H2 BE0# K15 B12 C4 B3
A6 S15 D4 M3 BE1# J16 B13 C5 B4
A7 Q13 D5 J2 BE2# J15 R17 E2 B5
A8 R13 D6 L2 BE3# F17 E16 E1
A9 Q11 D7 L3 BLAST# R16 G2 E17
A10 S13 D8 F2 BOFF# D17 G16 G1
A11 R12 D9 D1 BRDY# H15 H16 G17
A12 S7 D10 E3 BREQ Q15 J1 H1
A13 Q10 D11 C1 BS16# C17 K2 H17
A14 S5 D12 G3 BS8# D16 K16 K1
A15 R7 D13 D2 CLK C3 L16 K17
A16 Q9 D14 K3 D/C# M15 M2 L1
A17 Q3 D15 F3 DP0 N3 M16 L17
A18 R5 D16 J3 DP1 F1 P16 M1
A19 Q4 D17 D3 DP2 H3 R3 M17
A20 Q8 D18 C2 DP3 A5 R6 P17
A21 Q5 D19 B1 EADS# B17 R8 Q2
A22 Q7 D20 A1 FERR# C14 R9 R4
A23 S3 D21 B2 FLUSH# C15 R10 S6
A24 Q6 D22 A2 HLDA P15 R11 S8
A25 R2 D23 A4 HOLD E15 R14 S9
A26 S2 D24 A6 IGNNE# A15 S10
A27 S1 D25 B6 INTR A16 S11
A28 R1 D26 C7 KEN# F15 S12
A29 P2 D27 C6 LOCK# N15 S14
A30 P3 D28 C8 M/IO# N16
A31 Q1 D29 A8 NMI B15
D30 C9 PCD J17
D31 B8 PCHK# Q17
PLOCK# Q16
PWT L15
RDY# F16
RESERVED# C11
RESET C16
SMI# B10
SMIACT# C12

14
 Embedded IntelDX2™ Processor

Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 2 of 2)

Address Pin # Data Pin # Control Pin # NC INC Vcc Vss

SRESET C10
STPCLK# G15
TCK A3
TDI A14
TDO B16
TMS B14
W/R# N17

15
Embedded IntelDX2™ Processor

3.2 Pin Quick Reference

The following is a brief pin description. For detailed signal descriptions refer to Appendix A, “Signal Descrip-
tions,” in the Embedded Intel486™ Processor Family Developer’s Manual, order No. 273021.

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 1 of 7)

Symbol Type Name and Function

CLK I Clock provides the fundamental timing and internal operating frequency for the
embedded IntelDX2 processor. All external timing parameters are specified with
respect to the rising edge of CLK.
ADDRESS BUS
A31-A4 I/O Address Lines A31–A2, together with the byte enable signals, BE3#–BE0#,
A3–A2 O define the physical area of memory or input/output space accessed. Address
lines A31–A4 are used to drive addresses into the embedded IntelDX2 processor
to perform cache line invalidation. Input signals must meet setup and hold times
t22 and t23. A31–A2 are not driven during bus or address hold.
BE3# O Byte Enable signals indicate active bytes during read and write cycles. During
BE2# O the first cycle of a cache fill, the external system should assume that all byte
enables are active. BE3#–BE0# are active LOW and are not driven during bus
BE1# O hold.
BE0# O BE3# applies to D31–D24
BE2# applies to D23–D16
BE1# applies to D15–D8
BE0# applies to D7–D0
DATA BUS
D31–D0 I/O Data Lines. D7–D0 define the least significant byte of the data bus; D31–D24
define the most significant byte of the data bus. These signals must meet setup
and hold times t22 and t23 for proper operation on reads. These pins are driven
during the second and subsequent clocks of write cycles.
DATA PARITY
DP3–DP0 I/O There is one Data Parity pin for each byte of the data bus. Data parity is
generated on all write data cycles with the same timing as the data driven by the
embedded IntelDX2 processor. Even parity information must be driven back into
the processor on the data parity pins with the same timing as read information to
ensure that the correct parity check status is indicated by the embedded IntelDX2
processor. The signals read on these pins do not affect program execution.
Input signals must meet setup and hold times t22 and t23. DP3–DP0 must be
connected to VCC through a pull-up resistor in systems that do not use parity.
DP3–DP0 are active HIGH and are driven during the second and subsequent
clocks of write cycles.
PCHK# O Parity Status is driven on the PCHK# pin the clock after ready for read
operations. The parity status is for data sampled at the end of the previous clock.
A parity error is indicated by PCHK# being LOW. Parity status is only checked for
enabled bytes as indicated by the byte enable and bus size signals. PCHK# is
valid only in the clock immediately after read data is returned to the processor. At
all other times PCHK# is inactive (HIGH). PCHK# is never floated.

16
 Embedded IntelDX2™ Processor

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 2 of 7)

Symbol Type Name and Function

BUS CYCLE DEFINITION
M/IO# O Memory/Input-Output, Data/Control and Write/Read lines are the primary bus
D/C# O definition signals. These signals are driven valid as the ADS# signal is asserted.
W/R# O M/IO# D/C# W/R# Bus Cycle Initiated
0 0 0 Interrupt Acknowledge
0 0 1 HALT/Special Cycle (see details below)
0 1 0 I/O Read
0 1 1 I/O Write
1 0 0 Code Read
1 0 1 Reserved
1 1 0 Memory Read
1 1 1 Memory Write
HALT/Special Cycle
Cycle Name BE3# - BE0# A4-A2
Shutdown 1110 000
HALT 1011 000
Stop Grant bus cycle 1011 100
LOCK# O Bus Lock indicates that the current bus cycle is locked. The embedded IntelDX2
processor does not allow a bus hold when LOCK# is asserted (address holds are
allowed). LOCK# goes active in the first clock of the first locked bus cycle and
goes inactive after the last clock of the last locked bus cycle. The last locked cycle
ends when Ready is returned. LOCK# is active LOW and not driven during bus
hold. Locked read cycles are not transformed into cache fill cycles when KEN# is
returned active.
PLOCK# O Pseudo-Lock indicates that the current bus transaction requires more than one
bus cycle to complete. For the embedded IntelDX2 processor, examples of such
operations are segment table descriptor reads (64 bits) and cache line fills (128
bits). For Intel486 processors with on-chip Floating-Point Unit, floating-point long
reads and writes (64 bits) also require more than one bus cycle to complete.
The embedded IntelDX2 processor drives PLOCK# active until the addresses for
the last bus cycle of the transaction are driven, regardless of whether RDY# or
BRDY# have been returned.
Normally PLOCK# and BLAST# are inverse of each other. However, during the
first bus cycle of a 64-bit floating-point write (for Intel486 processors with on-chip
Floating-Point Unit) both PLOCK# and BLAST# are asserted.
PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be
sampled only in the clock in which Ready is returned. PLOCK# is active LOW and
is not driven during bus hold.
BUS CONTROL
ADS# O Address Status output indicates that a valid bus cycle definition and address are
available on the cycle definition lines and address bus. ADS# is driven active in
the same clock in which the addresses are driven. ADS# is active LOW and not
driven during bus hold.

17
Embedded IntelDX2™ Processor

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 3 of 7)

Symbol Type Name and Function

RDY# I Non-burst Ready input indicates that the current bus cycle is complete. RDY#
indicates that the external system has presented valid data on the data pins in
response to a read or that the external system has accepted data from the
embedded IntelDX2 processor in response to a write. RDY# is ignored when the
bus is idle and at the end of the first clock of the bus cycle.
RDY# is active during address hold. Data can be returned to the embedded
IntelDX2 processor while AHOLD is active.
RDY# is active LOW and is not provided with an internal pull-up resistor. RDY#
must satisfy setup and hold times t16 and t17 for proper chip operation.
BURST CONTROL
BRDY# I Burst Ready input performs the same function during a burst cycle that RDY#
performs during a non-burst cycle. BRDY# indicates that the external system has
presented valid data in response to a read or that the external system has
accepted data in response to a write. BRDY# is ignored when the bus is idle and
at the end of the first clock in a bus cycle.
BRDY# is sampled in the second and subsequent clocks of a burst cycle. Data
presented on the data bus is strobed into the embedded IntelDX2 processor
when BRDY# is sampled active. If RDY# is returned simultaneously with BRDY#,
BRDY# is ignored and the burst cycle is prematurely aborted.
BRDY# is active LOW and is provided with a small pull-up resistor. BRDY# must
satisfy the setup and hold times t16 and t17.
BLAST# O Burst Last signal indicates that the next time BRDY# is returned, the burst bus
cycle is complete. BLAST# is active for both burst and non-burst bus cycles.
BLAST# is active LOW and is not driven during bus hold.
INTERRUPTS
RESET I Reset input forces the embedded IntelDX2 processor to begin execution at a
known state. The processor cannot begin executing instructions until at least
1 ms after VCC , and CLK have reached their proper DC and AC specifications.
The RESET pin must remain active during this time to ensure proper processor
operation. However, for warm resets, RESET should remain active for at least 15
CLK periods. RESET is active HIGH. RESET is asynchronous but must meet
setup and hold times t20 and t21 for recognition in any specific clock.
INTR I Maskable Interrupt indicates that an external interrupt has been generated.
When the internal interrupt flag is set in EFLAGS, active interrupt processing is
initiated. The embedded IntelDX2 processor generates two locked interrupt
acknowledge bus cycles in response to the INTR pin going active. INTR must
remain active until the interrupt acknowledges have been performed to ensure
processor recognition of the interrupt.
INTR is active HIGH and is not provided with an internal pull-down resistor. INTR
is asynchronous, but must meet setup and hold times t20 and t21 for recognition in
any specific clock.
NMI I Non-Maskable Interrupt request signal indicates that an external non-maskable
interrupt has been generated. NMI is rising-edge sensitive and must be held LOW
for at least four CLK periods before this rising edge. NMI is not provided with an
internal pull-down resistor. NMI is asynchronous, but must meet setup and hold
times t20 and t21 for recognition in any specific clock.

18
 Embedded IntelDX2™ Processor

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 4 of 7)

Symbol Type Name and Function

SRESET I Soft Reset pin duplicates all functionality of the RESET pin except that the
SMBASE register retains its previous value. For soft resets, SRESET must
remain active for at least 15 CLK periods. SRESET is active HIGH. SRESET is
asynchronous but must meet setup and hold times t20 and t21 for recognition in
any specific clock.
SMI# I System Management Interrupt input invokes System Management Mode
(SMM). SMI# is a falling-edge triggered signal which forces the embedded
IntelDX2 processor into SMM at the completion of the current instruction. SMI# is
recognized on an instruction boundary and at each iteration for repeat string
instructions. SMI# does not break LOCKed bus cycles and cannot interrupt a
currently executing SMM. The embedded IntelDX2 processor latches the falling
edge of one pending SMI# signal while it is executing an existing SMI#. The
nested SMI# is not recognized until after the execution of a Resume (RSM)
instruction.
SMIACT# O System Management Interrupt Active, an active LOW output, indicates that the
embedded IntelDX2 processor is operating in SMM. It is asserted when the
processor begins to execute the SMI# state save sequence and remains active
LOW until the processor executes the last state restore cycle out of SMRAM.
STPCLK# I Stop Clock Request input signal indicates a request was made to turn off or
change the CLK input frequency. When the embedded IntelDX2 processor
recognizes a STPCLK#, it stops execution on the next instruction boundary
(unless superseded by a higher priority interrupt), empties all internal pipelines
and write buffers, and generates a Stop Grant bus cycle. STPCLK# is active
LOW. Though STPCLK# has an internal pull-up resistor, an external 10-KΩ pull-
up resistor is needed if the STPCLK# pin is unused. STPCLK# is an
asynchronous signal, but must remain active until the embedded IntelDX2
processor issues the Stop Grant bus cycle. STPCLK# may be de-asserted at
any time after the processor has issued the Stop Grant bus cycle.
BUS ARBITRATION
BREQ O Bus Request signal indicates that the embedded IntelDX2 processor has
internally generated a bus request. BREQ is generated whether or not the
processor is driving the bus. BREQ is active HIGH and is never floated.
HOLD I Bus Hold Request allows another bus master complete control of the embedded
IntelDX2 processor bus. In response to HOLD going active, the processor floats
most of its output and input/output pins. HLDA is asserted after completing the
current bus cycle, burst cycle or sequence of locked cycles. The embedded
IntelDX2 processor remains in this state until HOLD is de-asserted. HOLD is
active HIGH and is not provided with an internal pull-down resistor. HOLD must
satisfy setup and hold times t18 and t19 for proper operation.
HLDA O Hold Acknowledge goes active in response to a hold request presented on the
HOLD pin. HLDA indicates that the embedded IntelDX2 processor has given the
bus to another local bus master. HLDA is driven active in the same clock that the
processor floats its bus. HLDA is driven inactive when leaving bus hold. HLDA is
active HIGH and remains driven during bus hold.

19
Embedded IntelDX2™ Processor

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 5 of 7)

Symbol Type Name and Function

BOFF# I Backoff input forces the embedded IntelDX2 processor to float its bus in the next
clock. The processor floats all pins normally floated during bus hold but HLDA is
not asserted in response to BOFF#. BOFF# has higher priority than RDY# or
BRDY#; if both are returned in the same clock, BOFF# takes effect. The
embedded IntelDX2 processor remains in bus hold until BOFF# is negated. If a
bus cycle is in progress when BOFF# is asserted the cycle is restarted. BOFF# is
active LOW and must meet setup and hold times t18 and t19 for proper operation.
CACHE INVALIDATION
AHOLD I Address Hold request allows another bus master access to the embedded
IntelDX2 processor’s address bus for a cache invalidation cycle. The processor
stops driving its address bus in the clock following AHOLD going active. Only the
address bus is floated during address hold, the remainder of the bus remains
active. AHOLD is active HIGH and is provided with a small internal pull-down
resistor. For proper operation, AHOLD must meet setup and hold times t18 and
t19.
EADS# I External Address - This signal indicates that a valid external address has been
driven onto the embedded IntelDX2 processor address pins. This address is used
to perform an internal cache invalidation cycle. EADS# is active LOW and is
provided with an internal pull-up resistor. EADS# must satisfy setup and hold
times t12 and t13 for proper operation.
CACHE CONTROL
KEN# I Cache Enable pin is used to determine whether the current cycle is cacheable.
When the embedded IntelDX2 processor generates a cycle that can be cached
and KEN# is active one clock before RDY# or BRDY# during the first transfer of
the cycle, the cycle becomes a cache line fill cycle. Returning KEN# active one
clock before RDY# during the last read in the cache line fill causes the line to be
placed in the on-chip cache. KEN# is active LOW and is provided with a small
internal pull-up resistor. KEN# must satisfy setup and hold times t14 and t15 for
proper operation.
FLUSH# I Cache Flush input forces the embedded IntelDX2 processor to flush its entire
internal cache. FLUSH# is active LOW and need only be asserted for one clock.
FLUSH# is asynchronous but setup and hold times t20 and t21 must be met for
recognition in any specific clock.
PAGE CACHEABILITY
PWT O Page Write-Through and Page Cache Disable pins reflect the state of the page
PCD O attribute bits, PWT and PCD, in the page table entry, page directory entry or
control register 3 (CR3) when paging is enabled. When paging is disabled, the
embedded IntelDX2 processor ignores the PCD and PWT bits and assumes they
are zero for the purpose of caching and driving PCD and PWT pins. PWT and
PCD have the same timing as the cycle definition pins (M/IO#, D/C#, and W/R#).
PWT and PCD are active HIGH and are not driven during bus hold. PCD is
masked by the cache disable bit (CD) in Control Register 0.

20
 Embedded IntelDX2™ Processor

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 6 of 7)

Symbol Type Name and Function

BUS SIZE CONTROL
BS16# I Bus Size 16 and Bus Size 8 pins (bus sizing pins) cause the embedded IntelDX2
BS8# I processor to run multiple bus cycles to complete a request from devices that
cannot provide or accept 32 bits of data in a single cycle. The bus sizing pins are
sampled every clock. The processor uses the state of these pins in the clock
before Ready to determine bus size. These signals are active LOW and are
provided with internal pull-up resistors. These inputs must satisfy setup and hold
times t14 and t15 for proper operation.
ADDRESS MASK
A20M# I Address Bit 20 Mask pin, when asserted, causes the embedded IntelDX2
processor to mask physical address bit 20 (A20) before performing a lookup to
the internal cache or driving a memory cycle on the bus. A20M# emulates the
address wraparound at 1 Mbyte, which occurs on the 8086 processor. A20M# is
active LOW and should be asserted only when the embedded IntelDX2 processor
is in real mode. This pin is asynchronous but should meet setup and hold times
t20 and t21 for recognition in any specific clock. For proper operation, A20M#
should be sampled HIGH at the falling edge of RESET.
TEST ACCESS PORT
TCK I Test Clock, an input to the embedded IntelDX2 processor, provides the clocking
function required by the JTAG Boundary scan feature. TCK is used to clock state
information (via TMS) and data (via TDI) into the component on the rising edge of
TCK. Data is clocked out of the component (via TDO) on the falling edge of TCK.
TCK is provided with an internal pull-up resistor.
TDI I Test Data Input is the serial input used to shift JTAG instructions and data into
the processor. TDI is sampled on the rising edge of TCK, during the SHIFT-IR
and SHIFT-DR Test Access Port (TAP) controller states. During all other TAP
controller states, TDI is a “don’t care.” TDI is provided with an internal pull-up
resistor.
TDO O Test Data Output is the serial output used to shift JTAG instructions and data out
of the component. TDO is driven on the falling edge of TCK during the SHIFT-IR
and SHIFT-DR TAP controller states. At all other times TDO is driven to the high
impedance state.
TMS I Test Mode Select is decoded by the JTAG TAP to select test logic operation.
TMS is sampled on the rising edge of TCK. To guarantee deterministic behavior
of the TAP controller, TMS is provided with an internal pull-up resistor.

21
Embedded IntelDX2™ Processor

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 7 of 7)

Symbol Type Name and Function

NUMERIC ERROR REPORTING
FERR# O The Floating Point Error pin is driven active when a floating point error occurs.
FERR# is similar to the ERROR# pin on the Intel387™ Math CoProcessor.
FERR# is included for compatibility with systems using DOS type floating point
error reporting. FERR# will not go active if FP errors are masked in FPU register.
FERR# is active LOW, and is not floated during bus hold.
IGNNE# I When the Ignore Numeric Error pin is asserted the processor will ignore a
numeric error and continue executing non-control floating point instructions, but
FERR# will still be activated by the processor. When IGNNE# is de-asserted the
processor will freeze on a non-control floating point instruction, if a previous
floating point instruction caused an error. IGNNE# has no effect when the NE bit
in control register 0 is set. IGNNE# is active LOW and is provided with a small
internal pull-up resistor. IGNNE# is asynchronous but setup and hold times t20
and t21 must be met to ensure recognition on any specific clock.
RESERVED PINS
RESERVED# I Reserved is reserved for future use. This pin MUST be connected to an external
pull-up resistor circuit. The recommended resistor value is 10 kOhms. The pull-up
resistor must be connected only to the RESERVED# pin. Do not share this
resistor with other pins requiring pull-ups.

22
 Embedded IntelDX2™ Processor

Table 9. Output Pins

Output Signal
Name Active Level Floated During Floated During During Stop Grant and
Address Hold Bus Hold Stop Clock States
BREQ HIGH Previous State
HLDA HIGH As per HOLD
BE3#-BE0# LOW • Previous State
PWT, PCD HIGH • Previous State
W/R#, M/IO#, D/C# HIGH/LOW • Previous State
LOCK# LOW • HIGH (inactive)
PLOCK# LOW • HIGH (inactive)
ADS# LOW • HIGH (inactive)
BLAST# LOW • Previous State
PCHK# LOW Previous State
FERR# LOW Previous State
A3-A2 HIGH • • Previous State
SMIACT# LOW Previous State
NOTES: The term “Previous State” means that the processor maintains the logic level applied to the signal pin just before
the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.

Table 10. Input/Output Pins

Output Signal

Name Active Level Floated During Floated During During Stop Grant and
Address Hold Bus Hold Stop Clock States
D31-D0 HIGH • Floated
DP3–DP0 HIGH • Floated
A31-A4 HIGH • • Previous State
NOTES: The term “Previous State” means that the processor maintains the logic level applied to the signal pin just before the
processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.

Table 11. Test Pins

Name Input or Output Sampled/ Driven On

TCK Input N/A
TDI Input Rising Edge of TCK
TDO Output Failing Edge of TCK
TMS Input Rising Edge of TCK

23
Embedded IntelDX2™ Processor

Table 12. Input Pins

Synchronous/ Internal Pull-Up/

Name Active Level
Asynchronous Pull-Down
CLK
RESET HIGH Asynchronous
SRESET HIGH Asynchronous Pull-Down
HOLD HIGH Synchronous
AHOLD HIGH Synchronous Pull-Down
EADS# LOW Synchronous Pull-Up
BOFF# LOW Synchronous Pull-Up
FLUSH# LOW Asynchronous Pull-Up
A20M# LOW Asynchronous Pull-Up
BS16#, BS8# LOW Synchronous Pull-Up
KEN# LOW Synchronous Pull-Up
RDY# LOW Synchronous
BRDY# LOW Synchronous Pull-Up
INTR HIGH Asynchronous
NMI HIGH Asynchronous
IGNNE# LOW Asynchronous Pull-Up
RESERVED#
SMI# LOW Asynchronous Pull-Up
STPCLK# LOW Asynchronous Pull-Up1
TCK HIGH Pull-Up
TDI HIGH Pull-Up
TMS HIGH Pull-Up
NOTES:
1. Though STPCLK# has an internal pull-up resistor, an external 10-KΩ pull-up resistor is needed if the STPCLK# pin is
unused.

24
 Embedded IntelDX2™ Processor

4.0 ARCHITECTURAL AND can change the value of this flag, the CPUID
FUNCTIONAL OVERVIEW instruction is available. The actual state of the ID
Flag bit is irrelevant and provides no significance to
the hardware. This bit is cleared (reset to zero) upon
The embedded IntelDX2 processor architecture is
device reset (RESET or SRESET) for compatibility
essentially the same as the IntelDX2 processor.
with Intel486 processor designs that do not support
Refer to the Embedded Intel486™ Processor Family
the CPUID instruction.
Developer’s Manual for a description of the IntelDX2
processor.
CPUID-instruction details are provided here for the
embedded IntelDX2 processor. Refer to Intel Appli-
Note that the embedded IntelDX2 processor has one
cation Note AP-485 Intel Processor Identification
pin reserved for possible future use. This pin, an
with the CPUID Instruction (Order No. 241618) for a
input signal, is called RESERVED# and must be
description that covers all aspects of the CPUID
connected to a 10-KΩ pull-up resistor. The pull-up
instruction and how it pertains to other Intel
resistor must be connected only to the RESERVED#
processors.
pin. Do not share this resistor with other pins
requiring pull-ups.
4.1.1 Operation of the CPUID Instruction

4.1 CPUID Instruction The CPUID instruction requires the software

developer to pass an input parameter to the
The embedded IntelDX2 processor supports the processor in the EAX register. The processor
CPUID instruction (see Table 13). Because not all response is returned in registers EAX, EBX, EDX,
Intel processors support the CPUID instruction, a and ECX.
simple test can determine if the instruction is
supported. The test involves the processor’s ID Flag,
which is bit 21 of the EFLAGS register. If software

Table 13. CPUID Instruction Description

Parameter passed in
Processor
OP CODE Instruction EAX Description
Core Clocks
(Input Value)

0F A2 CPUID 9 0 Vendor (Intel) ID String

14 1 Processor Identification
9 >1 Undefined (Do Not Use)

Vendor ID String - When the parameter passed in EAX is 0 (zero), the register values returned upon
instruction execution are shown in the following table.

31-------------24 23-----------16 15--------------8 7--------------0

High Value (= 1) EAX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Vendor ID String EBX u (75) n (6E) e (65) G (47)

(ASCII EDX I (49) e (65) n (6E) i (69)
Characters) ECX l (6C) e (65) t (74) n (6E)

The values in EBX, EDX and ECX indicate an Intel processor. When taken in the proper order, they decode to
the string “GenuineIntel.”

25
Embedded IntelDX2™ Processor

Processor Identification - When the parameter passed to EAX is 1 (one), the register values returned upon
instruction execution are:
31---------------------------14 13,12 11----8 7----4 3----0
Processor EAX (Do Not Use) 00 0100 0011 XXXX
Signature Intel Reserved Processor Family Model Stepping
Type
(Intel releases information about stepping numbers as needed)
31--------------------------------------------------------------------------------------------------0
Intel Reserved EBX Intel Reserved
(Do Not Use) ECX Intel Reserved
31----------------------------------------------------------------------------2 1 0
Feature Flags EDX 0------------------------------------------------------------------------------0 1 0
VME FPU

4.2 Identification After Reset

Processor Identification - Upon reset, the EDX register contains the processor signature:
31---------------------------14 13,12 11----8 7----4 3----0
Processor EDX (Do Not Use) 00 0100 0011 XXXX
Signature Intel Reserved Processor Family Model Stepping
Type
(Intel releases information about stepping numbers as needed)

4.3 Boundary Scan (JTAG)

4.3.1 Device Identification

Tables 14 and 15 show the 32-bit code for the embedded IntelDX2 processor. This code is loaded into the
Device Identification Register.

Table 14. Boundary Scan Component Identification Code (3.3 Volt Processor)
Version Part Number Mfg ID 1
VCC Intel Family Model 009H = Intel
0=5 V Architecture 0100 = Intel486 00101 =
1=3.3 V Type CPU Family embedded IntelDX2
processor
31----28 27 26-----------21 20----17 16--------12 11------------1 0
XXXX 1 000001 0100 00101 00000001001 1
(Intel releases information about version numbers as needed)
Boundary Scan Component Identification Code = x828 5013 (Hex)

26
 Embedded IntelDX2™ Processor

Table 15. Boundary Scan Component Identification Code (5 Volt Processor)

Version Part Number Mfg ID 1
VCC Intel Family Model 009H = Intel
0=5 V Architecture 0100 = Intel486 00101 =
1=3.3 V Type CPU Family embedded IntelDX2
processor
31----28 27 26-----------21 20----17 16--------12 11------------1 0
XXXX 0 000001 0100 00101 00000001001 1
(Intel releases information about version numbers as needed)
Boundary Scan Component Identification Code = x028 5013 (Hex)

4.3.2 Boundary Scan Register Bits and Bit The following is the bit order of the embedded
Order IntelDX2 processor boundary scan register:

The boundary scan register contains a cell for each

pin as well as cells for control of bidirectional and TDO ← A2, A3, A4, A5, RESERVED#, A6,
three-state pins. There are “Reserved” bits which A7, A8, A9, A10, A11, A12, A13,
correspond to no-connect (N/C) signals of the A14, A15, A16, A17, A18, A19,
embedded IntelDX2 processor. Control registers A20, A21, A22, A23, A24, A25,
WRCTL, ABUSCTL, BUSCTL, and MISCCTL are A26, A27, A28, A29, A30, A31,
used to select the direction of bidirectional or three- DP0, D0, D1, D2, D3, D4, D5, D6,
state output signal pins. A “1” in these cells D7, DP1, D8, D9, D10, D11, D12,
designates that the associated bus or bits are floated D13, D14, D15, DP2, D16, D17,
if the pins are three-state, or selected as input if they D18, D19, D20, D21, D22, D23,
are bidirectional. DP3, D24, D25, D26, D27, D28,
D29, D30, D31, STPCLK#,
• WRCTL controls D31-D0 and DP3–DP0 IGNNE#, FERR#, SMI#,
• ABUSCTL controls A31-A2 SMIACT#, SRESET, NMI, INTR,
• BUSCTL controls ADS#, BLAST#, PLOCK#, FLUSH#, RESET, A20M#,
LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#, M/IO#, EADS#, PCD, PWT, D/C#, M/IO#,
D/C#, PWT, and PCD BE3#, BE2#, BE1#, BE0#, BREQ,
W/R#, HLDA, CLK, RESERVED#,
• MISCCTL controls PCHK#, HLDA, and BREQ AHOLD, HOLD, KEN#, RDY#,
BS8#, BS16#, BOFF#, BRDY#,
PCHK#, LOCK#, PLOCK#,
BLAST#, ADS#, MISCCTL,
BUSCTL, ABUSCTL, WRCTL ← TDI

27
Embedded IntelDX2™ Processor

5.0 ELECTRICAL SPECIFICATIONS 5.2 DC Specifications

5.1 Maximum Ratings
Table 16 is a stress rating only. Extended exposure
to the Maximum Ratings may affect device reliability.
The following tables show the operating supply
voltages, DC I/O specifications, and component
power consumption for the embedded IntelDX2
processor.

Furthermore, although the embedded IntelDX2 Table 17. Operating Supply Voltages
processor contains protective circuitry to resist
Product VCC
damage from electrostatic discharge, always take
precautions to avoid high static voltages or electric SB80486DX2SC50 3.3 V ± 0.3 V
fields.
A80486DX2SA66 5.0 V ± 0.25 V
Functional operating conditions are given in Section
5.2, DC Specifications and Section 5.3, AC Speci-
fications.

Table 16. Absolute Maximum Ratings

Case Temperature under -65 °C to +110 °C
Bias

Storage Temperature -65 °C to +150 °C

DC Voltage on Any Pin with -0.5 V to VCC + 0.5 V

Respect to Ground

Supply Voltage VCC with -0.5 V to +6.5 V

Respect to VSS

28
 Embedded IntelDX2™ Processor

Table 18. 3.3 V DC Specifications

Functional Operating Range: VCC = 3.3 V ± 0.3 V, TCASE=0 °C to +85 °C

Symbol Parameter Min. Max. Unit Notes

VIL Input LOW Voltage -0.3 +0.8 V
VIH Input HIGH Voltage 2.0 VCC +0.3 V Note 1
VIHC Input HIGH Voltage of CLK VCC -0.6 VCC +0.3 V
VOL Output LOW Voltage
I OL = 2.0 mA 0.4 V
I OL = 100 µA 0.2 V
VOH Output HIGH Voltage
I OH = -2.0 mA 2.4 V
I OH = -100 µA VCC -0.2 V
ILI Input Leakage Current 15 µA Note 2
IIH Input Leakage Current 200 µA Note 3
SRESET 300 µA Note 3
IIL Input Leakage Current 400 µA Note 4
I LO Output Leakage Current 15 µA
CIN Input Capacitance 10 pF Note 5
COUT I/O or Output Capacitance 10 pF Note 5
CCLK CLK Capacitance 6 pF Note 5
NOTES:
1. All inputs except CLK.
2. This parameter is for inputs without pull-up or pull-down resistors and 0V ≤ VIN ≤ VCC.
3. This parameter is for inputs with pull-down resistors and VIH = 2.4V.
4. This parameter is for inputs with pull-up resistors and VIL = 0.4V.
5. FC=1 MHz. Not 100% tested.

29
Embedded IntelDX2™ Processor

Table 19. 3.3 V ICC Values

Functional Operating Range: VCC = 3.3 V ±0.3 V; TCASE = 0°C to +85°C
Operating
Parameter Frequency Typ Maximum Notes
ICC Active 40 MHz 450 mA Note 1
(Power Supply) 50 MHz 550 mA
ICC Active 40 MHz 318 mA 416 mA Notes 2, 3, 4
(Thermal Design) 50 MHz 395 mA 507 mA
ICC Stop Grant 40 MHz 20 mA 40 mA Note 5
50 MHz 23 mA 50 mA
ICC Stop Clock 0 MHz 100 µA 1 mA Note 6
NOTES:
1. This parameter is for proper power supply selection. It is measured using the worst case instruction mix at VCC = 3.6V.
2. The maximum current column is for thermal design power dissipation. It is measured using the worst case instruction mix
at VCC = 3.3V.
3. The typical current column is the typical operating current in a system. This value is measured in a system using a typical
device at VCC = 3.3V, running Microsoft Windows 3.1 at an idle condition. This typical value is dependent upon the specific
system configuration.
4. Typical values are not 100% tested.
5. The ICC Stop Grant specification refers to the ICC value once the embedded IntelDX2 processor enters the Stop Grant or
Auto HALT Power Down state.
6. The ICC Stop Clock specification refers to the ICC value once the embedded IntelDX2 processor enters the Stop Clock
state. The VIH and VIL levels must be equal to VCC and 0 V, respectively, to meet the ICC Stop Clock specifications.

30
 Embedded IntelDX2™ Processor

Table 20. 5 V DC Specifications

Functional operating range: VCC = 5V ± 0.25V; TCASE = 0°C to +85°C
Symbol Parameter Min Max Unit Notes
VIL Input LOW Voltage -0.3 +0.8 V
VIH Input HIGH Voltage 2.0 VCC+0.3 V
VOL Output LOW Voltage 0.45 V Note 1
VOH Output HIGH Voltage 2.4 V Note 2
ILI Input Leakage Current 15 µA Note 3
IIH Input Leakage Current 200 µA Note 4
SRESET 300 µA Note 4
IIL Input Leakage Current 400 µA Note 5
ILO Output Leakage Current 15 µA
CIN Input Capacitance 20 pF Note 6
COUT Output or I/O Capacitance 20 pF Note 6
CCLK CLK Capacitance 20 pF Note 6
NOTES:
1. This parameter is measured at:
Address, Data, BEn # 4.0 mA
Definition, Control 5.0 #mA
2. This parameter is measured at:
Address, Data, BEn # -1.0 mA
Definition, Control -0.9 mA
3. This parameter is for inputs without pull-ups or pull-downs and 0V ≤ VIN ≤ VCC.
4. This parameter is for inputs with pull-downs and VIH = 2.4V.
5. This parameter is for inputs with pull-ups and VIL = 0.45V.
6. FC=1 MHz; Not 100% tested.

31
Embedded IntelDX2™ Processor

Table 21. 5 V ICC Values

Functional Operating Range: VCC = 5V ±0.25V; TCASE = 0°C to +85°C
Operating
Parameter Frequency Typ Maximum Notes
ICC Active 50 MHz 950 mA Note 1
(Power Supply) 66 MHz 1200 mA
ICC Active 50 MHz 680 mA 906 mA Notes 2, 3, 4
(Thermal Design) 66 MHz 901 mA 1145 mA
ICC Stop Grant 50 MHz 35 mA 70 mA Note 5
66 MHz 40 mA 90 mA
ICC Stop Clock 0 MHz 200 µA 2 mA Note 6
NOTES:
1. This parameter is for proper power supply selection. It is measured using the worst case instruction mix at VCC = 5.25V.
2. The maximum current column is for thermal design power dissipation. It is measured using the worst case instruction mix
at VCC = 5V.
3. The typical current column is the typical operating current in a system. This value is measured in a system using a typical
device at VCC = 5V, running Microsoft Windows 3.1 at an idle condition. This typical value is dependent upon the specific
system configuration.
4. Typical values are not 100% tested.
5. The ICC Stop Grant specification refers to the ICC value once the embedded IntelDX2 processor enters the Stop Grant or
Auto HALT Power Down state.
6. The ICC Stop Clock specification refers to the ICC value once the processor enters the Stop Clock state. The VIH and VIL
levels must be equal to VCC and 0V, respectively, in order to meet the ICC Stop Clock specifications.

32
 Embedded IntelDX2™ Processor

5.3 AC Specifications
The AC specifications for the embedded IntelDX2 processor are given in this section.

Table 22. AC Characteristics

TCASE = 0°C to +85°C; CL = 50pF, unless otherwise specified. (Sheet 1 of 2)
Vcc (Package)
3.3V 5V
(208-Lead (168-Pin
Symbol Parameter SQFP) PGA)
Min Max Min Max Unit Figure Notes
CLK Frequency 8 25 8 33 MHz Note 1
t1 CLK Period 40 125 30 125 ns 4
t1a CLK Period Stability ±250 ±250 ps 4 Adjacent
clocks
t2 CLK High Time 14 11 ns 4 at 2V
t3 CLK Low Time 14 11 ns 4 at 0.8V
t4 CLK Fall Time 4 3 ns 4 2V to 0.8V
t5 CLK Rise Time 4 3 ns 4 0.8V to 2V
t6 A31–A2, PWT, PCD, BE3–BE0#, 3 19 3 16 ns 8
M/IO#, D/C#, W/R#, ADS#, LOCK#,
BREQ, HLDA, SMIACT#, FERR#
Valid Delay
t7 A31–A2, PWT, PCD, BE3–BE0#, 28 20 ns 9 Note 2
M/IO#, D/C#, W/R#, ADS#, LOCK#,
BREQ, HLDA Float Delay
t8 PCHK# Valid Delay 3 24 3 22 ns 7
t8a BLAST#, PLOCK# Valid Delay 3 24 3 20 ns 8
t9 BLAST#, PLOCK# Float Delay 28 20 ns 9 Note 2
t10 D31–D0, DP3–DP0 Write Data Valid 3 20 3 18 ns 8
Delay
t11 D31–D0, DP3–DP0 Write Data Float 28 20 ns 9 Note 2
Delay
t12 EADS# Setup Time 8 5 ns 5
t13 EADS# Hold Time 3 3 ns 5
t14 KEN#, BS16#, BS8# Setup Time 8 5 ns 5
t15 KEN#, BS16#, BS8# Hold Time 3 3 ns 5
t16 RDY#, BRDY# Setup Time 8 5 ns 6
t17 RDY#, BRDY# Hold Time 3 3 ns 6
t18 HOLD, AHOLD Setup Time 10 6 ns 5
t18a BOFF# Setup Time 10 8 ns 5
t19 HOLD, AHOLD, BOFF# Hold Time 3 3 ns 5

33
Embedded IntelDX2™ Processor

Table 22. AC Characteristics

TCASE = 0°C to +85°C; CL = 50pF, unless otherwise specified. (Sheet 2 of 2)
Vcc (Package)
3.3V 5V
(208-Lead (168-Pin
Symbol Parameter SQFP) PGA)
Min Max Min Max Unit Figure Notes
t20 FLUSH#, A20M#, NMI, INTR, SMI#, 10 5 ns 5 Note 3
STPCLK#, SRESET, RESET,
IGNNE# Setup Time
t21 FLUSH#, A20M#, NMI, INTR, SMI#, 3 3 ns 5 Note 3
STPCLK#, SRESET, RESET,
IGNNE# Hold Time
t22 D31–D0, DP3–DP0, 6 5 ns 6
A31–A4 Read Setup Time 5
t23 D31–D0, DP3–DP0, 3 3 ns 6
A31–A4 Read Hold Time 5
NOTES:
1. 0-MHz operation is guaranteed when the STPCLK# and Stop Grant bus cycle protocol is used.
2. Not 100% tested, guaranteed by design characterization.
3. A reset pulse width of 15 CLK cycles is required for warm resets (RESET or SRESET). Power-up resets (cold resets)
require RESET to be asserted for at least 1 ms after VCC and CLK are stable.

Table 23. AC Specifications for the Test Access Port

(Both 3.3V SQFP and 5V PGA Processors)
TCASE = 0°C to +85°C; CL = 50 pF
Symbol Parameter Min Max Unit Figure Notes
t24 TCK Frequency 8 MHz Note 1
t25 TCK Period 125 ns 10
t26 TCK High Time 40 ns 10 @ 2.0V
t27 TCK Low Time 40 ns 10 @ 0.8V
t28 TCK Rise Time 8 ns 10 Note 2
t29 TCK Fall Time 8 ns 10 Note 2
t30 TDI, TMS Setup Time 8 ns 11 Note 3
t31 TDI, TMS Hold Time 10 ns 11 Note 3
t32 TDO Valid Delay 3 30 ns 11 Note 3
t33 TDO Float Delay 36 ns 11 Note 3
t34 All Outputs (except TDO) Valid Delay 3 30 ns 11 Note 3
t35 All Outputs (except TDO) Float Delay 36 ns 11 Note 3
t36 All Inputs (except TDI, TMS, TCK) Setup Time 8 ns 11 Note 3
t37 All Inputs (except TDI, TMS, TCK) Hold Time 10 ns 11 Note 3
NOTES:
1. TCK period ≤ CLK period.
2. Rise/Fall times are measured between 0.8V and 2.0V. Rise/Fall times can be relaxed by 1 ns per 10-ns increase in TCK
period.
3. Parameters t30 – t37 are measured from TCK.

34
 Embedded IntelDX2™ Processor

2.0 V 2.0 V
CLK 1.5 V 1.5 V
0.8 V 0.8 V
t2
t3
t5 t4

t1

tx ty

1.5 V

tx = input setup times

ty = input hold times, output float, valid and hold times

Figure 4. CLK Waveform

Tx Tx Tx Tx

CLK

t12 t13

EADS#

t14 t15
BS8#, BS16#, KEN#

t18 t19
BOFF#, AHOLD, HOLD

t20 t21
RESET, FLUSH#,
A20M#, INTR, NMI, SMI#,
STPCLK#, SRESET, IGNNE#
t22 t23
A31-A4
(READ)

Figure 5. Input Setup and Hold Timing

35
Embedded IntelDX2™ Processor

T2 Tx Tx

CLK

t16 t17
RDY#, BRDY# 1.5 V

t22 t23
D31-D0, DP3–DP0 1.5 V

Figure 6. Input Setup and Hold Timing

T2 Tx Tx Tx

CLK

RDY#, BRDY#

D31-D0,
VALID
DP3-DP0

t8 MIN
MAX

PCHK# VALID

Figure 7. PCHK# Valid Delay Timing

36
 Embedded IntelDX2™ Processor

Tx Tx Tx Tx

CLK

MIN

t6 MAX
A2-A31, PWT, PCD,
BE0-3#, M/IO#,
D/C#, W/R#, ADS#, VALID n VALID n+1
LOCK#, BREQ, HLDA,
SMIACT#
MIN

t10 MAX

D31-D0, DP3–DP0 VALID n VALID n+1

MIN

t8a MAX

BLAST#, VALID n VALID n+1

PLOCK#

Figure 8. Output Valid Delay Timing

Tx Tx Tx

CLK

MIN
t6 t7
A2-A31, PWT, PCD,
BE0-3#, M/IO#, D/C#,
W/R#, ADS#, LOCK#, VALID
BREQ, HLDA, FERR#
MIN
t10 t11

D31-D0, DP3–DP0 VALID

MIN
t8a t9
BLAST#,
VALID
PLOCK#

Figure 9. Maximum Float Delay Timing

37
Embedded IntelDX2™ Processor

2.0 V
2.0 V

t27
TCK 0.8 V 0.8 V

t26
t28 t29

t25

Figure 10. TCK Waveform

TCK 1.5 V

t30 t31

TMS,
VALID
TDI

t32 t33

TDO VALID

t34 t 35

OUTPUT VALID VALID

t36 t37

INPUT VALID

Figure 11. Test Signal Timing Diagram

38
 Embedded IntelDX2™ Processor

5.4 Capacitive Derating Curves

The following graphs are the capacitive derating curves for the embedded IntelDX2 processor.

nom+7
nom+6
nom+5

nom+4
Delay (ns)

nom+3

nom+2

nom+1
nom

nom-1

nom-2
25 50 75 100 125 150
Capacitive Load (pF)
NOTE: This graph will not be linear outside of the capacitive range shown.
nom = nominal value from the AC Characteristics table.

Figure 12. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a Low-to-High Transition, 3.3 V Processor

nom+5

nom+4
Delay (ns)

nom+3

nom+2

nom+1
nom

nom-1

nom-2
25 50 75 100 125 150
Capacitive Load (pF)

NOTE: This graph will not be linear outside of the capacitive range shown.
nom = nominal value from the AC Characteristics table.

Figure 13. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a High-to-Low Transition, 3.3 V Processor

39
Embedded IntelDX2™ Processor

nom+5

nom+4

nom+3
Delay (ns)

nom+2

nom+1

nom

nom-1

nom-2
25 50 75 100 125 150
Capacitive Load (pF)

Note: This graph will not be linear outside of the capacitive range shown.
nom = nominal value from the AC Characteristics table.
A3234-01

Figure 14. Typical Loading Delay versus Load Capacitance under

Worst-Case Conditions for a Low-to-High Transition, 5 V Processor

nom+7

nom+6
nom+5

nom+4
Delay (ns)

nom+3
nom+2

nom+1
nom

nom-1

nom-2
25 50 75 100 125 150
Capacitive Load (pF)

Note: This graph will not be linear outside of the capacitive range shown.
nom = nominal value from the AC Characteristics table.
A3235-01

Figure 15. Typical Loading Delay versus Load Capacitance under

Worst-Case Conditions for a High-to-Low Transition, 5 V Processor

40
 Embedded IntelDX2™ Processor

6.0 MECHANICAL DATA

This section describes the packaging dimensions and thermal specifications for the embedded IntelDX2
processor.

6.1 Package Dimensions

30.6 ± 0.25

28.0 ± 0.10

1.14 25.50 (ref)

(ref) 208 157 .40 Min
0.13 + 0.12-0.08
1
156
0˚ Min
7˚ Max

0.60 ± 0.10 0.50

1.30 Ref

Top View

3.37 ± 0.08
3.70 Max

52 105 0.13 Min

0.25 Max

53 104

NOTE: Length measurements same as width measurements

Tolerance Window for
1.76 Max Lead Skew from Theoretical
True Position

0.10 Max

Units: mm A3262-01

Figure 16. 208-Lead SQFP Package Dimensions

41
Embedded IntelDX2™ Processor

Figure 17. Principal Dimensions and Data for 168-Pin Pin Grid Array Package

Table 24. 168-Pin Ceramic PGA Package Dimensions

Millimeters Inches
Symbol
Min Max Notes Min Max Notes
A 3.56 4.57 0.140 0.180
A1 0.64 1.14 SOLID LID 0.025 0.045 SOLID LID
A2 2.8 3.5 SOLID LID 0.110 0.140 SOLID LID
A3 1.14 1.40 0.045 0.055
B 0.43 0.51 0.017 0.020
D 44.07 44.83 1.735 1.765
D1 40.51 40.77 1.595 1.605
e1 2.29 2.79 0.090 0.110
L 2.54 3.30 0.100 0.130
N 168 168
S1 1.52 2.54 0.060 0.100

42
 Embedded IntelDX2™ Processor

Table 25. Ceramic PGA Package Dimension Symbols

Letter or Symbol Description of Dimensions

A Distance from seating plane to highest point of body
A1 Distance between seating plane and base plane (lid)
A2 Distance from base plane to highest point of body
A3 Distance from seating plane to bottom of body
B Diameter of terminal lead pin
D Largest overall package dimension of length
D1 A body length dimension, outer lead center to outer lead center
e1 Linear spacing between true lead position centerlines
L Distance from seating plane to end of lead
S1 Other body dimension, outer lead center to edge of body
NOTES:
1. Controlling dimension: millimeter.
2. Dimension “e1” (“e”) is non-cumulative.
3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415–0.0430 inch.
4. Dimensions “B”, “B1” and “C” are nominal.
5. Details of Pin 1 identifier are optional.

43
Embedded IntelDX2™ Processor

6.2 Package Thermal Specifications
The embedded IntelDX2 processor is specified for
operation when the case temperature (TC) is within
the range of 0°C to 85°C. TC may be measured in
any environment to determine whether the processor
is within the specified operating range.
The ambient temperature (TA) can be calculated
from θJC and θJA from the following equations:
TJ = TC + P * θJC
TA = TJ - P * θJA
TC = TA + P * [θJA - θJC]
TA = TC - P * [θJA - θJC]
Where TJ, TA, TC equals Junction, Ambient and
Case Temperature respectively. θJC, θJA equals
Junction-to-Case and Junction-to-Ambient thermal
Resistance, respectively. P is defined as Maximum
Power Consumption.
Values for θJA and θJC are given in the following
tables for each product at its maximum operating
frequencies. Maximum TA is shown for each product
operating at various processor frequencies (twice
the CLK frequencies).

Table 26. Thermal Resistance, θJA (°C/W)

θJA vs. Airflow — ft/min. (m/sec)

0 200 400 600 800 1000
(0) (1.01) (2.03) (3.04) (4.06) (5.07)
208-Lead SQFP (3.3V) - Without Heat Sink 24.0 17.0 15.0 13.0 – –
168-Pin PGA (5V) - Without Heat Sink 17.0 14.5 12.5 11.0 10.0 9.5
168-Pin PGA (5V) - With Heat Sink* 13.0 8.0 6.0 5.0 4.5 4.25
*0.350" high omnidirectional heat sink.

Table 27. Thermal Resistance, θJC (°C/W)

θJC vs. Airflow — ft/min. (m/sec)

0 200 400 600
(0) (1.01) (2.03) (3.04)
0 200 400 600
208-Lead SQFP (3.3V) 3.5 6.0 6.0 6.0
168-Pin PGA (5V) 1.5 – – –

Table 28. Maximum Tambient, TA max (°C)

Airflow — ft/min. (m/sec)

Freq. 0 200 400 600
(MHz) (0) (1.01) (2.03) (3.04)
IntelDX2™ Processor
208-Lead SQFP (3.3V) 40 57 70 73 75
Without Heat Sink 50 51 67 70 73
168-Pin PGA (5V) 50 15 26 35 46
Without Heat Sink 66 -4 11 22 36
168-Pin PGA (5V) 50 33 56 65 69
With Heat Sink 66 19 48 59 65

44