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description
The SN74CBTLV3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance
of the switch allows connections to be made with minimal propagation delay.
The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the
output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74CBTLV3257 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
FUNCTION
OE S
L L A port = B1 port
L H A port = B2 port
H X Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 1999, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
3
SW 1B2
7 5
2A SW 2B1
6
SW 2B2
9 11
3A SW 3B1
10
SW 3B2
12 14
4A SW 4B1
13
SW 4B2
1
S
15
OE
A B
(OE)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
2 × VCC TEST S1
500 Ω S1 Open tpd Open
From Output
tPLZ/tPZL 2 × VCC
Under Test GND
tPHZ/tPZH GND
CL = 30 pF
(see Note A) 500 Ω
VCC
Output VCC/2 VCC/2
LOAD CIRCUIT Control
0V
tPZL tPLZ
Output VCC
VCC Waveform 1
Input VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + 0.15 V
0V (see Note B) VOL
2 × VCC
S1 TEST S1
From Output 500 Ω Open
tpd Open
Under Test GND tPLZ/tPZL 2 × VCC
CL = 50 pF tPHZ/tPZH GND
(see Note A) 500 Ω
VCC
Output VCC/2 VCC/2
LOAD CIRCUIT Control
0V
tPZL tPLZ
Output VCC
VCC Waveform 1
Input VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + 0.3 V
0V (see Note B) VOL
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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In order to minimize risks associated with the customer’s applications, adequate design and operating
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