Lab Session # 4

ROM Implementation Using Cyclone IV E

1. Introduction
In this experiment, you will get introduced to the implementation of Read-Only Memory (ROM) in Altera
Cyclone IV E FPGA and the operation of 7-Segment LED display.

2. Objectives
By the end of this lab experiment, students will:
 Be familiar with the concept of data storage.
 Learn how to use Memory.
 Be able to use ROM to implement Multiple-Output circuit.
 Practice testing their designs by simulation and downloading on the Cyclone IV E FPGA on Altera
DE2-115 board.

3. Using ROM to Implement Multiple-Output Circuits

3.1 Memory Unit

 A memory unit is a device where binary information can be stored and retrieved when needed.
 The process of storing information into memory is referred to as memory write operation. The
process of transferring the stored information out of memory is referred to as memory read
operation.
 Two types of memories that are commonly used in digital systems:
i. Random-Access Memory (RAM)
ii. Read-Only Memory (ROM)
 Random-access memory can perform both, write and read operations, whereas read-only
memory can only be read.
 Random-access memory is considered as volatile memory, meaning that it requires power to
maintain the stored data, and data stored will be lost once power goes off. On the other hand,
read-only memory is a non-volatile memory, meaning that it does not require power to maintain
stored data, hence, once the data is written, it remains stored even if power goes off.

3.2 ROM Structure

A block diagram of a ROM is shown in Figure 1. It consists of k inputs and n outputs. The inputs specify
the address to be read from the memory and the outputs gives the stored data bits in the addressed
memory location.
 Figure 1: ROM Block Diagram

 ROM does not have data input lines because it does not have a write operation.
 Integrated circuit ROM chips have one or more enable input(s) and sometimes come with three-
state outputs to facilitate the construction of large arrays of ROM.
 ROM can also be used to implement a k-inputs, n-outputs truth table or function, with no
specific relation between the number of inputs and the number of outputs.

3.3 Seven Segment Display

A 7-Segment display has small light emitting diodes (LEDs) organized as shown in Figure 2. The seven
segments are labeled as a to g, and decimal point is labeled as dp as shown in Figure 2(a).
 There are two types of 7-Segment LEDs in use, namely, Common Anode (CA) type and Common
Cathode (CC) type.
 The segments of a CA type LED glow when individual segments are driven by logic ‘0’ value
whereas CC type LEDs glow when driven by logic ‘1’ signal.
 In order to display a character on a 7-segment LED, the segments representing the character
must be driven by suitable signals. For example, display of character ‘3’ on a CA-type 7-segment
display is shown in Figure 2(b) where segments a, b, c, d and g are driven by ‘0’ and segments e,
f, and dp are driven by ‘1’.

Figure 2: Display format of 7- Segment display

3.4 Clock Signal

A timing device, called a clock generator, provides a periodic train of clock pulses. The clock pulses are
distributed throughout the system in such a way that some elements are affected only with the arrival of
each pulse.

Figure 3: Timing Diagram of Clock Pulses

When circuits are tested in Quartus II Software using Functional or Timing Simulation, a built-in Clock is
used. Testing circuits on Altera DE2-115 Board needs some modification in the circuit since we cannot
observe the output of a sequential circuit for every clock pulse as the built-in clock is 50 MHz. Therefore, a
push button will be used to provide a clock pulse in a controlled manner.

A push button (pb) is a simple switch mechanism that requires a spring to return to its un-pushed state,
as it is prone to bouncing. When a push button is connected in a circuit to pass on logic ’1’ / logic ’0’, due
to bouncing effect, instead of passing one pulse, several clock pulses are passed, which in turn will alter
the output. By using a counter to measure an appropriately long delay to wait for the bouncing to stop
(LFC), the on-board clock on the Altera DE2-115 Board is modified by LFC, as shown in Figure 4, so that
the switch is read only once for every press.

Figure 4: Clock Pulse Controlled with a PB

3.5 Megafunctions in Quartus II Software

Megafunctions in Quartus II Software include high-level building blocks that are complex, including
functions from the Library of Parameterized Modules (LPMs). In LPMs, user can change various design
parameters in the chosen module. In this lab you will learn how to design a circuit using the lpm_rom
Megafunction available in Quartus II Software.

Problem Statement: Designing 7-Segment Display Selector Circuit

Modify the custom megafunction ROM in Quartus II Software Library to store the truth table of a 7-
Segment Display Selector Circuit. The circuit accepts a 3-bit number and displays the specified character
as per Table 1 on any of the CA type 7-Segment Displays available on Altera DE2-115 Board.

Table 1: Display Selector Circuit

Inputs Character on a 7-Segment

I2 I1 I0 Display

0 0 0 2

0 0 1 5

0 1 0 4

0 1 1 7

1 0 0 6

1 0 1 A

1 1 0 C

1 1 1 L
4. Design Procedure
The design of any combinational circuit always starts with problem definition, which is solved by
designing appropriate logic circuit. The procedure involves the following steps:

Step 1: Identifying Number of Inputs and Outputs

The display selector takes three inputs (I2, I1, I0) and needs to generate 8 outputs signals which
represent the character to be displayed on the 7-segment LED (D1, D2, D3, D4, D5, D6, D7, D8).

Step 2: Truth Table Preparation

As there are 3 inputs, the truth table will have 8 rows (2 3) as shown in Table 2. The output values for
displaying the first character, i.e. 2, is illustrated in Table 2. Find the output values to display the
remaining characters on 7-segment display by filling the missing entries in Table 2.

Table 2: Display Selector Circuit

Outputs
Inputs Character on a 7-
a/0 b/1 c/2 d/3 e/4 f/5 g/6 dp/NA
Segment Display
I2 I1 I0 D1 D2 D3 D4 D5 D6 D7 D8

0 0 0 2 0 0 1 0 0 1 0 1

0 0 1 5

0 1 0 4

0 1 1 7

1 0 0 6

1 0 1 A

1 1 0 C

1 1 1 L

Step 3: Identifying Size of Memory to Store Derived Table

1. The truth table has 8 rows, hence, 8 locations in memory are required.
2. Since number of rows = 2k = 8. Thus, the number of address lines required is 3 (k = 3).
3. Each location should store 8 bits of data, since the number of outputs is 8 (n = 8).
4. The memory size is 2k X n, so, we need 23 X 8 ROM, i.e. with 3 Address lines and 8 data lines as
shown in Figure 5.

Figure 5: ROM Block Diagram

Step 5: Storing Data/Table in Memory
Using Quartus software, create a file to store the data you filled in Table 2 as the initialization data/file for
the memory.
1. Choose File (top menu bar) → New → Memory Initialization File
 Enter Number of words = Number of rows in the truth table
 Word size = Number of output bits
 Click on OK → A new window opens.
2. Choose View (top menu bar)
 Set Both (Address Radix and Memory Radix) to Binary.
 Set Cells Per Row to 1.
3. Choose File (top menu bar) → Save As → rom8.mif (in the same Project directory/folder).
4. For Every row, Double-Click on every location → Overwrite the data with the values of D1 to D8,
as you specified in Table 2.
5. Once done → Click on Save → Close file.

Step 6: Design Entry

1. Create a new Block Diagram/Schematic File → Save As → lab5.bdf
2. Double-Click on the empty screen to enter a new symbol → select lpm_rom by either
 Expanding the hierarchy in the c:/altera/13.1/quartus/libraries box →
Megafunctions → Storage → lpm_rom → Ok.
 Typing lpm_rom in the space indicated by 1 in Figure 6 → Ok.

Figure 6: Finding lpm_rom

3. Click in any empty space in lab5.bdf file to place the new ROM symbol.
4. Right-Click on the ROM symbol → select Properties.
5. In the Parameter Tab, fill in the following information (as in Figure 7):
 LPM_ADDRESS_CONTROL:
o Checks if the address and control ports should be registered?
o select “REGISTERED”
  LPM_FILE:
o Requests for the name of file that contains the initial contents of memory array
(*.mif file)
o Type in “rom8.mif” (Note: The *.mif file name should be types between Double
Quotes, as in exactly “rom8.mif” )
 LPM_NUMWORDS:
o Requests for the number of memory words, which is the number of rows in the
truth table or 2(number of address lines), default is 2^LPM_WIDTHAD
o In our example 8  Type 8
 LPM_OUTDATA:
o Checks if the output data should be registered?
o Leave it as “UNREGISTERED”
 LPM_WIDTH:
o Requests for the data width in bits, any integer > 0
o In our example 8  Type 8
 LPM_WIDTHAD:
o Requests for number of address lines, any integer > 0
o In our example 3  Type 3

Figure 7: Parameter Tab

6. In the Ports Tab, Double-Click on the “Used” Word under the Status Column to change it to
“Unused”, for memenab and outclock ONLY. The others (address, inclock, q) should be kept as
“Used” (as in Figure 8).
7. Click on Ok.
 Figure 8: Ports Tab

8. In the ROM symbol, input and output lines will be thick indicating it is a bus.
9. Take care to drag the lines from the ROM symbol towards the input/output ports so that thick
line continues.
10. Name the input ports as I[2..0] and Clock.
11. Name the output port as D[1..8] as in Figure 9.
12. Click on Save.

Figure 9: Design Ready for Simulation (without LFC Symbol)

Step 7: Simulation
1. Analyze and synthesize your design for the implemented circuit (refer to Section 3.2.5 in Lab
Session#1).
2. Perform Functional Simulation (refer to Section 3.4 in Lab Session#1).
3. Make sure grouped signals in the waveform are in the same order as they appear in the Table 2
(I2, I1, I0, D1 to D8). You can verify for every input condition (I2 I1 I0) on a row, the
corresponding output (D1 to D8) of Table 2 must match with the simulation waveform.
Step 8: Fit and Program Cyclone IV E FPGA on Altera DE2-115 Board
1. You need to add the LFC symbol, which will provide control over the Clock signal using a Push
Button (PB).
2. Your instructor will provide you with the LFC symbol, or LFC Verilog code, for which you will
have to create a symbol (refer to Section 3.5 in Lab Session#1).
3. Place the LFC symbol in the same Block Diagram/Schematic file where you have the ROM design.
4. Connect the Clock through LFC circuit as shown in Figure 10.

Figure 10: Design Ready for Download (with LFC Symbol)

5. Save your new design with a different name. Note that you cannot use the new design (with the
LFC symbol) to perform functional simulation. The LFC symbol is added only when downloading
your design to Altera DE2-115 Board.
6. Analyze and synthesize your design for the implemented circuit (refer to Section 3.2.5 in Lab
Session#1).
7. Compile your design.
8. Using the pin assignment datasheet assign the pins for switches and 7-Segment Display (HEX7).

Table 3: Pin Assignment

Input Selected DE2-115 Output Selected DE2-115

Signal Switch Cyclone IV E Pin Signal LED Cyclone IV E Pin
Pin
I2 SW2 AC27 D1 HEX7[0] PIN_AD17
SW1 D2 HEX7[1]
SW0 HEX7[2]
PB KEY0 HEX7[3]
Clock CLOCK_50 HEX7[4]
HEX7[5]
HEX7[6]

9. Fit, Analyze and download the design into Cyclone IV E FPGA on Altera DE2-115 Board.
10. Compile your design AGAIN.
11. Program and configure the FPGA to test the implemented design physically using switches and
LEDs.
12. Test your downloaded design. For every switch condition given in Table 1, the corresponding
character should appear on the 7-Segment Display.
Student Name: Date:
Student ID:

Lab Exercise # 4

Problem Statement:
Implement the Problem Statement illustrated in the experiment description.

Procedure:
1. If a table that has 12 rows and 10 columns is to be implemented in a ROM. Answer the following
questions:
a. How many input bits are required ? ……..……………..

b. How many output bits needed to accommodate this table? ……..……………..

c. What is the size of the ROM needed? ……..……………..

d. What is the end time required in the Functional simulation waveform to test your design ?
……..……………..

2. Follow the Design Procedure presented in the experiment description.

3. Synthesize it (refer to Section 3.2.5 in Lab Session#1).
4. Perform a Functional Simulation (refer to Section 3.4 in Lab Session#1) to test your design for all
the possible test cases (Table 2).
5. Download your design to Altera DE2-115 Board to check and verify its functionality correctness.
6. Print your design files and simulation waveform.

Ask your engineer to check your results, write his/her comments and sign below:

………………………………………………………………………………………………………………………...…………………………...……….
……………………………………………………………………………………………………………………...………………………...…………….
…………………………………………………………………………………………………………………...…………………………………………

Engineer Signature
……..……………..

Attachments:
Please attach with the lab exercise sheet printouts of the files indicated below. Don't forget to
write your Name and ID Number as comments in every file before printing.

1. ROM content file (Memory Initialization File - *.mif file)

2. Graphical design file without Pin Assignment (*.bdf file)
3. Waveform file (*.sim.vwf file)
4. Graphical design file with Pin Assignment (*.bdf file)