Registers

† A single flip-flop stores one bit of information.

† A collection of n flip-flops stores n bits of information – these flip-flops form what

is called an n-bit register.

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Registers

† Illustration of a 4-bit register.

I0 D Q A0
„ When clear=0, all flip-flop outputs are R
forced to zero (active low reset).

I1 A1
When clear=1, the rising edge of the
D Q
„
clock (the active clock edge), results in R

the 4-bit input transferred to register

output.
I2 D Q A2
R

I3 D Q A3
R

clock clear

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Register With Parallel Load

† We might want to prevent the transfer of data from input to output even though the
active clock edge arrives.

„ I.e., we want the register to hold its current value.

† We can do this by feeding the register outputs back to the inputs and adding some
additional logic to control the register operation.

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Register With Parallel Load

D Q A0
I0
R

D Q A1
I1
R

D Q A2
I2
R

D Q A3
I3
R

load clock clear

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Register With Parallel Load

† When load=1, the data inputs reach the D-input of the flip-flop.

„ When the active clock edge arrives, the data gets transferred, or loaded, to the
register output.

† When load=0, the data output of each flip-flop is fed back to its D-input.

„ When the active clock edge arrives, the data input gets transferred to the
register output, but since the values are the same for all flip-flops, the register
holds its current value.

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An Aside… Different Register Functions

† To permit loading or holding of data, we have, in effect simply placed a multiplexer in

from each flip-flop input in order to “direct” the correct information to the flip-flop
inputs to obtain our desired operation.

„ In our previous example of parallel load, the AND/OR gates are working as a
multiplexer – the load signal is the multiplexer control line.

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Shift Registers

† Might want a register that can shift data serially in a direction… This type of
register is called a shift register.

† Illustration of a 4-bit shift register.

serial serial
in out
D Q D Q D Q D Q

R R R R

clock
clear

† As active clock edges arrive, the data present at the serial input gets transferred
towards the serial output – so, data gets shifted to the right one bit at a time as
clock edges arrive.

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Universal Shift Registers

† Perhaps we want a more general circuit – e.g., we want to be able to clear the
register, load the register, and perform both a shift right and a shift left
operation.

† We can do this by adding addition logic in front of each flip-flop in the register:

„ We need to make sure the correct data is present at the D-input to each flip-
flop to perform each operation correctly according to the settings on the
register control lines.

† We can use a bunch of flip-flops and multiplexers…

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Universal Shift Registers

† 4-bit register capable of multiple operations (use multiplexers instead of AND/OR

gates at flip-flop inputs):
data in (rshift)

00
I0 01 D Q A0
10
11 R

00
I1 01 D Q A1
10
11 R

00
I2 01 D Q A2
10
11 R

00
I3 01 D Q A3
10
11 R

data in (lshift) c1 c0 clock clear

E&CE 223 Digital Circuits and Systems Page 9

Universal Shift Registers

† Has an asynchronous clear signal…

† Has a clock signal…
† Has data inputs for parallel load…
† Has data inputs for both left and right shifts…

† Has two control inputs that determine behavior:

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Textbook

† Registers are covered in Chapter 6, Sections 6.1 and 6.2 of the course textbook.

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Counters

† A counter is a register whose outputs go through a prescribed sequence of states

upon the arrival of the active edge of some triggering signal.

„ The triggering signal could be the clock signal, or some other signal.

† The prescribed sequence of states, or register outputs, can be anything.

† Counters can come in two varieties – (i) asynchronous or (ii) synchronous.

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Asynchronous (Ripple) Counters

† Ripple counters consist of a series of flip-flops where the output Q of one flip-flop
is used (somehow) as the clock for the next flip-flop.

† It is the lack of a common clock signal for each flip-flop that makes the counter
asynchronous.

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Binary Ripple Counters

† A type of ripple counter that has n-bits, and can count in binary from 0 to 2n -1
and repeat.

† E.g., count sequence for 4-bits:

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Binary Ripple Counters

† We can make a binary ripple counter easily via observation…

„ A0 always flips…
„ A1 flips with A0 goes 1 ! 0…
„ A2 flips with A1 goes 1 ! 0…
„ Etc…

† So, the i-th bit complements the (i+1)-th bit when it goes 1 ! 0.

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Binary Ripple Counters

† Binary ripple counter with TFF: 1 T Q A0

count R

T Q A1
R

T Q A2
R

T Q A3
R

clear

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Binary Ripple Counters – Up and Down Counters

† BINARY UP COUNTERS:

„ A counter that counts 0, 1, 2, L , 2n-1 and repeats.

† BINARY DOWN COUNTERS:

„ A counter that counts 2n-1, L , 2, 1, 0 and repeats.

† Should be able to take our previous example and construct a binary ripple down
counter…

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Problems With Ripple Counters - Delays

† Recall: Flip-flops have clock-to-output times.

† It takes time for the output to change once the active clock edge arrives.

† Because of this, it can take a lot of time for the higher order bits to change
(remember that the i-th bit output is used as the clock for the (i+1)-th bit).

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Problems With Ripple Counters – Delays

count

A0

A1

A2

A3

transition time due to clock-to-output times

† So, the FF outputs do not change at the same time due to the ripple effect in the
clock inputs. We would like FF outputs to change simultaneously.

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Textbook

† Binary ripple counters are covered in Chapter 6, Sections 6.3 of the course
textbook.

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Synchronous Counters

† Different from ripple counters in that (the same) clock pulses are applied to the
clock inputs of all flip-flops simultaneously.

† It is the application of the same clock signal to all flip-flops that makes the counter
synchronous.

† Flip-flop outputs then change simultaneously.

† We can design synchronous counters just like the design of clocked sequential
circuits… state diagram, state table, flip-flop selection, etc…

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Synchronous Binary Counters – Up Counter

† Can design a 4-bit synchronous binary up counter:

0000 0001 0010 0011 1111

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Synchronous Binary Counters – Up Counter

† We can short-cut and avoid K-Maps to make the up counter if we see that:

„ A0 is always toggling…
„ A1 toggles if A0 is 1…
„ A2 toggles if A0, A1 are 1…
„ A3 toggles if A0, A1, A2 are 1…

† So, we can draw the circuit directly, but first we will add an enable signal.

† If enable=0, then the circuit should not count.

† If enable=1, then the circuit should behave normally and count up.

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Synchronous Binary Counters – Up Counter

† Synchronous 4-bit binary up counter with enable using TFF:

enable T Q A0
R

T Q A1
R

T Q A2
R

T Q A3
R

next
stage
clock clear

E&CE 223 Digital Circuits and Systems Page 24

Synchronous Binary Counters – Down Counter

† Can design a 4-bit synchronous binary down counter:

0000 0001 0010 0011 1111

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Synchronous Binary Counters – Down Counter

† We can short-cut and avoid K-Maps to make the down counter if we see that:

„ A0 is always toggling…
„ A1 toggles if A0 is 0…
„ A2 toggles if A0, A1 are 0…
„ A3 toggles if A0, A1, A2 are 0…

† So, we can draw the circuit directly, but first we will add an enable signal.

† If enable=0, then the circuit should not count.

† If enable=1, then the circuit should behave normally and count down.

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Synchronous Binary Counters – Down Counter

† Synchronous 4-bit binary down counter with enable using TFF:

down T Q A0
R

T Q A1
R

T Q A2
R

T Q A3
R

next
stage
clock clear

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Synchronous Binary Counters – Up/Down Counter

† Can combine the up and down counter to get an up/down counter:

† Trick is getting correct input to the FF in order to perform correct operation.

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Synchronous Binary Counters – Up/Down Counter

up

T Q A0
down
R

T Q A1
R

T Q A2
R

T Q A3
R

clock clear

† Have both logic for up count and down count; up has priority (it disables down).

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Parallel Load

† Often useful to have a counter that we can load with a “starting” count.

† This requires adding another control line (load) and data inputs:

E&CE 223 Digital Circuits and Systems Page 30

Parallel Load

load
up

down
L D U

I0 T Q A0
R

I1 T Q A1
R

I2 T Q A2
R

I3 T Q A3
R

clock clear

E&CE 223 Digital Circuits and Systems Page 31

Comments

† All of the previous counters could have been built using DFF or JKFF.

† The “trick” is simply:

„ Making sure that the correct inputs get to the flip-flop to perform a specific
function (input equations will change depending on flip-flop type!!!)

„ Making sure that control priority disables the effect of other control lines (e.g.,
parallel load “turns off” up/down count signals.

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Symbols

† We might have different symbols to represent counters:

† E.g.,

I0 A0
I1 A1
I2 A2
I3 A3
CLR
UP

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Modulo Counters

† Sometimes we don’t want to count through the entire sequence of binary numbers.

† E.g., we might want to count 0, 1, ,2 , … , 10 and repeat.

† This is modulo counting (e.g., modulo-10).

† We can use additional circuitry to detect our maximum count number and use a
parallel load to restart the counting.

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Modulo Counters

† E.g., design a counter that counts 0, 1, ,2 , … , 10 and repeats.

0 I0 A0
0 I1 A1
0 I2 A2
0 I3 A3
1 CLR

1 UP

CLK
LOAD

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Textbook

† Synchronous Binary Counters (Up, Down, Parallel Load, Etc.) and Modulo Counters
are covered in Chapter 6, Sections 6.4 of the course textbook.

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Counters With Unused States

† Often we will have an n-bit counter that does not count through all 2n possible values.

† In this case, there will be unused states (unused output patterns).

† We should try to examine what can happen with these states.

„ E.g., when we “power up” the circuit, or perhaps due to “noise” elsewhere in the
circuit, we might accidentally find the output of our counter is an unexpected
value…

„ We would like to know what would happen!!!

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Counters With Unused States

† Consider designing a counter that counts 0, 1, 2, 4, 5, 6 and then repeats.

† We can follow a clocked sequential circuit design (state table, etc.)…

† We are only concerned with the states involved with the count sequence; we will
consider the unused states later…

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Counters With Unused States

† Can list necessary flip-flop inputs for all types of flip-flops:

† We will proceed with TFF only… JKFF is actually in the textbook…

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Counters With Unused States

† Derive TFF input equations from the K-Maps.

† Note that unused states result in don’t cares in the K-Map!!!

A1A0 A1A0 A1A0

A2 00 01 11 10 A2 00 01 11 10 A2 00 01 11 10
0 0 0 X 1 0 0 1 X 1 0 1 1 X 0
1 0 0 X 1 1 0 1 X 1 1 1 1 X 0

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Counters With Unused States

† We can draw the circuit:

T Q
A0
R

T Q
A1
R

T Q
A2
R

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Counters With Unused States

† We can now ask what would happen if we accidentally found ourselves in one of the
unused states.

† Assume the state is an unused state, evaluate flip-flop inputs to see what the next
output state will be…

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Counters With Unused States

† Can draw a state diagram showing both the used and unused states:

111 011

000 001 010 100 101 110

† This counter, as designed, is self-correcting.

† If it accidentally enters into an unused state, it will return to the normal count
sequence after the next active clock edge.

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Counters With Unused States

† Consider the following situation:

111 011

000 001 010 100 101 110

† In this case, if the counter accidentally enters an unused state, it will never return
to the correct count sequence.

† This counter is not self-correcting.

† We should likely redesign such a counter, forcing unused states to have a next
state in the normal count sequence.

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Johnson Counters

† We can add additional detection circuitry in order to generate the disjoint timing
signals like a ring counter.

† This results in a Johnson Counter.

† With a Johnson Counter, we can get 2n non-overlapping timing signals using n flip-
flops and some extra 2-input AND gates.

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Textbook

† Unused states are covered in Chapter 6, Section 6.5.

† IMPORTANT: This section also describes some other types of counters (Switch-
Tail and Johnson Counters).

„ These are interesting examples…

„ They have unused states and are not self-correcting.

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