Chapter 7

Memory and
Programmable Logic Devices

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Memory
• Random Access Memory (RAM)
– Contrary to Serial Access Memory (e.g. Tape)
– Static Random Access Memory (SRAM)
• Data stored so long as Vdd is applied
• 6-transistors per cell
• Faster
• Differential
– Dynamic Random Access Memory (DRAM)
• Require periodic refresh
• Smaller (can be implemented with 1 or 3 transistor)
• Slower
• Single-Ended
– Can be read and written
– Typically, addressable at byte granularity
• Read-Only Memory (ROM)
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Block Diagram of Memory
N-bit Data Input
N (for Write)
K-bit address
lines Memory Unit
K
Read/Write 2k words
N-bit per word
Chip Enable
N N-bit Data Output
(for Read)
• Example: 2MB memory, byte-addressable
– N = 8 (because of byte-addressability)
– K = 21 (1 word = 8-bit)
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Static Random Access Memory (SRAM)

Wordline (WL)

BitLine BitLine

• Typically each bit is implemented with 6 transistors (6T SRAM Cell)

• During read, the bitline and its inverse are precharged to Vdd (1) before set
WL=1
• During write, put the value on Bitline and its inverse on Bitline_bar before
set WL=1

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Dynamic Random Access Memory (DRAM)

Wordline (WL)

Bitline

• 1-transistor DRAM cell

• During a write, put value on bitline and then set WL=1
• During a read, precharge bitline to Vdd (1) before assert WL to 1
• Storage decays, thus requires periodic refreshing (read-sense-write)

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Memory Description
• Capacity of a memory is described as
– # addresses x Word size
– Examples:

Memory # of addr # of data lines # of addr lines # of total bytes

1M x 8 1,048,576 8 20 1 MB

2M x 4 2,097,152 4 21 1 MB

1K x 4 1024 4 10 512 B

4M x 32 4,194,304 32 22 16 MB

16K x 64 16,384 64 14 128 KB

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Building Memory in Hierarchy
• Design a 1Mx8 using 1Mx4 memory chips
D7

D6
1Mx4
D5

D4
CS R/W

A19 A19 D3
A18 A18
A17 A17 D2
1Mx4
D1

A0 A0 D0
CS CS R/W

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 Building Memory in Hierarchy
• Design a 2Mx4 using 1Mx4 memory chips
A19 D3
Note that 1-to-2 A18
decoder is the wire A17 D2
itself (or use 1Mx4
an inverter) D1

D0
A0 CS R/W
1
A20 1-to-2
Decoder
0
A19
A18
CS A17
1Mx4

A0 CS R/W

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 Building Memory in Hierarchy
• Design a 2Mx8 using 1Mx4 memory chips
A19 A19 D7
A18 A18
A17 D6
A17 1Mx4
D5
A0 CS R/W D4
A0
A19 D3
1 A18
A20 1-to-2 A17 D2
Decoder 1Mx4
D1
0
A0 CS R/W D0

CS A19
A18
A17
1Mx4

A0 CS R/W

A19
A18
A17
1Mx4

A0 CS R/W
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Memory Model
• 32-bit address space can address up to 4GB (232) different
memory locations

0x00000000 0x0A Lower

Memory
0x00000001 0xB6 Address

0x00000002 0x41

0x00000003 0xFC

Higher
Memory
0xFFFFFFFF 0x0D Address
Flat Memory Model
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Read Only Memory (ROM)
• “Permanent” binary information is stored
• Non-volatile memory
– Power off does not erase information stored

K-bit address ROM

N-bit Data Output
lines 2k words
K N
N-bit per work

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32x8 ROM

32x8 ROM
5 8
Each
represents
A4
0 32 wires
1
2
A3
5-to-32 3
A2
Decoder
A1
28
29
A0
30
31

Fuse can be
implemented as
a diode or a D7 D6 D5 D4 D3 D2 D1 D0
pass transistor
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Programming the 32x8 ROM
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 1 1 0 0 0 1 0 1
0 0 0 0 1 1 0 0 0 1 0 1 1
0 0 0 1 0 1 0 1 1 0 0 0 0
… … … … … … … … … … … … …
1 1 1 0 1 0 0 0 1 0 0 0 0
1 1 1 1 0 0 1 0 1 0 1 1 0
1 1 1 1 1 1 1 1 0 0 0 0 1

0
A4 1
2
A3 5-to-32
A2
A1 Decoder
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A0 30
31

D7 D6 D5 D4 D3 D2 D1 D0 13
Example: Lookup Table
• Design a square lookup table for F(X) = X2 using ROM

X F(X)=X2 X F(X)=X2
0 0 000 000000
1 1 001 000001
2 4 010 000100
3 9 011 001001
4 16 100 010000
5 25 101 011001
6 36 110 100100
7 49 111 110001

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Square Lookup Table using ROM

X F(X)=X2 1
X2 3-to-8 2
000 000000
3
001 000001 X1
Decoder 4
010 000100
X0 5
011 001001 6
100 010000 7
101 011001
110 100100
111 110001
F5 F4 F3 F2 F1 F0

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Square Lookup Table using ROM

X F(X)=X2 1
X2 3-to-8 2
000 000000
3
001 000001 X1
Decoder 4
010 000100
X0 5
011 001001 6
100 010000 7
101 011001
110 100100
111 110001
F5 F4 F3 F2 F1 F0
Not Used = X0

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Square Lookup Table using ROM

0
1
X F(X)=X2
X2 3-to-8 2
000 000000
3
001 000001
X1
Decoder 4
010 000100 X0 5
011 001001 6
100 010000 7

101 011001
110 100100
111 110001
F5 F4 F3 F2 F1 F0

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Classifying Three Basic PLDs
Programmable
Connections
Fixed AND plane Programmable
INPUT (decoder) OR plane
OUTPUT

(Programmable) Read-Only Memory (ROM)

Programmable
Connections
Programmable Programmable
AND plane OR plane
INPUT OUTPUT

Programmable Logic Array (PLA)

Programmable Fixed F/F

INPUT AND plane OR plane
OUTPUT
Programmable Array Logic (PAL) Devices
PAL: trademark of AMD, use PAL as an adjective or
expect to receive a letter from AMD’s lawyers
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 Programmable Logic Array (PLA)

A Programmable
OR Plane
B

Programmable
AND Plane

C C B B A A

F2
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Example using PLA
F1(A, B, C)   m(0,1,2,4)
F2(A, B, C)   m(0,5,6,7)

F1  A B  AC  BC
F1  AB  AC  BC

F2  AB  AC  A BC

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Example using PLA
A F1  AB  AC  BC
B F2  AB  AC  ABC
C
AB

AC

BC

ABC

C C B B A A

F1
F2
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PAL Device
A A B B IO1 IO2 IO1 IO1

Programmable IO1
AND Plane

IO2

Fixed
OR Plane

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PAL Device Design Example
A A B B C C D D IO1 IO1

IO1

Not programmed
A

IO2

IO1  ABC  ABCD

IO2  ABC  ABCD  ACD  ABCD
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CPLD and FPGA [Brown&Rose 96]
• Complex Programmable Logic Device (CPLD)
– Multiple PLDs (e.g. PALs, PLAs) with programmable
interconnection structure
– Pioneered by Altera
• Field-Programmable Gate Array (FPGA)
– High logic capacity with large distributed interconnection
structure
• Logic capacity  number of 2-input NAND gates
– Offers more narrow logic resources
• CPLD offers logic resources w/ a wide number of inputs (AND planes)
– Offer a higher ratio of Flip-flops to logic resources than CPLD
• HCPLD (High Capacity PLD) is often used to refer to
both CPLD and FPGA

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CPLD structure
Logic block

PLD PLD PLD PLD I/O block

Interconnects

PLD PLD PLD PLD

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FPGA Structure
Logic block

I/O block

Interconnects

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FPGA Programmability
• Floating gate transistor
– Used in EPROM and EEPROM
• SRAM-controlled switch  Control
– Pass transistors
– Multiplexers (to determine how to route inputs)
• Antifuse
– Similar to fuse
– Originally an Open-Circuit
– One-Time Programmable (OTP)

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