VERILOG PROGRAM : PARALLEL ADDER

module padd1(sum,carry,in1,in2,in3,in4,in5,in6,in7,in8);
input[11:0]in1,in2,in3,in4,in5,in6,in7,in8;
output[11:0] sum;
output[2:0] carry;
reg[11:0] sum;
reg[2:0] carry;
reg[12:0]temp=13'b1000000000000;
reg[15:0]temp1=16'b1000000000000000;
reg[11:0]a1,a2,a3,a4,a5,a6,a7,a8;
reg[14:0]c=15'b000000000000000;
reg[14:0]res=15'b000000000000000;
always @(temp,in1,in2,in3,in4,in5,in6,in7,in8,temp1,a1,a2,a3,a4,a5,a6,a7,a8,res,c)
begin
a1<=temp-in1;
a2<=temp-in2;
a3<=temp-in3;
a4<=temp-in4;
a5<=temp-in5;
a6<=temp-in6;
a7<=temp-in7;
a8<=temp-in8;
c<=a1+a2+a3+a4+a5+a6+a7+a8;
res<=temp1-c;
sum<=res[11:0];
carry<=res[14:12];
end
endmodule
VERILOG PROGRAM PARALLEL SUBTRACTOR
module psub1(res,sign,in1,in2,in3,in4,in5,in6,in7,in8);
output[14:0]res;
output sign;
input[11:0]in1,in2,in3,in4,in5,in6,in7,in8;
reg sign;
reg[14:0]res;
reg[15:0]temp=16'b1000000000000000;
reg[16:0]temp1=17'b10000000000000000;
reg[14:0]store,p1;
reg[15:0]p2,res1;
always@(in1,in2,in3,in4,in5,in6,in7,in8,temp,p1,p2,res1,store)
begin
store<=in2+in3+in4+in5+in6+in7+in8;
p1<=temp-store;
p2<=in1+p1;
if(p2[15]==1'b1)
begin
res<=p2[14:0];
sign<=1'b0;
end
else begin
res1<=temp1-p2;
res<=res1[14:0];
sign<=1'b1;
end
end
endmodule
SERIAL ADDER
VERILOG PROGRAM
module sadd(sum,carry);
output[11:0]sum;
output[2:0]carry;
reg[11:0]sum;
reg[2:0]carry;
reg[11:0]in1=12'b000000000001;
reg[11:0]in2=12'b000000000001;
reg[11:0]in3=12'b000000000001;
reg[11:0]in4=12'b000000000001;
reg[11:0]in5=12'b000000000010;
reg[11:0]in6=12'b000000000010;
reg[11:0]in7=12'b000000000010;
reg[11:0]in8=12'b000000000010;
reg[12:0]a1,a2,a3,a4,a5,a6,a7,a8;
reg[12:0]temp=13'b1000000000000;
reg[15:0]temp1=16'b1000000000000000;
reg[14:0] c=15'b000000000000000;
reg[14:0]res=15'b000000000000000;
reg[3:0]bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8,bit9,bit10,bit11,bit12;
always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,a1,a2,a3,a4,a5,a6,a7,a8,temp1,c,res,bit0,bit1,bit2,b
it3,bit4,bit5,bit6,bit7,bit8,bit9,bit10,bit11,bit12)
begin
a1<=temp-in1;
a2<=temp-in2;
a3<=temp-in3;
a4<=temp-in4;
a5<=temp-in5;
a6<=temp-in6;
a7<=temp-in7;
a8<=temp-in8;
bit0<=a1[0]+a2[0]+a3[0]+a4[0]+a5[0]+a6[0]+a7[0]+a8[0];
bit1<=a1[1]+a2[1]+a3[1]+a4[1]+a5[1]+a6[1]+a7[1]+a8[1]+bit0[3:1];
bit2<=a1[2]+a2[2]+a3[2]+a4[2]+a5[2]+a6[2]+a7[2]+a8[2]+bit1[3:1];
bit3<=a1[3]+a2[3]+a3[3]+a4[3]+a5[3]+a6[3]+a7[3]+a8[3]+bit2[3:1];
bit4<=a1[4]+a2[4]+a3[4]+a4[4]+a5[4]+a6[4]+a7[4]+a8[4]+bit3[3:1];
bit5<=a1[5]+a2[5]+a3[5]+a4[5]+a5[5]+a6[5]+a7[5]+a8[5]+bit4[3:1];
bit6<=a1[6]+a2[6]+a3[6]+a4[6]+a5[6]+a6[6]+a7[6]+a8[6]+bit5[3:1];
bit7<=a1[7]+a2[7]+a3[7]+a4[7]+a5[7]+a6[7]+a7[7]+a8[7]+bit6[3:1];
bit8<=a1[8]+a2[8]+a3[8]+a4[8]+a5[8]+a6[8]+a7[8]+a8[8]+bit7[3:1];
bit9<=a1[9]+a2[9]+a3[9]+a4[9]+a5[9]+a6[9]+a7[9]+a8[9]+bit8[3:1];
bit10<=a1[10]+a2[10]+a3[10]+a4[10]+a5[10]+a6[10]+a7[10]+a8[10]+bit9[3:1];
bit11<=a1[11]+a2[11]+a3[11]+a4[11]+a5[11]+a6[11]+a7[11]+a8[11]+bit10[3:1];
bit12<=a1[12]+a2[12]+a3[12]+a4[12]+a5[12]+a6[12]+a7[12]+a8[12]+bit11[3:1];
c<={bit12,bit11[0],bit10[0],bit9[0],bit8[0],bit7[0],bit6[0],bit5[0],bit4[0],bit3[0],bit2[0],
 bit1[0],bit0[0]};
res<=temp1-c;
sum<=res[11:0];
carry<=res[14:12];
end
endmodule
SERIAL SUBTRACTOR
VERILOG PROGRAM:
module ssub(res,sign);
output[14:0]res;
output sign;
reg[14:0]res;
reg sign;
reg[11:0]in1=12'b000000000011;
reg[11:0]in2=12'b000000000011;
reg[11:0]in3=12'b000000000011;
reg[11:0]in4=12'b000000000011;
reg[11:0]in5=12'b000000000011;
reg[11:0]in6=12'b000000000011;
reg[11:0]in7=12'b000000000011;
reg[11:0]in8=12'b000000000011;
reg[15:0]temp=16'b1000000000000000;
reg[16:0]temp1=17'b10000000000000000;
reg[3:0]bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8,bit9,bit10,bit11;
reg[1:0]bits0,bits1,bits2,bits3,bits4,bits5,bits6,bits7,bits8,bits9,bits10, bits11,bits12,bits13,bits14;
reg[15:0]c,res1;
reg[14:0]store,p1;
always@(in1,in2,in3,in4,in5,in6,in7,in8,c,temp,res1,store,bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit
8,bit9,bit10,bit11,bits0,bits1,bits2,bits3,bits4,bits5,bits6,bits7,bits8,bits9,bits10,
bits11,bits12,bits13,bits14,p1)
begin
bit0<=in2[0]+in3[0]+in4[0]+in5[0]+in6[0]+in7[0]+in8[0];
bit1<=in2[1]+in3[1]+in4[1]+in5[1]+in6[1]+in7[1]+in8[1]+bit0[3:1];
bit2<=in2[2]+in3[2]+in4[2]+in5[2]+in6[2]+in7[2]+in8[2]+bit1[3:1];
bit3<=in2[3]+in3[3]+in4[3]+in5[3]+in6[3]+in7[3]+in8[3]+bit2[3:1];
bit4<=in2[4]+in3[4]+in4[4]+in5[4]+in6[4]+in7[4]+in8[4]+bit3[3:1];
bit5<=in2[5]+in3[5]+in4[5]+in5[5]+in6[5]+in7[5]+in8[5]+bit4[3:1];
bit6<=in2[6]+in3[6]+in4[6]+in5[6]+in6[6]+in7[6]+in8[6]+bit5[3:1];
bit7<=in2[7]+in3[7]+in4[7]+in5[7]+in6[7]+in7[7]+in8[7]+bit6[3:1];
bit8<=in2[8]+in3[8]+in4[8]+in5[8]+in6[8]+in7[8]+in8[8]+bit7[3:1];
bit9<=in2[9]+in3[9]+in4[9]+in5[9]+in6[9]+in7[9]+in8[9]+bit8[3:1];
bit10<=in2[10]+in3[10]+in4[10]+in5[10]+in6[10]+in7[10]+in8[10]+bit9[3:1];
bit11<=in2[11]+in3[11]+in4[11]+in5[11]+in6[11]+in7[11]+in8[11]+bit10[3:1];
store<={bit11,bit10[0],bit9[0],bit8[0],bit7[0],bit6[0],bit5[0],bit4[0],bit3[0],
bit2[0],bit1[0],bit0[0]};
p1<=temp-store;
bits0<=in1[0]+p1[0];
bits1<=in1[1]+p1[1]+bits0[1];
bits2<=in1[2]+p1[2]+bits1[1];
bits3<=in1[3]+p1[3]+bits2[1];
bits4<=in1[4]+p1[4]+bits3[1];
bits5<=in1[5]+p1[5]+bits4[1];
bits6<=in1[6]+p1[6]+bits5[1];
bits7<=in1[7]+p1[7]+bits6[1];
bits8<=in1[8]+p1[8]+bits7[1];
bits9<=in1[9]+p1[9]+bits8[1];
bits10<=in1[10]+p1[10]+bits9[1];
bits11<=in1[11]+p1[11]+bits10[1];
bits12<=1'b0+p1[12]+bits11[1];
bits13<=1'b0+p1[13]+bits12[1];
bits14<=1'b0+p1[14]+bits13[1];
c<={bits14,bits13[0],bits12[0],bits11[0],bits10[0],bits9[0],bits8[0],bits8[0],bits7[0],
bits6[0],bits6[0],bits5[0],bits4[0],bits3[0],bits2[0],bits1[0],bits0[0]};
if(c[15]==1'b0)
begin
sign<=1'b0;
res<=c[14:0];
end
else
begin
sign<=1'b1;
res1<=temp1-c;
res<=res1[14:0];
end
end
endmodule
VERILOG PROGRAM
module traffic(clk,reset,p1,p2,p3,p4,pl);
input clk;
input reset;
output [4:0] p1,p2,p3,p4;
output [3:0] pl;
reg [4:0] p1,p2,p3,p4;
reg [3:0] pl;
reg [5:0] sig;
always @(posedge clk or negedge reset)
begin
if(reset == 1'b0)
begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
sig<=6'b000000;
end
else
begin
sig<=sig+1;
case(sig[5:0])
6'b000000:begin
p1<=5'b10011;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
end
6'b000100:begin
p1<=5'b01000;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
end
6'b001000:begin
p1<=5'b00100;
p2<=5'b10011;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
end
6'b001100:begin
 p1<=5'b00100;
p2<=5'b01000;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b1111;
end
6'b010000:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b10011;
p4<=5'b00100;
pl<=4'b1111;
end
6'b010100:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b01000;
p4<=5'b00100;
pl<=4'b1111;
end
6'b011000:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b10011;
pl<=4'b1111;
end
6'b011100:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b01000;
pl<=4'b1111;
end
6'b100000:begin
p1<=5'b00100;
p2<=5'b00100;
p3<=5'b00100;
p4<=5'b00100;
pl<=4'b0000;
end
6'b100100: sig<=6'b000000;

default: begin
end
endcase
end
end
endmodule
VERILOG PROGRAM
module rtc(clk,rst,mode,set,sl,atoh);
input clk;
input rst;
input[1:0]mode;
input[7:0]set;
output[5:0]sl;
output[7:0]atoh;
reg[5:0]sl;
reg[7:0]atoh;
reg[26:0]sig2;
reg[19:0]sig3;
reg[7:0]ssdigit1,ssdigit2,ssdigit3,ssdigit4,ssdigit5,ssdigit6;
reg[3:0]digit1,digit2,digit3,digit4,digit5,digit6;

always @ (posedge clk or negedge rst)

begin
if(rst==1'b0)begin
sig2=0;
sig3=0;
digit1=0;
digit2=0;
digit3=0;
digit4=0;
digit5=0;
digit6=0;
end
else begin
if(mode==2'b00)begin
if(set[7:4]<=4'b0010)
digit1=set[7:4];
else
digit1=0;
if(set[3:0]<=4'b1001)
digit2=set[3:0];
else
digit2=0;
end

else if(mode==2'b01)begin
if(set[7:4]<=4'b0101)
digit3=set[7:4];
else
digit3=0;
if(set[3:0]<=4'b1001)
digit4=set[3:0];
else
 digit4=0;
end
else if(mode==2'b10)begin
if(set[7:4]<=4'b0101)
digit5=set[7:4];
else
digit5=0;
if(set[3:0]<=4'b1001)
digit6=set[3:0];
else
digit6=0;
end
else begin
sig2=sig2+1;
case(sig2[24:23])
2'b00:begin
digit6=digit6+1;
if(digit6>4'b1001)begin
digit6=4'b0000;
digit5=digit5+1;
if(digit5>4'b0101)begin
digit5=4'b0000;
digit4=digit4+1;
if(digit4>4'b1001)begin
digit4=4'b0000;
digit3=digit3+1;
if(digit3>4'b0101)begin
digit3=4'b0000;
digit2=digit2+1;
if(digit2>4'b1001)begin
digit2=4'b0000;
digit1=digit1+1;
if((digit1>=4'b0010)&(digit2>4'b0100))begin
digit1=4'b0000;
digit2=4'b0000;
end
end
end
end
end
end
sig2[24:23]=2'b01;
end
2'b11:begin
if(sig2[22:19]==4'b1001)
sig2=0;
end
default: begin
end
endcase
 end
sig3=sig3+1;
case(sig3[17:15])
3'b000:begin
sl=6'b111110;
case(digit1)
4'b0000:ssdigit1=8'b00111111;
4'b0001:ssdigit1=8'b00000110;
4'b0010:ssdigit1=8'b01011011;
default:ssdigit1=8'b00000000;
endcase
atoh=ssdigit1;
end
3'b001:begin
sl=6'b111101;
case(digit2)
4'b0000:ssdigit2=8'b00111111;
4'b0001:ssdigit2=8'b00000110;
4'b0010:ssdigit2=8'b01011011;
4'b0011:ssdigit2=8'b01001111;
4'b0100:ssdigit2=8'b01100110;
4'b0101:ssdigit2=8'b01101101;
4'b0110:ssdigit2=8'b01111101;
4'b0111:ssdigit2=8'b00000111;
4'b1000:ssdigit2=8'b01111111;
4'b1001:ssdigit2=8'b01101111;
default:ssdigit2=8'b00000000;
endcase
atoh=ssdigit2;
end
3'b011:begin
sl=6'b111011;
case(digit3)
4'b0000:ssdigit3=8'b00111111;
4'b0001:ssdigit3=8'b00000110;
4'b0010:ssdigit3=8'b01011011;
4'b0011:ssdigit3=8'b01001111;
4'b0100:ssdigit3=8'b01100110;
4'b0101:ssdigit3=8'b01101101;
default:ssdigit3=8'b00000000;
endcase
atoh=ssdigit3;
end
3'b100:begin
sl=6'b110111;
case(digit4)
4'b0000:ssdigit4=8'b00111111;
4'b0001:ssdigit4=8'b00000110;
4'b0010:ssdigit4=8'b01011011;
4'b0011:ssdigit4=8'b01001111;
 4'b0100:ssdigit4=8'b01100110;
4'b0101:ssdigit4=8'b01101101;
4'b0110:ssdigit4=8'b01111101;
4'b0111:ssdigit4=8'b00000111;
4'b1000:ssdigit4=8'b01111111;
4'b1001:ssdigit4=8'b01101111;
default:ssdigit4=8'b00000000;
endcase
atoh=ssdigit4;
end
3'b110:begin
sl=6'b101111;
case(digit5)
4'b0000:ssdigit5=8'b00111111;
4'b0001:ssdigit5=8'b00000110;
4'b0010:ssdigit5=8'b01011011;
4'b0011:ssdigit5=8'b01001111;
4'b0100:ssdigit5=8'b01100110;
4'b0101:ssdigit5=8'b01101101;
default:ssdigit5=8'b00000000;
endcase
atoh=ssdigit5;
end
3'b111:begin
sl=6'b011111;
case(digit6)
4'b0000:ssdigit6=8'b00111111;
4'b0001:ssdigit6=8'b00000110;
4'b0010:ssdigit6=8'b01011011;
4'b0011:ssdigit6=8'b01001111;
4'b0100:ssdigit6=8'b01100110;
4'b0101:ssdigit6=8'b01101101;
4'b0110:ssdigit6=8'b01111101;
4'b0111:ssdigit6=8'b00000111;
4'b1000:ssdigit6=8'b01111111;
4'b1001:ssdigit6=8'b01101111;
default:ssdigit6=8'b00000000;
endcase
atoh=ssdigit6;
end
endcase
end
end
endmodule