Professional Documents
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March 2007
FAN7602B
Green Current-Mode PWM Controller
Features Description
Green Current-Mode PWM Control The FAN7602B is a green current-mode PWM controller.
Fixed 65kHz Operation It is specially designed for off-line adapter applications;
Internal High-Voltage Start-up Switch DVDP, VCR, LCD monitor applications; and auxiliary
power supplies.
Burst-Mode Operation
Line Voltage Feedforward to Limit Maximum Power The internal high-voltage start-up switch and the burst-
mode operation reduce the power loss in standby mode.
Line Under-Voltage Protection
As a result, it is possible to supply 0.5W load, limiting the
Latch Protection & Internal Soft-Start (10ms) Function
input power under 1W when the input line voltage is
Overload Protection 265VAC. On no-load condition, input power is under 0.3W.
Over-Voltage Protection
The maximum power can be limited constantly, regard-
Low Operation Current: 1mA Typical less of the line voltage change, using the power limit
8-pin DIP/SOP function.
The switching frequency is internally fixed at 65kHz.
Applications
The FAN7602B includes various protections for the sys-
Adapter
tem reliability and the internal soft-start prevents the out-
LCD Monitor Power put voltage over-shoot at start-up.
Auxiliary Power Supply
Ordering Information
Operating Temp. Marking
Part Number Range Pb-Free Package Packing Method Code
FAN7602BN 8-DIP Rail FAN7602B
FAN7602BM -25°C to +125°C Yes Rail FAN7602B
8-SOP
FAN7602BMX Tape & Reel FAN7602B
FAN7602B
6 VCC
LUVP 1 LUVP OVP
Auto Restart
OLP Protection SS End 19V
2V/1.5V OVP
Latch Reset
Latch Protection Circuit
5V Ref
12V/8V
VCC UVLO
10ms SS End
Soft Start
Driver
5 OUT
Circuit
PWM
Block Plimit
Offset
65kHz clock
Delay 3 CS/FB
Circuit
0.95V/0.88V
Latch/ Latch
2
Plimit
PWM+
OLP Power Limit
4V Soft
Start
Plimit
Plimit Offset Plimit
Offset OLP Offset
4 GND
Generator Soft
Start
FAN7602B
YWW
1 2 3 4
LUVP Latch/ CS/FB GND
Plimit
Pin Definitions
Pin # Name Description
Line Under-Voltage Protection Pin. This pin is used to protect the set when the
1 LUVP
input voltage is lower than the rated input voltage range.
Latch Protection and Power Limit Pin. When the pin voltage exceeds 4V, the latch
2 Latch/Plimit protection works; the latch protection is reset when the VCC voltage is lower than 5V.
For the power limit function, the OCP level decreases as the pin voltage increases.
Current Sense and Feedback Pin. This pin is used to sense the MOSFET current
3 CS/FB for the current mode PWM and OCP. The output voltage feedback information and
the current sense information are added using an external RC filter.
Ground Pin. This pin is used for the ground potential of all the pins. For proper oper-
4 GND
ation, the signal ground and the power ground should be separated.
Gate Drive Output Pin. This pin is an output pin to drive an external MOSFET. The
5 OUT peak sourcing current is 450mA and the peak sinking current is 600mA. For proper
operation, the stray inductance in the gate driving path must be minimized.
Supply Voltage Pin. IC operating current and MOSFET driving current are supplied
6 VCC
using this pin.
7 NC No Connection.
Start-up Pin. This pin is used to supply IC operating current during IC start-up. After
8 VSTR
start-up, the internal JFET is turned off to reduce power loss.
Thermal Impedance
Symbol Parameter Value Unit
θJA Thermal Resistance, Junction-to-Ambient 8-DIP 100 °C/W
Note:
1. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.
12.8 8.8
12.4 8.4
VTH[V]
VTL[V]
12.0 8.0
11.6 7.6
11.2 7.2
Figure 4. Start Threshold Voltage vs. Temp. Figure 5. Stop Threshold Voltage vs. Temp.
4.4 350
4.3
UVLO Hysteresis [V]
4.2 300
4.1
Ist [μA]
4.0 250
3.9
3.8 200
3.7
3.6 150
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [°C] Temperature [°C]
Figure 6. UVLO Hysteresis vs. Temp. Figure 7. Start-up Supply Current vs. Temp.
1.5 1.3
1.4
1.2
1.3
Iop [mA]
Istr [mA]
1.2 1.1
1.1 1.0
1.0
0.9
0.9
0.8 0.8
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [°C] Temperature [°C]
Figure 8. Operating Supply Current vs. Temp. Figure 9. VSTR Star-up Current vs. Temp.
1.10 70
CSFB2
1.05
CSFB3 68
CS/FB Threshold [V]
1.00
Fosc [kHz]
0.95 66
0.90
64
0.85
0.80
62
0.75
0.70 60
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [°C] Temperature [°C]
Figure 10. Burst On/Off Voltage vs. Temp. Figure 11. Operating Frequency vs. Temp.
0.20 80
0.18 78
Dmax [%]
Kplimit
0.16 76
0.14 74
0.12 72
0.10 70
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [°C] Temperature [°C]
Figure 12. Offset Gain vs. Temp. Figure 13. Maximum Duty Cycle vs. Temp.
20.0 4.4
19.6
4.2
VLATCH [V]
VOVP [V]
19.2
4.0
18.8
3.8
18.4
18.0 3.6
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [°C] Temperature [°C]
Figure 14. OVP Voltage vs. Temp. Figure 15. Latch Voltage vs. Temp.
2.10 1.70
1.65
2.05
1.60
VLUVPon [V]
VLUVPoff [V]
2.00 1.55
1.50
1.95
1.45
1.90 1.40
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [°C] Temperature [°C]
Figure 16. LUVP On-to-Off Voltage vs. Temp. Figure 17. LUVP Off-to-On Voltage vs. Temp.
1.08
CSFB1 Threshold voltage [V]
1.04
1.00
0.96
0.92
-25 0 25 50 75 100 125
Temperature [°C]
8V Vcc
Start-up
Plimit
Current PWM Offset
Comparator
Soft Start RFB
PWM+ Power IFB
1.5V Voltage Soft Limit
RF
1V Start CS/FB
Isw
0.5V 3
Soft Start t CF
Time (10ms) RS
5ms
rent-mode PWM and the output voltage feedback with (a) Low-Power Limit Offset Case
only one pin, pin3. To achieve the two functions with one 1V
Power Limit
pin, an internal leading edge blanking (LEB) circuit to fil- PWM+
Offset
50mV
Soft-Start
Features
Low stand-by power (<0.3W at 265VAC)
Constant output power control
1. Schematic
R206 C204
D202
D204 L201
1 T1 12
C106
R103
BD101
C201 C202
C105
D101 9
R112 R114 3
Q101 6 D102 R109 R110
R105 C222
C109
R106
C103 C104 5
ZD101
R102
R202
R201
R113
OP1
C102 4 1 R204
C110
1 8
LF1
Plimit NC
R101 3
C107 IC201 1
3 6
CS/FB VCC R111 2
R104
C101 4 5 R205
RT101
IC101 D103
AC INPUT
OP2 R207
4 1
3 2
Np2 Ns Np2
2 9 NVcc
3 5 Ns
5
Shield
Ns
NVcc Shield
Np1
6 5
3. Winding Specification
4. Electrical Characteristics
Minimize leakage
inductance
DC
Link
Minimize loop area
8 7 6 5
VSTR NC VCC Out
FAN7602B
Latch/
YWW
LUVP Plimit CS/FB GND
1 2 3 4
Separate power
and signal ground
8. Performance Data
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
Rev. I24