chain cell type edge inv gate# clocks

instance_name (type)
----------------- ---- ------- ---- --- ------ ----------------------
------------------------------------
Chain[1] 0 MASTER LE NN 288694 + GPIO_07
I_DCORE/\SNPS_PipeTail_u_waimea_dcore_glue/u_dft_test_ctrl/scan_chain_out[1]_1
(M31_1P5V6T_DFFQX1)
Chain[1] 1 MASTER LE NN 283105 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 257313 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/LOCKUP (M31_1P5V6T_LOWLATCHX2)
Chain[1] 2 MASTER LE NN 283098 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3 MASTER LE NN 283097 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 4 MASTER LE NN 283984 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[3] (M31_1P5V6T_SFFRBQX2)
Chain[1] 5 MASTER LE NN 283198 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_int_soft_start_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 6 MASTER LE NN 283763 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 7 MASTER LE NN 283596 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 8 MASTER LE NN 283594 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 9 MASTER LE NN 283597 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 10 MASTER LE NN 283760 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 11 MASTER LE NN 283463 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/d_vreg_ready_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 12 MASTER LE NN 283595 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 13 MASTER LE NN 283758 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
 Chain[1] 14 MASTER LE NN 283761 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_EN_CFG_VIN_FF_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 15 MASTER LE NN 283610 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_SPARE_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 16 MASTER LE NN 283608 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 17 MASTER LE NN 283751 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CURRENT_CFG_reg
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 18 MASTER LE NN 283739 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_VOLT_CFG_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 19 MASTER LE NN 283611 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_SPARE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 20 MASTER LE NN 283095 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 21 MASTER LE NN 283738 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_VOLT_CFG_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 22 MASTER LE NN 283750 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CURRENT_CFG_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 23 MASTER LE NN 283737 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_OUT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 24 MASTER LE NN 283631 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 25 MASTER LE II 283109 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 26 MASTER LE II 283749 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CAP_CFG_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 27 MASTER LE II 283592 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 28 MASTER LE II 283916 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[1] 29 MASTER LE II 283970 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 30 MASTER LE II 283920 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 31 MASTER LE II 283650 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 32 MASTER LE II 283915 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 33 MASTER LE II 283919 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 34 MASTER LE II 283917 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 35 MASTER LE II 283918 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 36 MASTER LE II 283520 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/d_ocp_perph_en_master_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 37 MASTER LE II 283982 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 38 MASTER LE II 283934 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 39 MASTER LE II 283966 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 40 MASTER LE II 283932 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 41 MASTER LE II 283967 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 42 MASTER LE II 283965 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 43 MASTER LE II 283964 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 44 MASTER LE II 283769 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 45 MASTER LE II 283632 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 46 MASTER LE II 283883 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 47 MASTER LE II 283884 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 48 MASTER LE II 283768 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 49 MASTER LE II 283770 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 50 MASTER LE II 283945 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 51 MASTER LE II 283220 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_clk_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 52 MASTER LE II 283237 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_lfrc_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 53 MASTER LE II 283238 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_lfrc_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 54 MASTER LE II 283221 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_clk_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 55 MASTER LE II 283771 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 56 MASTER LE II 283796 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_EN_CTL__PERPH_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 57 MASTER LE NN 283108 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 58 MASTER LE NN 283649 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 59 MASTER LE NN 283648 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 60 MASTER LE NN 283772 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_2__POWER_BOOST_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 61 MASTER LE NN 283669 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPDOWN_READY_CTL__VOUT_EQ_VREF_WAIT_BYPASS_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 62 MASTER LE NN 283591 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 63 MASTER LE NN 283593 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 64 MASTER LE NN 283590 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 65 MASTER LE NN 283607 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 66 MASTER LE NN 283407 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 67 MASTER LE NN 283277 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_update_fsm_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 68 MASTER LE NN 283355 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 69 MASTER LE NN 283358 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 70 MASTER LE NN 284007 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_timer1_exp_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 71 MASTER LE NN 283359 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 72 MASTER LE NN 283814 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_slib_sync
/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 73 MASTER LE NN 283245 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_blank_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 74 MASTER LE NN 283521 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_pong_blank_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 75 MASTER LE NN 283244 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_toggle_in_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 76 MASTER LE NN 283357 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_timer0_exp_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 77 MASTER LE NN 283102 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor14_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 78 MASTER LE NN 283088 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 79 MASTER LE NN 283083 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp5_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 80 MASTER LE NN 283103 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor15_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 81 MASTER LE NN 283093 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 82 MASTER LE NN 283101 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 83 MASTER LE NN 283089 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor16_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 84 MASTER LE NN 283100 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 85 MASTER LE NN 283734 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 86 MASTER LE NN 283733 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 87 MASTER LE NN 283764 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 88 MASTER LE NN 283743 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PHASE_STAGGER_COMP_CAP_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 89 MASTER LE NN 283745 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PING_PONG_COMP_CAP_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 90 MASTER LE NN 283762 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 91 MASTER LE NN 283606 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 92 MASTER LE NN 283387 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__RETENTION_QUAL_rifi_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 93 MASTER LE NN 283731 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_RANGE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 94 MASTER LE NN 283519 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_npm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 95 MASTER LE NN 283141 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_out_reg_re
g (M31_1P5V6T_SFFRBQX1)
Chain[1] 96 MASTER LE NN 283759 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 97 MASTER LE NN 283529 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__MODE_STATE_rifi_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 98 MASTER LE NN 283756 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 99 MASTER LE NN 283467 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/d_vreg_error_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 100 MASTER LE NN 283609 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 101 MASTER LE NN 283766 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_EN_COMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 102 MASTER LE NN 283997 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__OPEN_LOOP_ACTIVE_CFG_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX2)
Chain[1] 103 MASTER LE NN 283951 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 104 MASTER LE NN 283767 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_EN_DLL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 105 MASTER LE NN 283765 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 106 MASTER LE NN 283732 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 107 MASTER LE NN 283957 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 108 MASTER LE NN 283950 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 109 MASTER LE NN 283956 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 110 MASTER LE NN 283958 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 111 MASTER LE NN 283952 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 112 MASTER LE NN 283949 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 113 MASTER LE NN 283955 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 114 MASTER LE NN 283757 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 115 MASTER LE NN 283865 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 116 MASTER LE NN 283755 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 117 MASTER LE NN 283863 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 118 MASTER LE NN 283179 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_rpm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 119 MASTER LE NN 283659 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CTL__MULTIPHASE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 120 MASTER LE NN 283959 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 121 MASTER LE NN 283657 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 122 MASTER LE NN 283518 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_npm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 123 MASTER LE NN 283654 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 124 MASTER LE NN 283954 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 125 MASTER LE NN 283960 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 126 MASTER LE NN 283658 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 127 MASTER LE NN 284000 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 128 MASTER LE NN 283653 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 129 MASTER LE NN 283655 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 130 MASTER LE NN 283188 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_19p2_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 131 MASTER LE NN 283189 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_19p2_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 132 MASTER LE NN 283178 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_rpm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 133 MASTER LE NN 283913 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 134 MASTER LE NN 283674 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 135 MASTER LE NN 283912 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 136 MASTER LE NN 283675 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 137 MASTER LE NN 283899 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 138 MASTER LE NN 283900 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 139 MASTER LE NN 283910 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 140 MASTER LE NN 283911 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 141 MASTER LE NN 283671 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 142 MASTER LE NN 283896 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_slib_sync/s
ync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 143 MASTER LE NN 283176 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_en_rb/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 144 MASTER LE NN 283673 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 145 MASTER LE NN 283672 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 146 MASTER LE NN 283670 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 147 MASTER LE NN 283888 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 148 MASTER LE NN 283897 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_slib_sync/s
ync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 149 MASTER LE NN 283942 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_slib_sync/sync_d_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 150 MASTER LE NN 283941 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_slib_sync/sync_d_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 151 MASTER LE NN 283177 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_en_rb/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 152 MASTER LE NN 283948 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 153 MASTER LE NN 283947 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 154 MASTER LE NN 283998 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 155 MASTER LE NN 283909 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX3)
Chain[1] 156 MASTER LE NN 283914 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 157 MASTER LE NN 283656 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 158 MASTER LE NN 283651 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 159 MASTER LE NN 283664 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 160 MASTER LE NN 283953 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 161 MASTER LE NN 283667 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 162 MASTER LE NN 283777 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__DIS_RETENTION_MODE_DLY_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX3)
Chain[1] 163 MASTER LE NN 283773 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_PS_DLY_reg/dout_reg[1
] (M31_1P5V6T_SFFRBQX2J)
Chain[1] 164 MASTER LE NN 283835 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 165 MASTER LE NN 283833 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 166 MASTER LE NN 283662 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 167 MASTER LE NN 283834 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 168 MASTER LE NN 283829 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[0
] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 169 MASTER LE NN 283831 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[2
] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 170 MASTER LE NN 283830 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[1
] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 171 MASTER LE NN 283837 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 172 MASTER LE NN 283838 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 173 MASTER LE NN 283836 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 174 MASTER LE NN 283839 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 175 MASTER LE NN 283832 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[3
] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 176 MASTER LE NN 283652 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 177 MASTER LE NN 283774 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_PS_DLY_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[1] 178 MASTER LE NN 283775 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_REFSAMPLE_TIMER_reg/do
ut_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 179 MASTER LE NN 283776 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_REFSAMPLE_TIMER_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX3)
 Chain[1] 180 MASTER LE NN 283735 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 181 MASTER LE NN 283742 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PING_PONG_CP_CURRNT_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 182 MASTER LE NN 283740 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__BW_PHASE_STAGGER_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 183 MASTER LE NN 283744 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PHASE_STAGGER_COMP_CAP_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 184 MASTER LE NN 283741 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__BW_PHASE_STAGGER_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 185 MASTER LE NN 283092 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 186 MASTER LE NN 283084 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 187 MASTER LE NN 283086 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 188 MASTER LE NN 283085 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 189 MASTER LE NN 283087 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 190 MASTER LE NN 284006 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[7]
(M31_1P5V6T_SFFRBQX2J)
Chain[1] 191 MASTER LE NN 283353 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 192 MASTER LE NN 283350 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 193 MASTER LE NN 283352 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 194 MASTER LE NN 283136 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 195 MASTER LE NN 283354 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 196 MASTER LE NN 283349 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 197 MASTER LE NN 283348 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 198 MASTER LE NN 283347 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 199 MASTER LE NN 283346 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 200 MASTER LE NN 283342 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 201 MASTER LE NN 283345 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 202 MASTER LE NN 283243 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_tgl_counter_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 203 MASTER LE NN 283242 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_tgl_counter_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 204 MASTER LE NN 283370 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 205 MASTER LE NN 283369 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 206 MASTER LE NN 283809 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 207 MASTER LE NN 283807 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[1] 208 MASTER LE NN 283241 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 209 MASTER LE NN 283343 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 210 MASTER LE NN 283344 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 211 MASTER LE NN 283337 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_setpoint_gt_vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 212 MASTER LE NN 283130 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 213 MASTER LE NN 283131 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 214 MASTER LE NN 283133 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 215 MASTER LE NN 283132 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 216 MASTER LE NN 283338 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_setpoint_eq_vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 217 MASTER LE NN 283139 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 218 MASTER LE NN 283291 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 219 MASTER LE NN 283539 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 220 MASTER LE NN 283810 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 221 MASTER LE NN 283808 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 222 MASTER LE NN 283187 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 223 MASTER LE NN 283115 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[9] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 224 MASTER LE NN 283157 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[8]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 225 MASTER LE NN 283163 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 226 MASTER LE NN 283116 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[11] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 227 MASTER LE NN 283120 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 228 MASTER LE NN 283281 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
clk_req_u/d_clk_req_stepper_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 229 MASTER LE NN 283280 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
clk_req_u/d_clk_req_stepper_meta_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 230 MASTER LE NN 283339 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 231 MASTER LE NN 283135 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 232 MASTER LE NN 283351 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 233 MASTER LE NN 283815 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 234 MASTER LE NN 283341 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_STEPPER_DONE_d
_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 235 MASTER LE NN 283816 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 236 MASTER LE NN 283285 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 237 MASTER LE NN 283389 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_bypass_
en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 238 MASTER LE NN 283284 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 239 MASTER LE NN 283390 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_bypass_
en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 240 MASTER LE NN 283134 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 241 MASTER LE NN 283278 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_master_
en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 242 MASTER LE NN 283340 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 243 MASTER LE NN 283137 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 244 MASTER LE NN 283279 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_master_
en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 245 MASTER LE NN 283138 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 246 MASTER LE NN 283282 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 247 MASTER LE NN 283288 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 248 MASTER LE NN 283660 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 249 MASTER LE NN 283828 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 250 MASTER LE NN 283827 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 251 MASTER LE NN 283287 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 252 MASTER LE NN 283826 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 253 MASTER LE NN 283286 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 254 MASTER LE NN 283289 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[1] 255 MASTER LE NN 283283 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 256 MASTER LE NN 283290 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[1] 257 MASTER LE NN 283804 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/sync_u0/sync_d_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 258 MASTER LE NN 283805 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/sync_u0/sync_d_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 259 MASTER LE NN 283924 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 260 MASTER LE NN 283921 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 261 MASTER LE NN 283922 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 262 MASTER LE NN 283923 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 263 MASTER LE NN 283877 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 264 MASTER LE NN 283875 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 265 MASTER LE NN 283985 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 266 MASTER LE NN 283806 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 267 MASTER LE NN 283881 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 268 MASTER LE NN 283869 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 269 MASTER LE NN 283871 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 270 MASTER LE NN 283935 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[1] 271 MASTER LE NN 283983 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 272 MASTER LE NN 283981 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 273 MASTER LE NN 283938 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/dtmp_reg (M31_1P5V6T_SFFRSBQX1)
Chain[1] 274 MASTER LE NN 283890 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 275 MASTER LE NN 283886 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 276 MASTER LE NN 283939 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 277 MASTER LE NN 283999 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 278 MASTER LE NN 283940 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 279 MASTER LE NN 283240 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 280 MASTER LE NN 283936 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 281 MASTER LE NN 283929 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[1] 282 MASTER LE NN 283933 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 283 MASTER LE NN 283927 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[1] 284 MASTER LE NN 283931 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[1] 285 MASTER LE NN 283879 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 286 MASTER LE NN 283873 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 287 MASTER LE NN 284003 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 288 MASTER LE NN 283161 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 289 MASTER LE NN 283159 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 290 MASTER LE NN 283266 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_clear_latch_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 291 MASTER LE NN 283271 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 292 MASTER LE NN 283270 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 293 MASTER LE NN 283158 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 294 MASTER LE NN 283162 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 295 MASTER LE NN 283254 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 296 MASTER LE NN 283239 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 297 MASTER LE NN 283937 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 298 MASTER LE NN 283268 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 299 MASTER LE NN 283269 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 300 MASTER LE NN 283272 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 301 MASTER LE NN 283273 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 302 MASTER LE NN 283165 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 303 MASTER LE NN 283114 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[10] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 304 MASTER LE NN 283117 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 305 MASTER LE NN 283535 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 306 MASTER LE NN 283184 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 307 MASTER LE NN 283185 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 308 MASTER LE NN 283371 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[1] 309 MASTER LE NN 283367 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 310 MASTER LE NN 283315 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 311 MASTER LE NN 283313 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 312 MASTER LE NN 283316 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 313 MASTER LE NN 283975 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_curr_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 314 MASTER LE NN 283548 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_capture1_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 315 MASTER LE NN 283314 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 316 MASTER LE NN 283248 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 317 MASTER LE NN 283247 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 318 MASTER LE NN 283326 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 319 MASTER LE NN 283327 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 320 MASTER LE NN 283320 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 321 MASTER LE NN 283328 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 322 MASTER LE NN 283140 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_out_reg_re
g (M31_1P5V6T_SFFRBQX1)
Chain[1] 323 MASTER LE NN 283246 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_u1/cl
k_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 324 MASTER LE NN 283329 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 325 MASTER LE NN 283534 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 326 MASTER LE NN 283363 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 327 MASTER LE NN 283180 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 328 MASTER LE NN 283181 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 329 MASTER LE NN 283186 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 330 MASTER LE NN 283356 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[1] 331 MASTER LE NN 283368 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 332 MASTER LE NN 283372 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[1] 333 MASTER LE NN 283365 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 334 MASTER LE NN 283366 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 335 MASTER LE NN 283364 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 336 MASTER LE NN 283362 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 337 MASTER LE NN 283183 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 338 MASTER LE NN 283661 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 339 MASTER LE NN 283182 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 340 MASTER LE NN 283663 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 341 MASTER LE NN 283665 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 342 MASTER LE NN 283668 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 343 MASTER LE NN 283666 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 344 MASTER LE NN 284002 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 345 MASTER LE NN 283110 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 346 MASTER LE NN 283111 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 347 MASTER LE NN 283113 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 348 MASTER LE NN 283112 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[4] (M31_1P5V6T_SFFSRBQX1)
 Chain[1] 349 MASTER LE NN 283119 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 350 MASTER LE NN 283118 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 351 MASTER LE NN 283323 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/slib_clkreq_gate_1p0_hf_clk_u1
/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 352 MASTER LE NN 283322 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 353 MASTER LE NN 283325 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 354 MASTER LE NN 283121 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ps_fsm_reg (M31_1P5V6T_SFFSRBQX1)
Chain[1] 355 MASTER LE NN 283524 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_disable_awake_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 356 MASTER LE NN 283523 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_fsm_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 357 MASTER LE NN 283540 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_a2d_comp_out_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 358 MASTER LE NN 283972 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_sync1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 359 MASTER LE NN 283472 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 360 MASTER LE NN 283317 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_force_wake_ps_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 361 MASTER LE NN 283306 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_fsm_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 362 MASTER LE NN 283974 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_curr_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 363 MASTER LE NN 283310 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 364 MASTER LE NN 283474 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 365 MASTER LE NN 283475 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 366 MASTER LE NN 283502 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 367 MASTER LE NN 283503 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 368 MASTER LE NN 283486 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 369 MASTER LE NN 283487 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 370 MASTER LE NN 283490 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 371 MASTER LE NN 283489 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 372 MASTER LE NN 283305 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_refdac_sample_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 373 MASTER LE NN 283324 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ctrl_fsm_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 374 MASTER LE NN 283321 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 375 MASTER LE NN 283330 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 376 MASTER LE NN 283541 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 377 MASTER LE NN 283526 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_enable_toggle_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 378 MASTER LE NN 284004 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 379 MASTER LE NN 283253 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 380 MASTER LE NN 283249 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 381 MASTER LE NN 283250 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 382 MASTER LE NN 283265 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_calc_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 383 MASTER LE NN 283154 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[11]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 384 MASTER LE NN 283155 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[10]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 385 MASTER LE NN 283156 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[9]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 386 MASTER LE NN 283160 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 387 MASTER LE NN 283252 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_sync_b_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 388 MASTER LE NN 283228 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 389 MASTER LE NN 283251 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_sync_b_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 390 MASTER LE NN 283122 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 391 MASTER LE NN 283164 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 392 MASTER LE NN 283225 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_en
_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 393 MASTER LE NN 283224 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_en
_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 394 MASTER LE NN 283222 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_sl
ib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 395 MASTER LE NN 283223 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_sl
ib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 396 MASTER LE NN 283258 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 397 MASTER LE NN 283259 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 398 MASTER LE NN 283319 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 399 MASTER LE NN 283257 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 400 MASTER LE NN 283264 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_sample_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 401 MASTER LE NN 283542 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ctrl_fsm_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 402 MASTER LE NN 283256 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 403 MASTER LE NN 283255 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 404 MASTER LE NN 283468 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 405 MASTER LE NN 283470 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 406 MASTER LE NN 283471 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 407 MASTER LE NN 283469 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 408 MASTER LE NN 283261 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 409 MASTER LE NN 283260 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 410 MASTER LE NN 283944 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 411 MASTER LE NN 283262 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 412 MASTER LE NN 283263 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 413 MASTER LE NN 283943 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 414 MASTER LE NN 283538 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 415 MASTER LE NN 283537 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 416 MASTER LE NN 283233 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 417 MASTER LE NN 283229 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 418 MASTER LE NN 283230 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 419 MASTER LE NN 283232 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 420 MASTER LE NN 283231 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 421 MASTER LE NN 283481 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 422 MASTER LE NN 283530 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 423 MASTER LE NN 283488 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 424 MASTER LE NN 283512 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 425 MASTER LE NN 283309 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 426 MASTER LE NN 283308 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 427 MASTER LE NN 283464 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/slib_sync_u1
/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 428 MASTER LE NN 283311 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 429 MASTER LE NN 283312 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 430 MASTER LE NN 284009 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/slib_sync_u1
/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 431 MASTER LE NN 283152 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 432 MASTER LE NN 283151 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 433 MASTER LE NN 283150 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 434 MASTER LE NN 283465 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/slib_sync_u1
/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 435 MASTER LE NN 283142 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 436 MASTER LE NN 283143 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 437 MASTER LE NN 283508 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 438 MASTER LE NN 283466 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/slib_sync_u1
/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 439 MASTER LE NN 283149 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
3] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 440 MASTER LE NN 283500 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 441 MASTER LE NN 283148 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 442 MASTER LE NN 283153 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 443 MASTER LE NN 283501 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 444 MASTER LE NN 283483 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 445 MASTER LE NN 283504 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 446 MASTER LE NN 283473 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 447 MASTER LE NN 283506 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 448 MASTER LE NN 283477 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 449 MASTER LE NN 283476 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 450 MASTER LE NN 283511 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 451 MASTER LE NN 283510 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 452 MASTER LE NN 283513 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 453 MASTER LE NN 283533 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 454 MASTER LE NN 283147 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 455 MASTER LE NN 283509 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 456 MASTER LE NN 283515 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 457 MASTER LE NN 283514 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 458 MASTER LE NN 283532 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 459 MASTER LE NN 283496 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 460 MASTER LE NN 283493 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 461 MASTER LE NN 283491 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 462 MASTER LE NN 283505 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 463 MASTER LE NN 283507 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 464 MASTER LE NN 283485 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 465 MASTER LE NN 283531 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 466 MASTER LE NN 283480 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 467 MASTER LE NN 283235 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 468 MASTER LE NN 283478 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 469 MASTER LE NN 283479 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 470 MASTER LE NN 284001 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 471 MASTER LE NN 283484 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 472 MASTER LE NN 283226 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 473 MASTER LE NN 283482 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 474 MASTER LE NN 283234 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 475 MASTER LE NN 283236 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 476 MASTER LE NN 283227 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 477 MASTER LE NN 283128 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 478 MASTER LE NN 283129 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 479 MASTER LE NN 283495 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 480 MASTER LE NN 283123 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 481 MASTER LE NN 283127 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 482 MASTER LE NN 283124 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 483 MASTER LE NN 283498 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 484 MASTER LE NN 283126 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 485 MASTER LE NN 283125 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 486 MASTER LE NN 283499 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 487 MASTER LE NN 283492 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 488 MASTER LE NN 283497 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 489 MASTER LE NN 283517 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 490 MASTER LE NN 283516 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 491 MASTER LE NN 283146 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 492 MASTER LE NN 283145 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 493 MASTER LE NN 283144 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 494 MASTER LE NN 286613 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 495 MASTER LE NN 283528 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_glitchfree_mux_1p0_c
lk_qual_u/sel0_0_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 496 MASTER LE NN 282219 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
3] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 257305 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/LO
CKUP (M31_1P5V6T_LOWLATCHX1)
Chain[1] 497 MASTER LE NN 282220 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 498 MASTER LE NN 282212 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 499 MASTER LE NN 282213 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 500 MASTER LE NN 282221 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 501 MASTER LE NN 282214 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 502 MASTER LE NN 282215 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 503 MASTER LE NN 282217 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 504 MASTER LE NN 282335 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_sample_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 505 MASTER LE NN 282327 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 506 MASTER LE NN 282326 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 507 MASTER LE NN 282331 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 508 MASTER LE NN 282332 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 509 MASTER LE NN 282334 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 510 MASTER LE NN 282333 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 511 MASTER LE NN 282553 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 512 MASTER LE NN 282552 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 513 MASTER LE NN 282607 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 514 MASTER LE NN 282554 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 515 MASTER LE NN 282577 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 516 MASTER LE NN 282580 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 517 MASTER LE NN 282582 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 518 MASTER LE NN 282583 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 519 MASTER LE NN 282581 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 520 MASTER LE NN 282576 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 521 MASTER LE NN 282587 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 522 MASTER LE NN 282586 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 523 MASTER LE NN 282589 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 524 MASTER LE NN 282584 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 525 MASTER LE NN 282590 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 526 MASTER LE NN 282585 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 527 MASTER LE NN 282592 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 528 MASTER LE NN 282593 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 529 MASTER LE NN 282573 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 530 MASTER LE NN 282574 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 531 MASTER LE NN 282575 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 532 MASTER LE NN 282572 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 533 MASTER LE NN 282567 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 534 MASTER LE NN 282571 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 535 MASTER LE NN 282609 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 536 MASTER LE NN 282591 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 537 MASTER LE NN 282608 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 538 MASTER LE NN 283063 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 539 MASTER LE NN 282560 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 540 MASTER LE NN 282570 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 541 MASTER LE NN 282551 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 542 MASTER LE NN 282606 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 543 MASTER LE NN 282329 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 544 MASTER LE NN 282330 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 545 MASTER LE NN 282328 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 546 MASTER LE NN 282542 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/slib_sync_u1
/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 547 MASTER LE NN 282540 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/slib_sync_u1
/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 548 MASTER LE NN 282216 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 549 MASTER LE NN 282218 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 550 MASTER LE NN 282222 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 551 MASTER LE NN 282223 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 552 MASTER LE NN 282189 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 553 MASTER LE NN 282190 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 554 MASTER LE NN 283062 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 555 MASTER LE NN 282539 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/slib_sync_u1
/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 556 MASTER LE NN 282541 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/slib_sync_u1
/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 557 MASTER LE NN 282324 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 558 MASTER LE NN 282320 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 559 MASTER LE NN 282224 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[11]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 560 MASTER LE NN 282226 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[9]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 561 MASTER LE NN 282184 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 562 MASTER LE NN 282183 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 563 MASTER LE NN 282233 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 564 MASTER LE NN 282225 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[10]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 565 MASTER LE NN 282182 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 566 MASTER LE NN 282186 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[9] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 567 MASTER LE NN 282181 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 568 MASTER LE NN 282232 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 569 MASTER LE NN 282227 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[8]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 570 MASTER LE NN 282234 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 571 MASTER LE NN 282235 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 572 MASTER LE NN 282321 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 573 MASTER LE NN 282336 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_calc_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 574 MASTER LE NN 282230 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 575 MASTER LE NN 282228 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 576 MASTER LE NN 282325 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 577 MASTER LE NN 282231 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 578 MASTER LE NN 282229 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 579 MASTER LE NN 283077 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 580 MASTER LE NN 283014 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[1] 581 MASTER LE NN 282588 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 582 MASTER LE NN 282958 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 583 MASTER LE NN 282952 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 584 MASTER LE NN 282954 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 585 MASTER LE NN 282975 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_slib_sync/s
ync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 586 MASTER LE NN 282967 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 587 MASTER LE NN 282947 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 588 MASTER LE NN 282962 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 589 MASTER LE NN 282963 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 590 MASTER LE NN 282487 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 591 MASTER LE NN 282969 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 592 MASTER LE NN 282965 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 593 MASTER LE NN 282339 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 594 MASTER LE NN 282323 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_sync_b_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 595 MASTER LE NN 282322 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_sync_b_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 596 MASTER LE NN 282548 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 597 MASTER LE NN 282557 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 598 MASTER LE NN 282579 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 599 MASTER LE NN 282578 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 600 MASTER LE NN 282564 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 601 MASTER LE NN 282550 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 602 MASTER LE NN 282558 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 603 MASTER LE NN 282561 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 604 MASTER LE NN 282559 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 605 MASTER LE NN 282563 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 606 MASTER LE NN 282562 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 607 MASTER LE NN 282549 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 608 MASTER LE NN 282546 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 609 MASTER LE NN 282614 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 610 MASTER LE NN 282305 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 611 MASTER LE NN 282565 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 612 MASTER LE NN 282566 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 613 MASTER LE NN 282547 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 614 MASTER LE NN 282544 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 615 MASTER LE NN 282297 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 616 MASTER LE NN 282298 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 617 MASTER LE NN 282301 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 618 MASTER LE NN 282613 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[1] 619 MASTER LE NN 282300 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 620 MASTER LE NN 282306 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 621 MASTER LE NN 282304 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 622 MASTER LE NN 282489 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 623 MASTER LE NN 282294 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_sl
ib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 624 MASTER LE NN 282293 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_sl
ib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 625 MASTER LE NN 282950 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 626 MASTER LE NN 282611 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 627 MASTER LE NN 282193 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 628 MASTER LE NN 282310 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 629 MASTER LE NN 282299 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 630 MASTER LE NN 283074 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 631 MASTER LE NN 282267 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 632 MASTER LE NN 282255 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 633 MASTER LE NN 282257 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
 Chain[1] 634 MASTER LE NN 282250 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 635 MASTER LE NN 282610 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 636 MASTER LE NN 282307 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 637 MASTER LE NN 282200 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 638 MASTER LE NN 282303 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 639 MASTER LE NN 282302 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 640 MASTER LE NN 282194 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 641 MASTER LE NN 282555 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 642 MASTER LE NN 282545 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 643 MASTER LE NN 282569 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 644 MASTER LE NN 282556 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 645 MASTER LE NN 282568 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 646 MASTER LE NN 282195 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 647 MASTER LE NN 282196 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 648 MASTER LE NN 282197 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 649 MASTER LE NN 282198 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 650 MASTER LE NN 282199 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 651 MASTER LE NN 282251 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 652 MASTER LE NN 282252 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 653 MASTER LE NN 282253 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 654 MASTER LE NN 282256 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 655 MASTER LE NN 282254 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 656 MASTER LE NN 283021 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_slib_sync/sync_d_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 657 MASTER LE NN 282296 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_en
_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 658 MASTER LE NN 282295 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_en
_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 659 MASTER LE NN 282490 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 660 MASTER LE NN 282488 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 661 MASTER LE NN 282976 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_slib_sync/s
ync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 662 MASTER LE NN 282340 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 663 MASTER LE NN 282337 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_clear_latch_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 664 MASTER LE NN 282341 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 665 MASTER LE NN 282342 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 666 MASTER LE NN 282343 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 667 MASTER LE NN 282344 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 668 MASTER LE NN 282185 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[10] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 669 MASTER LE NN 282187 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[11] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 670 MASTER LE NN 282191 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 671 MASTER LE NN 282188 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 672 MASTER LE NN 283081 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 673 MASTER LE NN 282515 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 674 MASTER LE NN 282520 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 675 MASTER LE NN 282519 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 676 MASTER LE NN 282523 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 677 MASTER LE NN 282522 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 678 MASTER LE NN 282521 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 679 MASTER LE NN 282516 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 680 MASTER LE NN 282518 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 681 MASTER LE NN 282517 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 682 MASTER LE NN 282471 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 683 MASTER LE NN 282512 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 684 MASTER LE NN 282513 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 685 MASTER LE NN 282507 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 686 MASTER LE NN 282511 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 687 MASTER LE NN 282510 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 688 MASTER LE NN 282476 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 689 MASTER LE NN 282506 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 690 MASTER LE NN 282508 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 691 MASTER LE NN 282509 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 692 MASTER LE NN 283082 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_out_reg_re
g (M31_1P5V6T_SFFRBQX1)
 Chain[1] 693 MASTER LE NN 282478 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 694 MASTER LE NN 282474 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 695 MASTER LE NN 282473 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 696 MASTER LE NN 282475 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 697 MASTER LE NN 282479 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 698 MASTER LE NN 282477 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 699 MASTER LE NN 282472 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 700 MASTER LE NN 283075 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 701 MASTER LE NN 283012 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 702 MASTER LE NN 283003 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 703 MASTER LE NN 283002 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 704 MASTER LE NN 283000 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 705 MASTER LE NN 283001 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 706 MASTER LE NN 283010 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[1] 707 MASTER LE NN 283008 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[1] 708 MASTER LE NN 283006 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[1] 709 MASTER LE NN 283059 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 710 MASTER LE NN 283061 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 711 MASTER LE NN 282960 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 712 MASTER LE NN 282961 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 713 MASTER LE NN 282971 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 714 MASTER LE NN 282973 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 715 MASTER LE NN 282745 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 716 MASTER LE NN 282741 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 717 MASTER LE NN 282743 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 718 MASTER LE NN 282739 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 719 MASTER LE NN 283080 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 720 MASTER LE NN 282755 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 721 MASTER LE NN 282758 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 722 MASTER LE NN 282793 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 723 MASTER LE NN 282796 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 724 MASTER LE NN 282760 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 725 MASTER LE NN 282797 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 726 MASTER LE NN 282798 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 727 MASTER LE NN 282978 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 728 MASTER LE NN 282979 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 729 MASTER LE NN 282929 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_slib_sync/sync_d_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 730 MASTER LE NN 283020 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_slib_sync/sync_d_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 731 MASTER LE NN 283023 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 732 MASTER LE NN 283022 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 733 MASTER LE NN 282930 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_slib_sync/sync_d_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 734 MASTER LE NN 282247 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_en_rb/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 735 MASTER LE NN 282246 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_en_rb/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 736 MASTER LE NN 282956 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 737 MASTER LE NN 282264 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 738 MASTER LE NN 282263 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 739 MASTER LE NN 282265 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 740 MASTER LE NN 282266 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 741 MASTER LE NN 282260 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_CTLR_MISC4__DUTY_GENERATOR_EN_rifo_del_r
eg (M31_1P5V6T_SFFRBQX1)
Chain[1] 742 MASTER LE NN 282928 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 743 MASTER LE NN 282919 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 744 MASTER LE NN 282921 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 745 MASTER LE NN 283016 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 746 MASTER LE NN 283015 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 747 MASTER LE NN 282258 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_19p2_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 748 MASTER LE NN 282923 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 749 MASTER LE NN 282925 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 750 MASTER LE NN 282920 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 751 MASTER LE NN 282927 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 752 MASTER LE NN 282261 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_duty_out_half_int_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[1] 753 MASTER LE NN 282926 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 754 MASTER LE NN 282922 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 755 MASTER LE NN 282924 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 756 MASTER LE NN 282262 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_duty_out_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 757 MASTER LE NN 282259 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_19p2_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 758 MASTER LE NN 282913 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 759 MASTER LE NN 282906 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 760 MASTER LE NN 282905 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 761 MASTER LE NN 282912 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 762 MASTER LE NN 282914 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 763 MASTER LE NN 283019 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 764 MASTER LE NN 282311 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 765 MASTER LE NN 283017 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/dtmp_reg (M31_1P5V6T_SFFRSBQX1)
Chain[1] 766 MASTER LE NN 282753 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 767 MASTER LE NN 282759 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 768 MASTER LE NN 282800 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 769 MASTER LE NN 282736 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 770 MASTER LE NN 282737 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 771 MASTER LE NN 282785 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 772 MASTER LE NN 283004 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 773 MASTER LE NN 283060 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 774 MASTER LE NN 282790 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 775 MASTER LE NN 282791 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 776 MASTER LE NN 282786 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 777 MASTER LE NN 282788 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[1] 778 MASTER LE NN 282803 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 779 MASTER LE NN 282787 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[1] 780 MASTER LE NN 282802 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 781 MASTER LE NN 283011 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 782 MASTER LE NN 282805 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 783 MASTER LE NN 282804 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[1] 784 MASTER LE NN 282792 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 785 MASTER LE NN 282543 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/d_vreg_error_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 786 MASTER LE NN 282505 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync4/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 787 MASTER LE NN 282504 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync4/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 788 MASTER LE NN 282470 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 789 MASTER LE NN 282312 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 790 MASTER LE NN 282313 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_tgl_counter_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 791 MASTER LE NN 282314 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_tgl_counter_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 792 MASTER LE NN 282155 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 793 MASTER LE NN 282170 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 794 MASTER LE NN 282166 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 795 MASTER LE NN 283035 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 796 MASTER LE NN 282839 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 797 MASTER LE NN 282834 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 798 MASTER LE NN 282514 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 799 MASTER LE NN 282316 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_blank_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 800 MASTER LE NN 282315 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_toggle_in_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 801 MASTER LE NN 283034 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 802 MASTER LE NN 282172 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 803 MASTER LE NN 282175 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor15_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 804 MASTER LE NN 282156 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 805 MASTER LE NN 282154 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 806 MASTER LE NN 282173 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 807 MASTER LE NN 282615 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 808 MASTER LE NN 282538 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/d_vreg_ready_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 809 MASTER LE NN 282824 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__OPEN_LOOP_ACTIVE_CFG_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 810 MASTER LE NN 282818 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__BW_PHASE_STAGGER_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 811 MASTER LE NN 282823 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PING_PONG_COMP_CAP_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 812 MASTER LE NN 282819 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__BW_PHASE_STAGGER_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 813 MASTER LE NN 282820 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PING_PONG_CP_CURRNT_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 814 MASTER LE NN 282822 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PHASE_STAGGER_COMP_CAP_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 815 MASTER LE NN 282843 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 816 MASTER LE NN 282845 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_EN_COMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 817 MASTER LE NN 282846 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_EN_DLL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 818 MASTER LE NN 282642 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 819 MASTER LE NN 283013 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 820 MASTER LE NN 283009 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 821 MASTER LE NN 282691 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 822 MASTER LE NN 282972 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 823 MASTER LE NN 282806 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 824 MASTER LE NN 283007 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 825 MASTER LE NN 282808 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 826 MASTER LE NN 283058 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 827 MASTER LE NN 282807 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 828 MASTER LE NN 282988 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 829 MASTER LE NN 282990 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 830 MASTER LE NN 282991 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 831 MASTER LE NN 282993 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 832 MASTER LE NN 283005 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 833 MASTER LE NN 282992 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 834 MASTER LE NN 282693 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 835 MASTER LE NN 282801 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 836 MASTER LE NN 282692 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 837 MASTER LE NN 282970 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 838 MASTER LE NN 282974 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 839 MASTER LE NN 282689 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 840 MASTER LE NN 282953 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 841 MASTER LE NN 282986 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 842 MASTER LE NN 282794 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 843 MASTER LE NN 282675 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PWM_F_RIGHT_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 844 MASTER LE NN 282740 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 845 MASTER LE NN 282981 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_M1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 846 MASTER LE NN 282718 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 847 MASTER LE NN 282752 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 848 MASTER LE NN 282982 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 849 MASTER LE NN 282985 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 850 MASTER LE NN 282951 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 851 MASTER LE NN 282799 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 852 MASTER LE NN 282949 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 853 MASTER LE NN 282955 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 854 MASTER LE NN 282714 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 855 MASTER LE NN 282878 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 856 MASTER LE NN 282876 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 857 MASTER LE NN 282847 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 858 MASTER LE NN 282849 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 859 MASTER LE NN 282749 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 860 MASTER LE NN 282750 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 861 MASTER LE NN 282747 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 862 MASTER LE NN 282738 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 863 MASTER LE NN 282734 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 864 MASTER LE NN 283018 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 865 MASTER LE NN 282907 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 866 MASTER LE NN 282732 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 867 MASTER LE NN 282731 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 868 MASTER LE NN 282875 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_EN_CTL__PERPH_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 869 MASTER LE NN 282733 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 870 MASTER LE NN 282748 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 871 MASTER LE NN 282730 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 872 MASTER LE NN 282918 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 873 MASTER LE NN 282915 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 874 MASTER LE NN 282916 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 875 MASTER LE NN 282917 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 876 MASTER LE NN 282728 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 877 MASTER LE NN 282908 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[0
] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 878 MASTER LE NN 282909 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[1
] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 879 MASTER LE NN 282911 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[3
] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 880 MASTER LE NN 282931 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 881 MASTER LE NN 282877 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 882 MASTER LE NN 282880 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 883 MASTER LE NN 282879 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 884 MASTER LE NN 282941 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 885 MASTER LE NN 282940 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 886 MASTER LE NN 282932 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 887 MASTER LE NN 282910 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[2
] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 888 MASTER LE NN 282933 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 889 MASTER LE NN 282729 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 890 MASTER LE NN 282727 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 891 MASTER LE NN 282848 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 892 MASTER LE NN 282850 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 893 MASTER LE NN 282751 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 894 MASTER LE NN 282744 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 895 MASTER LE NN 282959 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 896 MASTER LE NN 282957 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 897 MASTER LE NN 282742 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 898 MASTER LE NN 282966 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 899 MASTER LE NN 282989 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 900 MASTER LE NN 282688 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__RET_CMP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 901 MASTER LE NN 282690 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 902 MASTER LE NN 282844 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[1] 903 MASTER LE NN 282821 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PHASE_STAGGER_COMP_CAP_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 904 MASTER LE NN 282841 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 905 MASTER LE NN 282842 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 906 MASTER LE NN 282597 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_pong_blank_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 907 MASTER LE NN 283029 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 908 MASTER LE NN 283028 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 909 MASTER LE NN 283036 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 910 MASTER LE NN 283037 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 911 MASTER LE NN 282174 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor14_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 912 MASTER LE NN 283046 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 913 MASTER LE NN 283043 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 914 MASTER LE NN 283047 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 915 MASTER LE NN 282817 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_VOLT_CFG_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 916 MASTER LE NN 283045 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 917 MASTER LE NN 283039 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 918 MASTER LE NN 282837 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 919 MASTER LE NN 283038 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 920 MASTER LE NN 282840 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_EN_CFG_VIN_FF_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 921 MASTER LE NN 282685 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 922 MASTER LE NN 283030 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 923 MASTER LE NN 282524 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 924 MASTER LE NN 283031 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 925 MASTER LE NN 282836 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 926 MASTER LE NN 282838 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 927 MASTER LE NN 283033 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 928 MASTER LE NN 283032 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 929 MASTER LE NN 282682 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 930 MASTER LE NN 282724 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 931 MASTER LE NN 282211 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_out_reg_re
g (M31_1P5V6T_SFFRBQX1)
Chain[1] 932 MASTER LE NN 282643 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 933 MASTER LE NN 282725 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 934 MASTER LE NN 282726 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 935 MASTER LE NN 282781 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__PWM_19P2M_CLK_FORCE_ON_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 936 MASTER LE NN 282835 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 937 MASTER LE NN 282811 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 938 MASTER LE NN 282466 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 939 MASTER LE NN 282812 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 940 MASTER LE NN 282707 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 941 MASTER LE NN 282706 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 942 MASTER LE NN 282709 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 943 MASTER LE NN 282708 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 944 MASTER LE NN 282813 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 945 MASTER LE NN 282810 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 946 MASTER LE NN 282968 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 947 MASTER LE NN 283076 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 948 MASTER LE NN 282695 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__NC_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 949 MASTER LE NN 282697 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 950 MASTER LE NN 282694 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__NC_TEST_MODE_EN_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 951 MASTER LE NN 282698 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 952 MASTER LE NN 282700 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
3] (M31_1P5V6T_SFFSBQX1)
Chain[1] 953 MASTER LE NN 282789 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 954 MASTER LE NN 282715 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 955 MASTER LE NN 282677 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PP_PWM_LOCK_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 956 MASTER LE NN 282678 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PHASE_STAGGERED_LOCK_EN_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 957 MASTER LE NN 282881 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 958 MASTER LE NN 282681 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PHASE_STAGGERED_LOO
P_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 959 MASTER LE NN 282679 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PP_PWMBY2_LOOP_EN_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 960 MASTER LE NN 282716 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 961 MASTER LE NN 282711 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 962 MASTER LE NN 282948 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 963 MASTER LE NN 282864 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 964 MASTER LE NN 282860 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 965 MASTER LE NN 282946 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 966 MASTER LE NN 282861 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 967 MASTER LE NN 282857 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 968 MASTER LE NN 282626 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 969 MASTER LE NN 282717 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 970 MASTER LE NN 282627 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 971 MASTER LE NN 282710 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 972 MASTER LE NN 282637 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 973 MASTER LE NN 282713 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 974 MASTER LE NN 282712 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 975 MASTER LE NN 283027 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 976 MASTER LE NN 282862 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
 Chain[1] 977 MASTER LE NN 282874 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_AWAKE_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 978 MASTER LE NN 282866 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 979 MASTER LE NN 283026 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 980 MASTER LE NN 282756 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 981 MASTER LE NN 282873 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN2_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 982 MASTER LE NN 282867 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 983 MASTER LE NN 282869 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 984 MASTER LE NN 282754 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 985 MASTER LE NN 282871 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN0_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 986 MASTER LE NN 282702 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
5] (M31_1P5V6T_SFFSBQX1)
Chain[1] 987 MASTER LE NN 282285 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 988 MASTER LE NN 282280 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 989 MASTER LE NN 282284 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 990 MASTER LE NN 282283 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 991 MASTER LE NN 282281 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 992 MASTER LE NN 282282 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 993 MASTER LE NN 282938 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 994 MASTER LE NN 282937 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 995 MASTER LE NN 282882 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 996 MASTER LE NN 282936 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 997 MASTER LE NN 282935 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 998 MASTER LE NN 282934 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 999 MASTER LE NN 282939 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 1000 MASTER LE NN 282703 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
6] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1001 MASTER LE NN 282865 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1002 MASTER LE NN 282872 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN1_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1003 MASTER LE NN 282868 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1004 MASTER LE NN 282870 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1005 MASTER LE NN 282757 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1006 MASTER LE NN 282795 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1007 MASTER LE NN 282680 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PP_PWM_LOOP_EN_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1008 MASTER LE NN 282676 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PP_PWMBY2_LOCK_EN_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1009 MASTER LE NN 282674 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PWM_R_RIGHT_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1010 MASTER LE NN 282977 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1011 MASTER LE NN 282699 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
2] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1012 MASTER LE NN 282696 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1013 MASTER LE NN 282964 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1014 MASTER LE NN 282701 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
4] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1015 MASTER LE NN 282942 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1016 MASTER LE NN 282777 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__VREG_MON_CFG_NPM_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1017 MASTER LE NN 282531 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
l2r_trim_cal_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1018 MASTER LE NN 282945 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1019 MASTER LE NN 282780 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__PWM_SMPS_CLK_FORCE_ON_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1020 MASTER LE NN 282704 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_MANUAL_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1021 MASTER LE NN 283049 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1022 MASTER LE NN 283041 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1023 MASTER LE NN 282809 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_RANGE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1024 MASTER LE NN 282480 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1025 MASTER LE NN 283042 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1026 MASTER LE NN 283040 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1027 MASTER LE NN 283048 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1028 MASTER LE NN 282816 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_VOLT_CFG_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1029 MASTER LE NN 283044 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1030 MASTER LE II 282179 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1031 MASTER LE II 282164 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1032 MASTER LE II 283079 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1033 MASTER LE NN 282180 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1034 MASTER LE NN 282171 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1035 MASTER LE NN 282169 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1036 MASTER LE NN 282159 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor16_reg (M31_1P5V6T_SFFRBQX1)
 Chain[1] 1037 MASTER LE NN 282668 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1038 MASTER LE NN 282683 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1039 MASTER LE NN 282814 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_FORCE_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1040 MASTER LE NN 282815 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_OUT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1041 MASTER LE NN 282828 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CAP_CFG_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1042 MASTER LE NN 282831 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_LP_CFG_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1043 MASTER LE NN 282829 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CURRENT_CFG_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1044 MASTER LE II 282178 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1045 MASTER LE II 282830 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CURRENT_CFG_reg
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1046 MASTER LE II 282672 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1047 MASTER LE II 282833 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_NOTCH_CFG_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1048 MASTER LE II 282671 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1049 MASTER LE II 282670 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1050 MASTER LE II 282827 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CAP_CFG_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1051 MASTER LE II 282673 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1052 MASTER LE II 282994 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1053 MASTER LE II 282658 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1054 MASTER LE II 282659 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1055 MASTER LE II 282457 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1056 MASTER LE II 282660 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1057 MASTER LE II 282998 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1058 MASTER LE II 282458 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1059 MASTER LE II 282997 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1060 MASTER LE II 282996 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1061 MASTER LE II 282832 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_NOTCH_CFG_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1062 MASTER LE II 282782 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__DUTY_GEN_SI_CURRENT_REDUCTION_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1063 MASTER LE II 282765 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1064 MASTER LE II 282766 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1065 MASTER LE II 282775 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1066 MASTER LE II 282769 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__DACREF_HYST_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1067 MASTER LE II 282779 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__CAL_FLT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1068 MASTER LE II 282773 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1069 MASTER LE II 282288 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_comp_fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1070 MASTER LE II 282995 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1071 MASTER LE II 282461 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1072 MASTER LE II 282460 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__RETENTION_QUAL_rifi_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1073 MASTER LE II 282705 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_POLARITY_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1074 MASTER LE II 282645 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1075 MASTER LE II 282644 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1076 MASTER LE II 282943 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1077 MASTER LE II 282761 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1078 MASTER LE II 282944 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1079 MASTER LE II 282605 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__MODE_STATE_rifi_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1080 MASTER LE II 282764 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1081 MASTER LE II 282774 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1082 MASTER LE II 282826 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_INT_CFG__DUTY_GEN_INT_CAP_CFG_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1083 MASTER LE II 282825 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_INT_CFG__DUTY_GEN_INT_CAP_CFG_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1084 MASTER LE II 282980 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_M1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1085 MASTER LE II 282746 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPDOWN_READY_CTL__VOUT_EQ_VREF_WAIT_BYPASS_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1086 MASTER LE II 282767 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1087 MASTER LE II 282639 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1088 MASTER LE II 282784 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__DETACH_VREG_READY_CHAIN_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1089 MASTER LE II 282771 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1090 MASTER LE II 282987 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1091 MASTER LE II 282783 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__TRAP_GEN_SI_CURRENT_REDUCTION_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1092 MASTER LE II 282723 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1093 MASTER LE II 282721 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1094 MASTER LE II 282720 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1095 MASTER LE II 282735 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CTL__MULTIPHASE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
 Chain[1] 1096 MASTER LE II 282858 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1097 MASTER LE II 282984 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1098 MASTER LE II 282641 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1099 MASTER LE II 282640 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1100 MASTER LE II 282722 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1101 MASTER LE II 282625 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1102 MASTER LE II 282634 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1103 MASTER LE II 282638 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1104 MASTER LE II 282628 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1105 MASTER LE II 282629 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL2__GANG_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1106 MASTER LE II 282631 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1107 MASTER LE II 282632 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1108 MASTER LE II 282630 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1109 MASTER LE II 282635 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1110 MASTER LE II 282636 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1111 MASTER LE II 282633 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1112 MASTER LE II 282275 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1113 MASTER LE II 282525 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_sync_3p0_trimout_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1114 MASTER LE II 282534 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/u_
slib_sync_3p0_trim_cal_act_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1115 MASTER LE II 282527 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_sync_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1116 MASTER LE II 282526 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_sync_3p0_trimout_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1117 MASTER LE II 282272 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1118 MASTER LE II 282276 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1119 MASTER LE II 282277 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_en_meas_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1120 MASTER LE II 282236 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1121 MASTER LE II 282286 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1122 MASTER LE II 282287 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1123 MASTER LE II 282237 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1124 MASTER LE II 282274 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1125 MASTER LE II 282273 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1126 MASTER LE II 282279 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1127 MASTER LE II 282278 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1128 MASTER LE II 282535 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/u_
slib_sync_3p0_trim_cal_act_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1129 MASTER LE II 282529 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_en_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1130 MASTER LE II 282619 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_en_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1131 MASTER LE II 282530 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1132 MASTER LE II 282528 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1133 MASTER LE II 282596 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/d_ocp_perph_en_master_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1134 MASTER LE II 282859 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1135 MASTER LE II 282983 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1136 MASTER LE II 282863 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1137 MASTER LE II 282763 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1138 MASTER LE II 282768 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1139 MASTER LE II 282770 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__DACREF_HYST_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1140 MASTER LE II 282762 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1141 MASTER LE II 282772 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1142 MASTER LE II 282853 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_PS_DLY_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1143 MASTER LE II 282776 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1144 MASTER LE II 282778 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__VREG_MON_CFG_RM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1145 MASTER LE II 282999 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1146 MASTER LE II 282269 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_int_soft_start_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1147 MASTER LE II 282667 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1148 MASTER LE II 282686 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_SPARE_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1149 MASTER LE II 282687 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_SPARE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1150 MASTER LE II 282669 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1151 MASTER LE II 282666 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1152 MASTER LE II 282167 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1153 MASTER LE II 282176 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp5_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1154 MASTER LE II 282157 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1155 MASTER LE II 282648 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1156 MASTER LE II 282651 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1157 MASTER LE II 282650 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1158 MASTER LE II 282655 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1159 MASTER LE II 282646 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1160 MASTER LE II 282684 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1161 MASTER LE II 282661 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1162 MASTER LE II 282663 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1163 MASTER LE II 282656 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1164 MASTER LE II 282662 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1165 MASTER LE II 282665 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1166 MASTER LE II 282664 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1167 MASTER LE II 282657 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1168 MASTER LE II 282653 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1169 MASTER LE II 282654 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1170 MASTER LE II 282652 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1171 MASTER LE II 282649 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1172 MASTER LE II 282647 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1173 MASTER LE II 282158 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1174 MASTER LE II 282168 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1175 MASTER LE II 282162 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1176 MASTER LE II 282160 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1177 MASTER LE II 282163 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1178 MASTER LE II 282161 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1179 MASTER LE II 282165 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1180 MASTER LE II 282355 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1181 MASTER LE II 282359 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1182 MASTER LE II 282361 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1183 MASTER LE II 282414 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_STEPPER_DONE_d
_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1184 MASTER LE II 282363 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1185 MASTER LE II 282362 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1186 MASTER LE II 282891 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_slib_sync/sy
nc_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1187 MASTER LE II 282498 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_foldback_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1188 MASTER LE II 282499 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_npm_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1189 MASTER LE II 282603 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_power_boost_en_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 1190 MASTER LE II 283025 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1191 MASTER LE II 282459 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__PS_TRUE_rifi_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1192 MASTER LE II 282852 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_PS_DLY_reg/dout_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1193 MASTER LE II 282855 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_REFSAMPLE_TIMER_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1194 MASTER LE II 282854 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_REFSAMPLE_TIMER_reg/do
ut_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1195 MASTER LE II 282719 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1196 MASTER LE II 282903 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_slib_sync/sync_d
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1197 MASTER LE II 282856 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__DIS_RETENTION_MODE_DLY_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1198 MASTER LE II 282851 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_2__POWER_BOOST_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1199 MASTER LE II 282890 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_slib_sync/sy
nc_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1200 MASTER LE II 282899 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1201 MASTER LE II 282900 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1202 MASTER LE II 282904 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_slib_sync/sync_d
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1203 MASTER LE II 282595 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_npm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1204 MASTER LE II 282447 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_mask_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1205 MASTER LE II 282464 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_stepper_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1206 MASTER LE II 282249 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_rpm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1207 MASTER LE II 282902 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1208 MASTER LE II 282901 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1209 MASTER LE II 282892 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_slib_sync
/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1210 MASTER LE II 282896 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1211 MASTER LE II 282898 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 1212 MASTER LE II 283024 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1213 MASTER LE II 282532 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_clkreq_gate_3p0_clk_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1214 MASTER LE II 282897 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[1] 1215 MASTER LE II 282248 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_rpm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1216 MASTER LE II 282594 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_npm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1217 MASTER LE II 282536 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_cal_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1218 MASTER LE II 282308 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_lfrc_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1219 MASTER LE II 282885 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 1220 MASTER LE II 282889 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1221 MASTER LE II 282309 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_lfrc_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1222 MASTER LE II 282244 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_19p2_req_synchro_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1223 MASTER LE II 282270 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_lfrc_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1224 MASTER LE II 282465 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_stepper_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1225 MASTER LE II 282448 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_mask_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1226 MASTER LE II 282346 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1227 MASTER LE II 282347 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1228 MASTER LE II 282348 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1229 MASTER LE II 282271 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_lfrc_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1230 MASTER LE II 282537 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_cal_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1231 MASTER LE II 282492 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1232 MASTER LE II 282245 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_19p2_req_synchro_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1233 MASTER LE II 282291 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_clk_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1234 MASTER LE II 282888 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1235 MASTER LE II 282883 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/sync_u0/sync_d_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1236 MASTER LE II 282289 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1237 MASTER LE II 282533 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_sync_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1238 MASTER LE II 282290 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1239 MASTER LE II 282884 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/sync_u0/sync_d_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1240 MASTER LE II 282887 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1241 MASTER LE II 282886 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1242 MASTER LE II 282292 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_clk_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1243 MASTER LE II 282493 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1244 MASTER LE II 282494 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1245 MASTER LE II 282495 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1246 MASTER LE II 282496 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1247 MASTER LE II 282497 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1248 MASTER LE II 282408 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1249 MASTER LE II 282409 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1250 MASTER LE II 282456 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_mode_update_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1251 MASTER LE II 282243 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_ps_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1252 MASTER LE II 282433 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_timer_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1253 MASTER LE II 282242 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_ps_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1254 MASTER LE II 282345 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1255 MASTER LE II 282893 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_slib_sync
/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1256 MASTER LE II 282428 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_timer1_exp_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1257 MASTER LE II 282350 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1258 MASTER LE II 282483 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_clk_lfrc_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1259 MASTER LE II 282481 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_buck_en_ret_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1260 MASTER LE II 282468 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_npm_lpm_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1261 MASTER LE II 282501 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_6_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1262 MASTER LE II 282491 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_clk_19p2_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1263 MASTER LE II 282486 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_smps_clk_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1264 MASTER LE II 282482 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_refen_to_bckcmn_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1265 MASTER LE II 282467 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_mask_pwmcmp_inwarmup_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1266 MASTER LE II 282351 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_master_
en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1267 MASTER LE II 282352 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_master_
en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1268 MASTER LE II 282463 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_bypass_
en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1269 MASTER LE II 282413 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1270 MASTER LE II 282209 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1271 MASTER LE II 282356 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1272 MASTER LE II 282360 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1273 MASTER LE II 282206 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1274 MASTER LE II 283078 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1275 MASTER LE II 282201 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1276 MASTER LE II 282425 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1277 MASTER LE II 282421 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1278 MASTER LE II 282420 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1279 MASTER LE II 282422 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1280 MASTER LE II 282424 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1281 MASTER LE II 282426 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1282 MASTER LE II 282268 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1283 MASTER LE II 282207 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1284 MASTER LE II 282423 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1285 MASTER LE II 282204 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1286 MASTER LE II 282202 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1287 MASTER LE II 282205 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1288 MASTER LE II 282358 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1289 MASTER LE II 282208 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1290 MASTER LE II 282895 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1291 MASTER LE II 282894 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1292 MASTER LE II 282203 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1293 MASTER LE II 282357 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1294 MASTER LE II 282364 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1295 MASTER LE II 282411 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_setpoint_eq_vset_delay_reg (M31_1P5V6T_SFFRBQX1)
 Chain[1] 1296 MASTER LE II 282410 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_setpoint_gt_vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1297 MASTER LE II 282210 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1298 MASTER LE II 282416 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1299 MASTER LE II 282417 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1300 MASTER LE II 282399 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1301 MASTER LE II 282400 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1302 MASTER LE II 282397 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ctrl_fsm_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1303 MASTER LE II 282618 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ctrl_fsm_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1304 MASTER LE II 282412 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1305 MASTER LE II 282401 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1306 MASTER LE II 282393 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1307 MASTER LE II 282354 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
clk_req_u/d_clk_req_stepper_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1308 MASTER LE II 282353 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
clk_req_u/d_clk_req_stepper_meta_reg (M31_1P5V6T_SFFRBQX1)
 Chain[1] 1309 MASTER LE II 282462 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_bypass_
en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1310 MASTER LE II 282502 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_1_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1311 MASTER LE II 282484 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_vreg_comp_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1312 MASTER LE II 282469 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_en_tx_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1313 MASTER LE II 282503 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1314 MASTER LE II 282485 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_smps_clk_buf_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1315 MASTER LE II 282396 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/slib_clkreq_gate_1p0_hf_clk_u1
/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1316 MASTER LE II 282402 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1317 MASTER LE II 282600 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_disable_awake_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 1318 MASTER LE II 282192 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ps_fsm_reg (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1319 MASTER LE II 282602 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_enable_toggle_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 1320 MASTER LE II 282599 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_fsm_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 1321 MASTER LE II 282394 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1322 MASTER LE II 283053 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_curr_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1323 MASTER LE II 282379 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_fsm_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1324 MASTER LE II 282385 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1325 MASTER LE II 282386 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1326 MASTER LE II 282319 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1327 MASTER LE II 282390 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_force_wake_ps_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1328 MASTER LE II 282318 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1329 MASTER LE II 282392 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1330 MASTER LE II 282617 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1331 MASTER LE II 282500 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_7_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1332 MASTER LE II 282450 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1333 MASTER LE II 282449 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1334 MASTER LE II 282452 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1335 MASTER LE II 282451 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1336 MASTER LE II 282454 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_fsm_mask_en_d2_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1337 MASTER LE II 282446 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_update_mask_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1338 MASTER LE II 282453 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_fsm_mask_en_d1_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1339 MASTER LE II 282317 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_u1/cl
k_en_sync_reg (M31_1P5V6T_SFFRBQX1)
 Chain[1] 1340 MASTER LE II 282378 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_refdac_sample_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1341 MASTER LE II 282616 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_a2d_comp_out_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1342 MASTER LE II 282431 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1343 MASTER LE II 282432 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1344 MASTER LE II 282427 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1345 MASTER LE II 282349 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_update_fsm_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1346 MASTER LE II 282430 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_timer0_exp_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1347 MASTER LE II 282405 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1348 MASTER LE II 282407 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1349 MASTER LE II 282406 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1350 MASTER LE II 282434 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_timer_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1351 MASTER LE II 282455 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_mode_update_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1352 MASTER LE II 282404 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_
qual_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1353 MASTER LE II 283054 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_glue_u/d_refdac_sample_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1354 MASTER LE II 282365 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_
u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1355 MASTER LE II 283050 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_sync1_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 1356 MASTER LE II 282624 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_capture1_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 1357 MASTER LE II 282384 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1358 MASTER LE II 283055 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1359 MASTER LE II 282382 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1360 MASTER LE II 283056 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1361 MASTER LE II 282367 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1362 MASTER LE II 283057 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1363 MASTER LE II 282370 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1364 MASTER LE II 282429 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1365 MASTER LE II 282445 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1366 MASTER LE II 282439 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1367 MASTER LE II 282438 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1368 MASTER LE II 282437 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1369 MASTER LE II 282369 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1370 MASTER LE II 282435 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1371 MASTER LE II 282373 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_1st_window_pulse_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1372 MASTER LE II 282372 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1373 MASTER LE II 282443 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1374 MASTER LE II 282442 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1375 MASTER LE II 282444 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1376 MASTER LE II 282440 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1377 MASTER LE II 282441 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1378 MASTER LE II 282371 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1379 MASTER LE II 282366 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1380 MASTER LE II 282375 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_glue_u/d_refdac_smpl_counter_high_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1381 MASTER LE II 282380 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_refd
ac_smpl_clk_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1382 MASTER LE II 282381 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1383 MASTER LE II 282388 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1384 MASTER LE II 282389 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1385 MASTER LE II 282387 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1386 MASTER LE II 283052 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_curr_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1387 MASTER LE II 282395 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1388 MASTER LE II 282403 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1389 MASTER LE II 282398 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1390 MASTER LE II 282419 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1391 MASTER LE II 282418 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1392 MASTER LE II 282415 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1393 MASTER LE II 286254 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1394 MASTER LE II 286261 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1395 MASTER LE II 286263 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1396 MASTER LE II 286249 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp6_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1397 MASTER LE II 286247 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1398 MASTER LE II 286242 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp7_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1399 MASTER LE II 286243 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1400 MASTER LE II 286248 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp5_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1401 MASTER LE II 286244 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1402 MASTER LE II 286245 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1403 MASTER LE II 286246 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1404 MASTER LE II 286365 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1405 MASTER LE II 286366 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1406 MASTER LE II 286368 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1407 MASTER LE II 286367 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1408 MASTER LE II 286374 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1409 MASTER LE II 286372 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1410 MASTER LE II 286369 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1411 MASTER LE II 286370 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1412 MASTER LE II 286364 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1413 MASTER LE II 286361 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1414 MASTER LE II 286362 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1415 MASTER LE II 286432 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1416 MASTER LE II 286431 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_PRE_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1417 MASTER LE II 286428 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__RET_WAKE_FREQ_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1418 MASTER LE II 286371 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1419 MASTER LE II 286400 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1420 MASTER LE II 286408 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1421 MASTER LE II 286398 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1422 MASTER LE II 286406 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1423 MASTER LE II 286401 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 1424 MASTER LE II 286409 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1425 MASTER LE II 286407 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1426 MASTER LE II 286393 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1427 MASTER LE II 286426 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLH_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1428 MASTER LE II 286422 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__ZX_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1429 MASTER LE II 286411 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1430 MASTER LE II 286427 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLH_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1431 MASTER LE II 286420 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_PRE_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1432 MASTER LE II 286405 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1433 MASTER LE II 286404 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1434 MASTER LE II 286379 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1435 MASTER LE II 286403 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1436 MASTER LE II 286413 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1437 MASTER LE II 286377 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1438 MASTER LE II 286396 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1439 MASTER LE II 286392 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1440 MASTER LE II 286545 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1441 MASTER LE II 286553 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1442 MASTER LE II 286549 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1443 MASTER LE II 286551 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1444 MASTER LE II 286539 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1445 MASTER LE II 286547 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1446 MASTER LE II 286541 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1447 MASTER LE II 286285 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1448 MASTER LE II 286543 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1449 MASTER LE II 286382 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1450 MASTER LE II 286390 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1451 MASTER LE II 286394 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1452 MASTER LE II 286386 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1453 MASTER LE II 286388 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1454 MASTER LE II 286384 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1455 MASTER LE II 282436 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1456 MASTER LE II 282368 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1457 MASTER LE II 282383 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1458 MASTER LE II 286318 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_cal_act
ivity_en_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1459 MASTER LE II 286306 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_cal_act
ivity_en_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1460 MASTER LE II 286305 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_fb_latc
h_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1461 MASTER LE II 286307 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_l2r_trim_cal
_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1462 MASTER LE II 286380 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1463 MASTER LE II 286410 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1464 MASTER LE II 286421 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_PRE_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1465 MASTER LE II 286402 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1466 MASTER LE II 286395 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1467 MASTER LE II 286423 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__ZX_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1468 MASTER LE II 286399 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1469 MASTER LE II 286389 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1470 MASTER LE II 286391 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
 Chain[1] 1471 MASTER LE II 286419 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_3__FOLDBACK_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1472 MASTER LE II 286425 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1473 MASTER LE II 286424 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1474 MASTER LE II 286448 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_BLANK_TIME_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1475 MASTER LE II 286418 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_3__FOLDBACK_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1476 MASTER LE II 286363 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1477 MASTER LE II 286447 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_BLANK_TIME_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1478 MASTER LE II 286417 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1479 MASTER LE II 286387 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1480 MASTER LE II 286357 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1481 MASTER LE II 286358 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1482 MASTER LE II 286359 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_POLARITY_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1483 MASTER LE II 286304 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_comp
_fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1484 MASTER LE II 286412 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1485 MASTER LE II 286378 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1486 MASTER LE II 286535 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1487 MASTER LE II 286536 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1488 MASTER LE II 286542 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1489 MASTER LE II 286537 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1490 MASTER LE II 286544 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1491 MASTER LE II 286385 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1492 MASTER LE II 286414 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1493 MASTER LE II 286381 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1494 MASTER LE II 286324 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1495 MASTER LE II 286323 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1496 MASTER LE II 286322 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1497 MASTER LE II 286320 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1498 MASTER LE II 286321 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1499 MASTER LE II 286325 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1500 MASTER LE II 286327 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1501 MASTER LE II 286326 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1502 MASTER LE II 286534 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1503 MASTER LE II 286383 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1504 MASTER LE II 286397 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC3__SENSE_IDAC_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1505 MASTER LE II 286429 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__SS_SI_ENABLE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1506 MASTER LE II 286415 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1507 MASTER LE II 286355 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1508 MASTER LE II 286540 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1509 MASTER LE II 286297 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_comp_
fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1510 MASTER LE II 286430 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_PRE_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1511 MASTER LE II 286580 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1512 MASTER LE NN 286281 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1513 MASTER LE II 286282 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1514 MASTER LE II 286255 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1515 MASTER LE II 286260 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1516 MASTER LE II 286262 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1517 MASTER LE II 286253 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1518 MASTER LE II 286259 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1519 MASTER LE II 286252 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1520 MASTER LE II 286258 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1521 MASTER LE II 286251 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1522 MASTER LE II 286329 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1523 MASTER LE II 286332 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1524 MASTER LE II 286331 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1525 MASTER LE II 286336 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1526 MASTER LE II 286570 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1527 MASTER LE II 286435 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1528 MASTER LE II 286441 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1529 MASTER LE II 286445 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1530 MASTER LE II 286440 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1531 MASTER LE II 286446 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1532 MASTER LE II 286338 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1533 MASTER LE II 286334 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1534 MASTER LE II 286459 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__D_P_MIN_ON_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1535 MASTER LE II 286328 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1536 MASTER LE II 286376 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 1537 MASTER LE II 286375 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1538 MASTER LE II 286330 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1539 MASTER LE II 286458 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__N_MIN_ON_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1540 MASTER LE II 286457 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__N_MIN_ON_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1541 MASTER LE II 286373 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1542 MASTER LE II 286433 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1543 MASTER LE II 286550 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1544 MASTER LE II 286552 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1545 MASTER LE II 286434 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLH_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1546 MASTER LE II 286333 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1547 MASTER LE II 286456 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__P_MIN_ON_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1548 MASTER LE II 286339 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1549 MASTER LE II 286465 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1550 MASTER LE II 286464 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1551 MASTER LE II 286460 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__SKIP_ZX_CMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1552 MASTER LE II 286461 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__SKIP_CL_CMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1553 MASTER LE II 286560 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1554 MASTER LE NN 286277 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1555 MASTER LE NN 286455 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__P_MIN_ON_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1556 MASTER LE NN 286436 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1557 MASTER LE II 286279 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1558 MASTER LE II 286437 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1559 MASTER LE NN 286278 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1560 MASTER LE NN 286443 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1561 MASTER LE NN 286463 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1562 MASTER LE NN 286468 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1563 MASTER LE NN 286462 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1564 MASTER LE NN 286442 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1565 MASTER LE NN 286466 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1566 MASTER LE NN 286485 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP1_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1567 MASTER LE NN 286451 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_SEL_DLY_CTRL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1568 MASTER LE NN 286356 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1569 MASTER LE NN 286416 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1570 MASTER LE NN 286453 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_SEL_DLY_CTRL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1571 MASTER LE NN 286449 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_BLANK_TIME_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1572 MASTER LE NN 286452 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_SEL_DLY_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1573 MASTER LE NN 286603 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1574 MASTER LE NN 286360 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_MANUAL_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1575 MASTER LE NN 286454 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_SEL_DLY_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1576 MASTER LE NN 286546 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1577 MASTER LE NN 286548 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1578 MASTER LE NN 286538 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1579 MASTER LE NN 286504 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1580 MASTER LE NN 286507 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1581 MASTER LE NN 286503 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1582 MASTER LE NN 286511 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1583 MASTER LE NN 286510 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1584 MASTER LE NN 286528 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1585 MASTER LE NN 286515 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1586 MASTER LE NN 286531 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1587 MASTER LE NN 286533 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1588 MASTER LE NN 286530 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1589 MASTER LE NN 286532 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1590 MASTER LE NN 286529 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1591 MASTER LE NN 286345 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1592 MASTER LE NN 286353 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1593 MASTER LE NN 286352 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1594 MASTER LE NN 286354 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1595 MASTER LE NN 286347 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL2__GANG_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1596 MASTER LE NN 286343 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1597 MASTER LE NN 286349 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1598 MASTER LE NN 286348 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1599 MASTER LE NN 286341 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1600 MASTER LE NN 286342 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1601 MASTER LE NN 286298 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1602 MASTER LE NN 286287 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1603 MASTER LE NN 286283 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1604 MASTER LE NN 286284 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1605 MASTER LE NN 286303 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1606 MASTER LE NN 286295 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1607 MASTER LE NN 286294 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1608 MASTER LE NN 286293 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1609 MASTER LE NN 286292 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1610 MASTER LE NN 286291 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1611 MASTER LE NN 286299 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1612 MASTER LE NN 286296 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1613 MASTER LE NN 286301 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1614 MASTER LE NN 286288 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1615 MASTER LE NN 286286 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1616 MASTER LE NN 286300 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1617 MASTER LE NN 286302 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1618 MASTER LE NN 286319 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1619 MASTER LE NN 286350 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1620 MASTER LE NN 286351 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1621 MASTER LE NN 286346 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1622 MASTER LE NN 286508 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1623 MASTER LE NN 286506 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1624 MASTER LE NN 286505 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1625 MASTER LE NN 286509 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1626 MASTER LE NN 286340 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1627 MASTER LE NN 286344 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1628 MASTER LE NN 286467 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1629 MASTER LE NN 286444 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1630 MASTER LE NN 286450 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_BLANK_TIME_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1631 MASTER LE NN 286558 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1632 MASTER LE NN 286559 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1633 MASTER LE NN 286335 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1634 MASTER LE NN 286337 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1635 MASTER LE NN 286257 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1636 MASTER LE NN 286256 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1637 MASTER LE NN 286439 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1638 MASTER LE II 286280 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1639 MASTER LE II 286579 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1640 MASTER LE II 286576 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1641 MASTER LE II 286568 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1642 MASTER LE II 286578 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1643 MASTER LE II 286577 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1644 MASTER LE II 286573 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1645 MASTER LE II 286566 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1646 MASTER LE II 286575 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1647 MASTER LE II 286571 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 1648 MASTER LE II 286565 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1649 MASTER LE II 286556 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1650 MASTER LE II 286554 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1651 MASTER LE II 286491 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__CL_TSTMD_MUX_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1652 MASTER LE II 286490 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__P_REF1_RATIO_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1653 MASTER LE II 286557 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1654 MASTER LE II 286438 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1655 MASTER LE II 286484 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP1_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1656 MASTER LE II 286564 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1657 MASTER LE II 286483 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP2_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1658 MASTER LE II 286489 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__P_REF2_RATIO_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1659 MASTER LE II 286488 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP1_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1660 MASTER LE II 286482 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP2_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1661 MASTER LE II 286472 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1662 MASTER LE II 286477 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1663 MASTER LE II 286478 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1664 MASTER LE II 286470 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1665 MASTER LE II 286561 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1666 MASTER LE II 286473 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1667 MASTER LE II 286469 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1668 MASTER LE II 286479 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1669 MASTER LE II 286475 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1670 MASTER LE II 286474 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1671 MASTER LE II 286486 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP2_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1672 MASTER LE II 286480 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP3_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1673 MASTER LE II 286487 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP2_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1674 MASTER LE II 286476 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1675 MASTER LE II 286481 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP3_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1676 MASTER LE II 286492 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1677 MASTER LE II 286516 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
 Chain[1] 1678 MASTER LE II 286517 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1679 MASTER LE II 286495 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1680 MASTER LE II 286497 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1681 MASTER LE II 286493 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1682 MASTER LE II 286501 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1683 MASTER LE II 286512 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1684 MASTER LE II 286521 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1685 MASTER LE II 286518 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1686 MASTER LE II 286498 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1687 MASTER LE II 286500 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1688 MASTER LE II 286499 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1689 MASTER LE II 286502 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1690 MASTER LE II 286519 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1691 MASTER LE II 286514 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1692 MASTER LE II 286513 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1693 MASTER LE II 286525 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1694 MASTER LE II 286309 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1695 MASTER LE II 286290 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1696 MASTER LE II 286289 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1697 MASTER LE II 286314 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1698 MASTER LE II 286315 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1699 MASTER LE II 286312 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1700 MASTER LE II 286313 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1701 MASTER LE II 286308 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1702 MASTER LE II 286310 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1703 MASTER LE II 286311 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1704 MASTER LE II 286524 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1705 MASTER LE II 286520 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1706 MASTER LE II 286526 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1707 MASTER LE II 286527 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1708 MASTER LE II 286523 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1709 MASTER LE II 286522 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1710 MASTER LE II 286494 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1711 MASTER LE II 286496 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1712 MASTER LE II 286471 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1713 MASTER LE II 286562 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1714 MASTER LE II 286563 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1715 MASTER LE II 286555 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1716 MASTER LE NN 286276 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1717 MASTER LE NN 286574 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1718 MASTER LE NN 286572 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1719 MASTER LE NN 286567 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1720 MASTER LE NN 286569 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1721 MASTER LE NN 282604 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_glitchfree_mux_1p0_c
lk_qual_u/sel0_0_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 1722 MASTER LE NN 286250 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1723 MASTER LE NN 286123 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP1_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 257560 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX1)
Chain[1] 1724 MASTER LE NN 286130 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__CL_TSTMD_MUX_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1725 MASTER LE NN 286202 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1726 MASTER LE NN 286206 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1727 MASTER LE NN 286207 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1728 MASTER LE NN 285973 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1729 MASTER LE NN 286204 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1730 MASTER LE NN 286191 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1731 MASTER LE NN 286205 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1732 MASTER LE NN 286203 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1733 MASTER LE NN 286210 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1734 MASTER LE NN 286212 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1735 MASTER LE NN 286208 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1736 MASTER LE NN 286211 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1737 MASTER LE NN 286209 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1738 MASTER LE II 285914 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1739 MASTER LE II 286192 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1740 MASTER LE II 286193 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1741 MASTER LE II 286194 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1742 MASTER LE II 286136 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
 Chain[1] 1743 MASTER LE II 286133 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1744 MASTER LE II 286135 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1745 MASTER LE II 286132 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1746 MASTER LE II 286109 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1747 MASTER LE II 286124 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP1_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1748 MASTER LE II 286138 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1749 MASTER LE II 286141 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1750 MASTER LE II 286170 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1751 MASTER LE II 286169 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1752 MASTER LE II 286111 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1753 MASTER LE II 286110 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1754 MASTER LE II 286131 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1755 MASTER LE II 286134 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1756 MASTER LE II 286122 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP2_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1757 MASTER LE II 286121 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP2_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1758 MASTER LE II 285975 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1759 MASTER LE II 285974 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1760 MASTER LE II 286240 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1761 MASTER LE II 286186 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1762 MASTER LE II 285933 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1763 MASTER LE II 285952 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1764 MASTER LE II 285953 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1765 MASTER LE II 285951 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1766 MASTER LE II 285950 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1767 MASTER LE II 285949 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1768 MASTER LE II 285948 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1769 MASTER LE II 285946 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1770 MASTER LE II 285947 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1771 MASTER LE II 285931 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1772 MASTER LE II 285932 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1773 MASTER LE II 285929 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1774 MASTER LE II 285927 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1775 MASTER LE II 285930 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1776 MASTER LE II 285928 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1777 MASTER LE II 286184 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1778 MASTER LE II 286178 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1779 MASTER LE II 285983 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1780 MASTER LE II 286145 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1781 MASTER LE II 286146 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1782 MASTER LE II 286148 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1783 MASTER LE II 285982 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1784 MASTER LE II 286144 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1785 MASTER LE II 286093 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_SEL_DLY_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1786 MASTER LE NN 285915 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1787 MASTER LE NN 286196 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1788 MASTER LE NN 286100 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__SKIP_CL_CMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1789 MASTER LE NN 286074 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1790 MASTER LE NN 285970 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1791 MASTER LE NN 286080 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1792 MASTER LE NN 286098 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__D_P_MIN_ON_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1793 MASTER LE NN 285966 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1794 MASTER LE NN 286197 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1795 MASTER LE NN 286075 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1796 MASTER LE NN 285972 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1797 MASTER LE NN 286082 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1798 MASTER LE NN 286076 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1799 MASTER LE NN 286079 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1800 MASTER LE NN 285976 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1801 MASTER LE NN 286103 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1802 MASTER LE NN 286084 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1803 MASTER LE NN 286078 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1804 MASTER LE NN 285977 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1805 MASTER LE NN 286085 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1806 MASTER LE NN 286129 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__P_REF1_RATIO_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[1] 1807 MASTER LE NN 286126 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP2_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1808 MASTER LE NN 286172 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1809 MASTER LE NN 286171 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1810 MASTER LE NN 286112 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1811 MASTER LE NN 286118 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1812 MASTER LE NN 286137 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1813 MASTER LE II 285916 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1814 MASTER LE II 286104 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1815 MASTER LE NN 285917 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1816 MASTER LE NN 286195 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1817 MASTER LE NN 286201 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1818 MASTER LE NN 286077 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1819 MASTER LE NN 286128 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__P_REF2_RATIO_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1820 MASTER LE NN 286127 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP1_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1821 MASTER LE NN 286198 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1822 MASTER LE NN 286119 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP3_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1823 MASTER LE NN 286199 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1824 MASTER LE NN 286108 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1825 MASTER LE NN 286107 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1826 MASTER LE NN 286102 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1827 MASTER LE NN 286101 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1828 MASTER LE NN 286200 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1829 MASTER LE NN 286083 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1830 MASTER LE NN 286081 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1831 MASTER LE NN 286105 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1832 MASTER LE NN 286106 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1833 MASTER LE NN 286120 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP3_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1834 MASTER LE NN 286115 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1835 MASTER LE NN 286139 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1836 MASTER LE NN 286113 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1837 MASTER LE NN 286114 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1838 MASTER LE NN 286125 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP2_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1839 MASTER LE NN 286116 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1840 MASTER LE NN 286117 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1841 MASTER LE NN 286142 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1842 MASTER LE NN 286140 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1843 MASTER LE NN 286163 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1844 MASTER LE NN 286165 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1845 MASTER LE NN 286159 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1846 MASTER LE NN 286162 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1847 MASTER LE NN 286166 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1848 MASTER LE NN 286164 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1849 MASTER LE NN 286161 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1850 MASTER LE NN 286160 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1851 MASTER LE NN 286153 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1852 MASTER LE NN 286157 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1853 MASTER LE NN 286158 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1854 MASTER LE NN 286154 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1855 MASTER LE NN 286152 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
 Chain[1] 1856 MASTER LE NN 286167 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1857 MASTER LE NN 286168 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1858 MASTER LE NN 286150 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1859 MASTER LE NN 286151 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1860 MASTER LE NN 286156 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1861 MASTER LE NN 286143 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1862 MASTER LE NN 286149 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1863 MASTER LE NN 286147 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1864 MASTER LE NN 286155 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1865 MASTER LE NN 285993 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1866 MASTER LE NN 285984 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1867 MASTER LE NN 285991 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1868 MASTER LE NN 285992 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1869 MASTER LE NN 285957 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1870 MASTER LE NN 286177 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1871 MASTER LE NN 285978 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1872 MASTER LE NN 286089 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_BLANK_TIME_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1873 MASTER LE NN 286183 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1874 MASTER LE NN 286215 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1875 MASTER LE NN 286213 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1876 MASTER LE NN 286095 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__P_MIN_ON_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1877 MASTER LE II 285918 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1878 MASTER LE II 285967 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1879 MASTER LE II 285968 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1880 MASTER LE II 285971 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1881 MASTER LE II 286241 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1882 MASTER LE II 286190 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1883 MASTER LE II 286188 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1884 MASTER LE II 286027 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1885 MASTER LE II 286025 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1886 MASTER LE II 286029 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1887 MASTER LE II 286035 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1888 MASTER LE II 286033 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[6] (M31_1P5V6T_SFFSRBQX1)
 Chain[1] 1889 MASTER LE II 285925 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1890 MASTER LE II 286031 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1891 MASTER LE II 285923 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1892 MASTER LE II 285936 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1893 MASTER LE II 285921 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1894 MASTER LE II 285940 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1895 MASTER LE II 285934 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1896 MASTER LE II 285937 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1897 MASTER LE II 285941 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1898 MASTER LE II 285939 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1899 MASTER LE II 285922 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1900 MASTER LE II 285924 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1901 MASTER LE II 285926 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1902 MASTER LE II 285938 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1903 MASTER LE II 286023 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1904 MASTER LE II 286021 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1905 MASTER LE II 286181 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1906 MASTER LE II 285958 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 1907 MASTER LE II 285959 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1908 MASTER LE II 285963 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1909 MASTER LE II 285965 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1910 MASTER LE II 285962 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1911 MASTER LE II 286051 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1912 MASTER LE II 286024 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1913 MASTER LE II 286020 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1914 MASTER LE II 285997 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1915 MASTER LE II 285998 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_POLARITY_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1916 MASTER LE II 286064 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1917 MASTER LE II 286062 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__ZX_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1918 MASTER LE II 286065 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLH_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1919 MASTER LE II 286066 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLH_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1920 MASTER LE II 286030 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1921 MASTER LE II 285935 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_comp_
fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1922 MASTER LE II 286002 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1923 MASTER LE II 286087 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_BLANK_TIME_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1924 MASTER LE II 286086 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_BLANK_TIME_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1925 MASTER LE II 286003 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1926 MASTER LE II 286001 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1927 MASTER LE II 286067 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__RET_WAKE_FREQ_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1928 MASTER LE II 286070 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_PRE_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1929 MASTER LE NN 285920 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1930 MASTER LE NN 286071 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1931 MASTER LE NN 286069 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_PRE_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1932 MASTER LE NN 286217 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1933 MASTER LE II 285919 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 1934 MASTER LE II 286073 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLH_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1935 MASTER LE II 286094 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__P_MIN_ON_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1936 MASTER LE II 286096 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__N_MIN_ON_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1937 MASTER LE II 285969 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1938 MASTER LE II 286099 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__SKIP_ZX_CMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1939 MASTER LE II 286097 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__N_MIN_ON_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1940 MASTER LE II 286185 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1941 MASTER LE II 286214 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1942 MASTER LE II 286179 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1943 MASTER LE II 286216 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1944 MASTER LE II 286010 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1945 MASTER LE II 286189 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1946 MASTER LE II 286072 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1947 MASTER LE II 286187 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1948 MASTER LE II 286182 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1949 MASTER LE II 286055 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1950 MASTER LE II 286088 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_BLANK_TIME_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1951 MASTER LE II 286000 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1952 MASTER LE II 286008 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1953 MASTER LE II 285985 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1954 MASTER LE II 286092 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_SEL_DLY_CTRL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1955 MASTER LE II 286091 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_SEL_DLY_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1956 MASTER LE II 286090 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_SEL_DLY_CTRL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1957 MASTER LE II 286176 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1958 MASTER LE II 286180 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1959 MASTER LE II 286175 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1960 MASTER LE II 285999 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_MANUAL_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1961 MASTER LE II 286068 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__SS_SI_ENABLE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1962 MASTER LE II 286053 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1963 MASTER LE II 286054 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1964 MASTER LE II 286056 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1965 MASTER LE II 286022 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1966 MASTER LE II 286036 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC3__SENSE_IDAC_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1967 MASTER LE II 286026 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1968 MASTER LE II 285995 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1969 MASTER LE II 285996 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1970 MASTER LE II 286028 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1971 MASTER LE II 285942 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_comp
_fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 1972 MASTER LE II 285994 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1973 MASTER LE II 286018 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1974 MASTER LE II 286174 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1975 MASTER LE II 286017 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1976 MASTER LE II 286173 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1977 MASTER LE II 285961 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1978 MASTER LE II 285986 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL2__GANG_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 1979 MASTER LE II 285990 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1980 MASTER LE II 285989 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1981 MASTER LE II 285987 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1982 MASTER LE II 285988 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1983 MASTER LE II 285979 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1984 MASTER LE II 285980 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1985 MASTER LE II 285981 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1986 MASTER LE II 285960 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1987 MASTER LE II 285964 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1988 MASTER LE II 286016 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1989 MASTER LE II 286052 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1990 MASTER LE II 286019 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1991 MASTER LE II 286049 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1992 MASTER LE II 286042 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1993 MASTER LE II 286034 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1994 MASTER LE II 286032 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 1995 MASTER LE II 286063 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1996 MASTER LE II 286058 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_3__FOLDBACK_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 1997 MASTER LE II 286057 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_3__FOLDBACK_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 1998 MASTER LE II 286012 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 1999 MASTER LE II 286007 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2000 MASTER LE II 286004 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2001 MASTER LE II 286005 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2002 MASTER LE II 282149 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2003 MASTER LE II 281471 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2004 MASTER LE II 281469 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2005 MASTER LE II 281473 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2006 MASTER LE II 281470 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2007 MASTER LE II 285893 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2008 MASTER LE II 285886 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp5_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2009 MASTER LE II 281453 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2010 MASTER LE II 281452 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2011 MASTER LE II 281466 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2012 MASTER LE II 281456 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2013 MASTER LE II 282122 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_curr_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2014 MASTER LE II 282123 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_curr_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2015 MASTER LE II 281465 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2016 MASTER LE II 281670 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_fsm_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 2017 MASTER LE II 281468 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ctrl_fsm_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2018 MASTER LE II 281689 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ctrl_fsm_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2019 MASTER LE II 281460 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2020 MASTER LE II 281688 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2021 MASTER LE II 281390 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2022 MASTER LE II 281459 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2023 MASTER LE II 281490 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2024 MASTER LE II 281496 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2025 MASTER LE II 281485 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2026 MASTER LE II 281687 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_a2d_comp_out_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2027 MASTER LE II 281673 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_enable_toggle_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 2028 MASTER LE II 281264 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ps_fsm_reg (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2029 MASTER LE II 281671 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_disable_awake_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 2030 MASTER LE II 281449 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_refdac_sample_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2031 MASTER LE II 281451 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_refd
ac_smpl_clk_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2032 MASTER LE II 282125 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2033 MASTER LE II 281438 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2034 MASTER LE II 281440 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2035 MASTER LE II 281439 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2036 MASTER LE II 282127 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2037 MASTER LE II 282126 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2038 MASTER LE II 282120 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_sync1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2039 MASTER LE II 281461 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_force_wake_ps_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2040 MASTER LE II 281695 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_capture1_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 2041 MASTER LE II 281450 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_fsm_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2042 MASTER LE II 281455 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2043 MASTER LE II 281454 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2044 MASTER LE II 285891 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2045 MASTER LE II 285887 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp6_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2046 MASTER LE II 285889 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2047 MASTER LE II 285888 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2048 MASTER LE II 285900 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2049 MASTER LE II 285881 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2050 MASTER LE II 285885 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2051 MASTER LE II 285880 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp7_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2052 MASTER LE II 285882 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2053 MASTER LE II 285883 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2054 MASTER LE II 285896 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2055 MASTER LE II 285884 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2056 MASTER LE II 285897 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2057 MASTER LE II 285894 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2058 MASTER LE II 285899 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2059 MASTER LE II 285892 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2060 MASTER LE II 285898 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2061 MASTER LE II 285895 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2062 MASTER LE II 286011 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 2063 MASTER LE II 285890 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2064 MASTER LE II 286006 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2065 MASTER LE II 286009 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2066 MASTER LE II 286015 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2067 MASTER LE II 286014 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2068 MASTER LE II 286013 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2069 MASTER LE II 286038 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2070 MASTER LE II 286041 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2071 MASTER LE II 286061 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__ZX_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2072 MASTER LE II 286046 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2073 MASTER LE II 286060 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_PRE_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2074 MASTER LE II 286059 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_PRE_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2075 MASTER LE II 286044 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2076 MASTER LE II 286043 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2077 MASTER LE II 286039 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2078 MASTER LE II 286047 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2079 MASTER LE II 286050 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2080 MASTER LE II 286037 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2081 MASTER LE II 286045 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2082 MASTER LE II 286040 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2083 MASTER LE II 286048 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2084 MASTER LE II 285956 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_cal_act
ivity_en_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2085 MASTER LE II 285945 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_l2r_trim_cal
_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2086 MASTER LE II 285944 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_cal_act
ivity_en_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2087 MASTER LE II 285943 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_fb_latc
h_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2088 MASTER LE II 281475 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2089 MASTER LE II 281476 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2090 MASTER LE II 281478 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2091 MASTER LE II 281477 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2092 MASTER LE II 281479 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2093 MASTER LE II 281444 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_1st_window_pulse_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2094 MASTER LE II 281474 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_
qual_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2095 MASTER LE II 281446 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_glue_u/d_refdac_smpl_counter_high_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2096 MASTER LE II 282124 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_glue_u/d_refdac_sample_dly_reg (M31_1P5V6T_SFFRBQX1)
 Chain[1] 2097 MASTER LE II 281463 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2098 MASTER LE II 281489 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2099 MASTER LE II 281487 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2100 MASTER LE II 281488 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2101 MASTER LE II 281425 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
clk_req_u/d_clk_req_stepper_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2102 MASTER LE II 281437 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2103 MASTER LE II 281441 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2104 MASTER LE II 281442 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2105 MASTER LE II 281506 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2106 MASTER LE II 281508 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2107 MASTER LE II 281510 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2108 MASTER LE II 281507 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2109 MASTER LE II 281509 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2110 MASTER LE II 281515 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2111 MASTER LE II 281500 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2112 MASTER LE II 281516 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2113 MASTER LE II 281511 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2114 MASTER LE II 281443 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2115 MASTER LE II 281436 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_
u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2116 MASTER LE II 281388 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_u1/cl
k_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2117 MASTER LE II 281467 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/slib_clkreq_gate_1p0_hf_clk_u1
/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2118 MASTER LE II 281389 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2119 MASTER LE II 281458 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2120 MASTER LE II 281457 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2121 MASTER LE II 281472 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2122 MASTER LE II 281464 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2123 MASTER LE II 281247 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1J)
Chain[1] 2124 MASTER LE II 281233 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2125 MASTER LE II 281234 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2126 MASTER LE II 281728 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2127 MASTER LE II 281724 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2128 MASTER LE II 281723 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2129 MASTER LE II 281431 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2130 MASTER LE II 281428 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2131 MASTER LE II 281429 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2132 MASTER LE II 281497 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2133 MASTER LE II 281492 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2134 MASTER LE II 281493 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2135 MASTER LE II 281494 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2136 MASTER LE II 281339 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2137 MASTER LE II 281964 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2138 MASTER LE II 281495 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2139 MASTER LE II 281275 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2140 MASTER LE II 281278 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2141 MASTER LE II 281965 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2142 MASTER LE II 281277 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2143 MASTER LE II 281274 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2144 MASTER LE II 281273 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2145 MASTER LE II 281491 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2146 MASTER LE II 281486 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2147 MASTER LE II 281480 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_setpoint_gt_vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2148 MASTER LE II 281280 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2149 MASTER LE II 281281 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2150 MASTER LE II 281276 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 2151 MASTER LE II 281430 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2152 MASTER LE II 281426 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2153 MASTER LE II 281427 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2154 MASTER LE II 281433 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2155 MASTER LE II 281232 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2156 MASTER LE II 281540 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_en_tx_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2157 MASTER LE II 281573 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_1_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2158 MASTER LE II 281279 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2159 MASTER LE II 281482 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2160 MASTER LE II 281435 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2161 MASTER LE II 281282 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2162 MASTER LE II 281481 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_setpoint_eq_vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2163 MASTER LE II 281424 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
clk_req_u/d_clk_req_stepper_meta_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2164 MASTER LE II 281512 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2165 MASTER LE II 281422 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_master_
en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2166 MASTER LE II 281533 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_bypass_
en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2167 MASTER LE II 281423 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_master_
en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2168 MASTER LE II 281534 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_bypass_
en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2169 MASTER LE II 281432 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2170 MASTER LE II 281434 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2171 MASTER LE II 281522 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2172 MASTER LE II 281484 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_STEPPER_DONE_d
_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2173 MASTER LE II 281538 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_mask_pwmcmp_inwarmup_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2174 MASTER LE II 281556 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_smps_clk_buf_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2175 MASTER LE II 281574 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2176 MASTER LE II 281571 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_7_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2177 MASTER LE II 281539 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_npm_lpm_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2178 MASTER LE II 281974 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_slib_sync/sync_d
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2179 MASTER LE II 281956 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2180 MASTER LE II 281319 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_rpm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2181 MASTER LE II 281554 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_clk_lfrc_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2182 MASTER LE II 281552 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_buck_en_ret_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2183 MASTER LE II 281520 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2184 MASTER LE II 281521 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2185 MASTER LE II 281523 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2186 MASTER LE II 281483 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2187 MASTER LE II 281525 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_fsm_mask_en_d2_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2188 MASTER LE II 281517 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_update_mask_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2189 MASTER LE II 281498 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2190 MASTER LE II 281524 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_fsm_mask_en_d1_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2191 MASTER LE II 281514 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2192 MASTER LE II 281513 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2193 MASTER LE II 281501 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_timer0_exp_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2194 MASTER LE II 281503 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2195 MASTER LE II 281313 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_ps_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2196 MASTER LE II 281314 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_ps_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2197 MASTER LE II 281527 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_mode_update_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2198 MASTER LE II 281526 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_mode_update_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2199 MASTER LE II 281499 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_timer1_exp_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2200 MASTER LE II 281502 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2201 MASTER LE II 281421 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2202 MASTER LE II 281963 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_slib_sync
/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2203 MASTER LE II 281420 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_update_fsm_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2204 MASTER LE II 281666 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_npm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2205 MASTER LE II 281416 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2206 MASTER LE II 281518 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_mask_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2207 MASTER LE II 281417 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2208 MASTER LE II 281504 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_timer_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2209 MASTER LE II 281505 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_timer_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2210 MASTER LE II 281568 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2211 MASTER LE II 281418 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2212 MASTER LE II 281419 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2213 MASTER LE II 281519 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_mask_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2214 MASTER LE II 281564 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2215 MASTER LE II 281563 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2216 MASTER LE II 281565 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2217 MASTER LE II 281315 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_19p2_req_synchro_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2218 MASTER LE II 281316 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_19p2_req_synchro_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2219 MASTER LE II 281566 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2220 MASTER LE II 281567 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2221 MASTER LE II 281536 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_stepper_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2222 MASTER LE II 281535 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_stepper_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2223 MASTER LE II 281320 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_rpm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2224 MASTER LE II 281665 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_npm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2225 MASTER LE II 281562 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_clk_19p2_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2226 MASTER LE II 281557 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_smps_clk_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2227 MASTER LE II 281570 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_npm_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2228 MASTER LE II 281572 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_6_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2229 MASTER LE II 281555 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_vreg_comp_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2230 MASTER LE II 281921 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_2__POWER_BOOST_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2231 MASTER LE II 281553 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_refen_to_bckcmn_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2232 MASTER LE II 281926 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__DIS_RETENTION_MODE_DLY_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2233 MASTER LE II 281925 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_REFSAMPLE_TIMER_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2234 MASTER LE II 281923 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_PS_DLY_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2235 MASTER LE II 281674 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_power_boost_en_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 2236 MASTER LE II 281236 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2237 MASTER LE II 281725 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2238 MASTER LE II 281727 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2239 MASTER LE II 281717 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2240 MASTER LE II 281726 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
 Chain[1] 2241 MASTER LE II 281720 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2242 MASTER LE II 281718 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2243 MASTER LE II 281230 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2244 MASTER LE II 282148 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2245 MASTER LE II 282094 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2246 MASTER LE II 281569 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_foldback_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2247 MASTER LE II 281924 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_REFSAMPLE_TIMER_reg/do
ut_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2248 MASTER LE II 281922 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_PS_DLY_reg/dout_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2249 MASTER LE II 281732 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2250 MASTER LE II 281736 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2251 MASTER LE II 281722 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2252 MASTER LE II 281721 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2253 MASTER LE II 281719 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2254 MASTER LE II 281225 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp5_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2255 MASTER LE II 281239 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2256 MASTER LE II 281231 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor16_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2257 MASTER LE II 281240 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2258 MASTER LE II 281238 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2259 MASTER LE NN 281251 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 2260 MASTER LE NN 281899 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CURRENT_CFG_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2261 MASTER LE NN 281898 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CAP_CFG_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2262 MASTER LE NN 281794 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2263 MASTER LE NN 281735 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2264 MASTER LE NN 281734 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2265 MASTER LE NN 281757 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_SPARE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2266 MASTER LE NN 281754 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2267 MASTER LE NN 281733 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2268 MASTER LE NN 281753 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2269 MASTER LE NN 281740 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2270 MASTER LE NN 281738 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2271 MASTER LE NN 281729 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
 Chain[1] 2272 MASTER LE NN 281739 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2273 MASTER LE NN 281902 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_NOTCH_CFG_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2274 MASTER LE NN 281737 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2275 MASTER LE NN 281340 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_int_soft_start_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2276 MASTER LE NN 281900 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CURRENT_CFG_reg
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2277 MASTER LE NN 281741 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2278 MASTER LE NN 281743 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2279 MASTER LE NN 281731 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2280 MASTER LE NN 281742 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2281 MASTER LE NN 282067 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2282 MASTER LE NN 281885 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_OUT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2283 MASTER LE NN 282012 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2284 MASTER LE NN 281834 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2285 MASTER LE NN 281715 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2286 MASTER LE NN 282068 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2287 MASTER LE NN 281903 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_NOTCH_CFG_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2288 MASTER LE NN 281528 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2289 MASTER LE NN 282065 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2290 MASTER LE NN 281848 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__VREG_MON_CFG_RM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2291 MASTER LE NN 281839 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__DACREF_HYST_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2292 MASTER LE NN 281849 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__CAL_FLT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2293 MASTER LE NN 281843 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2294 MASTER LE NN 281852 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__DUTY_GEN_SI_CURRENT_REDUCTION_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2295 MASTER LE NN 281531 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__RETENTION_QUAL_rifi_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2296 MASTER LE NN 281851 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__PWM_19P2M_CLK_FORCE_ON_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2297 MASTER LE NN 281845 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2298 MASTER LE NN 281805 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CTL__MULTIPHASE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2299 MASTER LE NN 281929 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2300 MASTER LE NN 281850 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__PWM_SMPS_CLK_FORCE_ON_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2301 MASTER LE NN 282013 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2302 MASTER LE NN 282014 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2303 MASTER LE NN 282050 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_M1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2304 MASTER LE NN 282057 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2305 MASTER LE NN 281603 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_clkreq_gate_3p0_clk_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2306 MASTER LE NN 281833 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2307 MASTER LE NN 282053 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2308 MASTER LE NN 281816 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPDOWN_READY_CTL__VOUT_EQ_VREF_WAIT_BYPASS_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2309 MASTER LE NN 282054 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2310 MASTER LE NN 281853 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__TRAP_GEN_SI_CURRENT_REDUCTION_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2311 MASTER LE NN 281835 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2312 MASTER LE NN 281609 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/d_vreg_ready_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2313 MASTER LE NN 281530 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__PS_TRUE_rifi_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2314 MASTER LE NN 281961 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_slib_sync/sy
nc_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2315 MASTER LE NN 281958 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
 Chain[1] 2316 MASTER LE NN 281607 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_cal_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2317 MASTER LE NN 281608 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_cal_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2318 MASTER LE NN 281341 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_lfrc_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2319 MASTER LE NN 281342 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_lfrc_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2320 MASTER LE NN 281363 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_clk_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2321 MASTER LE NN 281362 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_clk_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2322 MASTER LE NN 281380 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_lfrc_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2323 MASTER LE NN 281379 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_lfrc_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2324 MASTER LE NN 281347 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2325 MASTER LE NN 281346 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2326 MASTER LE NN 281605 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/u_
slib_sync_3p0_trim_cal_act_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2327 MASTER LE NN 281348 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_en_meas_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2328 MASTER LE NN 281360 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2329 MASTER LE NN 281361 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2330 MASTER LE NN 281349 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2331 MASTER LE NN 281343 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2332 MASTER LE NN 281604 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_sync_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2333 MASTER LE NN 281350 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2334 MASTER LE NN 281598 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_sync_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2335 MASTER LE NN 281597 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_sync_3p0_trimout_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2336 MASTER LE NN 281600 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_en_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2337 MASTER LE NN 281690 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_en_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2338 MASTER LE NN 281599 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2339 MASTER LE NN 281837 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2340 MASTER LE NN 281697 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2341 MASTER LE NN 281928 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2342 MASTER LE NN 281831 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2343 MASTER LE NN 281841 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2344 MASTER LE NN 281840 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__DACREF_HYST_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2345 MASTER LE NN 281854 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__DETACH_VREG_READY_CHAIN_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2346 MASTER LE NN 281838 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2347 MASTER LE NN 281832 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2348 MASTER LE NN 281842 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2349 MASTER LE NN 281667 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/d_ocp_perph_en_master_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2350 MASTER LE NN 281614 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/d_vreg_error_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2351 MASTER LE NN 281836 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2352 MASTER LE NN 281846 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2353 MASTER LE NN 281676 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__MODE_STATE_rifi_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2354 MASTER LE NN 281716 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2355 MASTER LE NN 282066 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2356 MASTER LE NN 281529 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2357 MASTER LE NN 282064 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2358 MASTER LE NN 281730 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2359 MASTER LE NN 281897 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CAP_CFG_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2360 MASTER LE NN 281744 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2361 MASTER LE NN 281884 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_FORCE_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2362 MASTER LE NN 282115 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2363 MASTER LE NN 282116 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2364 MASTER LE NN 282118 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2365 MASTER LE NN 281246 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1J)
Chain[1] 2366 MASTER LE II 281250 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 2367 MASTER LE II 282112 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2368 MASTER LE II 282117 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2369 MASTER LE II 281907 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2370 MASTER LE II 282113 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2371 MASTER LE II 281235 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2372 MASTER LE NN 281249 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[1] 2373 MASTER LE NN 282105 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2374 MASTER LE NN 281755 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2375 MASTER LE NN 282107 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2376 MASTER LE NN 281901 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_LP_CFG_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2377 MASTER LE NN 281886 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_VOLT_CFG_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2378 MASTER LE NN 282114 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2379 MASTER LE NN 281887 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_VOLT_CFG_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2380 MASTER LE NN 281551 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2381 MASTER LE NN 281752 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2382 MASTER LE NN 281908 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2383 MASTER LE NN 282099 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2384 MASTER LE NN 282100 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2385 MASTER LE NN 282101 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX2J)
Chain[1] 2386 MASTER LE NN 281778 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2387 MASTER LE NN 281779 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2388 MASTER LE NN 281770 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
3] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2389 MASTER LE NN 281761 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2390 MASTER LE NN 281776 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2391 MASTER LE NN 281880 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2392 MASTER LE NN 281883 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2393 MASTER LE NN 281881 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2394 MASTER LE NN 281882 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2395 MASTER LE NN 281879 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_RANGE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2396 MASTER LE NN 281844 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2397 MASTER LE NN 281532 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2398 MASTER LE NN 281359 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_comp_fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2399 MASTER LE NN 281795 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2400 MASTER LE NN 281713 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2401 MASTER LE NN 281714 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2402 MASTER LE NN 281895 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_INT_CFG__DUTY_GEN_INT_CAP_CFG_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2403 MASTER LE NN 281796 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2404 MASTER LE NN 281896 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_INT_CFG__DUTY_GEN_INT_CAP_CFG_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
 Chain[1] 2405 MASTER LE NN 281537 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2406 MASTER LE NN 282038 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2407 MASTER LE NN 281775 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_POLARITY_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2408 MASTER LE NN 282059 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2409 MASTER LE NN 282143 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2410 MASTER LE NN 281602 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
l2r_trim_cal_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2411 MASTER LE NN 281702 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2412 MASTER LE NN 281704 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2413 MASTER LE NN 282034 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2414 MASTER LE NN 281769 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
2] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2415 MASTER LE NN 282047 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2416 MASTER LE NN 281766 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2417 MASTER LE NN 281711 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2418 MASTER LE NN 281710 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2419 MASTER LE NN 281698 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2420 MASTER LE NN 281847 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__VREG_MON_CFG_NPM_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2421 MASTER LE NN 281712 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2422 MASTER LE NN 282011 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2423 MASTER LE NN 281927 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2424 MASTER LE NN 281932 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2425 MASTER LE NN 281931 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2426 MASTER LE NN 282015 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2427 MASTER LE NN 281771 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
4] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2428 MASTER LE NN 281935 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2429 MASTER LE NN 281696 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2430 MASTER LE NN 281700 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL2__GANG_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2431 MASTER LE NN 281705 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2432 MASTER LE NN 282023 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2433 MASTER LE NN 281699 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2434 MASTER LE NN 281780 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2435 MASTER LE NN 281708 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2436 MASTER LE NN 281773 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
6] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2437 MASTER LE NN 281772 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
5] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2438 MASTER LE NN 281382 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2439 MASTER LE NN 281596 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_sync_3p0_trimout_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2440 MASTER LE NN 281601 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2441 MASTER LE NN 281606 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/u_
slib_sync_3p0_trim_cal_act_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2442 MASTER LE NN 281345 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2443 MASTER LE NN 281344 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2444 MASTER LE NN 281356 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2445 MASTER LE NN 281355 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2446 MASTER LE NN 281352 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2447 MASTER LE NN 281377 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2448 MASTER LE NN 281351 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2449 MASTER LE NN 281353 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2450 MASTER LE NN 281354 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2451 MASTER LE NN 281357 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2452 MASTER LE NN 281358 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2453 MASTER LE NN 281308 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2454 MASTER LE NN 281307 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2455 MASTER LE NN 281709 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2456 MASTER LE NN 282052 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2457 MASTER LE NN 282055 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2458 MASTER LE NN 281959 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2459 MASTER LE NN 282029 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2460 MASTER LE NN 282051 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_M1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2461 MASTER LE NN 281957 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2462 MASTER LE NN 282056 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2463 MASTER LE NN 282027 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
 Chain[1] 2464 MASTER LE NN 281936 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2465 MASTER LE NN 281706 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2466 MASTER LE NN 281701 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2467 MASTER LE NN 281944 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_AWAKE_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2468 MASTER LE NN 281703 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2469 MASTER LE NN 281707 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2470 MASTER LE NN 282044 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2471 MASTER LE NN 281759 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2472 MASTER LE NN 281782 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2473 MASTER LE NN 281767 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2474 MASTER LE NN 281768 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2475 MASTER LE NN 282042 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2476 MASTER LE NN 281774 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_MANUAL_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2477 MASTER LE NN 282119 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2478 MASTER LE NN 281777 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2479 MASTER LE NN 282110 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2480 MASTER LE NN 281756 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_SPARE_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2481 MASTER LE NN 282106 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2482 MASTER LE NN 282108 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2483 MASTER LE NN 281910 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_EN_CFG_VIN_FF_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2484 MASTER LE NN 281904 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2485 MASTER LE NN 281909 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2486 MASTER LE NN 282147 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PHASE_STAGGERED_LOCK_EN_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2487 MASTER LE NN 281814 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2488 MASTER LE NN 281751 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PHASE_STAGGERED_LOO
P_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2489 MASTER LE NN 281793 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2490 MASTER LE NN 281810 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2491 MASTER LE NN 282109 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2492 MASTER LE NN 282111 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2493 MASTER LE NN 281584 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2494 MASTER LE NN 282097 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2495 MASTER LE NN 281906 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2496 MASTER LE NN 281241 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2497 MASTER LE NN 282103 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2498 MASTER LE NN 282098 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2499 MASTER LE NN 282104 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2500 MASTER LE NN 281386 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_toggle_in_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2501 MASTER LE NN 281387 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_blank_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2502 MASTER LE NN 281668 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_pong_blank_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2503 MASTER LE NN 282102 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX2J)
Chain[1] 2504 MASTER LE NN 282146 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_out_reg_re
g (M31_1P5V6T_SFFRBQX1)
Chain[1] 2505 MASTER LE NN 281758 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__RET_CMP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2506 MASTER LE NN 281859 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2507 MASTER LE NN 281764 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__NC_TEST_MODE_EN_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2508 MASTER LE NN 281765 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__NC_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2509 MASTER LE NN 281871 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2510 MASTER LE NN 281745 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PWM_R_RIGHT_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2511 MASTER LE NN 281973 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_slib_sync/sync_d
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2512 MASTER LE NN 281784 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2513 MASTER LE NN 281788 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2514 MASTER LE NN 281746 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PWM_F_RIGHT_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2515 MASTER LE NN 281785 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2516 MASTER LE NN 281951 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2517 MASTER LE NN 281821 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2518 MASTER LE NN 281918 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2519 MASTER LE NN 281818 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2520 MASTER LE NN 282076 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2521 MASTER LE NN 281817 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2522 MASTER LE NN 282074 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2523 MASTER LE NN 281819 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2524 MASTER LE NN 281822 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2525 MASTER LE NN 281748 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PP_PWM_LOCK_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2526 MASTER LE NN 282040 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2527 MASTER LE NN 281933 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2528 MASTER LE NN 281826 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2529 MASTER LE NN 281934 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2530 MASTER LE NN 281864 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2531 MASTER LE NN 281865 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2532 MASTER LE NN 281827 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2533 MASTER LE NN 281786 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2534 MASTER LE NN 281781 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2535 MASTER LE NN 281750 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PP_PWM_LOOP_EN_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2536 MASTER LE NN 281762 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2537 MASTER LE NN 281747 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PP_PWMBY2_LOCK_EN_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 2538 MASTER LE NN 281824 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2539 MASTER LE NN 281930 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2540 MASTER LE NN 281763 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2541 MASTER LE NN 281787 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2542 MASTER LE NN 282036 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2543 MASTER LE NN 282058 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2544 MASTER LE NN 282063 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2545 MASTER LE NN 282060 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2546 MASTER LE NN 281962 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_slib_sync
/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2547 MASTER LE NN 281938 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2548 MASTER LE NN 281942 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN1_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2549 MASTER LE NN 281940 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2550 MASTER LE NN 281941 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN0_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2551 MASTER LE NN 281943 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN2_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2552 MASTER LE NN 281939 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2553 MASTER LE NN 281937 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2554 MASTER LE NN 281945 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_EN_CTL__PERPH_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2555 MASTER LE NN 282021 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2556 MASTER LE NN 282031 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 2557 MASTER LE NN 282032 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2558 MASTER LE NN 282095 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2559 MASTER LE NN 282087 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2560 MASTER LE NN 282092 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2561 MASTER LE NN 281369 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2562 MASTER LE NN 281368 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2563 MASTER LE NN 281370 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2564 MASTER LE NN 281265 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2565 MASTER LE NN 281381 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2566 MASTER LE NN 281367 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_en
_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2567 MASTER LE NN 281366 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_en
_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2568 MASTER LE NN 281685 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2569 MASTER LE NN 281378 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2570 MASTER LE NN 281375 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2571 MASTER LE NN 281365 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_sl
ib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2572 MASTER LE NN 281364 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_sl
ib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2573 MASTER LE NN 281376 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2574 MASTER LE NN 281267 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2575 MASTER LE NN 281268 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2576 MASTER LE NN 281266 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2577 MASTER LE NN 281269 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2578 MASTER LE NN 281271 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2579 MASTER LE NN 281272 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2580 MASTER LE NN 282091 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2581 MASTER LE NN 282088 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2582 MASTER LE NN 282096 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2583 MASTER LE NN 282093 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2584 MASTER LE NN 282019 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2585 MASTER LE NN 282025 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2586 MASTER LE NN 282061 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2587 MASTER LE NN 282062 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2588 MASTER LE NN 282017 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2589 MASTER LE NN 281783 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2590 MASTER LE NN 282078 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2591 MASTER LE NN 281869 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2592 MASTER LE NN 281749 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PP_PWMBY2_LOOP_EN_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2593 MASTER LE NN 281876 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2594 MASTER LE NN 281760 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2595 MASTER LE NN 281860 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2596 MASTER LE NN 281915 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_EN_COMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[1] 2597 MASTER LE NN 281916 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_EN_DLL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2598 MASTER LE NN 281911 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2599 MASTER LE NN 281892 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PHASE_STAGGER_COMP_CAP_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2600 MASTER LE NN 281893 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PING_PONG_COMP_CAP_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2601 MASTER LE NN 281889 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__BW_PHASE_STAGGER_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2602 MASTER LE NN 281891 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PHASE_STAGGER_COMP_CAP_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2603 MASTER LE NN 281905 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2604 MASTER LE NN 281229 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2605 MASTER LE NN 281242 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2606 MASTER LE NN 281244 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor14_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2607 MASTER LE NN 282144 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2608 MASTER LE NN 281987 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2609 MASTER LE NN 281686 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2610 MASTER LE NN 281383 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2611 MASTER LE NN 281384 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_tgl_counter_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2612 MASTER LE NN 281385 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_tgl_counter_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2613 MASTER LE NN 281243 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2614 MASTER LE NN 281245 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor15_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2615 MASTER LE NN 281226 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2616 MASTER LE NN 281228 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2617 MASTER LE NN 281888 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__BW_PHASE_STAGGER_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2618 MASTER LE NN 281890 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PING_PONG_CP_CURRNT_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2619 MASTER LE NN 281227 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2620 MASTER LE NN 281912 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2621 MASTER LE NN 281913 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2622 MASTER LE NN 281894 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__OPEN_LOOP_ACTIVE_CFG_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2623 MASTER LE NN 281914 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2624 MASTER LE NN 281237 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2625 MASTER LE NN 281792 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2626 MASTER LE NN 281808 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2627 MASTER LE NN 281968 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 2628 MASTER LE NN 281800 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2629 MASTER LE NN 281803 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2630 MASTER LE NN 281948 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2631 MASTER LE NN 281283 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_out_reg_re
g (M31_1P5V6T_SFFRBQX1)
Chain[1] 2632 MASTER LE NN 281801 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2633 MASTER LE NN 281799 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2634 MASTER LE NN 281950 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2635 MASTER LE NN 282008 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 2636 MASTER LE NN 282002 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 2637 MASTER LE NN 281798 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2638 MASTER LE NN 281981 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[3
] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2639 MASTER LE NN 281986 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2640 MASTER LE NN 281985 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2641 MASTER LE NN 282000 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2642 MASTER LE NN 282006 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2643 MASTER LE NN 282001 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2644 MASTER LE NN 282005 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2645 MASTER LE NN 282004 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2646 MASTER LE NN 281952 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2647 MASTER LE NN 282010 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2648 MASTER LE NN 282003 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2649 MASTER LE NN 282009 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2650 MASTER LE NN 281855 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2651 MASTER LE NN 281877 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2652 MASTER LE NN 282128 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2653 MASTER LE NN 281875 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2654 MASTER LE NN 282080 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2655 MASTER LE NN 282130 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2656 MASTER LE NN 282082 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2657 MASTER LE NN 282132 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2658 MASTER LE NN 282073 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2659 MASTER LE NN 281861 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2660 MASTER LE NN 281967 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2661 MASTER LE NN 281970 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2662 MASTER LE NN 281791 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2663 MASTER LE NN 281790 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2664 MASTER LE NN 281947 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2665 MASTER LE NN 281812 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2666 MASTER LE NN 281789 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2667 MASTER LE NN 281960 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_slib_sync/sy
nc_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2668 MASTER LE NN 281920 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2669 MASTER LE NN 281969 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2670 MASTER LE NN 281919 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2671 MASTER LE NN 281820 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2672 MASTER LE NN 281955 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
 Chain[1] 2673 MASTER LE NN 281953 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/sync_u0/sync_d_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2674 MASTER LE NN 281954 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/sync_u0/sync_d_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2675 MASTER LE NN 282049 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2676 MASTER LE NN 282048 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2677 MASTER LE NN 282041 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2678 MASTER LE NN 281318 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_en_rb/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2679 MASTER LE NN 281317 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_en_rb/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2680 MASTER LE NN 282045 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_slib_sync/s
ync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2681 MASTER LE NN 282037 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2682 MASTER LE NN 282131 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2683 MASTER LE NN 282077 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2684 MASTER LE NN 282075 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2685 MASTER LE NN 282129 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2686 MASTER LE NN 282079 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2687 MASTER LE NN 282083 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2688 MASTER LE NN 282081 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2689 MASTER LE NN 282072 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2690 MASTER LE NN 281619 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2691 MASTER LE NN 281617 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2692 MASTER LE NN 282018 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2693 MASTER LE NN 282046 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_slib_sync/s
ync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2694 MASTER LE NN 282035 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2695 MASTER LE NN 282039 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2696 MASTER LE NN 282022 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2697 MASTER LE NN 282020 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2698 MASTER LE NN 282026 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2699 MASTER LE NN 282030 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2700 MASTER LE NN 282028 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2701 MASTER LE NN 282024 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2702 MASTER LE NN 282016 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2703 MASTER LE NN 281371 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2704 MASTER LE NN 281373 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2705 MASTER LE NN 281374 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2706 MASTER LE NN 281270 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2707 MASTER LE NN 281372 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2708 MASTER LE NN 281684 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2709 MASTER LE NN 282090 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_slib_sync/sync_d_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2710 MASTER LE NN 282085 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2711 MASTER LE NN 282089 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_slib_sync/sync_d_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2712 MASTER LE NN 282084 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2713 MASTER LE NN 282033 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2714 MASTER LE NN 282043 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2715 MASTER LE NN 282086 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/dtmp_reg (M31_1P5V6T_SFFRSBQX1)
Chain[1] 2716 MASTER LE NN 281330 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_19p2_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2717 MASTER LE NN 281329 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_19p2_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2718 MASTER LE NN 281971 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2719 MASTER LE NN 281917 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2720 MASTER LE NN 281949 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2721 MASTER LE NN 281972 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2722 MASTER LE NN 281946 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2723 MASTER LE NN 281966 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2724 MASTER LE NN 281797 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2725 MASTER LE NN 281804 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2726 MASTER LE NN 281802 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2727 MASTER LE NN 281595 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2728 MASTER LE NN 282152 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync4/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2729 MASTER LE NN 281575 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync4/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2730 MASTER LE NN 281585 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2731 MASTER LE NN 281588 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2732 MASTER LE NN 281586 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2733 MASTER LE NN 281589 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2734 MASTER LE NN 281582 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2735 MASTER LE NN 281561 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2736 MASTER LE NN 281560 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2737 MASTER LE NN 281559 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2738 MASTER LE NN 281558 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2739 MASTER LE NN 281975 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2740 MASTER LE NN 281982 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2741 MASTER LE NN 281806 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 2742 MASTER LE NN 281976 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2743 MASTER LE NN 281977 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 2744 MASTER LE NN 281983 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2745 MASTER LE NN 281984 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 2746 MASTER LE NN 281978 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[0
] (M31_1P5V6T_SFFSRBQX1)
 Chain[1] 2747 MASTER LE NN 281979 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[1
] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2748 MASTER LE NN 281980 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[2
] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2749 MASTER LE NN 281873 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2750 MASTER LE NN 281857 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2751 MASTER LE NN 282007 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2752 MASTER LE NN 281872 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2753 MASTER LE NN 281856 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2754 MASTER LE NN 281858 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2755 MASTER LE NN 281874 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[1] 2756 MASTER LE NN 281862 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2757 MASTER LE NN 281878 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2758 MASTER LE NN 281830 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2759 MASTER LE NN 281863 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2760 MASTER LE NN 281828 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2761 MASTER LE NN 281825 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2762 MASTER LE NN 281870 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2763 MASTER LE NN 281868 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2764 MASTER LE NN 281823 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2765 MASTER LE NN 281866 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2766 MASTER LE NN 281998 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_slib_sync/sync_d_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2767 MASTER LE NN 281577 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2768 MASTER LE NN 281999 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_slib_sync/sync_d_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2769 MASTER LE NN 281576 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2770 MASTER LE NN 281579 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2771 MASTER LE NN 281990 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 2772 MASTER LE NN 281322 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2773 MASTER LE NN 281324 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2774 MASTER LE NN 281328 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2775 MASTER LE NN 281325 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2776 MASTER LE NN 281682 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2777 MASTER LE NN 281254 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2778 MASTER LE NN 281255 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2779 MASTER LE NN 281257 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[9] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2780 MASTER LE NN 281659 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2781 MASTER LE NN 281829 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2782 MASTER LE NN 281867 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2783 MASTER LE NN 282071 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2784 MASTER LE NN 282069 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2785 MASTER LE NN 282070 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2786 MASTER LE NN 281263 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2787 MASTER LE NN 281256 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[10] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2788 MASTER LE NN 281259 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2789 MASTER LE NN 281253 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2790 MASTER LE NN 281252 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2791 MASTER LE NN 281261 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2792 MASTER LE NN 281262 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2793 MASTER LE NN 281618 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2794 MASTER LE NN 281260 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2795 MASTER LE NN 281296 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[10]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2796 MASTER LE NN 281258 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[11] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 2797 MASTER LE NN 281391 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2798 MASTER LE NN 281615 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2799 MASTER LE NN 281616 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2800 MASTER LE NN 282145 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2801 MASTER LE NN 281394 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_sync_b_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2802 MASTER LE NN 281393 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_sync_b_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2803 MASTER LE NN 281295 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[11]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2804 MASTER LE NN 281297 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[9]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2805 MASTER LE NN 281298 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[8]
(M31_1P5V6T_SFFSRBQX1)
 Chain[1] 2806 MASTER LE NN 281306 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2807 MASTER LE NN 281395 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2808 MASTER LE NN 281633 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2809 MASTER LE NN 281396 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2810 MASTER LE NN 281407 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_calc_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2811 MASTER LE NN 281305 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2812 MASTER LE NN 281415 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2813 MASTER LE NN 281392 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2814 MASTER LE NN 281414 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2815 MASTER LE NN 281413 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2816 MASTER LE NN 281412 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2817 MASTER LE NN 281408 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_clear_latch_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2818 MASTER LE NN 281411 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2819 MASTER LE NN 281410 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2820 MASTER LE NN 281301 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
 Chain[1] 2821 MASTER LE NN 281300 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2822 MASTER LE NN 281302 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2823 MASTER LE NN 281303 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2824 MASTER LE NN 281304 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2825 MASTER LE NN 281299 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2826 MASTER LE NN 281626 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2827 MASTER LE NN 281401 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2828 MASTER LE NN 281400 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2829 MASTER LE NN 281405 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2830 MASTER LE NN 281404 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2831 MASTER LE NN 281406 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_sample_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2832 MASTER LE NN 281632 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2833 MASTER LE NN 281634 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2834 MASTER LE NN 281637 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2835 MASTER LE NN 281636 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2836 MASTER LE NN 281620 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2837 MASTER LE NN 281649 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2838 MASTER LE NN 281327 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2839 MASTER LE NN 281326 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2840 MASTER LE NN 281321 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2841 MASTER LE NN 281681 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2842 MASTER LE NN 281578 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2843 MASTER LE NN 281580 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2844 MASTER LE NN 281581 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2845 MASTER LE NN 281583 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2846 MASTER LE NN 281591 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2847 MASTER LE NN 281590 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2848 MASTER LE NN 281592 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2849 MASTER LE NN 282150 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2850 MASTER LE NN 281294 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2851 MASTER LE NN 281293 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2852 MASTER LE NN 281611 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/slib_sync_u1
/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2853 MASTER LE NN 281610 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/slib_sync_u1
/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2854 MASTER LE NN 281550 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2855 MASTER LE NN 281587 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2856 MASTER LE NN 281594 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2857 MASTER LE NN 281541 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2858 MASTER LE NN 281542 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2859 MASTER LE NN 281548 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2860 MASTER LE NN 281807 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2861 MASTER LE NN 281813 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2862 MASTER LE NN 281815 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2863 MASTER LE NN 281284 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2864 MASTER LE NN 281811 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2865 MASTER LE NN 282153 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2866 MASTER LE NN 281549 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2867 MASTER LE NN 281543 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2868 MASTER LE NN 281546 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2869 MASTER LE NN 281547 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2870 MASTER LE NN 281593 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2871 MASTER LE NN 281545 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2872 MASTER LE NN 281989 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2873 MASTER LE NN 281988 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2874 MASTER LE NN 281544 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2875 MASTER LE NN 281612 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/slib_sync_u1
/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2876 MASTER LE NN 281809 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2877 MASTER LE NN 281613 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/slib_sync_u1
/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2878 MASTER LE NN 281287 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2879 MASTER LE NN 281335 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2880 MASTER LE NN 281996 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2881 MASTER LE NN 281997 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2882 MASTER LE NN 281995 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2883 MASTER LE NN 281994 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2884 MASTER LE NN 281993 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2885 MASTER LE NN 281323 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2886 MASTER LE NN 281331 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_CTLR_MISC4__DUTY_GENERATOR_EN_rifo_del_r
eg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2887 MASTER LE NN 281621 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2888 MASTER LE NN 281992 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2889 MASTER LE NN 281991 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2890 MASTER LE NN 281333 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_duty_out_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2891 MASTER LE NN 281658 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2892 MASTER LE NN 281677 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2893 MASTER LE NN 281332 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_duty_out_half_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2894 MASTER LE NN 281623 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2895 MASTER LE NN 281655 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2896 MASTER LE NN 281660 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2897 MASTER LE NN 281657 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2898 MASTER LE NN 281680 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2899 MASTER LE NN 281678 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2900 MASTER LE NN 281650 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2901 MASTER LE NN 281628 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2902 MASTER LE NN 281641 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2903 MASTER LE NN 281622 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2904 MASTER LE NN 281631 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2905 MASTER LE NN 281647 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2906 MASTER LE NN 281640 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2907 MASTER LE NN 281638 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2908 MASTER LE NN 281656 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2909 MASTER LE NN 281643 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2910 MASTER LE NN 281642 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
 Chain[1] 2911 MASTER LE NN 281679 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2912 MASTER LE NN 281651 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2913 MASTER LE NN 281625 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2914 MASTER LE NN 281630 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2915 MASTER LE NN 281629 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2916 MASTER LE NN 281635 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2917 MASTER LE NN 281402 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2918 MASTER LE NN 281648 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2919 MASTER LE NN 281653 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2920 MASTER LE NN 281652 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2921 MASTER LE NN 281403 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2922 MASTER LE NN 281399 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2923 MASTER LE NN 281398 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2924 MASTER LE NN 281397 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2925 MASTER LE NN 281627 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2926 MASTER LE NN 281654 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[1] 2927 MASTER LE NN 282151 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2928 MASTER LE NN 281646 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2929 MASTER LE NN 281639 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2930 MASTER LE NN 281645 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2931 MASTER LE NN 281644 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2932 MASTER LE NN 281664 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2933 MASTER LE NN 281663 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2934 MASTER LE NN 281662 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2935 MASTER LE NN 281661 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2936 MASTER LE NN 281624 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2937 MASTER LE NN 281338 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2938 MASTER LE NN 281337 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2939 MASTER LE NN 281336 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2940 MASTER LE NN 281334 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2941 MASTER LE NN 281288 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2942 MASTER LE NN 281286 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2943 MASTER LE NN 281285 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2944 MASTER LE NN 281289 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2945 MASTER LE NN 281290 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2946 MASTER LE NN 281291 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2947 MASTER LE NN 281292 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2948 MASTER LE NN 285901 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2949 MASTER LE NN 281675 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_glitchfree_mux_1p0_c
lk_qual_u/sel0_0_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 2950 MASTER TE NN 260372 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_addr_frame_align_reg[5]
(M31_1P5V6T_SFFRBQX2)
Chain[1] 2951 MASTER TE NN 260494 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_tx_master_wr/pre_tx_master_wr_ack_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2952 MASTER TE NN 260309 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_addr_frame_align_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2953 MASTER TE NN 260297 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_samp_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2954 MASTER TE NN 260307 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_addr_frame_align_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2955 MASTER TE NN 260366 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2956 MASTER TE NN 260373 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_samp_reg[0] (M31_1P5V6T_SFFRBQX2J)
Chain[1] 2957 MASTER TE NN 260299 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_samp_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2958 MASTER TE NN 260382 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2959 MASTER TE NN 260370 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[4] (M31_1P5V6T_SFFRBQX2)
Chain[1] 2960 MASTER TE NN 260368 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2961 MASTER TE NN 260384 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2962 MASTER TE NN 260354 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[8] (M31_1P5V6T_SFFRBQX2)
Chain[1] 2963 MASTER TE NN 260381 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2964 MASTER TE NN 260383 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2965 MASTER TE NN 260375 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[0] (M31_1P5V6T_SFFRBQX2J)
Chain[1] 2966 MASTER TE NN 260303 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_samp_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2967 MASTER TE NN 260302 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_samp_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2968 MASTER TE NN 260304 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_samp_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2969 MASTER TE NN 260374 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_samp_reg[0]
(M31_1P5V6T_SFFRBQX2J)
Chain[1] 2970 MASTER TE NN 260310 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_addr_frame_align_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2971 MASTER TE NN 260311 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_addr_frame_align_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2972 MASTER TE NN 260503 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/\u_spmi_s_bus_idle_conn_fsm/u_sdata_t_resout_gen/q1_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2973 MASTER TE NN 260501 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/\u_spmi_s_bus_idle_conn_fsm/u_sclk_t_resout_gen/q3_reg
(M31_1P5V6T_SFFQX1)
Chain[1] 2974 MASTER TE NN 260500 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/\u_spmi_s_bus_idle_conn_fsm/u_sclk_t_resout_gen/q2_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2975 MASTER TE NN 260505 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/\u_spmi_s_bus_idle_conn_fsm/u_sdata_t_resout_gen/q3_reg
(M31_1P5V6T_SFFQX1)
 Chain[1] 2976 MASTER TE NN 260504 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/\u_spmi_s_bus_idle_conn_fsm/u_sdata_t_resout_gen/q2_reg
(M31_1P5V6T_SFFSBQX1)
Chain[1] 2977 MASTER TE NN 260454 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_arbitration_monitor/arb_done_no_win_reg (M31_1P5V6T_SFFRBQX4J)
Chain[1] 2978 MASTER TE NN 260528 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/\u_spmi_s_ssc_det/ssc_det_raw_reg (M31_1P5V6T_SFFRSBQX1)
Chain[1] 2979 MASTER TE NN 260515 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/cmd_done_d1_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2980 MASTER TE NN 260529 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/\u_spmi_s_bus_idle_conn_fsm/s_cmd_frame_error_trap_t_reg
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 2981 MASTER TE NN 260514 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/sdata_in_n1_reg (M31_1P5V6T_SFFRBQX1J)
Chain[1] 2982 MASTER TE NN 260452 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_arbitration_monitor/\sa_samp_reg[0] (M31_1P5V6T_SFFRBQX2J)
Chain[1] 2983 MASTER TE NN 260389 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_arbitration_monitor/master_win_reg (M31_1P5V6T_SFFRBQX1J)
Chain[1] 2984 MASTER TE NN 260453 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_arbitration_monitor/\sa_samp_reg[1] (M31_1P5V6T_SFFRBQX2J)
Chain[1] 2985 MASTER TE NN 260449 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_arbitration_monitor/slave_participation_stop_reg
(M31_1P5V6T_SFFRBQX2J)
Chain[1] 2986 MASTER TE NN 260450 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_arbitration_monitor/\sa_samp_reg[2] (M31_1P5V6T_SFFRBQX2J)
Chain[1] 2987 MASTER TE NN 260451 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_arbitration_monitor/\sa_samp_reg[3] (M31_1P5V6T_SFFRBQX2J)
Chain[1] 2988 MASTER TE NN 260277 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/cmd_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2989 MASTER TE NN 260330 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/bus_addrctl_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2990 MASTER TE NN 260313 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/addr_in_use_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 2991 MASTER TE NN 260355 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\mapped_sid_samp_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 2992 MASTER TE NN 260296 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_samp_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2993 MASTER TE NN 260294 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_samp_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[1] 2994 MASTER TE NN 260295 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_samp_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2995 MASTER TE NN 260377 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_addr_frame_align_reg[0]
(M31_1P5V6T_SFFRBQX2J)
Chain[1] 2996 MASTER TE NN 260308 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_addr_frame_align_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2997 MASTER TE NN 260312 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_addr_frame_align_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2998 MASTER TE NN 260298 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_samp_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 2999 MASTER TE NN 260300 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_samp_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3000 MASTER TE NN 260349 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_align_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3001 MASTER TE NN 260378 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/bus_rden_reg (M31_1P5V6T_SFFRBQX2J)
Chain[1] 3002 MASTER TE NN 260243 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/bus_in_use_reg (M31_1P5V6T_SFFRBQX1J)
Chain[1] 3003 MASTER TE NN 260244 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/bus_wrclk_neg_reg (M31_1P5V6T_SFFRBQX1J)
Chain[1] 3004 MASTER TE NN 260301 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_samp_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3005 MASTER TE NN 260388 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3006 MASTER TE NN 260305 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_samp_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3007 MASTER TE NN 260387 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3008 MASTER TE NN 260306 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_samp_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3009 MASTER TE NN 260386 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3010 MASTER TE NN 260385 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3011 MASTER TE NN 260369 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3012 MASTER TE NN 260365 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3013 MASTER TE NN 260352 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_align_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3014 MASTER TE NN 260376 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_align_reg[0]
(M31_1P5V6T_SFFRBQX2J)
Chain[1] 3015 MASTER TE NN 260353 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_align_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3016 MASTER TE NN 260367 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\gentype_addr_reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3017 MASTER TE NN 260351 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_align_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3018 MASTER TE NN 260347 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_align_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3019 MASTER TE NN 260350 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_align_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3020 MASTER TE NN 260348 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/\reg_wr_data_frame_align_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3021 MASTER TE NN 260356 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/u_spmi_s_cmd_monitor/bus_data_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3022 MASTER TE NN 260798 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_sclk_gen/clk_en_neg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3023 MASTER TE NN 260770 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/x_main_fsm_ssc_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3024 MASTER TE NN 260540 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_bus_idle_conn_fsm/u_sdata_t_resout_gen/q
3_reg (M31_1P5V6T_SFFQX1)
Chain[1] 3025 MASTER TE NN 260539 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_bus_idle_conn_fsm/u_sdata_t_resout_gen/q
2_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3026 MASTER TE NN 260538 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_bus_idle_conn_fsm/u_sdata_t_resout_gen/q
1_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3027 MASTER TE NN 260750 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_connected_1d_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3028 MASTER TE NN 260732 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3029 MASTER TE NN 260873 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_bus_idle_conn_fsm/s_bus_idle_1d_1n_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3030 MASTER TE NN 260753 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3031 MASTER TE NN 260869 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_arbitration_monitor/arb_done_no_win_reg
(M31_1P5V6T_SFFRBQX1J)
Chain[1] 3032 MASTER TE NN 260860 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_arbitration_monitor/arb_done_with_win_re
g (M31_1P5V6T_SFFRBQX1J)
Chain[1] 3033 MASTER TE NN 260613 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_tbo_fsm/tbo_win_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3034 MASTER TE NN 260868 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/s_bus_idle_reg (M31_1P5V6T_SFFRSBQX4)
Chain[1] 3035 MASTER TE NN 260871 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_sdata_gen/s_bus_idle_not_1d_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3036 MASTER TE NN 260645 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_arbitration_monitor/slave_win_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3037 MASTER TE NN 260864 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_arbitration_monitor/master_win_reg
(M31_1P5V6T_SFFRBQX2)
Chain[1] 3038 MASTER TE NN 260600 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_ssc_det/ssc_det_raw_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 3039 MASTER TE NN 260790 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_bus_idle_conn_fsm/x_bus_idle_1d_1n_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3040 MASTER TE NN 260604 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_bus_idle_conn_fsm/s_bus_idle_2d_1n_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3041 MASTER TE NN 260754 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/x_arb_start_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3042 MASTER TE NN 260859 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/s_bus_idle_async_reg (M31_1P5V6T_SFFRSBQX1J)
 Chain[1] 3043 MASTER TE NN 260853 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_sdata_gen/s_sdata_oe_half_after_full_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3044 MASTER TE NN 260852 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_sdata_gen/s_sdata_oe_half_2_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3045 MASTER TE NN 260858 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_sclk_gen/sclk_oe_reg_reg
(M31_1P5V6T_SFFRSBQX1J)
Chain[1] 3046 MASTER TE NN 260857 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/s_cmd_frame_error_trap_reg (M31_1P5V6T_SFFRBQX2J)
Chain[1] 3047 MASTER TE NN 260867 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_arbitration_monitor/arb_is_bom_reg
(M31_1P5V6T_SFFRSBQX2J)
Chain[1] 3048 MASTER TE NN 260862 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/s_sdata_in_n1_reg (M31_1P5V6T_SFFRBQX3)
Chain[1] 3049 MASTER TE NN 260614 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_tbo_win_synch/level_in_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3050 MASTER TE NN 260781 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_cmd_done_synch/level_in_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3051 MASTER TE NN 260745 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_ssc_conn_fsm/ssc_conn_start_to_cnt_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3052 MASTER TE NN 260626 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_arb_is_bom_demet/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3053 MASTER TE NN 260733 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/geni_tbo_det_trap_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3054 MASTER TE NN 260628 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/x_arb_is_bom_1d_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3055 MASTER TE NN 260778 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/geni_mux_sel_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3056 MASTER TE NN 260627 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_arb_is_bom_demet/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3057 MASTER TE NN 260785 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/x_geni_arb_grant_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3058 MASTER TE NN 260756 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3059 MASTER TE NN 260760 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3060 MASTER TE NN 260761 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3061 MASTER TE NN 260757 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3062 MASTER TE NN 260759 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3063 MASTER TE NN 260758 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3064 MASTER TE NN 260755 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3065 MASTER TE NN 260752 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3066 MASTER TE NN 260787 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_bus_idle_conn_fsm/a_bus_idle_rst_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3067 MASTER TE NN 260734 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_state_reg[5]
(M31_1P5V6T_SFFSBQX3)
Chain[1] 3068 MASTER TE NN 260751 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_main_arb_fsm/main_fsm_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3069 MASTER TE NN 260845 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/x_mpm_arb_clk_req_reg (M31_1P5V6T_SFFRSBQX1)
Chain[1] 3070 MASTER TE NN 260861 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_arbitration_monitor/self_master_win_reg
(M31_1P5V6T_SFFRBQX1J)
Chain[1] 3071 MASTER TE NN 260788 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_bus_idle_conn_fsm/a_bus_idle_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[1] 3072 MASTER TE NN 260870 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/\u_sms_spmi_m_arbiter_core/u_sms_spmi_m_ssc_det/q2_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3073 MASTER TE NN 260875 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/\gen_modgen1_u_spmi_m_dig_c
ore/u_glitchfree_mux_sclk/sel1_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3074 MASTER LS NN 255801 + GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[337]_A_slice_u0/LOCKUP
(M31_1P5V6T_DLATCHQX1)
 DSLAVE TE NN 260502 - GPIO_07
I_DCORE/u_spmi_ss_rmod/u_spmi_ss_rdig/u_spmi_ss_dig_mod/gen_sms_wrapper_u_sms_wrapp
er/u_spmi_s/\u_spmi_s_bus_idle_conn_fsm/u_sclk_t_resout_gen/q1_reg
(M31_1P5V6T_SFFSBQX2)
Chain[1] 3075 MASTER TE NN 259819 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[337]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3076 MASTER TE NN 259818 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[337]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3077 MASTER TE NN 259783 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[336]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3078 MASTER TE NN 259784 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[336]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3079 MASTER TE NN 260029 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[343]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3080 MASTER TE NN 260028 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[343]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3081 MASTER TE NN 259993 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[342]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3082 MASTER TE NN 259994 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[342]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3083 MASTER TE NN 259293 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[322]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3084 MASTER TE NN 259294 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[322]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3085 MASTER TE NN 259329 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[323]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3086 MASTER TE NN 259328 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[323]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3087 MASTER TE NN 259258 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[321]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3088 MASTER TE NN 259259 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[321]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3089 MASTER TE NN 259433 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[326]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3090 MASTER TE NN 259434 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[326]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3091 MASTER TE NN 259398 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[325]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3092 MASTER TE NN 259399 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[325]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3093 MASTER TE NN 259503 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[328]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3094 MASTER TE NN 257985 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[49]_A_slice_u0/\G[0]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX2)
Chain[1] 3095 MASTER TE NN 257950 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[36]_A_slice_u0/\G[0]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3096 MASTER TE NN 258004 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[53]_A_slice_u0/\G[0]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3097 MASTER TE NN 257986 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[50]_A_slice_u0/\G[0]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3098 MASTER TE NN 258058 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[56]_A_slice_u0/\G[0]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3099 MASTER TE NN 258040 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[55]_A_slice_u0/\G[0]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3100 MASTER TE NN 257832 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[8]_A_slice_u0/\G[2]_A_sync_u0/gen
_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3101 MASTER TE NN 257830 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[8]_A_slice_u0/\G[4]_A_sync_u0/gen
_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3102 MASTER TE NN 257828 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[8]_A_slice_u0/\G[6]_A_sync_u0/gen
_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3103 MASTER TE NN 257834 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[8]_A_slice_u0/\G[0]_A_sync_u0/gen
_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3104 MASTER TE NN 257831 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[8]_A_slice_u0/\G[3]_A_sync_u0/gen
_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3105 MASTER TE NN 257833 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[8]_A_slice_u0/\G[1]_A_sync_u0/gen
_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3106 MASTER TE NN 257827 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[8]_A_slice_u0/\G[7]_A_sync_u0/gen
_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3107 MASTER TE NN 257829 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[8]_A_slice_u0/\G[5]_A_sync_u0/gen
_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3108 MASTER TE NN 258096 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[82]_A_slice_u0/\G[1]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3109 MASTER TE NN 258076 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[81]_A_slice_u0/\G[1]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3110 MASTER TE NN 258156 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[85]_A_slice_u0/\G[1]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3111 MASTER TE NN 258116 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[83]_A_slice_u0/\G[1]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3112 MASTER TE NN 258022 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[54]_A_slice_u0/\G[0]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
 Chain[1] 3113 MASTER TE NN 258229 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[96]_A_slice_u0/\G[0]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3114 MASTER TE NN 258247 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[97]_A_slice_u0/\G[1]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3115 MASTER TE NN 258781 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[192]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3116 MASTER TE NN 258586 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[117]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3117 MASTER TE NN 258585 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[117]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3118 MASTER TE NN 258579 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[117]_A_slice_u0/\G[7]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3119 MASTER TE NN 258581 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[117]_A_slice_u0/\G[5]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3120 MASTER TE NN 258582 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[117]_A_slice_u0/\G[4]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3121 MASTER TE NN 258580 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[117]_A_slice_u0/\G[6]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3122 MASTER TE NN 258584 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[117]_A_slice_u0/\G[2]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3123 MASTER TE NN 258583 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[117]_A_slice_u0/\G[3]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3124 MASTER TE NN 258316 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[114]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3125 MASTER TE NN 258317 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[114]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3126 MASTER TE NN 258467 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[116]_A_slice_u0/\G[4]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3127 MASTER TE NN 258464 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[116]_A_slice_u0/\G[7]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3128 MASTER TE NN 258466 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[116]_A_slice_u0/\G[5]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3129 MASTER TE NN 258468 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[116]_A_slice_u0/\G[3]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3130 MASTER TE NN 258465 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[116]_A_slice_u0/\G[6]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3131 MASTER TE NN 258469 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[116]_A_slice_u0/\G[2]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3132 MASTER TE NN 258470 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[116]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3133 MASTER TE NN 258471 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[116]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3134 MASTER TE NN 258284 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[113]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3135 MASTER TE NN 258283 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[113]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3136 MASTER TE NN 258265 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[98]_A_slice_u0/\G[0]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3137 MASTER TE NN 258136 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[84]_A_slice_u0/\G[1]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3138 MASTER TE NN 258177 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[89]_A_slice_u0/\G[0]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3139 MASTER TE NN 258176 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[89]_A_slice_u0/\G[1]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3140 MASTER TE NN 258209 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[91]_A_slice_u0/\G[1]_A_sync_u0/ge
n_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3141 MASTER TE NN 259924 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[340]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3142 MASTER TE NN 259923 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[340]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3143 MASTER TE NN 258817 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[194]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3144 MASTER TE NN 258835 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[195]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3145 MASTER TE NN 258853 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[196]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3146 MASTER TE NN 259853 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[338]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3147 MASTER TE NN 259854 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[338]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3148 MASTER TE NN 259049 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[285]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3149 MASTER TE NN 259048 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[285]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3150 MASTER TE NN 258943 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[276]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3151 MASTER TE NN 258944 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[276]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3152 MASTER TE NN 259679 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[333]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3153 MASTER TE NN 259084 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[288]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3154 MASTER TE NN 259083 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[288]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3155 MASTER TE NN 259678 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[333]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3156 MASTER TE NN 259644 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[332]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3157 MASTER TE NN 259643 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[332]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3158 MASTER TE NN 259538 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[329]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3159 MASTER TE NN 259539 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[329]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3160 MASTER TE NN 259608 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[331]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3161 MASTER TE NN 259609 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[331]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3162 MASTER TE NN 259504 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[328]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3163 MASTER TE NN 259573 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[330]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3164 MASTER TE NN 259574 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[330]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3165 MASTER TE NN 259469 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[327]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3166 MASTER TE NN 259468 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[327]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3167 MASTER TE NN 259363 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[324]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3168 MASTER TE NN 259364 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[324]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3169 MASTER TE NN 259713 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[334]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3170 MASTER TE NN 259714 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[334]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3171 MASTER TE NN 259154 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[294]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
 Chain[1] 3172 MASTER TE NN 259153 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[294]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3173 MASTER TE NN 259118 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[291]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3174 MASTER TE NN 259119 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[291]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3175 MASTER TE NN 259749 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[335]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3176 MASTER TE NN 259748 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[335]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3177 MASTER TE NN 259223 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[320]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3178 MASTER TE NN 259224 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[320]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3179 MASTER TE NN 259188 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[297]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3180 MASTER TE NN 259189 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[297]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3181 MASTER TE NN 258352 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[115]_A_slice_u0/\G[4]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3182 MASTER TE NN 258351 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[115]_A_slice_u0/\G[5]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3183 MASTER TE NN 258355 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[115]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3184 MASTER TE NN 258350 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[115]_A_slice_u0/\G[6]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3185 MASTER TE NN 258349 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[115]_A_slice_u0/\G[7]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3186 MASTER TE NN 258354 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[115]_A_slice_u0/\G[2]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3187 MASTER TE NN 258356 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[115]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3188 MASTER TE NN 258353 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[115]_A_slice_u0/\G[3]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3189 MASTER TE NN 259958 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[341]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3190 MASTER TE NN 259959 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[341]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3191 MASTER TE NN 259889 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[339]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3192 MASTER TE NN 259888 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[339]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3193 MASTER TE NN 258925 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[200]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3194 MASTER TE NN 258799 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[193]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3195 MASTER TE NN 258871 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[197]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3196 MASTER TE NN 258889 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[198]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3197 MASTER TE NN 258907 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[199]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3198 MASTER TE NN 259013 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[282]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3199 MASTER TE NN 259014 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[282]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3200 MASTER TE NN 258978 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[279]_A_slice_u0/\G[0]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3201 MASTER LS NN 256098 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\rfclk
_gen[1]_u_clks_dig_rf_buff/LOCKUP (M31_1P5V6T_DLATCHQX3)
DSLAVE TE NN 258979 - GPIO_07
I_DCORE/u_intr_rmod/u_intr_rdig/u_intr_dig_mod/\L[279]_A_slice_u0/\G[1]_A_sync_u0/g
en_u0/fe_stats_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3202 MASTER TE NN 265289 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\rfclk
_gen[1]_u_clks_dig_rf_buff/\timer_rstn_sync_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3203 MASTER TE NN 265463 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/ldo_vr
eg_en_RF_dfto_sync_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3204 MASTER TE NN 265265 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_buff_top/\u_clks_dig_int_buff/raw_xo_en_post_timer_sync4_reg
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3205 MASTER TE NN 265264 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_buff_top/\u_clks_dig_int_buff/raw_xo_en_post_timer_sync3_reg
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3206 MASTER TE NN 265263 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_buff_top/\u_clks_dig_int_buff/raw_xo_en_post_timer_sync2_reg
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3207 MASTER TE NN 265262 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_buff_top/\u_clks_dig_int_buff/raw_xo_en_post_timer_sync1_reg
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3208 MASTER TE NN 265255 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_buff_top/\u_clks_dig_int_buff/xo_clk_en_in_dly_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
 Chain[1] 3209 MASTER TE NN 265256 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_buff_top/\u_clks_dig_int_buff/xo_clk_en_in_dly_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3210 MASTER TE NN 265261 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_buff_top/\u_clks_dig_int_buff/xo_int_en_fall_s1_neg_reg
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3211 MASTER TE NN 265257 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_buff_top/\u_clks_dig_int_buff/xo_clk_en_in_dly_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3212 MASTER TE NN 265258 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_buff_top/\u_clks_dig_int_buff/xo_clk_en_in_dly_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3213 MASTER TE NN 265260 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_buff_top/\u_clks_dig_int_buff/xo_clk_en_in_dly_reg[5] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3214 MASTER TE NN 265259 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_buff_top/\u_clks_dig_int_buff/xo_clk_en_in_dly_reg[4] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3215 MASTER TE NN 265288 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\rfclk
_gen[1]_u_clks_dig_rf_buff/\timer_rstn_sync_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3216 MASTER TE NN 265324 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\rfclk
_gen[3]_u_clks_dig_rf_buff/\timer_rstn_sync_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3217 MASTER TE NN 265325 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\rfclk
_gen[3]_u_clks_dig_rf_buff/\timer_rstn_sync_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3218 MASTER TE NN 265344 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\inclu
de_lbclk_lbclk_gen[1]_u_clks_dig_lb_buff/xo_out_postimer_en_syn_reg
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3219 MASTER TE NN 265307 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\rfclk
_gen[2]_u_clks_dig_rf_buff/\timer_rstn_sync_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3220 MASTER TE NN 265306 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\rfclk
_gen[2]_u_clks_dig_rf_buff/\timer_rstn_sync_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3221 MASTER TE NN 265343 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\inclu
de_lbclk_lbclk_gen[1]_u_clks_dig_lb_buff/\timer_rstn_sync_reg[1]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3222 MASTER TE NN 265342 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\inclu
de_lbclk_lbclk_gen[1]_u_clks_dig_lb_buff/\timer_rstn_sync_reg[0]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3223 MASTER TE NN 265369 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\inclu
de_lbclk_lbclk_gen[2]_u_clks_dig_lb_buff/xo_out_postimer_en_syn_reg
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3224 MASTER TE NN 265368 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\inclu
de_lbclk_lbclk_gen[2]_u_clks_dig_lb_buff/\timer_rstn_sync_reg[1]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3225 MASTER TE NN 265367 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\inclu
de_lbclk_lbclk_gen[2]_u_clks_dig_lb_buff/\timer_rstn_sync_reg[0]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3226 MASTER TE NN 265393 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\inclu
de_lbclk_lbclk_gen[3]_u_clks_dig_lb_buff/\timer_rstn_sync_reg[1]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3227 MASTER TE NN 265392 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\inclu
de_lbclk_lbclk_gen[3]_u_clks_dig_lb_buff/\timer_rstn_sync_reg[0]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3228 MASTER TE NN 265394 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/\inclu
de_lbclk_lbclk_gen[3]_u_clks_dig_lb_buff/xo_out_postimer_en_syn_reg
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3229 MASTER TE NN 265173 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\sstepper_rstn_fr_timer_sync_reg[0] (M31_1P5V6T_SFFCKBSRBQX1)
Chain[1] 3230 MASTER LS NN 256086 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/LOCKUP (M31_1P5V6T_LOWLATCHX3)
DSLAVE TE NN 265174 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\sstepper_rstn_fr_timer_sync_reg[1] (M31_1P5V6T_SFFCKBSRBQX1)
Chain[1] 3231 MASTER TE NN 264344 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_i_inst/edge_180deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3232 MASTER TE NN 264302 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_i_inst/edge_180deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3233 MASTER TE NN 264316 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_i_inst/edge_180deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3234 MASTER TE NN 264260 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_i_inst/edge_180deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3235 MASTER TE NN 264274 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_i_inst/edge_180deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3236 MASTER TE NN 264288 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_i_inst/edge_180deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3237 MASTER TE NN 264246 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_i_inst/edge_180deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3238 MASTER TE NN 264330 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_i_inst/edge_180deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3239 MASTER TE NN 264056 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\mp3_div_count_reg[2]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3240 MASTER TE NN 264058 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\mp3_div_count_reg[0]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3241 MASTER TE NN 264057 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\mp3_div_count_reg[1]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3242 MASTER TE NN 264055 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\mp3_div_count_reg[3]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3243 MASTER TE NN 264054 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\mp3_div_count_reg[4]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3244 MASTER TE NN 264053 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\mp3_div_count_reg[5]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3245 MASTER TE NN 264050 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/rADJSel_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3246 MASTER TE NN 264049 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/rpADJSel_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3247 MASTER TE NN 263879 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/smps_clk4m8_en_sync_
reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3248 MASTER TE NN 263931 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_halt/sel1_1_reg (M31_1P5V6T_SFFCKBRBQX2J)
Chain[1] 3249 MASTER TE NN 263932 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_halt/\watchdog0_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3250 MASTER TE NN 263881 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/rst_n_sync_posneg_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3251 MASTER TE NN 263882 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/rst_n_sync_neg_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3252 MASTER TE NN 263933 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_halt/\watchdog0_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3253 MASTER TE NN 263934 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_halt/\watchdog0_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3254 MASTER TE NN 263935 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_halt/\watchdog0_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3255 MASTER TE NN 263940 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_halt/\watchdog1_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3256 MASTER TE NN 263939 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_halt/\watchdog1_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3257 MASTER TE NN 263937 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_halt/\watchdog1_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3258 MASTER TE NN 263938 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_halt/\watchdog1_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3259 MASTER TE NN 263936 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_halt/sel0_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3260 MASTER TE NN 263926 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_extcalrcalt_32k/\watchdog1_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3261 MASTER TE NN 263925 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_extcalrcalt_32k/\watchdog1_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3262 MASTER TE NN 263919 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_extcalrcalt_32k/sel1_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3263 MASTER TE NN 263961 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/alt_32k_clk_en_sync_
reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3264 MASTER TE NN 263768 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_gp_clk/\watchdog0_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3265 MASTER TE NN 263767 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_gp_clk/\watchdog0_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3266 MASTER TE NN 263766 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_gp_clk/\watchdog0_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3267 MASTER TE NN 263871 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_hfrc_en_sync/sync
_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3268 MASTER TE NN 263907 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_ext_calrc_32k/sel1_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3269 MASTER TE NN 263912 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_ext_calrc_32k/sel0_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3270 MASTER TE NN 263908 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_ext_calrc_32k/\watchdog0_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3271 MASTER TE NN 263909 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_ext_calrc_32k/\watchdog0_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3272 MASTER TE NN 263914 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_ext_calrc_32k/\watchdog1_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3273 MASTER TE NN 263913 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_ext_calrc_32k/\watchdog1_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3274 MASTER TE NN 263840 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/gp_clk4m8_en_sync_re
g (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3275 MASTER TE NN 263869 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_hfrc_en_sync/sync
_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3276 MASTER TE NN 263870 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_hfrc_en_sync/sync
_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3277 MASTER TE NN 263880 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_hfrc_en_sync/sync
_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3278 MASTER TE NN 263781 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_smps_clk/sel0_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3279 MASTER TE NN 263776 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_smps_clk/sel1_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3280 MASTER TE NN 263771 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_gp_clk/\watchdog1_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
 Chain[1] 3281 MASTER TE NN 263770 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_gp_clk/\watchdog1_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3282 MASTER TE NN 263765 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_gp_clk/\watchdog0_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3283 MASTER TE NN 263769 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_gp_clk/sel0_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3284 MASTER TE NN 263764 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_gp_clk/sel1_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3285 MASTER TE NN 263773 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_gp_clk/\watchdog1_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3286 MASTER TE NN 263772 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_gp_clk/\watchdog1_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3287 MASTER TE NN 263804 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/u_clks_dig_gfreemux2_xorc_clk/sel1_1_reg
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3288 MASTER TE NN 263782 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_smps_clk/\watchdog1_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3289 MASTER TE NN 263785 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_smps_clk/\watchdog1_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3290 MASTER TE NN 263830 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog0_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3291 MASTER TE NN 263809 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/u_clks_dig_gfreemux2_xorc_clk/sel0_1_reg
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3292 MASTER TE NN 263810 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/u_clks_dig_gfreemux2_xorc_clk/\watchdog1_reg[0]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3293 MASTER TE NN 263805 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/u_clks_dig_gfreemux2_xorc_clk/\watchdog0_reg[0]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3294 MASTER TE NN 263806 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/u_clks_dig_gfreemux2_xorc_clk/\watchdog0_reg[1]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3295 MASTER TE NN 263920 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_extcalrcalt_32k/\watchdog0_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3296 MASTER TE NN 263924 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_extcalrcalt_32k/sel0_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3297 MASTER TE NN 263927 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_extcalrcalt_32k/\watchdog1_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3298 MASTER TE NN 263928 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_extcalrcalt_32k/\watchdog1_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
 Chain[1] 3299 MASTER TE NN 263923 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_extcalrcalt_32k/\watchdog0_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3300 MASTER TE NN 263922 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_extcalrcalt_32k/\watchdog0_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3301 MASTER TE NN 263921 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_extcalrcalt_32k/\watchdog0_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3302 MASTER TE NN 263808 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/u_clks_dig_gfreemux2_xorc_clk/\watchdog0_reg[3]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3303 MASTER TE NN 263807 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/u_clks_dig_gfreemux2_xorc_clk/\watchdog0_reg[2]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3304 MASTER TE NN 263811 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/u_clks_dig_gfreemux2_xorc_clk/\watchdog1_reg[1]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3305 MASTER TE NN 263812 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/u_clks_dig_gfreemux2_xorc_clk/\watchdog1_reg[2]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3306 MASTER TE NN 263813 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/u_clks_dig_gfreemux2_xorc_clk/\watchdog1_reg[3]
(M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3307 MASTER TE NN 263816 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/sel1_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3308 MASTER TE NN 263821 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/sel0_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3309 MASTER TE NN 263831 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog0_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3310 MASTER TE NN 263832 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog0_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3311 MASTER TE NN 263829 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog0_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3312 MASTER TE NN 263834 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog1_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3313 MASTER TE NN 263836 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog1_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3314 MASTER TE NN 263835 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog1_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3315 MASTER TE NN 263828 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/sel1_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3316 MASTER TE NN 263822 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog1_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
 Chain[1] 3317 MASTER TE NN 263825 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog1_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3318 MASTER TE NN 263818 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog0_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3319 MASTER TE NN 263819 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog0_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3320 MASTER TE NN 263820 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog0_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3321 MASTER TE NN 263817 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog0_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3322 MASTER TE NN 263837 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog1_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3323 MASTER TE NN 263833 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/sel0_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3324 MASTER TE NN 263784 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_smps_clk/\watchdog1_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3325 MASTER TE NN 263783 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_smps_clk/\watchdog1_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3326 MASTER TE NN 263780 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_smps_clk/\watchdog0_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3327 MASTER TE NN 263779 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_smps_clk/\watchdog0_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3328 MASTER TE NN 263778 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_smps_clk/\watchdog0_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3329 MASTER TE NN 263777 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_smps_clk/\watchdog0_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3330 MASTER TE NN 263788 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/rst_n_sync_posneg_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3331 MASTER TE NN 263789 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/rst_n_sync_neg_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3332 MASTER TE NN 263916 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_ext_calrc_32k/\watchdog1_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3333 MASTER TE NN 263915 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_ext_calrc_32k/\watchdog1_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3334 MASTER TE NN 263911 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_ext_calrc_32k/\watchdog0_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3335 MASTER TE NN 263910 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_ext_calrc_32k/\watchdog0_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3336 MASTER TE NN 263824 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog1_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3337 MASTER TE NN 263823 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/\watchdog1_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3338 MASTER TE NN 263472 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/u_clks_dig_gfreemux2_calrc_32k/\watchdog1_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3339 MASTER TE NN 263469 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/u_clks_dig_gfreemux2_calrc_32k/\watchdog1_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3340 MASTER TE NN 263467 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/u_clks_dig_gfreemux2_calrc_32k/\watchdog0_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3341 MASTER TE NN 263465 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/u_clks_dig_gfreemux2_calrc_32k/\watchdog0_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3342 MASTER TE NN 263466 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/u_clks_dig_gfreemux2_calrc_32k/\watchdog0_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3343 MASTER TE NN 263470 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/u_clks_dig_gfreemux2_calrc_32k/\watchdog1_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3344 MASTER TE NN 263471 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/u_clks_dig_gfreemux2_calrc_32k/\watchdog1_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3345 MASTER TE NN 263463 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/u_clks_dig_gfreemux2_calrc_32k/sel1_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3346 MASTER TE NN 263464 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/u_clks_dig_gfreemux2_calrc_32k/\watchdog0_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3347 MASTER TE NN 263468 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/u_clks_dig_gfreemux2_calrc_32k/sel0_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3348 MASTER TE NN 263753 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/comp_out_negedge_reg (M31_1P5V6T_SFFCKBRBQX2)
Chain[1] 3349 MASTER TE NN 263475 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[33] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3350 MASTER TE NN 263476 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[32] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3351 MASTER TE NN 263477 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[31] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3352 MASTER TE NN 263478 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[30] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3353 MASTER TE NN 263479 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[29] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3354 MASTER TE NN 263480 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[28] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3355 MASTER TE NN 263505 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3356 MASTER TE NN 263754 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3357 MASTER TE NN 263645 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3358 MASTER TE NN 263643 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3359 MASTER TE NN 263646 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3360 MASTER TE NN 263641 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3361 MASTER TE NN 263647 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3362 MASTER TE NN 263629 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3363 MASTER TE NN 263630 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3364 MASTER TE NN 263632 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[17] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3365 MASTER TE NN 263628 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_en_xodom_ne_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3366 MASTER TE NN 263627 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_en_met_ne_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3367 MASTER TE NN 263603 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_reset_met_ne_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3368 MASTER TE NN 263633 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[16] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3369 MASTER TE NN 263604 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_reset_xodom_ne_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3370 MASTER TE NN 263631 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[18] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3371 MASTER TE NN 263634 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3372 MASTER TE NN 263635 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3373 MASTER TE NN 263636 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3374 MASTER TE NN 263637 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3375 MASTER TE NN 263638 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[11] (M31_1P5V6T_SFFRBQX1)
 Chain[1] 3376 MASTER TE NN 263639 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3377 MASTER TE NN 263640 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3378 MASTER TE NN 263503 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[5] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3379 MASTER TE NN 263500 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[8] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3380 MASTER TE NN 263494 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[14] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3381 MASTER TE NN 263493 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[15] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3382 MASTER TE NN 263492 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[16] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3383 MASTER TE NN 263490 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[18] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3384 MASTER TE NN 263488 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[20] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3385 MASTER TE NN 263483 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[25] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3386 MASTER TE NN 263481 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[27] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3387 MASTER TE NN 263482 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[26] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3388 MASTER TE NN 263484 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[24] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3389 MASTER TE NN 263485 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[23] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3390 MASTER TE NN 263486 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[22] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3391 MASTER TE NN 263487 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[21] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3392 MASTER TE NN 263489 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[19] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3393 MASTER TE NN 263491 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[17] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3394 MASTER TE NN 263495 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[13] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3395 MASTER TE NN 263496 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[12] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3396 MASTER TE NN 263497 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[11] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3397 MASTER TE NN 263498 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[10] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3398 MASTER TE NN 263499 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[9] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3399 MASTER TE NN 263501 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[7] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3400 MASTER TE NN 263502 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[6] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3401 MASTER TE NN 263504 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[4] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3402 MASTER TE NN 263506 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3403 MASTER TE NN 263741 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_negedge_reg[1] (M31_1P5V6T_SFFCKBRBQX2)
Chain[1] 3404 MASTER TE NN 263642 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3405 MASTER LS NN 256232 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/LOCKUP (M31_1P5V6T_DLATCHQX2)
DSLAVE TE NN 263644 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_negedge_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3406 MASTER LS NN 257164 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 266048 - GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\u_pmic_pbus_write_sync/u_rif_ctl/inc_r
if_clk_req_rif_bypass_fedge_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3407 MASTER TE NN 281078 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3408 MASTER TE NN 281079 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3409 MASTER TE NN 281077 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3410 MASTER TE NN 281074 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3411 MASTER TE NN 281080 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3412 MASTER TE NN 281082 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3413 MASTER TE NN 281081 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3414 MASTER TE NN 281075 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3415 MASTER TE NN 281076 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3416 MASTER TE NN 281085 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3417 MASTER TE NN 281084 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3418 MASTER LS NN 257138 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
DSLAVE TE NN 281086 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3419 MASTER TE NN 280748 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3420 MASTER TE NN 280752 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3421 MASTER TE NN 280749 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3422 MASTER TE NN 280751 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3423 MASTER TE NN 280746 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3424 MASTER TE NN 280753 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3425 MASTER TE NN 280756 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3426 MASTER TE NN 280758 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3427 MASTER TE NN 280757 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3428 MASTER TE NN 280754 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3429 MASTER TE NN 280747 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3430 MASTER LS NN 257116 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 280750 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3431 MASTER TE NN 280430 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3432 MASTER TE NN 280428 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
 Chain[1] 3433 MASTER TE NN 280429 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3434 MASTER TE NN 280425 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3435 MASTER TE NN 280426 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3436 MASTER TE NN 280421 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3437 MASTER TE NN 280423 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3438 MASTER TE NN 280424 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3439 MASTER TE NN 280422 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3440 MASTER TE NN 280418 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3441 MASTER TE NN 280420 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3442 MASTER LS NN 257090 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
DSLAVE TE NN 280419 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3443 MASTER TE NN 280101 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3444 MASTER TE NN 280099 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3445 MASTER TE NN 280100 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3446 MASTER TE NN 280091 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3447 MASTER TE NN 280094 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3448 MASTER TE NN 280096 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3449 MASTER TE NN 280090 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3450 MASTER TE NN 280093 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3451 MASTER TE NN 280092 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3452 MASTER TE NN 280089 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3453 MASTER TE NN 280097 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3454 MASTER LS NN 257066 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
DSLAVE TE NN 280095 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3455 MASTER TE NN 279773 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3456 MASTER TE NN 279771 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3457 MASTER TE NN 279772 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3458 MASTER TE NN 279769 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3459 MASTER TE NN 279764 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3460 MASTER TE NN 279763 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3461 MASTER TE NN 279768 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3462 MASTER TE NN 279762 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3463 MASTER TE NN 279767 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3464 MASTER TE NN 279761 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
 Chain[1] 3465 MASTER TE NN 279766 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3466 MASTER LS NN 257042 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
DSLAVE TE NN 279765 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3467 MASTER TE NN 279442 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3468 MASTER TE NN 279441 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3469 MASTER TE NN 279438 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3470 MASTER TE NN 279440 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3471 MASTER TE NN 279437 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3472 MASTER TE NN 279439 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3473 MASTER TE NN 279435 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3474 MASTER TE NN 279434 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3475 MASTER TE NN 279436 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND
_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1
p0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_
u/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3476 MASTER TE NN 279445 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3477 MASTER TE NN 279444 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3478 MASTER LS NN 257020 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX3)
DSLAVE TE NN 279446 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3479 MASTER TE NN 279092 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3480 MASTER TE NN 279091 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3481 MASTER TE NN 279090 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3482 MASTER TE NN 279088 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3483 MASTER TE NN 279245 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3484 MASTER TE NN 279246 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3485 MASTER TE NN 279253 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3486 MASTER TE NN 279250 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3487 MASTER TE NN 279251 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3488 MASTER TE NN 279249 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3489 MASTER TE NN 279248 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3490 MASTER TE NN 279247 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3491 MASTER LS NN 256992 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 279252 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3492 MASTER TE NN 278727 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3493 MASTER TE NN 278723 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3494 MASTER TE NN 278726 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3495 MASTER TE NN 278725 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3496 MASTER TE NN 278724 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3497 MASTER TE NN 278722 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3498 MASTER TE NN 278729 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3499 MASTER TE NN 278728 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3500 MASTER TE NN 278721 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3501 MASTER TE NN 278731 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3502 MASTER TE NN 278733 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3503 MASTER LS NN 256967 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
DSLAVE TE NN 278732 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3504 MASTER TE NN 278382 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3505 MASTER TE NN 278386 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3506 MASTER TE NN 278385 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3507 MASTER TE NN 278384 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3508 MASTER TE NN 278383 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3509 MASTER TE NN 278378 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3510 MASTER TE NN 278381 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3511 MASTER TE NN 278379 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3512 MASTER TE NN 278380 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3513 MASTER TE NN 278387 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3514 MASTER TE NN 278389 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3515 MASTER TE NN 278390 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3516 MASTER LS NN 256939 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
DSLAVE TE NN 278391 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3517 MASTER TE NN 278006 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3518 MASTER TE NN 278004 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3519 MASTER TE NN 278005 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3520 MASTER TE NN 278002 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3521 MASTER TE NN 277999 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3522 MASTER TE NN 278001 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3523 MASTER TE NN 277995 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3524 MASTER TE NN 277996 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3525 MASTER TE NN 277993 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3526 MASTER TE NN 277994 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3527 MASTER TE NN 278000 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3528 MASTER TE NN 277998 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3529 MASTER LS NN 256910 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
DSLAVE TE NN 277997 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
 Chain[1] 3530 MASTER TE NN 277609 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3531 MASTER TE NN 277611 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3532 MASTER TE NN 277610 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3533 MASTER TE NN 277767 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3534 MASTER TE NN 277766 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3535 MASTER TE NN 277765 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3536 MASTER TE NN 277764 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3537 MASTER TE NN 277773 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3538 MASTER TE NN 277607 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3539 MASTER TE NN 277769 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3540 MASTER TE NN 277768 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3541 MASTER TE NN 277763 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3542 MASTER LS NN 256883 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 277762 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3543 MASTER TE NN 277233 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3544 MASTER TE NN 277231 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3545 MASTER TE NN 277232 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3546 MASTER TE NN 277229 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3547 MASTER TE NN 277222 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3548 MASTER TE NN 277220 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3549 MASTER TE NN 277223 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3550 MASTER TE NN 277228 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3551 MASTER TE NN 277224 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3552 MASTER TE NN 277221 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3553 MASTER TE NN 277225 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3554 MASTER TE NN 277227 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3555 MASTER LS NN 256852 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
DSLAVE TE NN 277226 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3556 MASTER TE NN 277002 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3557 MASTER TE NN 276994 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3558 MASTER TE NN 277003 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3559 MASTER TE NN 276998 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3560 MASTER TE NN 276996 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3561 MASTER TE NN 277001 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3562 MASTER TE NN 276838 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
 Chain[1] 3563 MASTER TE NN 276999 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3564 MASTER TE NN 276997 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3565 MASTER TE NN 276995 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3566 MASTER TE NN 276840 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3567 MASTER TE NN 276841 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3568 MASTER LS NN 256824 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
DSLAVE TE NN 276842 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3569 MASTER TE NN 276463 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3570 MASTER TE NN 276465 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3571 MASTER TE NN 276464 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3572 MASTER TE NN 276458 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3573 MASTER TE NN 276460 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3574 MASTER TE NN 276456 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3575 MASTER TE NN 276455 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3576 MASTER TE NN 276454 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3577 MASTER TE NN 276461 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3578 MASTER TE NN 276614 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[0] (M31_1P5V6T_SFFSRBQX2)
Chain[1] 3579 MASTER TE NN 276457 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3580 MASTER TE NN 276453 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3581 MASTER LS NN 256798 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 276459 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3582 MASTER TE NN 276095 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3583 MASTER TE NN 276094 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3584 MASTER TE NN 276093 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3585 MASTER TE NN 276083 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3586 MASTER TE NN 276091 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3587 MASTER TE NN 276090 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3588 MASTER TE NN 276084 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3589 MASTER TE NN 276086 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3590 MASTER TE NN 276088 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3591 MASTER TE NN 276089 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3592 MASTER TE NN 276087 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3593 MASTER LS NN 256772 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX3)
DSLAVE TE NN 276085 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/PBUS_VSET_SYNC_reg_voltage_stepper_1p0_dig_sw_setpoint_sat_sync_u
/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[1] 3594 MASTER TE NN 275748 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3595 MASTER TE NN 275746 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3596 MASTER TE NN 275745 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3597 MASTER LS NN 256745 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
 DSLAVE TE NN 275747 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3598 MASTER TE NN 275342 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3599 MASTER TE NN 275344 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3600 MASTER TE NN 275343 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3601 MASTER LS NN 256720 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 275345 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3602 MASTER TE NN 274936 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3603 MASTER TE NN 274937 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3604 MASTER TE NN 274935 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3605 MASTER LS NN 256692 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX3)
DSLAVE TE NN 274938 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3606 MASTER TE NN 274534 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3607 MASTER TE NN 274536 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3608 MASTER TE NN 274535 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3609 MASTER LS NN 256665 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX3)
DSLAVE TE NN 274537 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3610 MASTER TE NN 274132 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3611 MASTER TE NN 274130 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3612 MASTER TE NN 274129 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3613 MASTER LS NN 256639 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 274131 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3614 MASTER TE NN 273726 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3615 MASTER TE NN 273728 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3616 MASTER TE NN 273727 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3617 MASTER LS NN 256606 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
DSLAVE TE NN 273729 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3618 MASTER TE NN 273323 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3619 MASTER TE NN 273321 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3620 MASTER TE NN 273322 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3621 MASTER LS NN 256579 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
DSLAVE TE NN 273324 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3622 MASTER TE NN 272921 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3623 MASTER TE NN 272919 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3624 MASTER TE NN 272920 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3625 MASTER LS NN 256554 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 272918 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3626 MASTER TE NN 272514 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3627 MASTER TE NN 272512 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3628 MASTER TE NN 272513 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3629 MASTER LS NN 256486 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/LO
CKUP (M31_1P5V6T_LOWLATCHX3)
DSLAVE TE NN 272511 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3630 MASTER TE NN 271356 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3631 MASTER TE NN 271357 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3632 MASTER TE NN 271355 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3633 MASTER TE NN 271359 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_load_flag_reg
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 3634 MASTER TE NN 271314 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_set_to_rsrv_hroom_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3635 MASTER TE NN 271338 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_wake_ctrl_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3636 MASTER TE NN 271232 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_force_wake_ps_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3637 MASTER TE NN 271341 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_disable_awake_refdac_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3638 MASTER TE NN 271217 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_comp_out_sync1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3639 MASTER LS NN 256429 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/LO
CKUP (M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 271215 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_a2d_comp_out_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3640 MASTER TE NN 270353 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_comp_out_sync1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3641 MASTER TE NN 270351 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_a2d_comp_out_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3642 MASTER TE NN 270368 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_force_wake_ps_dly_reg (M31_1P5V6T_SFFRBQX1)
 Chain[1] 3643 MASTER TE NN 270474 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_wake_ctrl_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3644 MASTER TE NN 270477 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_disable_awake_refdac_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3645 MASTER TE NN 270492 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3646 MASTER TE NN 270491 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3647 MASTER TE NN 270493 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3648 MASTER TE NN 270495 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_load_flag_reg
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 3649 MASTER LS NN 256365 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/LO
CKUP (M31_1P5V6T_LOWLATCHX3)
DSLAVE TE NN 270450 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_set_to_rsrv_hroom_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3650 MASTER TE NN 269503 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_force_wake_ps_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3651 MASTER TE NN 269611 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_disable_awake_refdac_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3652 MASTER TE NN 269486 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_a2d_comp_out_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3653 MASTER TE NN 269488 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_comp_out_sync1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3654 MASTER TE NN 269608 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_wake_ctrl_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3655 MASTER TE NN 269584 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_set_to_rsrv_hroom_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3656 MASTER TE NN 269629 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_load_flag_reg
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 3657 MASTER TE NN 269625 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3658 MASTER TE NN 269626 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3659 MASTER LS NN 257525 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/LO
CKUP (M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 269627 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3660 MASTER TE NN 285398 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3661 MASTER TE NN 287357 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_0_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3662 MASTER TE NN 287354 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_3_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3663 MASTER TE NN 287356 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3664 MASTER TE NN 287355 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_2_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3665 MASTER TE NN 287352 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_5_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3666 MASTER TE NN 287353 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_4_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3667 MASTER TE NN 287403 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_en_re
q_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3668 MASTER TE NN 287402 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_en_r
eq_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3669 MASTER TE NN 287350 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_clk_lfrc_req_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3670 MASTER TE NN 287351 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_ncll_pre_force_low_reg_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3671 MASTER TE NN 287358 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3672 MASTER TE NN 287360 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3673 MASTER TE NN 287361 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3674 MASTER TE NN 287359 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3675 MASTER TE NN 285189 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_force_wake_ps_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3676 MASTER TE NN 285175 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_a2d_comp_out_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3677 MASTER TE NN 285850 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_sync1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3678 MASTER TE NN 285401 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_disable_awake_refdac_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3679 MASTER TE NN 284964 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_glitchfree_mux_1p0_c
lk_qual_u/sel0_1_reg (M31_1P5V6T_SFFCKBRSBQX1)
Chain[1] 3680 MASTER TE NN 285172 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_window_pulse_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3681 MASTER TE NN 285174 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_ret_mode_dly_u/d_retention_mode_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3682 MASTER TE NN 285412 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3683 MASTER TE NN 285423 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_reg
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 3684 MASTER TE NN 285028 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3685 MASTER TE NN 285027 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3686 MASTER TE NN 285128 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_set_to_rsrv_hroom_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3687 MASTER TE NN 285420 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3688 MASTER TE NN 285422 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3689 MASTER TE NN 285421 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3690 MASTER TE NN 285026 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3691 MASTER LS NN 257455 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/LO
CKUP (M31_1P5V6T_LOWLATCHX3)
DSLAVE TE NN 285025 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3692 MASTER TE NN 284099 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3693 MASTER TE NN 284100 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3694 MASTER TE NN 284483 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3695 MASTER TE NN 284482 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3696 MASTER TE NN 284233 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_window_pulse_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3697 MASTER TE NN 284197 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_set_to_rsrv_hroom_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3698 MASTER TE NN 284484 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_reg
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 3699 MASTER TE NN 287327 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3700 MASTER TE NN 286998 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3701 MASTER TE NN 286997 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3702 MASTER TE NN 286996 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3703 MASTER TE NN 286990 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_5_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3704 MASTER TE NN 286992 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_3_reg (M31_1P5V6T_SFFCKBRBQX1)
 Chain[1] 3705 MASTER TE NN 286995 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_0_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3706 MASTER TE NN 286994 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3707 MASTER TE NN 286993 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_2_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3708 MASTER TE NN 286991 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_4_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3709 MASTER TE NN 286989 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_ncll_pre_force_low_reg_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3710 MASTER TE NN 286988 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_clk_lfrc_req_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3711 MASTER TE NN 287039 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_en_r
eq_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3712 MASTER TE NN 287040 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_en_re
q_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3713 MASTER TE NN 284459 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3714 MASTER TE NN 284250 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_force_wake_ps_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3715 MASTER TE NN 284462 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_disable_awake_refdac_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3716 MASTER TE NN 284910 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_sync1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3717 MASTER TE NN 284236 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_a2d_comp_out_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3718 MASTER TE NN 284481 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3719 MASTER TE NN 284035 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_glitchfree_mux_1p0_c
lk_qual_u/sel0_1_reg (M31_1P5V6T_SFFCKBRSBQX1)
Chain[1] 3720 MASTER TE NN 284235 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_ret_mode_dly_u/d_retention_mode_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3721 MASTER TE NN 284473 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3722 MASTER TE NN 284098 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3723 MASTER LS NN 257378 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/LO
CKUP (M31_1P5V6T_LOWLATCHX1)
DSLAVE TE NN 284097 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3724 MASTER TE NN 283522 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3725 MASTER TE NN 286630 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_3_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3726 MASTER TE NN 286632 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3727 MASTER TE NN 286631 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_2_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3728 MASTER TE NN 286628 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_5_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3729 MASTER TE NN 286629 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_4_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3730 MASTER TE NN 286636 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3731 MASTER TE NN 286634 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3732 MASTER TE NN 286635 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3733 MASTER TE NN 286633 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_0_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3734 MASTER TE NN 286626 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_clk_lfrc_req_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3735 MASTER TE NN 286627 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_ncll_pre_force_low_reg_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3736 MASTER TE NN 286637 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3737 MASTER TE NN 286679 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_en_re
q_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3738 MASTER TE NN 286678 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_en_r
eq_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3739 MASTER TE NN 283106 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_glitchfree_mux_1p0_c
lk_qual_u/sel0_1_reg (M31_1P5V6T_SFFCKBRSBQX1)
Chain[1] 3740 MASTER TE NN 283301 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_window_pulse_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3741 MASTER TE NN 283303 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_ret_mode_dly_u/d_retention_mode_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3742 MASTER TE NN 283536 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3743 MASTER TE NN 283267 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_set_to_rsrv_hroom_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3744 MASTER TE NN 283547 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_reg
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 3745 MASTER TE NN 283169 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3746 MASTER TE NN 283168 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3747 MASTER TE NN 283304 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_a2d_comp_out_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3748 MASTER TE NN 283973 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_sync1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3749 MASTER TE NN 283171 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3750 MASTER TE NN 283170 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3751 MASTER TE NN 283544 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3752 MASTER TE NN 283545 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3753 MASTER TE NN 283546 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3754 MASTER TE NN 283525 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_disable_awake_refdac_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3755 MASTER LS NN 257595 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 283318 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_force_wake_ps_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3756 MASTER TE NN 286317 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_en_re
q_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3757 MASTER TE NN 286316 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_en_r
eq_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3758 MASTER TE NN 282338 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_set_to_rsrv_hroom_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3759 MASTER TE NN 282623 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_reg
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 3760 MASTER TE NN 282622 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3761 MASTER TE NN 282620 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3762 MASTER TE NN 282621 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3763 MASTER TE NN 282240 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3764 MASTER TE NN 282241 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3765 MASTER TE NN 282239 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3766 MASTER TE NN 282238 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3767 MASTER TE NN 282612 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3768 MASTER TE NN 282598 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3769 MASTER TE NN 282601 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_disable_awake_refdac_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3770 MASTER TE NN 282391 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_force_wake_ps_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3771 MASTER TE NN 282376 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_ret_mode_dly_u/d_retention_mode_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3772 MASTER TE NN 282374 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_window_pulse_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3773 MASTER TE NN 282177 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_glitchfree_mux_1p0_c
lk_qual_u/sel0_1_reg (M31_1P5V6T_SFFCKBRSBQX1)
Chain[1] 3774 MASTER TE NN 283051 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_sync1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3775 MASTER TE NN 282377 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[2]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_a2d_comp_out_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3776 MASTER TE NN 286275 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3777 MASTER TE NN 286272 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3778 MASTER TE NN 286273 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3779 MASTER TE NN 286264 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_clk_lfrc_req_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3780 MASTER TE NN 286271 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_0_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3781 MASTER TE NN 286268 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_3_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3782 MASTER TE NN 286266 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_5_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3783 MASTER TE NN 286274 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3784 MASTER TE NN 286265 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_ncll_pre_force_low_reg_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3785 MASTER TE NN 286267 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_4_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3786 MASTER TE NN 286269 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_2_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3787 MASTER LS NN 257561 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 286270 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[2]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3788 MASTER TE NN 285954 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_en_r
eq_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3789 MASTER TE NN 285955 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_en_re
q_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3790 MASTER TE NN 285912 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[2] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3791 MASTER TE NN 285903 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_ncll_pre_force_low_reg_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3792 MASTER TE NN 285905 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_4_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3793 MASTER TE NN 285907 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_2_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3794 MASTER TE NN 285906 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_3_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3795 MASTER TE NN 285909 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_0_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3796 MASTER TE NN 285908 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_1_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3797 MASTER TE NN 285904 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_en_5_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3798 MASTER TE NN 285902 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_fsm_clk_lfrc_req_reg (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3799 MASTER TE NN 285911 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[1] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3800 MASTER TE NN 285913 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[3] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3801 MASTER TE NN 285910 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[1]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_glue_logic/d_mode_fsm_reg[0] (M31_1P5V6T_SFFCKBRBQX1)
Chain[1] 3802 MASTER TE NN 281462 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_force_wake_ps_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3803 MASTER TE NN 281448 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_a2d_comp_out_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3804 MASTER TE NN 282121 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_sync1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[1] 3805 MASTER TE NN 281672 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_disable_awake_refdac_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3806 MASTER TE NN 281445 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_window_pulse_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3807 MASTER TE NN 281248 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_glitchfree_mux_1p0_c
lk_qual_u/sel0_1_reg (M31_1P5V6T_SFFCKBRSBQX1)
Chain[1] 3808 MASTER TE NN 281447 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_ret_mode_dly_u/d_retention_mode_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3809 MASTER TE NN 281669 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_reg (M31_1P5V6T_SFFSBQX1)
Chain[1] 3810 MASTER TE NN 281683 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3811 MASTER TE NN 281311 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3812 MASTER TE NN 281312 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3813 MASTER TE NN 281409 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_set_to_rsrv_hroom_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3814 MASTER TE NN 281694 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_reg
(M31_1P5V6T_SFFSRBQX1)
Chain[1] 3815 MASTER TE NN 281691 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_en_req_reg (M31_1P5V6T_SFFRBQX1)
Chain[1] 3816 MASTER TE NN 281692 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3817 MASTER TE NN 281693 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_vset_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3818 MASTER TE NN 281309 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3819 MASTER LS NN 257787 + GPIO_07
I_DCORE/LOCKUP (M31_1P5V6T_LOWLATCHX2)
DSLAVE TE NN 281310 - GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[1]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_reg
(M31_1P5V6T_SFFRBQX1)
Chain[1] 3820 MASTER TE NN 288692 - GPIO_07
I_DCORE/\SNPS_PipeHead_u_waimea_dcore_glue/u_dft_test_ctrl/scan_chain_in[1]_1
(M31_1P5V6T_SFFQX1J)
Chain[2] 0 MASTER LE NN 288695 + GPIO_07
I_DCORE/\SNPS_PipeTail_u_waimea_dcore_glue/u_dft_test_ctrl/scan_chain_out[2]_1
(M31_1P5V6T_DFFQX1)
Chain[2] 1 MASTER LE NN 270031 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256364 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/LO
CKUP1 (M31_1P5V6T_LOWLATCHX3)
Chain[2] 2 MASTER LE NN 269790 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3 MASTER LE NN 269775 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 4 MASTER LE NN 269778 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 5 MASTER LE NN 269785 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 6 MASTER LE NN 269777 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[2] 7 MASTER LE NN 269786 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 8 MASTER LE NN 269782 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 9 MASTER LE NN 269781 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 10 MASTER LE NN 269796 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 11 MASTER LE NN 269789 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 12 MASTER LE NN 269958 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[7] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 13 MASTER LE NN 269959 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[7] (M31_1P5V6T_SFFSRBQX2J)
Chain[2] 14 MASTER LE NN 269955 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 15 MASTER LE NN 269957 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 16 MASTER LE NN 269953 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 17 MASTER LE NN 269951 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 18 MASTER LE NN 269266 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 19 MASTER LE NN 269263 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 20 MASTER LE NN 269261 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 21 MASTER LE NN 269265 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 22 MASTER LE NN 269262 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 23 MASTER LE NN 269215 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 24 MASTER LE NN 269561 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 25 MASTER LE NN 269555 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_clear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 26 MASTER LE NN 269553 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_clear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 27 MASTER LE NN 269554 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_error_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 28 MASTER LE NN 269523 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync11/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 29 MASTER LE NN 269552 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync6/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 30 MASTER LE NN 269519 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 31 MASTER LE NN 269260 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[9] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 32 MASTER LE NN 269591 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 33 MASTER LE NN 269264 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 34 MASTER LE NN 269213 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 35 MASTER LE NN 269214 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 36 MASTER LE NN 269615 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vset_valid_sync_first_reg
(M31_1P5V6T_SFFSBQX1)
Chain[2] 37 MASTER LE NN 269616 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vset_valid_sync_reg
(M31_1P5V6T_SFFSBQX1)
Chain[2] 38 MASTER LE NN 269556 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 39 MASTER LE NN 269558 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 40 MASTER LE NN 270033 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 41 MASTER LE NN 269618 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 42 MASTER LE NN 269559 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 43 MASTER LE NN 269557 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 44 MASTER LE NN 269560 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_s
tate_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 45 MASTER LE NN 269549 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_s
tate_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 46 MASTER LE NN 269550 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 47 MASTER LE NN 270035 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_s
tate_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 48 MASTER LE NN 269562 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 49 MASTER LE NN 269401 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 50 MASTER LE NN 269403 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 51 MASTER LE NN 269402 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 52 MASTER LE NN 269400 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 53 MASTER LE NN 269399 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 54 MASTER LE NN 269404 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 55 MASTER LE NN 269405 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 56 MASTER LE NN 269408 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[2] 57 MASTER LE NN 269407 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[2] 58 MASTER LE NN 269476 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 59 MASTER LE NN 269467 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/u_slib_sync_1p0_freq_data_ready/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 60 MASTER LE NN 269477 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 61 MASTER LE NN 269468 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_data_ready_hf_sync_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 62 MASTER LE NN 269485 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_data_ready_hf_sync_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 63 MASTER LE NN 269406 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 64 MASTER LE NN 269393 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_curr_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 65 MASTER LE NN 269465 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/slib_clkreq_gate_1p0_hf_clk_u1/clk_en
_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 66 MASTER LE NN 269568 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 67 MASTER LE NN 269221 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 68 MASTER LE NN 269409 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_sqm_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 69 MASTER LE NN 269567 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 70 MASTER LE NN 269217 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 71 MASTER LE NN 269216 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 72 MASTER LE NN 269210 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[11] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 73 MASTER LE NN 269211 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[10] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 74 MASTER LE NN 269259 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[10] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 75 MASTER LE NN 269258 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[11] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 76 MASTER LE NN 269212 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[9] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 77 MASTER LE NN 269220 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 78 MASTER LE NN 269219 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 79 MASTER LE NN 269396 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_curr_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 80 MASTER LE NN 269392 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 81 MASTER LE NN 271826 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__ATEST1_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 82 MASTER LE NN 271808 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM3__AUTO_THRS_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 83 MASTER LE NN 271810 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM3__AUTO_THRS_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 84 MASTER LE NN 271832 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__OPEN_LOOP_TEST_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 85 MASTER LE NN 271852 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST4__ECM_INPUT_MUX_CTRL_reg/dout
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 86 MASTER LE NN 271813 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM2__INZERO_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 87 MASTER LE NN 271850 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST4__ECM_INPUT_MUX_CTRL_reg/dout
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 88 MASTER LE NN 271809 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM3__AUTO_THRS_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 89 MASTER LE NN 271833 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__ATEST2_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 90 MASTER LE NN 271867 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CAL_EN_CTL1__INZERO_TRIM_CAL_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 91 MASTER LE NN 271895 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_SWITCH_SIZE_CTL__N_SWITCH_SIZE_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 92 MASTER LE NN 271869 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CAL_EN_CTL1__IPLIM_TRIM_CAL_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 93 MASTER LE NN 271866 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CAL_EN_CTL1__INLIM_TRIM_CAL_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 94 MASTER LE NN 271839 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__IPLIM_TEST_CTRL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 95 MASTER LE NN 271896 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_SWITCH_SIZE_CTL__P_SWITCH_SIZE_reg/dout_re
g[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 96 MASTER LE NN 271874 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_INZERO_CTL__INZERO_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 97 MASTER LE NN 271871 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_INZERO_CTL__INZERO_FORCE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 98 MASTER LE NN 271872 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_INZERO_CTL__INZERO_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 99 MASTER LE NN 271900 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_QM_PS_ENTRY__QMODE_PS_ENTRY_reg/dout_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[2] 100 MASTER LE NN 271835 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__ATEST2_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 101 MASTER LE NN 271834 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__ATEST2_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 102 MASTER LE NN 271868 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CAL_EN_CTL1__AUTO_THRES_TRIM_CAL_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 103 MASTER LE NN 271842 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST3_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 104 MASTER LE NN 271843 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST3_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 105 MASTER LE NN 271901 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_QM_PS_ENTRY__QMODE_PS_ENTRY_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[2] 106 MASTER LE NN 271837 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__DTEST2_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 107 MASTER LE NN 271822 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 108 MASTER LE NN 271917 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_PFM_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 109 MASTER LE NN 271877 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_BLNK_TIME_CTL__MIN_PON_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 110 MASTER LE NN 271873 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_INZERO_CTL__INZERO_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 111 MASTER LE NN 271919 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_RET_SEL_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 112 MASTER LE NN 271899 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_QM_PS_ENTRY__QMODE_PS_ENTRY_reg/dout_reg[2
] (M31_1P5V6T_SFFSBQX1)
Chain[2] 113 MASTER LE NN 271898 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_QM_PS_ENTRY__QMODE_PS_ENTRY_reg/dout_reg[3
] (M31_1P5V6T_SFFRBQX1)
Chain[2] 114 MASTER LE NN 271894 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_SWITCH_SIZE_CTL__N_SWITCH_SIZE_reg/dout_re
g[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 115 MASTER LE NN 271897 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_SWITCH_SIZE_CTL__P_SWITCH_SIZE_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 116 MASTER LE NN 271928 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_AUTOINT_S
EL_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[2] 117 MASTER LE NN 271784 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 118 MASTER LE NN 271791 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor17_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 119 MASTER LE NN 271796 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_core/hfs_ps_pwm_curr_lim_logic_u1/switch_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 120 MASTER LE NN 271770 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 121 MASTER LE NN 271790 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor16_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 122 MASTER LE NN 271777 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 123 MASTER LE NN 271776 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 124 MASTER LE NN 271774 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 125 MASTER LE NN 271794 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor20_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 126 MASTER LE NN 269377 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/slib_clkreq_gate_1p0_clk_u1/clk_en_sy
nc_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 127 MASTER LE NN 271778 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 128 MASTER LE NN 271779 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 129 MASTER LE NN 271772 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 130 MASTER LE NN 271771 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 131 MASTER LE NN 271769 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
 Chain[2] 132 MASTER LE NN 271787 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 133 MASTER LE NN 271780 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 134 MASTER LE NN 271773 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor22_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 135 MASTER LE NN 271789 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor15_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 136 MASTER LE NN 271788 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor14_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 137 MASTER LE NN 271795 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor21_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 138 MASTER LE NN 271792 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor18_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 139 MASTER LE NN 271793 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor19_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 140 MASTER LE NN 271782 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 141 MASTER LE NN 271783 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 142 MASTER LE NN 271781 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 143 MASTER LE NN 271875 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_BLNK_TIME_CTL__ISNS_BLNK_TIME_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 144 MASTER LE NN 271921 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_RET_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 145 MASTER LE NN 271920 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_RET_SEL_r
eg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[2] 146 MASTER LE NN 271927 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_AUTOINT_S
EL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 147 MASTER LE NN 271929 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_AUTOINT_S
EL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 148 MASTER LE NN 271828 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__ATEST1_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 149 MASTER LE NN 271827 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__ATEST1_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 150 MASTER LE NN 269218 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 151 MASTER LE NN 269391 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 152 MASTER LE NN 269395 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_curr_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 153 MASTER LE NN 269398 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_sqm_timer_start_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 154 MASTER LE NN 269394 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_wait_timer_start_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 155 MASTER LE NN 269469 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_grey_counter_capture_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 156 MASTER LE NN 269479 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 157 MASTER LE NN 269475 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 158 MASTER LE NN 269474 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 159 MASTER LE NN 269466 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/u_slib_sync_1p0_freq_data_ready/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 160 MASTER LE NN 270030 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 161 MASTER LE NN 269378 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 162 MASTER LE NN 269382 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 163 MASTER LE NN 269379 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 164 MASTER LE NN 269381 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_data_ready_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 165 MASTER LE NN 269380 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 166 MASTER LE NN 269228 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 167 MASTER LE NN 269225 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 168 MASTER LE NN 269222 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 169 MASTER LE NN 269478 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 170 MASTER LE NN 269471 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 171 MASTER LE NN 269470 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 172 MASTER LE NN 269472 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 173 MASTER LE NN 269473 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 174 MASTER LE NN 271811 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM2__INZERO_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 175 MASTER LE NN 271807 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM3__AUTO_THRS_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 176 MASTER LE NN 271829 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__DTEST1_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 177 MASTER LE NN 271857 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__AFSM_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 178 MASTER LE NN 271814 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM2__INZERO_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 179 MASTER LE NN 271818 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM1__PWM_IPLIM_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 180 MASTER LE NN 271816 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM1__PWM_IPLIM_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 181 MASTER LE NN 271815 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM1__PWM_IPLIM_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 182 MASTER LE NN 271854 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__ILIM_DLY_SEL_reg/dout_re
g[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 183 MASTER LE NN 271912 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ILIM_SS_CTL__ILIM_SS_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 184 MASTER LE NN 271855 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__ILIM_DLY_SEL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 185 MASTER LE NN 271805 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM4__PFM_IPLIM_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 186 MASTER LE NN 271910 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ILIM_SS_CTL__ILIM_SS_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 187 MASTER LE NN 271934 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_CURRENT_LIM_CTRL_
SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 188 MASTER LE NN 271860 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 189 MASTER LE NN 271903 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PS_ENTRY_PWM_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 190 MASTER LE NN 271906 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PFM_ENTRY_AUTO_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 191 MASTER LE NN 271865 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 192 MASTER LE NN 271863 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 193 MASTER LE NN 271859 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 194 MASTER LE NN 271905 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PS_ENTRY_PWM_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 195 MASTER LE NN 271909 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PFM_ENTRY_AUTO_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 196 MASTER LE NN 271862 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 197 MASTER LE NN 271861 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 198 MASTER LE NN 271883 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__APT_STEPDOWN_PSW_DEAD_TIME
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 199 MASTER LE NN 271902 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PS_ENTRY_PWM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 200 MASTER LE NN 271858 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 201 MASTER LE NN 271908 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PFM_ENTRY_AUTO_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 202 MASTER LE NN 271904 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PS_ENTRY_PWM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 203 MASTER LE NN 271880 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__NSW_DEAD_TIME_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 204 MASTER LE NN 271881 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__NSW_DEAD_TIME_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 205 MASTER LE NN 271870 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DIG_FSM_CTL__FSM_LAT_DIS_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 206 MASTER LE NN 271798 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 207 MASTER LE NN 271802 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 208 MASTER LE NN 271801 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_re
g/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 209 MASTER LE NN 271800 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 210 MASTER LE NN 271799 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 211 MASTER LE NN 271878 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__PSW_DEAD_TIME_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 212 MASTER LE NN 271886 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__N_ON_DRIVER_SIZE_reg/
dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 213 MASTER LE NN 271887 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__N_ON_DRIVER_SIZE_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 214 MASTER LE NN 271879 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__PSW_DEAD_TIME_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 215 MASTER LE NN 271892 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__P_OFF_DRIVER_SIZE_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 216 MASTER LE NN 271884 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__APT_STEPDOWN_NSW_DEAD_TIME
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 217 MASTER LE NN 271890 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__P_ON_DRIVER_SIZE_reg/
dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 218 MASTER LE NN 271882 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__APT_STEPDOWN_PSW_DEAD_TIME
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 219 MASTER LE NN 271888 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__N_OFF_DRIVER_SIZE_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 220 MASTER LE NN 271891 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__P_ON_DRIVER_SIZE_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 221 MASTER LE NN 271889 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__N_OFF_DRIVER_SIZE_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 222 MASTER LE NN 271893 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__P_OFF_DRIVER_SIZE_reg
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 223 MASTER LE NN 271885 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__APT_STEPDOWN_NSW_DEAD_TIME
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 224 MASTER LE NN 271864 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 225 MASTER LE NN 271907 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PFM_ENTRY_AUTO_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 226 MASTER LE NN 271856 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__ILIM_DLY_SEL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 227 MASTER LE NN 271933 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_CURRENT_LIM_CTRL_
SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 228 MASTER LE NN 271806 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM4__PFM_IPLIM_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 229 MASTER LE NN 271932 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_CURRENT_LIM_CTRL_
SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 230 MASTER LE NN 271804 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM4__PFM_IPLIM_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 231 MASTER LE NN 271853 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__ILIM_DLY_SEL_reg/dout_re
g[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 232 MASTER LE NN 271831 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__DTEST1_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 233 MASTER LE NN 271830 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__DTEST1_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 234 MASTER LE NN 271803 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM4__PFM_IPLIM_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 235 MASTER LE NN 271812 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM2__INZERO_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 236 MASTER LE NN 271849 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST4__ECM_TEST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 237 MASTER LE NN 271851 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST4__ECM_INPUT_MUX_CTRL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 238 MASTER LE NN 271840 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__IPLIM_TEST_CTRL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 239 MASTER LE NN 271823 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_FORCE_FET_TEST__KELVIN_SENSING_TEST_EN_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 240 MASTER LE NN 271836 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__DTEST2_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 241 MASTER LE NN 271824 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_FORCE_FET_TEST__FORCE_PFET_NFET_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 242 MASTER LE NN 271935 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_IPLIM_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 243 MASTER LE NN 271924 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_PWM_SEL_r
eg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[2] 244 MASTER LE NN 271844 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST4_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 245 MASTER LE NN 271847 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__EN_SENSE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 246 MASTER LE NN 271914 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CURRENT_LIM_CTL__RET_PFM_PWM_CURRENT_LIM_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 247 MASTER LE NN 271845 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST4_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 248 MASTER LE NN 271841 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST3_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 249 MASTER LE NN 271930 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_AUTOINT_S
EL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 250 MASTER LE NN 271922 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_RET_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 251 MASTER LE NN 271925 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_PWM_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 252 MASTER LE NN 271821 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 253 MASTER LE NN 271820 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 254 MASTER LE NN 271916 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_PFM_SEL_r
eg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[2] 255 MASTER LE NN 271819 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 256 MASTER LE NN 271876 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_BLNK_TIME_CTL__MIN_PON_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 257 MASTER LE NN 271797 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_core/hfs_ps_trim_logic/d_l2r_cal_comp_state_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 258 MASTER LE NN 271918 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_PFM_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 259 MASTER LE NN 271926 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_PWM_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 260 MASTER LE NN 271838 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__DTEST2_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 261 MASTER LE NN 271915 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_PFM_SEL_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 262 MASTER LE NN 271923 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_PWM_SEL_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 263 MASTER LE NN 271846 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST4_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 264 MASTER LE NN 271848 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__EN_ADC_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 265 MASTER LE NN 271911 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ILIM_SS_CTL__ILIM_SS_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 266 MASTER LE NN 271825 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_FORCE_FET_TEST__FORCE_PFET_NFET_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 267 MASTER LE NN 271817 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM1__PWM_IPLIM_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 268 MASTER LE NN 271931 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_CURRENT_LIM_CTRL_
SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 269 MASTER LE NN 271913 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ILIM_SS_CTL__ILIM_SS_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 270 MASTER LE NN 269230 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[2] 271 MASTER LE NN 269231 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[2] 272 MASTER LE NN 269229 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[2] 273 MASTER LE NN 269223 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 274 MASTER LE NN 269224 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 275 MASTER LE NN 269226 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 276 MASTER LE NN 269227 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 277 MASTER LE NN 269208 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX2J)
Chain[2] 278 MASTER LE NN 269185 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 279 MASTER LE NN 271775 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 280 MASTER LE NN 271785 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 281 MASTER LE NN 271786 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[1]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 282 MASTER LE NN 269155 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256307 - GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
Chain[2] 283 MASTER LE NN 269156 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 284 MASTER LE NN 269153 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 285 MASTER LE NN 269165 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 286 MASTER LE NN 269166 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 287 MASTER LE NN 269162 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 288 MASTER LE NN 269168 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 289 MASTER LE NN 269169 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 290 MASTER LE NN 269167 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 291 MASTER LE NN 269172 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 292 MASTER LE NN 269141 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 293 MASTER LE NN 269157 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 294 MASTER LE NN 269173 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 295 MASTER LE NN 269154 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 296 MASTER LE NN 269161 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_INVERT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 297 MASTER LE NN 269171 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX2)
Chain[2] 298 MASTER LE NN 269150 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 299 MASTER LE NN 269151 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 300 MASTER LE NN 269152 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_EN_
CTL__PERPH_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 301 MASTER LE NN 269138 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_ok/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 302 MASTER LE NN 269137 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
 Chain[2] 303 MASTER LE NN 269136 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 304 MASTER LE NN 269139 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_val
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 305 MASTER LE NN 269140 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 306 MASTER LE NN 269142 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 307 MASTER LE NN 269149 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 308 MASTER LE NN 269148 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 309 MASTER LE NN 269159 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 310 MASTER LE NN 269147 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 311 MASTER LE NN 269160 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 312 MASTER LE NN 269143 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 313 MASTER LE NN 269144 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 314 MASTER LE NN 269146 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 315 MASTER LE NN 269145 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 316 MASTER LE NN 269170 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 317 MASTER LE NN 269164 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 318 MASTER LE NN 269163 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 319 MASTER LE NN 269158 + GPIO_07
I_DCORE/\gpio_rmod_gen[9]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 320 MASTER LE NN 269104 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256304 - GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
Chain[2] 321 MASTER LE NN 269103 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 322 MASTER LE NN 269102 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 323 MASTER LE NN 269125 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 324 MASTER LE NN 269126 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 325 MASTER LE NN 269113 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 326 MASTER LE NN 269098 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 327 MASTER LE NN 269099 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 328 MASTER LE NN 269112 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 329 MASTER LE NN 269134 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 330 MASTER LE NN 269129 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 331 MASTER LE NN 269132 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 332 MASTER LE NN 269135 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 333 MASTER LE NN 269127 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 334 MASTER LE NN 269114 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_EN_
CTL__PERPH_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 335 MASTER LE NN 269130 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 336 MASTER LE NN 269124 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 337 MASTER LE NN 269107 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 338 MASTER LE NN 269108 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 339 MASTER LE NN 269122 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 340 MASTER LE NN 269131 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 341 MASTER LE NN 269100 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_ok/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 342 MASTER LE NN 269101 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_val
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 343 MASTER LE NN 269128 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 344 MASTER LE NN 269121 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 345 MASTER LE NN 269133 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 346 MASTER LE NN 269116 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 347 MASTER LE NN 269115 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 348 MASTER LE NN 269117 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 349 MASTER LE NN 269118 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 350 MASTER LE NN 269123 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_INVERT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 351 MASTER LE NN 269119 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 352 MASTER LE NN 269120 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 353 MASTER LE NN 269109 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 354 MASTER LE NN 269110 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 355 MASTER LE NN 269106 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 356 MASTER LE NN 269111 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 357 MASTER LE NN 269105 + GPIO_07
I_DCORE/\gpio_rmod_gen[8]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 358 MASTER LE NN 269066 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256301 - GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
Chain[2] 359 MASTER LE NN 269076 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_EN_
CTL__PERPH_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
 Chain[2] 360 MASTER LE NN 269065 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 361 MASTER LE NN 269082 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 362 MASTER LE NN 269086 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 363 MASTER LE NN 269069 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 364 MASTER LE NN 269071 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 365 MASTER LE NN 269072 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 366 MASTER LE NN 269084 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 367 MASTER LE NN 269070 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 368 MASTER LE NN 269083 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 369 MASTER LE NN 269081 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 370 MASTER LE NN 269093 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 371 MASTER LE NN 269085 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_INVERT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 372 MASTER LE NN 269095 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX2)
Chain[2] 373 MASTER LE NN 269096 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 374 MASTER LE NN 269074 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 375 MASTER LE NN 269075 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 376 MASTER LE NN 269097 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 377 MASTER LE NN 269080 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 378 MASTER LE NN 269079 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 379 MASTER LE NN 269077 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 380 MASTER LE NN 269078 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 381 MASTER LE NN 269094 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 382 MASTER LE NN 269092 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 383 MASTER LE NN 269091 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 384 MASTER LE NN 269088 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 385 MASTER LE NN 269089 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 386 MASTER LE NN 269090 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 387 MASTER LE NN 269087 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 388 MASTER LE NN 269064 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 389 MASTER LE NN 269067 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 390 MASTER LE NN 269073 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 391 MASTER LE NN 269068 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 392 MASTER LE NN 269063 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_val
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 393 MASTER LE NN 269062 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_ok/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 394 MASTER LE NN 269060 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 395 MASTER LE NN 269061 + GPIO_07
I_DCORE/\gpio_rmod_gen[7]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 396 MASTER LE NN 269044 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256298 - GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
Chain[2] 397 MASTER LE NN 269046 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 398 MASTER LE NN 269043 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 399 MASTER LE NN 269045 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 400 MASTER LE NN 269047 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_INVERT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 401 MASTER LE NN 269048 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 402 MASTER LE NN 269034 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 403 MASTER LE NN 269033 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 404 MASTER LE NN 269031 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 405 MASTER LE NN 269022 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 406 MASTER LE NN 269023 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 407 MASTER LE NN 269036 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 408 MASTER LE NN 269041 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 409 MASTER LE NN 269042 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 410 MASTER LE NN 269039 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 411 MASTER LE NN 269040 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 412 MASTER LE NN 269025 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_val
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 413 MASTER LE NN 269026 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 414 MASTER LE NN 269027 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 415 MASTER LE NN 269049 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 416 MASTER LE NN 269032 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 417 MASTER LE NN 269051 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 418 MASTER LE NN 269038 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_EN_
CTL__PERPH_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 419 MASTER LE NN 269050 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 420 MASTER LE NN 269028 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 421 MASTER LE NN 269024 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_ok/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 422 MASTER LE NN 269055 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 423 MASTER LE NN 269052 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 424 MASTER LE NN 269035 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 425 MASTER LE NN 269030 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 426 MASTER LE NN 269053 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 427 MASTER LE NN 269037 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 428 MASTER LE NN 269058 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 429 MASTER LE NN 269056 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 430 MASTER LE NN 269059 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 431 MASTER LE NN 269057 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 432 MASTER LE NN 269054 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 433 MASTER LE NN 269029 + GPIO_07
I_DCORE/\gpio_rmod_gen[6]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 434 MASTER LE NN 268997 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
DSLAVE LS NN 256294 - GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX3)
Chain[2] 435 MASTER LE NN 268992 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 436 MASTER LE NN 268991 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 437 MASTER LE NN 269014 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 438 MASTER LE NN 269017 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 439 MASTER LE NN 269021 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 440 MASTER LE NN 269018 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 441 MASTER LE NN 269019 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 442 MASTER LE NN 269016 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 443 MASTER LE NN 269015 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 444 MASTER LE NN 269020 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 445 MASTER LE NN 268994 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 446 MASTER LE NN 268990 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 447 MASTER LE NN 268988 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 448 MASTER LE NN 268993 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 449 MASTER LE NN 268999 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 450 MASTER LE NN 268996 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 451 MASTER LE NN 269000 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_EN_
CTL__PERPH_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 452 MASTER LE NN 268986 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_ok/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 453 MASTER LE NN 268987 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_val
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 454 MASTER LE NN 269008 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 455 MASTER LE NN 269010 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 456 MASTER LE NN 269013 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 457 MASTER LE NN 269006 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 458 MASTER LE NN 268995 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 459 MASTER LE NN 269001 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 460 MASTER LE NN 268989 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 461 MASTER LE NN 268998 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 462 MASTER LE NN 269011 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 463 MASTER LE NN 269012 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 464 MASTER LE NN 269007 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 465 MASTER LE NN 269009 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_INVERT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 466 MASTER LE NN 269005 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 467 MASTER LE NN 269002 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 468 MASTER LE NN 269004 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 469 MASTER LE NN 269003 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 470 MASTER LE NN 268985 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 471 MASTER LE NN 268984 + GPIO_07
I_DCORE/\gpio_rmod_gen[5]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 472 MASTER LE NN 268979 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256291 - GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
Chain[2] 473 MASTER LE NN 268954 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 474 MASTER LE NN 268978 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
 Chain[2] 475 MASTER LE NN 268959 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 476 MASTER LE NN 268953 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 477 MASTER LE NN 268976 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 478 MASTER LE NN 268981 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 479 MASTER LE NN 268983 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 480 MASTER LE NN 268980 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 481 MASTER LE NN 268957 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 482 MASTER LE NN 268961 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 483 MASTER LE NN 268966 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 484 MASTER LE NN 268965 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 485 MASTER LE NN 268964 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 486 MASTER LE NN 268975 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 487 MASTER LE NN 268974 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 488 MASTER LE NN 268951 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 489 MASTER LE NN 268952 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 490 MASTER LE NN 268969 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 491 MASTER LE NN 268972 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 492 MASTER LE NN 268956 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 493 MASTER LE NN 268970 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 494 MASTER LE NN 268968 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 495 MASTER LE NN 268955 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 496 MASTER LE NN 268958 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 497 MASTER LE NN 268967 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 498 MASTER LE NN 268973 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 499 MASTER LE NN 268971 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_INVERT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 500 MASTER LE NN 268960 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 501 MASTER LE NN 268963 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 502 MASTER LE NN 268977 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 503 MASTER LE NN 268982 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 504 MASTER LE NN 268950 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 505 MASTER LE NN 268949 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_val
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 506 MASTER LE NN 268962 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_EN_
CTL__PERPH_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 507 MASTER LE NN 268948 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_ok/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 508 MASTER LE NN 268946 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 509 MASTER LE NN 268947 + GPIO_07
I_DCORE/\gpio_rmod_gen[4]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 510 MASTER LE NN 268911 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_val
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
DSLAVE LS NN 256287 - GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
Chain[2] 511 MASTER LE NN 268910 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_ok/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 512 MASTER LE NN 268915 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 513 MASTER LE NN 268921 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 514 MASTER LE NN 268916 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 515 MASTER LE NN 268940 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 516 MASTER LE NN 268939 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 517 MASTER LE NN 268944 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 518 MASTER LE NN 268942 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 519 MASTER LE NN 268945 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 520 MASTER LE NN 268938 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 521 MASTER LE NN 268941 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 522 MASTER LE NN 268943 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 523 MASTER LE NN 268917 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 524 MASTER LE NN 268912 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 525 MASTER LE NN 268929 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 526 MASTER LE NN 268932 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 527 MASTER LE NN 268931 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 528 MASTER LE NN 268913 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 529 MASTER LE NN 268919 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 530 MASTER LE NN 268924 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_EN_
CTL__PERPH_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 531 MASTER LE NN 268918 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 532 MASTER LE NN 268914 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 533 MASTER LE NN 268930 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 534 MASTER LE NN 268920 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 535 MASTER LE NN 268937 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 536 MASTER LE NN 268933 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_INVERT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 537 MASTER LE NN 268925 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 538 MASTER LE NN 268922 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 539 MASTER LE NN 268935 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 540 MASTER LE NN 268936 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 541 MASTER LE NN 268934 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 542 MASTER LE NN 268923 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 543 MASTER LE NN 268927 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 544 MASTER LE NN 268926 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 545 MASTER LE NN 268928 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 546 MASTER LE NN 268909 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 547 MASTER LE NN 268908 + GPIO_07
I_DCORE/\gpio_rmod_gen[3]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 548 MASTER LE NN 268902 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
DSLAVE LS NN 256284 - GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
Chain[2] 549 MASTER LE NN 268901 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 550 MASTER LE NN 268881 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 551 MASTER LE NN 268903 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 552 MASTER LE NN 268900 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 553 MASTER LE NN 268878 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 554 MASTER LE NN 268883 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 555 MASTER LE NN 268877 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 556 MASTER LE NN 268905 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 557 MASTER LE NN 268907 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 558 MASTER LE NN 268906 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 559 MASTER LE NN 268904 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 560 MASTER LE NN 268880 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 561 MASTER LE NN 268879 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 562 MASTER LE NN 268882 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 563 MASTER LE NN 268896 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 564 MASTER LE NN 268892 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 565 MASTER LE NN 268893 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 566 MASTER LE NN 268875 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 567 MASTER LE NN 268899 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 568 MASTER LE NN 268898 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 569 MASTER LE NN 268897 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 570 MASTER LE NN 268895 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_INVERT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 571 MASTER LE NN 268872 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_ok/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 572 MASTER LE NN 268889 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 573 MASTER LE NN 268890 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 574 MASTER LE NN 268871 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 575 MASTER LE NN 268870 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 576 MASTER LE NN 268884 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 577 MASTER LE NN 268885 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 578 MASTER LE NN 268888 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 579 MASTER LE NN 268887 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 580 MASTER LE NN 268873 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_val
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 581 MASTER LE NN 268886 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_EN_
CTL__PERPH_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 582 MASTER LE NN 268874 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 583 MASTER LE NN 268876 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 584 MASTER LE NN 268894 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 585 MASTER LE NN 268891 + GPIO_07
I_DCORE/\gpio_rmod_gen[2]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 586 MASTER LE NN 268840 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256281 - GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
Chain[2] 587 MASTER LE NN 268839 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 588 MASTER LE NN 268845 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 589 MASTER LE NN 268862 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
 Chain[2] 590 MASTER LE NN 268869 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 591 MASTER LE NN 268867 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 592 MASTER LE NN 268868 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_MOD
E_CTL__MODE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 593 MASTER LE NN 268866 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 594 MASTER LE NN 268865 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_VIN_CTL__VOLTAGE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 595 MASTER LE NN 268864 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 596 MASTER LE NN 268863 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_PULL_CTL__PULLUP_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 597 MASTER LE NN 268838 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 598 MASTER LE NN 268844 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 599 MASTER LE NN 268837 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 600 MASTER LE NN 268836 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_LOC
KBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 601 MASTER LE NN 268843 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 602 MASTER LE NN 268849 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 603 MASTER LE NN 268835 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_val
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 604 MASTER LE NN 268846 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 605 MASTER LE NN 268848 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_EN_
CTL__PERPH_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 606 MASTER LE NN 268857 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_INVERT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 607 MASTER LE NN 268861 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 608 MASTER LE NN 268834 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\rlib_reg_gpio_ok/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 609 MASTER LE NN 268855 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 610 MASTER LE NN 268842 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 611 MASTER LE NN 268841 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_PER
PH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 612 MASTER LE NN 268858 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 613 MASTER LE NN 268854 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 614 MASTER LE NN 268853 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 615 MASTER LE NN 268856 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_SOURCE_CTL__OUTPUT_SOURCE_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 616 MASTER LE NN 268860 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 617 MASTER LE NN 268859 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_IN_DTEST_SEL__DTEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 618 MASTER LE NN 268852 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 619 MASTER LE NN 268851 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_TYPE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 620 MASTER LE NN 268850 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_DIG
_OUT_DRV_CTL__OUTPUT_DRV_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 621 MASTER LE NN 268847 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/\gpio_rif_u1/u_ANA
_PASS_THRU_SEL__ATEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 622 MASTER LE NN 268833 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 623 MASTER LE NN 268832 + GPIO_07
I_DCORE/\gpio_rmod_gen[1]_u_gpio_rmod/u_gpio_rdig/u_gpio_dig_mod/u_gpio_dig_mod_dft
_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 624 MASTER LE NN 287346 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 257666 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/LOCKUP (M31_1P5V6T_LOWLATCHX2)
Chain[2] 625 MASTER LE NN 287345 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 626 MASTER LE NN 287344 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 627 MASTER LE NN 287340 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 628 MASTER LE NN 287343 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 629 MASTER LE NN 287342 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 630 MASTER LE NN 287347 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 631 MASTER LE NN 287330 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 632 MASTER LE NN 287328 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp7_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 633 MASTER LE NN 287331 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 634 MASTER LE NN 287336 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 635 MASTER LE NN 287348 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 636 MASTER LE NN 287335 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp6_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 637 MASTER LE NN 287334 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 638 MASTER LE NN 287333 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 639 MASTER LE NN 287397 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 640 MASTER LE NN 287395 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 641 MASTER LE NN 287398 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 642 MASTER LE NN 287400 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 643 MASTER LE NN 287399 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 644 MASTER LE NN 287394 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 645 MASTER LE NN 287349 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX2)
 Chain[2] 646 MASTER LE NN 287339 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 647 MASTER LE NN 287645 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 648 MASTER LE NN 287647 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 649 MASTER LE NN 287338 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 650 MASTER LE NN 287653 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 651 MASTER LE NN 287648 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 652 MASTER LE NN 287652 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 653 MASTER LE NN 287651 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 654 MASTER LE II 287365 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 655 MASTER LE II 287523 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 656 MASTER LE II 287525 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 657 MASTER LE II 287658 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 658 MASTER LE II 287654 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 659 MASTER LE II 287649 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 660 MASTER LE II 287657 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 661 MASTER LE II 287660 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 662 MASTER LE II 287659 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 663 MASTER LE NN 287362 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 664 MASTER LE NN 287422 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 665 MASTER LE NN 287416 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 666 MASTER LE NN 287421 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 667 MASTER LE NN 287638 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 668 MASTER LE NN 287639 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 669 MASTER LE NN 287640 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 670 MASTER LE NN 287655 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 671 MASTER LE NN 287637 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 672 MASTER LE NN 287656 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 673 MASTER LE NN 287650 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 674 MASTER LE II 287364 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 675 MASTER LE NN 287363 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 676 MASTER LE NN 287524 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 677 MASTER LE NN 287520 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 678 MASTER LE NN 287646 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 679 MASTER LE NN 287641 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 680 MASTER LE NN 287546 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__SKIP_CL_CMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 681 MASTER LE NN 287662 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 682 MASTER LE II 287367 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 683 MASTER LE NN 287368 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 684 MASTER LE NN 287341 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 685 MASTER LE NN 287332 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 686 MASTER LE NN 287329 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 687 MASTER LE NN 287376 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 688 MASTER LE NN 287396 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 689 MASTER LE NN 287375 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 690 MASTER LE NN 287401 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 691 MASTER LE NN 285224 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[6]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 692 MASTER LE NN 285213 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 693 MASTER LE NN 284950 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 694 MASTER LE NN 284943 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 695 MASTER LE NN 284942 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 696 MASTER LE NN 285101 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_tgl_counter_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 697 MASTER LE NN 285100 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_tgl_counter_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 698 MASTER LE NN 284944 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 699 MASTER LE NN 284945 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 700 MASTER LE NN 284962 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor14_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 701 MASTER LE NN 284952 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 702 MASTER LE NN 284941 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 703 MASTER LE NN 285834 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 704 MASTER LE NN 285833 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 705 MASTER LE NN 285835 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 706 MASTER LE NN 285836 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 707 MASTER LE NN 285827 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 708 MASTER LE NN 285837 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 709 MASTER LE NN 285832 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 710 MASTER LE NN 285636 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 711 MASTER LE NN 285637 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 712 MASTER LE NN 285484 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 713 MASTER LE II 284966 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 714 MASTER LE II 285840 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 715 MASTER LE II 285633 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 716 MASTER LE NN 284965 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 717 MASTER LE NN 285635 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 718 MASTER LE NN 284953 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 719 MASTER LE NN 285215 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 720 MASTER LE NN 285217 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 721 MASTER LE NN 285216 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 722 MASTER LE NN 285218 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 723 MASTER LE NN 285219 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 724 MASTER LE NN 285221 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 725 MASTER LE NN 285220 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 726 MASTER LE NN 287386 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 727 MASTER LE NN 287372 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 728 MASTER LE NN 287385 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 729 MASTER LE NN 287382 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 730 MASTER LE NN 287381 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 731 MASTER LE NN 287380 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 732 MASTER LE NN 287379 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 733 MASTER LE NN 287378 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 734 MASTER LE NN 287377 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 735 MASTER LE NN 287389 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 736 MASTER LE NN 287433 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 737 MASTER LE NN 287370 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 738 MASTER LE NN 287388 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 739 MASTER LE NN 287387 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 740 MASTER LE NN 287384 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 741 MASTER LE NN 284991 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 742 MASTER LE NN 284989 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 743 MASTER LE NN 285225 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 744 MASTER LE NN 285222 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 745 MASTER LE NN 285055 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 746 MASTER LE NN 285208 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_setpoint_gt_vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 747 MASTER LE NN 285214 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 748 MASTER LE NN 285451 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 749 MASTER LE NN 284948 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 750 MASTER LE NN 284949 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 751 MASTER LE NN 284951 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 752 MASTER LE NN 284956 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 753 MASTER LE NN 284955 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 754 MASTER LE NN 284957 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 755 MASTER LE NN 284959 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 756 MASTER LE NN 284958 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 757 MASTER LE NN 284946 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 758 MASTER LE NN 284947 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor16_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 759 MASTER LE NN 284960 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 760 MASTER LE NN 284963 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor15_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 761 MASTER LE NN 284961 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 762 MASTER LE NN 285099 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 763 MASTER LE NN 285415 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 764 MASTER LE NN 285103 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_blank_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 765 MASTER LE NN 287689 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 766 MASTER LE NN 287542 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__N_MIN_ON_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
 Chain[2] 767 MASTER LE NN 287644 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 768 MASTER LE NN 287643 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 769 MASTER LE NN 287534 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_BLANK_TIME_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 770 MASTER LE NN 287539 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_SEL_DLY_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 771 MASTER LE NN 287454 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 772 MASTER LE NN 287453 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 773 MASTER LE NN 287541 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__P_MIN_ON_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 774 MASTER LE NN 287419 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 775 MASTER LE NN 287545 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__SKIP_ZX_CMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 776 MASTER LE NN 287518 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 777 MASTER LE NN 287530 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 778 MASTER LE NN 287527 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 779 MASTER LE NN 287531 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 780 MASTER LE NN 287521 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 781 MASTER LE NN 287415 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 782 MASTER LE NN 287414 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 783 MASTER LE NN 287417 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 784 MASTER LE NN 287420 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 785 MASTER LE NN 287418 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 786 MASTER LE NN 287424 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 787 MASTER LE NN 287425 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 788 MASTER LE II 287366 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 789 MASTER LE II 287569 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP1_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 790 MASTER LE II 287570 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP1_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 791 MASTER LE II 287661 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 792 MASTER LE II 287575 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__P_REF1_RATIO_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 793 MASTER LE II 287529 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 794 MASTER LE II 287528 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 795 MASTER LE II 287522 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 796 MASTER LE II 287544 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__D_P_MIN_ON_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 797 MASTER LE II 287540 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__P_MIN_ON_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 798 MASTER LE II 287515 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_PRE_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 799 MASTER LE II 287519 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLH_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 800 MASTER LE II 287543 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__N_MIN_ON_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 801 MASTER LE II 287513 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__RET_WAKE_FREQ_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 802 MASTER LE II 287448 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 803 MASTER LE II 287449 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 804 MASTER LE II 287451 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 805 MASTER LE II 287452 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 806 MASTER LE II 287446 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_POLARITY_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 807 MASTER LE II 287390 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_comp
_fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 808 MASTER LE II 287383 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_comp_
fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 809 MASTER LE II 287374 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 810 MASTER LE II 287373 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 811 MASTER LE II 287369 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 812 MASTER LE II 287371 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 813 MASTER LE II 284990 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 814 MASTER LE II 284993 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 815 MASTER LE II 284996 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 816 MASTER LE II 285691 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 817 MASTER LE II 284998 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 818 MASTER LE II 285457 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 819 MASTER LE II 285634 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 820 MASTER LE II 285455 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 821 MASTER LE II 285847 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 822 MASTER LE II 285838 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 823 MASTER LE II 285841 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 824 MASTER LE II 285632 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 825 MASTER LE II 285487 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_SPARE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 826 MASTER LE II 285614 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_VOLT_CFG_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 827 MASTER LE II 285607 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_RANGE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 828 MASTER LE II 285830 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 829 MASTER LE II 285621 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PING_PONG_COMP_CAP_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 830 MASTER LE II 285617 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__BW_PHASE_STAGGER_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 831 MASTER LE II 285622 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__OPEN_LOOP_ACTIVE_CFG_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 832 MASTER LE II 285482 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 833 MASTER LE II 285828 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 834 MASTER LE II 285826 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 835 MASTER LE II 285483 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 836 MASTER LE II 285485 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 837 MASTER LE II 285638 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_EN_CFG_VIN_FF_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 838 MASTER LE II 285738 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 839 MASTER LE II 285526 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 840 MASTER LE II 285525 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 841 MASTER LE NN 284967 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 842 MASTER LE NN 285845 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 843 MASTER LE NN 285445 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 844 MASTER LE NN 285846 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 845 MASTER LE NN 285446 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 846 MASTER LE NN 285449 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 847 MASTER LE NN 285452 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 848 MASTER LE NN 285210 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 849 MASTER LE NN 285261 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_bypass_
en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 850 MASTER LE NN 285262 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_bypass_
en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 851 MASTER LE NN 285158 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 852 MASTER LE NN 284995 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 853 MASTER LE NN 285153 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 854 MASTER LE NN 285154 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 855 MASTER LE NN 285160 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[2] 856 MASTER LE NN 285157 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 857 MASTER LE NN 285223 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 858 MASTER LE NN 284994 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 859 MASTER LE NN 284992 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 860 MASTER LE NN 285156 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 861 MASTER LE NN 285692 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 862 MASTER LE NN 285155 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 863 MASTER LE NN 285209 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_setpoint_eq_vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 864 MASTER LE NN 285162 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 865 MASTER LE NN 285212 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_STEPPER_DONE_d
_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 866 MASTER LE NN 285456 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 867 MASTER LE NN 285450 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 868 MASTER LE NN 285454 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 869 MASTER LE NN 285453 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 870 MASTER LE NN 285447 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 871 MASTER LE NN 285448 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 872 MASTER LE NN 285839 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 873 MASTER LE NN 285844 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 874 MASTER LE NN 285842 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 875 MASTER LE NN 285843 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 876 MASTER LE NN 285486 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_SPARE_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 877 MASTER LE NN 285612 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_FORCE_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 878 MASTER LE NN 285613 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_OUT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 879 MASTER LE NN 285644 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_EN_DLL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 880 MASTER LE NN 285259 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__RETENTION_QUAL_rifi_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 881 MASTER LE NN 285619 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PHASE_STAGGER_COMP_CAP_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 882 MASTER LE NN 285610 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 883 MASTER LE NN 285616 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__BW_PHASE_STAGGER_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 884 MASTER LE NN 285620 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PHASE_STAGGER_COMP_CAP_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 885 MASTER LE NN 285876 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 886 MASTER LE NN 285646 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 887 MASTER LE NN 285102 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_toggle_in_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 888 MASTER LE NN 285647 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 889 MASTER LE NN 285397 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_pong_blank_reg
(M31_1P5V6T_SFFSBQX1)
Chain[2] 890 MASTER LE NN 285473 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 891 MASTER LE NN 285470 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 892 MASTER LE NN 285628 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CURRENT_CFG_reg
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 893 MASTER LE NN 285615 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_VOLT_CFG_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 894 MASTER LE NN 285469 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 895 MASTER LE NN 285467 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 896 MASTER LE NN 285625 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CAP_CFG_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 897 MASTER LE NN 285626 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CAP_CFG_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 898 MASTER LE NN 285793 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 899 MASTER LE NN 285792 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 900 MASTER LE NN 285463 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 901 MASTER LE NN 285631 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_NOTCH_CFG_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 902 MASTER LE NN 285629 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_LP_CFG_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 903 MASTER LE NN 285461 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 904 MASTER LE NN 285458 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 905 MASTER LE NN 285056 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_int_soft_start_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 906 MASTER LE NN 285823 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 907 MASTER LE NN 285573 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 908 MASTER LE NN 285563 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 909 MASTER LE NN 285299 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_7_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 910 MASTER LE NN 285280 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_buck_en_ret_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 911 MASTER LE NN 287516 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_PRE_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 912 MASTER LE NN 287560 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 913 MASTER LE NN 287456 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 914 MASTER LE NN 287510 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 915 MASTER LE NN 287442 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 916 MASTER LE NN 287430 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 917 MASTER LE NN 287427 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 918 MASTER LE NN 287505 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_PRE_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 919 MASTER LE NN 287533 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_BLANK_TIME_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 920 MASTER LE NN 287431 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 921 MASTER LE NN 287532 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_BLANK_TIME_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 922 MASTER LE NN 287450 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 923 MASTER LE NN 287642 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 924 MASTER LE NN 287426 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 925 MASTER LE NN 287455 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 926 MASTER LE NN 287548 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 927 MASTER LE NN 287538 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_SEL_DLY_CTRL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 928 MASTER LE NN 287535 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_BLANK_TIME_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 929 MASTER LE NN 287549 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 930 MASTER LE NN 287536 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_SEL_DLY_CTRL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 931 MASTER LE NN 287517 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 932 MASTER LE NN 287553 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 933 MASTER LE NN 287566 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP3_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 934 MASTER LE NN 287580 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 935 MASTER LE NN 287558 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 936 MASTER LE NN 287551 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 937 MASTER LE NN 287564 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 938 MASTER LE NN 287577 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 939 MASTER LE NN 287554 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 940 MASTER LE NN 287567 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP2_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 941 MASTER LE NN 287576 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__CL_TSTMD_MUX_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 942 MASTER LE NN 287423 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 943 MASTER LE NN 287555 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 944 MASTER LE NN 287572 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP2_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 945 MASTER LE NN 287571 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP2_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 946 MASTER LE NN 287581 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 947 MASTER LE NN 287557 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 948 MASTER LE NN 287568 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP2_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 949 MASTER LE NN 287574 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__P_REF2_RATIO_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 950 MASTER LE NN 287573 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP1_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 951 MASTER LE NN 287552 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 952 MASTER LE NN 287547 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 953 MASTER LE NN 287526 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 954 MASTER LE NN 287565 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP3_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 955 MASTER LE NN 287550 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 956 MASTER LE NN 287537 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_SEL_DLY_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 957 MASTER LE NN 287508 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__ZX_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 958 MASTER LE NN 287447 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_MANUAL_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 959 MASTER LE NN 287514 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__SS_SI_ENABLE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 960 MASTER LE NN 287462 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 961 MASTER LE NN 287457 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 962 MASTER LE NN 287482 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC3__SENSE_IDAC_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 963 MASTER LE NN 287459 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 964 MASTER LE NN 287404 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_cal_act
ivity_en_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 965 MASTER LE NN 287391 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_fb_latc
h_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 966 MASTER LE NN 285266 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_mask_pwmcmp_inwarmup_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 967 MASTER LE NN 285268 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_en_tx_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 968 MASTER LE NN 285302 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 969 MASTER LE NN 285161 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[2] 970 MASTER LE NN 284997 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[2] 971 MASTER LE NN 285301 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 972 MASTER LE NN 285150 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_master_
en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 973 MASTER LE NN 285151 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
clk_req_u/d_clk_req_stepper_meta_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 974 MASTER LE NN 285152 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
clk_req_u/d_clk_req_stepper_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 975 MASTER LE NN 285159 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[2] 976 MASTER LE NN 285149 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_master_
en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 977 MASTER LE NN 285281 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_refen_to_bckcmn_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 978 MASTER LE NN 285688 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_slib_sync/sy
nc_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 979 MASTER LE NN 285566 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 980 MASTER LE NN 285568 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__DACREF_HYST_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 981 MASTER LE NN 285297 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_foldback_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 982 MASTER LE NN 285405 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__MODE_STATE_rifi_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 983 MASTER LE NN 285524 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 984 MASTER LE NN 285460 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 985 MASTER LE NN 285630 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_NOTCH_CFG_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 986 MASTER LE NN 285459 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 987 MASTER LE NN 285466 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 988 MASTER LE NN 285468 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 989 MASTER LE NN 285627 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CURRENT_CFG_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 990 MASTER LE NN 285829 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 991 MASTER LE NN 285831 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 992 MASTER LE NN 285640 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 993 MASTER LE NN 285643 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_EN_COMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 994 MASTER LE NN 285608 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 995 MASTER LE NN 285642 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 996 MASTER LE NN 285639 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 997 MASTER LE NN 285609 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 998 MASTER LE NN 285611 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 999 MASTER LE NN 285618 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PING_PONG_CP_CURRNT_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1000 MASTER LE NN 285641 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1001 MASTER LE NN 285303 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync4/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 1002 MASTER LE NN 285304 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync4/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1003 MASTER LE NN 285314 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1004 MASTER LE NN 285313 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1005 MASTER LE NN 287685 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX2)
Chain[2] 1006 MASTER LE NN 287484 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1007 MASTER LE NN 287503 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_3__FOLDBACK_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1008 MASTER LE NN 287485 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1009 MASTER LE NN 287621 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1010 MASTER LE NN 287486 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1011 MASTER LE NN 287504 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_3__FOLDBACK_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1012 MASTER LE NN 287506 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_PRE_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1013 MASTER LE NN 287428 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1014 MASTER LE NN 287499 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1015 MASTER LE NN 287618 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1016 MASTER LE NN 287409 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1017 MASTER LE NN 287413 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1018 MASTER LE NN 287458 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1019 MASTER LE NN 287502 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1020 MASTER LE NN 287410 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1021 MASTER LE NN 287501 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1022 MASTER LE NN 287635 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1023 MASTER LE NN 287460 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1024 MASTER LE NN 287444 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1025 MASTER LE NN 287443 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1026 MASTER LE NN 287445 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1027 MASTER LE NN 287461 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1028 MASTER LE NN 287507 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__ZX_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1029 MASTER LE NN 287429 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1030 MASTER LE NN 287631 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1031 MASTER LE NN 287629 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1032 MASTER LE NN 287584 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1033 MASTER LE NN 287587 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1034 MASTER LE NN 287583 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1035 MASTER LE NN 287588 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1036 MASTER LE NN 287585 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1037 MASTER LE NN 287579 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1038 MASTER LE NN 287578 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1039 MASTER LE NN 287582 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1040 MASTER LE NN 287586 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1041 MASTER LE NN 287562 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1042 MASTER LE NN 287563 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1043 MASTER LE NN 287589 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1044 MASTER LE NN 287509 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1045 MASTER LE NN 287561 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1046 MASTER LE NN 287559 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1047 MASTER LE NN 287556 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1048 MASTER LE NN 287633 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1049 MASTER LE NN 287432 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1050 MASTER LE NN 287511 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLH_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1051 MASTER LE NN 287483 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1052 MASTER LE NN 287512 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLH_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1053 MASTER LE NN 287393 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_l2r_trim_cal
_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1054 MASTER LE NN 285240 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1055 MASTER LE NN 285243 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1056 MASTER LE NN 285252 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_fsm_mask_en_d1_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1057 MASTER LE NN 285253 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_fsm_mask_en_d2_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1058 MASTER LE NN 285245 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_update_mask_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1059 MASTER LE NN 285248 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1060 MASTER LE NN 285300 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_6_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1061 MASTER LE NN 285285 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_smps_clk_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1062 MASTER LE NN 285298 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_npm_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1063 MASTER LE NN 285571 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1064 MASTER LE NN 285338 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/d_vreg_ready_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1065 MASTER LE NN 285403 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_power_boost_en_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 1066 MASTER LE NN 285580 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__PWM_19P2M_CLK_FORCE_ON_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1067 MASTER LE NN 285561 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1068 MASTER LE NN 285578 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__CAL_FLT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1069 MASTER LE NN 285575 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1070 MASTER LE NN 285740 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1071 MASTER LE NN 285783 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1072 MASTER LE NN 285574 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1073 MASTER LE NN 285780 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1074 MASTER LE NN 285564 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1075 MASTER LE NN 285147 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_update_fsm_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1076 MASTER LE NN 285290 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_clk_19p2_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1077 MASTER LE NN 285282 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_clk_lfrc_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1078 MASTER LE NN 285148 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1079 MASTER LE NN 285211 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1080 MASTER LE NN 285226 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1081 MASTER LE NN 285250 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1082 MASTER LE NN 287392 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_cal_act
ivity_en_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1083 MASTER LE NN 285236 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1084 MASTER LE NN 285238 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1085 MASTER LE NN 285237 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1086 MASTER LE NN 285228 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1087 MASTER LE NN 285244 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1088 MASTER LE NN 285251 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1089 MASTER LE NN 285249 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1090 MASTER LE NN 285283 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_vreg_comp_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1091 MASTER LE NN 285284 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_smps_clk_buf_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1092 MASTER LE NN 285267 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_npm_lpm_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1093 MASTER LE NN 285258 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__PS_TRUE_rifi_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1094 MASTER LE NN 285579 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__PWM_SMPS_CLK_FORCE_ON_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1095 MASTER LE NN 285582 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__TRAP_GEN_SI_CURRENT_REDUCTION_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1096 MASTER LE NN 285874 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__DETACH_VREG_READY_CHAIN_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1097 MASTER LE NN 285464 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1098 MASTER LE NN 285256 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1099 MASTER LE NN 285257 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 1100 MASTER LE NN 285465 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1101 MASTER LE NN 285265 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1102 MASTER LE NN 285848 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1103 MASTER LE NN 285260 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1104 MASTER LE NN 285462 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1105 MASTER LE NN 285623 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_INT_CFG__DUTY_GEN_INT_CAP_CFG_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1106 MASTER LE NN 285796 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1107 MASTER LE NN 285624 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_INT_CFG__DUTY_GEN_INT_CAP_CFG_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1108 MASTER LE NN 285795 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1109 MASTER LE NN 285471 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1110 MASTER LE NN 285507 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1111 MASTER LE NN 285472 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1112 MASTER LE NN 285279 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1113 MASTER LE NN 285645 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1114 MASTER LE NN 285324 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1115 MASTER LE NN 285494 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__NC_TEST_MODE_EN_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1116 MASTER LE NN 285480 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PP_PWM_LOOP_EN_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1117 MASTER LE NN 285306 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1118 MASTER LE NN 285305 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1119 MASTER LE NN 285310 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1120 MASTER LE NN 285312 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1121 MASTER LE NN 285311 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1122 MASTER LE NN 285315 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1123 MASTER LE NN 285309 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1124 MASTER LE NN 285308 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1125 MASTER LE NN 287687 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1126 MASTER LE NN 287604 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1127 MASTER LE NN 287603 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1128 MASTER LE NN 287598 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1129 MASTER LE NN 287607 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1130 MASTER LE NN 287597 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
 Chain[2] 1131 MASTER LE NN 287596 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1132 MASTER LE NN 287601 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1133 MASTER LE NN 287595 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1134 MASTER LE NN 287613 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1135 MASTER LE NN 287590 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1136 MASTER LE NN 287592 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1137 MASTER LE NN 287615 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1138 MASTER LE NN 287614 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1139 MASTER LE NN 287593 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1140 MASTER LE NN 287594 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1141 MASTER LE NN 287591 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1142 MASTER LE NN 287434 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL2__GANG_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1143 MASTER LE NN 287437 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1144 MASTER LE NN 287617 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1145 MASTER LE NN 287489 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1146 MASTER LE NN 287412 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1147 MASTER LE NN 285191 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1148 MASTER LE NN 285200 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1149 MASTER LE NN 285234 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1150 MASTER LE NN 285239 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1151 MASTER LE NN 285227 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_timer1_exp_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1152 MASTER LE NN 285229 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_timer0_exp_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1153 MASTER LE NN 285690 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_slib_sync
/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1154 MASTER LE NN 285699 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1155 MASTER LE NN 285567 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1156 MASTER LE NN 285739 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1157 MASTER LE NN 285570 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1158 MASTER LE NN 285752 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1159 MASTER LE NN 285782 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1160 MASTER LE NN 285439 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1161 MASTER LE NN 285474 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PWM_R_RIGHT_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1162 MASTER LE NN 285276 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1163 MASTER LE NN 285278 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1164 MASTER LE NN 285273 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 1165 MASTER LE NN 285476 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PP_PWMBY2_LOCK_EN_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1166 MASTER LE NN 285594 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1167 MASTER LE NN 285477 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PP_PWM_LOCK_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1168 MASTER LE NN 285593 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1169 MASTER LE NN 285599 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1170 MASTER LE NN 285600 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1171 MASTER LE NN 285596 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1172 MASTER LE NN 285606 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1173 MASTER LE NN 285604 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1174 MASTER LE NN 285475 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PWM_F_RIGHT_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1175 MASTER LE NN 285555 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1176 MASTER LE NN 285481 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PHASE_STAGGERED_LOO
P_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1177 MASTER LE NN 285595 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1178 MASTER LE NN 285603 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1179 MASTER LE NN 285552 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1180 MASTER LE NN 285479 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PP_PWMBY2_LOOP_EN_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1181 MASTER LE NN 285478 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PHASE_STAGGERED_LOCK_EN_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1182 MASTER LE NN 285597 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1183 MASTER LE NN 285601 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1184 MASTER LE NN 285490 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1185 MASTER LE NN 285661 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1186 MASTER LE NN 285750 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1187 MASTER LE NN 285513 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1188 MASTER LE NN 285514 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1189 MASTER LE NN 285491 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1190 MASTER LE NN 285488 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__RET_CMP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1191 MASTER LE NN 285508 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1192 MASTER LE NN 285506 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1193 MASTER LE NN 285509 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1194 MASTER LE NN 285797 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1195 MASTER LE NN 285441 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1196 MASTER LE NN 285075 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_comp_fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1197 MASTER LE NN 285741 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1198 MASTER LE NN 285781 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1199 MASTER LE NN 285581 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__DUTY_GEN_SI_CURRENT_REDUCTION_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1200 MASTER LE NN 285576 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__VREG_MON_CFG_NPM_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1201 MASTER LE NN 285577 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__VREG_MON_CFG_RM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1202 MASTER LE NN 285698 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1203 MASTER LE NN 285697 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1204 MASTER LE NN 285701 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_slib_sync/sync_d
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1205 MASTER LE NN 285235 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1206 MASTER LE NN 285199 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1207 MASTER LE NN 285241 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1208 MASTER LE NN 285242 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1209 MASTER LE NN 285231 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1210 MASTER LE NN 285685 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1211 MASTER LE NN 285696 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1212 MASTER LE NN 285694 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1213 MASTER LE NN 285658 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1214 MASTER LE NN 285756 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1215 MASTER LE NN 285650 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_PS_DLY_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1216 MASTER LE NN 285560 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1217 MASTER LE NN 285569 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__DACREF_HYST_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1218 MASTER LE NN 285565 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1219 MASTER LE NN 285784 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1220 MASTER LE NN 285562 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1221 MASTER LE NN 285572 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1222 MASTER LE NN 285343 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/d_vreg_error_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1223 MASTER LE NN 285444 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1224 MASTER LE NN 285443 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 1225 MASTER LE NN 285521 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1226 MASTER LE NN 285520 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1227 MASTER LE NN 285370 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1228 MASTER LE NN 285517 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1229 MASTER LE NN 285504 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_MANUAL_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1230 MASTER LE NN 285442 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1231 MASTER LE NN 285794 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1232 MASTER LE NN 285505 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_POLARITY_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1233 MASTER LE NN 285659 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1234 MASTER LE NN 285602 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1235 MASTER LE NN 285559 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1236 MASTER LE NN 285495 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__NC_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1237 MASTER LE NN 285493 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1238 MASTER LE NN 285489 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1239 MASTER LE NN 285598 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1240 MASTER LE NN 285591 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1241 MASTER LE NN 284954 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1242 MASTER LE NN 285307 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1243 MASTER LE NN 285277 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1244 MASTER LE NN 285274 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1245 MASTER LE NN 287688 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1246 MASTER LE NN 287600 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1247 MASTER LE NN 287599 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1248 MASTER LE NN 287616 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1249 MASTER LE NN 287605 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1250 MASTER LE NN 287609 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1251 MASTER LE NN 287610 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1252 MASTER LE NN 287602 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1253 MASTER LE NN 287606 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1254 MASTER LE NN 287608 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1255 MASTER LE NN 287612 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1256 MASTER LE NN 287611 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1257 MASTER LE NN 287620 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
 Chain[2] 1258 MASTER LE NN 287627 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1259 MASTER LE NN 287467 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1260 MASTER LE NN 287436 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1261 MASTER LE NN 287438 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1262 MASTER LE NN 287441 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1263 MASTER LE NN 287490 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1264 MASTER LE NN 287487 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1265 MASTER LE NN 287411 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1266 MASTER LE NN 287405 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1267 MASTER LE NN 287435 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1268 MASTER LE NN 287500 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1269 MASTER LE NN 287439 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1270 MASTER LE NN 287440 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1271 MASTER LE NN 287407 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1272 MASTER LE NN 287623 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1273 MASTER LE NN 287625 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1274 MASTER LE NN 287408 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1275 MASTER LE NN 287619 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1276 MASTER LE NN 287464 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1277 MASTER LE NN 287465 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1278 MASTER LE NN 287463 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1279 MASTER LE NN 287488 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1280 MASTER LE NN 287466 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1281 MASTER LE NN 287498 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1282 MASTER LE NN 285198 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1283 MASTER LE NN 285197 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1284 MASTER LE NN 285192 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1285 MASTER LE NN 285196 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1286 MASTER LE NN 285195 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ctrl_fsm_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1287 MASTER LE NN 285418 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ctrl_fsm_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1288 MASTER LE NN 284980 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ps_fsm_reg (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1289 MASTER LE NN 285030 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_ps_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 1290 MASTER LE NN 285144 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1291 MASTER LE NN 285684 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1292 MASTER LE NN 285523 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1293 MASTER LE NN 285519 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1294 MASTER LE NN 285769 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1295 MASTER LE NN 285774 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1296 MASTER LE NN 285515 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1297 MASTER LE NN 285502 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
5] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1298 MASTER LE NN 285553 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1299 MASTER LE NN 285531 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1300 MASTER LE NN 285554 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1301 MASTER LE NN 285558 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1302 MASTER LE NN 285556 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1303 MASTER LE NN 285533 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1304 MASTER LE NN 285592 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1305 MASTER LE NN 285557 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1306 MASTER LE NN 285492 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1307 MASTER LE NN 285678 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1308 MASTER LE NN 285503 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
6] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1309 MASTER LE NN 285499 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
2] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1310 MASTER LE NN 285511 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1311 MASTER LE NN 285677 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1312 MASTER LE NN 285497 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1313 MASTER LE NN 285512 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1314 MASTER LE NN 285501 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
4] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1315 MASTER LE NN 285744 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1316 MASTER LE NN 285605 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1317 MASTER LE NN 285516 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1318 MASTER LE NN 285785 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1319 MASTER LE NN 285652 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_REFSAMPLE_TIMER_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1320 MASTER LE NN 285522 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1321 MASTER LE NN 285328 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1322 MASTER LE NN 285325 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_sync_3p0_trimout_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1323 MASTER LE NN 285326 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_sync_3p0_trimout_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1324 MASTER LE NN 285334 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/u_
slib_sync_3p0_trim_cal_act_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1325 MASTER LE NN 285419 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_en_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1326 MASTER LE NN 285335 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/u_
slib_sync_3p0_trim_cal_act_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1327 MASTER LE NN 285683 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1328 MASTER LE NN 285233 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_timer_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1329 MASTER LE NN 285029 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_ps_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1330 MASTER LE NN 285255 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_mode_update_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1331 MASTER LE NN 285402 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_enable_toggle_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 1332 MASTER LE NN 285400 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_disable_awake_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 1333 MASTER LE NN 285254 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_mode_update_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1334 MASTER LE NN 285230 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1335 MASTER LE NN 285143 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1336 MASTER LE NN 285395 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_npm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1337 MASTER LE NN 285686 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1338 MASTER LE NN 285689 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_slib_sync
/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1339 MASTER LE NN 285700 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_slib_sync/sync_d
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1340 MASTER LE NN 285687 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_slib_sync/sy
nc_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1341 MASTER LE NN 285329 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_en_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1342 MASTER LE NN 285693 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1343 MASTER LE NN 285695 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 1344 MASTER LE NN 285649 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_PS_DLY_reg/dout_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1345 MASTER LE NN 285651 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_REFSAMPLE_TIMER_reg/do
ut_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1346 MASTER LE NN 285440 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1347 MASTER LE NN 285771 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1348 MASTER LE NN 285518 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1349 MASTER LE NN 285583 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1350 MASTER LE NN 285802 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1351 MASTER LE NN 285587 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1352 MASTER LE NN 285429 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL2__GANG_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1353 MASTER LE NN 285496 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1354 MASTER LE NN 285498 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1355 MASTER LE NN 285584 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1356 MASTER LE NN 285676 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1357 MASTER LE NN 285534 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1358 MASTER LE NN 285275 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1359 MASTER LE NN 285317 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1360 MASTER LE NN 285323 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1361 MASTER LE NN 285271 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1362 MASTER LE NN 285272 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1363 MASTER LE NN 285322 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 1364 MASTER LE NN 285316 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1365 MASTER LE NN 287686 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[4] (M31_1P5V6T_SFFSRBQX2J)
Chain[2] 1366 MASTER LE NN 287477 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1367 MASTER LE NN 287630 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1368 MASTER LE NN 287632 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1369 MASTER LE NN 287481 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[7] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1370 MASTER LE NN 287624 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1371 MASTER LE NN 287636 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1372 MASTER LE NN 287475 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1373 MASTER LE NN 287480 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1374 MASTER LE NN 287493 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1375 MASTER LE NN 287491 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1376 MASTER LE NN 287476 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1377 MASTER LE NN 287497 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1378 MASTER LE NN 287471 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1379 MASTER LE NN 287478 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1380 MASTER LE NN 287473 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1381 MASTER LE NN 287492 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1382 MASTER LE NN 287495 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1383 MASTER LE NN 287494 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1384 MASTER LE NN 287469 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1385 MASTER LE NN 287496 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1386 MASTER LE NN 287406 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1387 MASTER LE NN 285186 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1388 MASTER LE NN 285201 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1389 MASTER LE NN 285185 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1390 MASTER LE NN 285193 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1391 MASTER LE NN 285190 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1392 MASTER LE NN 285145 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1393 MASTER LE NN 285232 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_timer_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1394 MASTER LE NN 285682 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 1395 MASTER LE NN 285264 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_stepper_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1396 MASTER LE NN 285333 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_sync_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1397 MASTER LE NN 285330 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1398 MASTER LE NN 285648 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_2__POWER_BOOST_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1399 MASTER LE NN 285437 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1400 MASTER LE NN 285331 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
l2r_trim_cal_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1401 MASTER LE NN 285878 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_out_reg_re
g (M31_1P5V6T_SFFRBQX1)
Chain[2] 1402 MASTER LE NN 285500 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
3] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1403 MASTER LE NN 285673 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1404 MASTER LE NN 285532 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1405 MASTER LE NN 285710 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 1406 MASTER LE NN 285318 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1407 MASTER LE NN 285320 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1408 MASTER LE NN 285321 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1409 MASTER LE NN 285319 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1410 MASTER LE NN 285708 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1411 MASTER LE NN 285737 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1412 MASTER LE NN 285736 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1413 MASTER LE NN 285530 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1414 MASTER LE NN 285547 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1415 MASTER LE NN 285675 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1416 MASTER LE NN 285588 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1417 MASTER LE NN 285761 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1418 MASTER LE NN 285549 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1419 MASTER LE NN 285789 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1420 MASTER LE NN 285803 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1421 MASTER LE NN 285396 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/d_ocp_perph_en_master_reg
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1422 MASTER LE NN 285807 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1423 MASTER LE NN 285763 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1424 MASTER LE NN 285765 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 1425 MASTER LE NN 285438 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1426 MASTER LE NN 285332 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_clkreq_gate_3p0_clk_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1427 MASTER LE NN 285327 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_sync_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1428 MASTER LE NN 285263 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_stepper_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1429 MASTER LE NN 285291 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1430 MASTER LE NN 285292 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1431 MASTER LE NN 285394 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_npm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1432 MASTER LE NN 285294 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1433 MASTER LE NN 285681 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/sync_u0/sync_d_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1434 MASTER LE NN 285680 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/sync_u0/sync_d_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1435 MASTER LE NN 285246 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_mask_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1436 MASTER LE NN 285247 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_mask_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1437 MASTER LE NN 285146 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1438 MASTER LE NN 285417 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1439 MASTER LE NN 285188 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_force_wake_ps_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1440 MASTER LE NN 285851 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_curr_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1441 MASTER LE NN 285179 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1442 MASTER LE NN 285187 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1443 MASTER LE NN 285399 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_fsm_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 1444 MASTER LE NN 285184 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1445 MASTER LE NN 285183 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1446 MASTER LE NN 285182 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1447 MASTER LE NN 285852 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_curr_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1448 MASTER LE NN 285177 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_fsm_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1449 MASTER LE NN 285106 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1450 MASTER LE NN 285105 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1451 MASTER LE NN 285176 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_refdac_sample_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1452 MASTER LE NN 285104 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_u1/cl
k_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1453 MASTER LE NN 285194 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/slib_clkreq_gate_1p0_hf_clk_u1
/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1454 MASTER LE NN 285296 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1455 MASTER LE NN 285295 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1456 MASTER LE NN 285293 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1457 MASTER LE NN 285032 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_19p2_req_synchro_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1458 MASTER LE NN 285031 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_19p2_req_synchro_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1459 MASTER LE NN 285337 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_cal_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1460 MASTER LE NN 285660 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1461 MASTER LE NN 285035 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_rpm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1462 MASTER LE NN 285036 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_rpm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1463 MASTER LE NN 285336 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_cal_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1464 MASTER LE NN 285653 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__DIS_RETENTION_MODE_DLY_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1465 MASTER LE NN 285535 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CTL__MULTIPHASE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1466 MASTER LE NN 285510 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1467 MASTER LE NN 285545 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPDOWN_READY_CTL__VOUT_EQ_VREF_WAIT_BYPASS_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1468 MASTER LE NN 285537 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1469 MASTER LE NN 285589 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1470 MASTER LE NN 285586 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1471 MASTER LE NN 285585 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1472 MASTER LE NN 285539 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1473 MASTER LE NN 285590 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1474 MASTER LE NN 285674 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1475 MASTER LE NN 285529 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1476 MASTER LE NN 285528 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1477 MASTER LE NN 285527 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1478 MASTER LE NN 285709 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1479 MASTER LE NN 285712 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1480 MASTER LE NN 285711 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1481 MASTER LE NN 285713 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1482 MASTER LE NN 285714 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1483 MASTER LE NN 285269 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 1484 MASTER LE NN 285270 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1485 MASTER LE NN 285875 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[1
] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1486 MASTER LE NN 285705 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[0
] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1487 MASTER LE NN 285706 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[2
] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1488 MASTER LE NN 285707 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[3
] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1489 MASTER LE NN 285729 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 1490 MASTER LE NN 285733 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1491 MASTER LE NN 285728 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1492 MASTER LE NN 285734 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1493 MASTER LE NN 285735 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 1494 MASTER LE NN 285679 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1495 MASTER LE NN 285730 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1496 MASTER LE NN 285731 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1497 MASTER LE NN 285732 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1498 MASTER LE NN 285665 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1499 MASTER LE NN 285669 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN1_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1500 MASTER LE NN 285543 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1501 MASTER LE NN 285667 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1502 MASTER LE NN 285668 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN0_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1503 MASTER LE NN 285670 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN2_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1504 MASTER LE NN 285664 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1505 MASTER LE NN 285666 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1506 MASTER LE NN 285541 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1507 MASTER LE NN 285435 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1508 MASTER LE NN 285425 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1509 MASTER LE NN 285671 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_AWAKE_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1510 MASTER LE NN 285432 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1511 MASTER LE NN 285431 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1512 MASTER LE NN 285433 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1513 MASTER LE NN 285809 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1514 MASTER LE NN 285822 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1515 MASTER LE NN 285824 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1516 MASTER LE NN 285767 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1517 MASTER LE NN 285663 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1518 MASTER LE NN 285746 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1519 MASTER LE NN 285655 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1520 MASTER LE NN 285163 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_
u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1521 MASTER LE NN 285181 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1522 MASTER LE NN 287634 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1523 MASTER LE NN 287468 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1524 MASTER LE NN 287626 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1525 MASTER LE NN 287472 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1526 MASTER LE NN 287470 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1527 MASTER LE NN 287474 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1528 MASTER LE NN 287628 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1529 MASTER LE NN 287479 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[6] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1530 MASTER LE NN 287622 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1531 MASTER LE NN 285180 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1532 MASTER LE NN 285849 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_sync1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1533 MASTER LE NN 285424 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_capture1_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 1534 MASTER LE NN 285416 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_a2d_comp_out_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1535 MASTER LE NN 285853 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_glue_u/d_refdac_sample_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1536 MASTER LE NN 285170 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1537 MASTER LE NN 285057 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_lfrc_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1538 MASTER LE NN 285079 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_clk_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1539 MASTER LE NN 285095 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_lfrc_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1540 MASTER LE NN 285858 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1541 MASTER LE NN 285812 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1542 MASTER LE NN 285860 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 1543 MASTER LE NN 285799 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1544 MASTER LE NN 285798 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1545 MASTER LE NN 285801 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1546 MASTER LE NN 285800 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1547 MASTER LE NN 285808 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1548 MASTER LE NN 285806 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1549 MASTER LE NN 285804 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1550 MASTER LE NN 285810 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1551 MASTER LE NN 285058 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_lfrc_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1552 MASTER LE NN 285164 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1553 MASTER LE NN 285168 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1554 MASTER LE NN 285167 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1555 MASTER LE NN 285173 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_glue_u/d_refdac_smpl_counter_high_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1556 MASTER LE NN 285166 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1557 MASTER LE NN 285165 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1558 MASTER LE NN 285204 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1559 MASTER LE NN 285205 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1560 MASTER LE NN 285207 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1561 MASTER LE NN 285202 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_
qual_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1562 MASTER LE NN 285171 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_1st_window_pulse_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1563 MASTER LE NN 285169 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1564 MASTER LE NN 285873 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1565 MASTER LE NN 285096 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_lfrc_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1566 MASTER LE NN 285078 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_clk_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1567 MASTER LE NN 285748 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1568 MASTER LE NN 285742 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1569 MASTER LE NN 285777 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_M1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1570 MASTER LE NN 285754 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1571 MASTER LE NN 285657 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1572 MASTER LE NN 285656 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1573 MASTER LE NN 285778 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_M1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1574 MASTER LE NN 285654 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1575 MASTER LE NN 285779 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1576 MASTER LE NN 285426 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1577 MASTER LE NN 285098 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1578 MASTER LE NN 285786 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1579 MASTER LE NN 285788 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1580 MASTER LE NN 285859 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1581 MASTER LE NN 285791 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1582 MASTER LE NN 285811 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1583 MASTER LE NN 285857 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1584 MASTER LE NN 285787 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1585 MASTER LE NN 285388 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1586 MASTER LE NN 285427 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1587 MASTER LE NN 285805 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1588 MASTER LE NN 285428 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1589 MASTER LE NN 285551 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1590 MASTER LE NN 285436 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1591 MASTER LE NN 285430 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1592 MASTER LE NN 285662 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1593 MASTER LE NN 285434 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1594 MASTER LE NN 285550 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1595 MASTER LE NN 285548 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1596 MASTER LE NN 285546 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1597 MASTER LE NN 285720 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1598 MASTER LE NN 285716 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1599 MASTER LE NN 285715 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1600 MASTER LE NN 285717 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 1601 MASTER LE NN 285727 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 1602 MASTER LE NN 285704 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 1603 MASTER LE NN 285703 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1604 MASTER LE NN 285702 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1605 MASTER LE NN 285879 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 1606 MASTER LE NN 285719 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1607 MASTER LE NN 285721 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1608 MASTER LE NN 285718 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1609 MASTER LE NN 285724 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1610 MASTER LE NN 285068 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1611 MASTER LE NN 285069 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1612 MASTER LE NN 285722 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1613 MASTER LE NN 285723 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1614 MASTER LE NN 285070 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1615 MASTER LE NN 285067 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1616 MASTER LE NN 285049 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_duty_out_int_reg (M31_1P5V6T_SFFRBQX1)
 Chain[2] 1617 MASTER LE NN 285048 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_duty_out_half_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1618 MASTER LE NN 285536 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1619 MASTER LE NN 285054 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1620 MASTER LE NN 285820 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1621 MASTER LE NN 285862 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1622 MASTER LE NN 285726 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_slib_sync/sync_d_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1623 MASTER LE NN 285725 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_slib_sync/sync_d_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1624 MASTER LE NN 285071 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1625 MASTER LE NN 285072 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1626 MASTER LE NN 285073 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1627 MASTER LE NN 285074 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1628 MASTER LE NN 285023 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1629 MASTER LE NN 285024 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1630 MASTER LE NN 285815 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/dtmp_reg (M31_1P5V6T_SFFRSBQX1)
Chain[2] 1631 MASTER LE NN 285061 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1632 MASTER LE NN 285060 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1633 MASTER LE NN 285064 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_en_meas_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1634 MASTER LE NN 285066 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1635 MASTER LE NN 285046 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_19p2_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1636 MASTER LE NN 285045 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_19p2_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1637 MASTER LE NN 285047 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_CTLR_MISC4__DUTY_GENERATOR_EN_rifo_del_r
eg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1638 MASTER LE NN 285813 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1639 MASTER LE NN 285033 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_en_rb/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1640 MASTER LE NN 285816 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1641 MASTER LE NN 285065 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1642 MASTER LE NN 285286 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1643 MASTER LE NN 285758 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 1644 MASTER LE NN 285034 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_en_rb/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1645 MASTER LE NN 285817 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1646 MASTER LE NN 285672 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_EN_CTL__PERPH_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
 Chain[2] 1647 MASTER LE NN 285814 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1648 MASTER LE NN 285759 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1649 MASTER LE NN 285760 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1650 MASTER LE NN 285775 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1651 MASTER LE NN 285287 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1652 MASTER LE NN 285059 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1653 MASTER LE NN 285825 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1654 MASTER LE NN 285062 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1655 MASTER LE NN 285790 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1656 MASTER LE NN 285063 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1657 MASTER LE NN 285077 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1658 MASTER LE NN 285076 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1659 MASTER LE NN 285289 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1660 MASTER LE NN 285288 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1661 MASTER LE NN 285768 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1662 MASTER LE NN 285770 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1663 MASTER LE NN 285776 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1664 MASTER LE NN 285766 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1665 MASTER LE NN 285773 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_slib_sync/s
ync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1666 MASTER LE NN 285133 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_sample_4_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1667 MASTER LE NN 285131 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_sample_2_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1668 MASTER LE NN 285139 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1669 MASTER LE NN 285138 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1670 MASTER LE NN 285745 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1671 MASTER LE NN 285743 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1672 MASTER LE NN 285755 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1673 MASTER LE NN 285757 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1674 MASTER LE NN 285753 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1675 MASTER LE NN 285749 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1676 MASTER LE NN 284974 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[11] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1677 MASTER LE NN 285751 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1678 MASTER LE NN 285747 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1679 MASTER LE NN 285012 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[10]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1680 MASTER LE NN 284975 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1681 MASTER LE NN 284979 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1682 MASTER LE NN 284973 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[9] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1683 MASTER LE NN 285854 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1684 MASTER LE NN 285178 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_refd
ac_smpl_clk_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1685 MASTER LE NN 285206 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1686 MASTER LE NN 285203 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1687 MASTER LE NN 285856 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1688 MASTER LE NN 285855 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1689 MASTER LE NN 284972 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[10] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1690 MASTER LE NN 284969 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1691 MASTER LE NN 284968 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1692 MASTER LE NN 284971 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1693 MASTER LE NN 284970 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1694 MASTER LE NN 284977 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1695 MASTER LE NN 285011 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[11]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1696 MASTER LE NN 285016 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1697 MASTER LE NN 285022 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1698 MASTER LE NN 285140 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1699 MASTER LE NN 285020 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1700 MASTER LE NN 285019 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1701 MASTER LE NN 285017 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1702 MASTER LE NN 285018 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1703 MASTER LE NN 285137 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1704 MASTER LE NN 285136 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1705 MASTER LE NN 285135 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[7]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 1706 MASTER LE NN 285132 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_sample_3_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1707 MASTER LE NN 285134 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_sample_5_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1708 MASTER LE NN 285764 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1709 MASTER LE NN 285762 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1710 MASTER LE NN 285772 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_slib_sync/s
ync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 1711 MASTER LE NN 285082 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_en
_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1712 MASTER LE NN 285081 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_sl
ib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1713 MASTER LE NN 285097 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1714 MASTER LE NN 285086 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1715 MASTER LE NN 284981 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1716 MASTER LE NN 285080 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_sl
ib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1717 MASTER LE NN 285821 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1718 MASTER LE NN 285819 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_slib_sync/sync_d_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1719 MASTER LE NN 285818 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_slib_sync/sync_d_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1720 MASTER LE NN 285542 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1721 MASTER LE NN 285538 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1722 MASTER LE NN 285053 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1723 MASTER LE NN 285050 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1724 MASTER LE NN 285052 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1725 MASTER LE NN 285877 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1726 MASTER LE NN 285008 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1727 MASTER LE NN 285007 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1728 MASTER LE NN 285002 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1729 MASTER LE NN 285341 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/slib_sync_u1
/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1730 MASTER LE NN 285010 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1731 MASTER LE NN 285009 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1732 MASTER LE NN 285039 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1733 MASTER LE NN 285040 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1734 MASTER LE NN 285410 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1735 MASTER LE NN 285051 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1736 MASTER LE NN 285038 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1737 MASTER LE NN 285037 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1738 MASTER LE NN 285540 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1739 MASTER LE NN 285041 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1740 MASTER LE NN 285411 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1741 MASTER LE NN 285042 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1742 MASTER LE NN 285340 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/slib_sync_u1
/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1743 MASTER LE NN 285006 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1744 MASTER LE NN 284987 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1745 MASTER LE NN 285084 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1746 MASTER LE NN 284985 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1747 MASTER LE NN 284982 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1748 MASTER LE NN 285375 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1749 MASTER LE NN 285367 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1750 MASTER LE NN 285353 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1751 MASTER LE NN 285354 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1752 MASTER LE NN 285085 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1753 MASTER LE NN 284988 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1754 MASTER LE NN 285339 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/slib_sync_u1
/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1755 MASTER LE NN 285044 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1756 MASTER LE NN 285043 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1757 MASTER LE NN 285544 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1758 MASTER LE NN 285346 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1759 MASTER LE NN 285365 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1760 MASTER LE NN 284999 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_out_reg_re
g (M31_1P5V6T_SFFRBQX1)
Chain[2] 1761 MASTER LE NN 285378 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1762 MASTER LE NN 285379 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1763 MASTER LE NN 285355 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1764 MASTER LE NN 285377 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1765 MASTER LE NN 285359 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[2] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 1766 MASTER LE NN 285364 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1767 MASTER LE NN 285366 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1768 MASTER LE NN 285347 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1769 MASTER LE NN 285348 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1770 MASTER LE NN 285083 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_en
_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1771 MASTER LE NN 285349 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1772 MASTER LE NN 285357 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1773 MASTER LE NN 285362 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1774 MASTER LE NN 285358 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1775 MASTER LE NN 285363 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1776 MASTER LE NN 285361 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1777 MASTER LE NN 285360 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1778 MASTER LE NN 285369 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1779 MASTER LE NN 285376 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1780 MASTER LE NN 285408 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1781 MASTER LE NN 285384 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1782 MASTER LE NN 285381 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1783 MASTER LE NN 285391 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1784 MASTER LE NN 285386 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1785 MASTER LE NN 285393 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1786 MASTER LE NN 285407 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1787 MASTER LE NN 285406 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1788 MASTER LE NN 285350 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1789 MASTER LE NN 285351 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1790 MASTER LE NN 285344 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1791 MASTER LE NN 285127 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_clear_latch_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1792 MASTER LE NN 285129 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1793 MASTER LE NN 285345 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1794 MASTER LE NN 285413 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1795 MASTER LE NN 285414 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1796 MASTER LE NN 285087 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1797 MASTER LE NN 285090 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1798 MASTER LE NN 285111 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1799 MASTER LE NN 285093 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1800 MASTER LE NN 285094 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1801 MASTER LE NN 285120 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1802 MASTER LE NN 285118 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1803 MASTER LE NN 285091 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1804 MASTER LE NN 285112 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1805 MASTER LE NN 285125 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_calc_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1806 MASTER LE NN 285109 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_sync_b_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1807 MASTER LE NN 285130 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1808 MASTER LE NN 285126 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_sample_1_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1809 MASTER LE NN 285141 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1810 MASTER LE NN 285142 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 1811 MASTER LE NN 285021 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1812 MASTER LE NN 285110 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_sync_b_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1813 MASTER LE NN 285107 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1814 MASTER LE NN 285124 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_sample_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1815 MASTER LE NN 285122 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1816 MASTER LE NN 285123 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1817 MASTER LE NN 285114 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1818 MASTER LE NN 285113 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1819 MASTER LE NN 285108 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1820 MASTER LE NN 284976 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1821 MASTER LE NN 284978 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1822 MASTER LE NN 285015 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1823 MASTER LE NN 285014 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[8]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1824 MASTER LE NN 285013 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[9]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1825 MASTER LE NN 285116 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1826 MASTER LE NN 285115 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1827 MASTER LE NN 285117 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1828 MASTER LE NN 285121 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1829 MASTER LE NN 285119 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1830 MASTER LE NN 285092 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1831 MASTER LE NN 285089 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1832 MASTER LE NN 285088 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1833 MASTER LE NN 285385 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1834 MASTER LE NN 285392 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1835 MASTER LE NN 285389 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1836 MASTER LE NN 285387 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1837 MASTER LE NN 285371 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1838 MASTER LE NN 285356 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1839 MASTER LE NN 285861 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1840 MASTER LE NN 285352 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1841 MASTER LE NN 284986 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1842 MASTER LE NN 285342 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/slib_sync_u1
/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1843 MASTER LE NN 285003 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1844 MASTER LE NN 285001 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1845 MASTER LE NN 285390 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1846 MASTER LE NN 285409 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1847 MASTER LE NN 285383 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1848 MASTER LE NN 285382 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1849 MASTER LE NN 285372 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1850 MASTER LE NN 285380 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1851 MASTER LE NN 285374 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1852 MASTER LE NN 285373 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1853 MASTER LE NN 285368 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1854 MASTER LE NN 284984 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1855 MASTER LE NN 284983 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1856 MASTER LE NN 285004 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
4] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 1857 MASTER LE NN 285005 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1858 MASTER LE NN 285000 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1859 MASTER LE NN 287337 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[5]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1860 MASTER LE NN 285404 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[5]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_glitchfree_mux_1p0_c
lk_qual_u/sel0_0_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 1861 MASTER LE NN 287265 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
DSLAVE LS NN 257663 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX3)
Chain[2] 1862 MASTER LE NN 287108 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1863 MASTER LE NN 287114 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1864 MASTER LE NN 287016 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1865 MASTER LE NN 284454 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1866 MASTER LE NN 284436 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1867 MASTER LE NN 284445 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1868 MASTER LE NN 284428 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1869 MASTER LE NN 284432 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1870 MASTER LE NN 284415 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1871 MASTER LE NN 284924 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1872 MASTER LE NN 284441 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1873 MASTER LE NN 284166 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1874 MASTER LE NN 284165 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1875 MASTER LE NN 284053 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1876 MASTER LE NN 284190 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1877 MASTER LE NN 284192 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1878 MASTER LE NN 284193 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1879 MASTER LE NN 284185 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1880 MASTER LE NN 284186 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1881 MASTER LE NN 284191 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1882 MASTER LE NN 284187 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1883 MASTER LE NN 284189 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1884 MASTER LE NN 284194 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_sample_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1885 MASTER LE NN 284825 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1886 MASTER LE NN 284183 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1887 MASTER LE NN 284821 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 1888 MASTER LE NN 284110 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1889 MASTER LE NN 284198 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1890 MASTER LE NN 284109 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1891 MASTER LE NN 284113 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1892 MASTER LE NN 284112 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1893 MASTER LE NN 284116 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1894 MASTER LE NN 284115 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1895 MASTER LE NN 284268 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1896 MASTER LE NN 284266 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1897 MASTER LE NN 284227 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1898 MASTER LE NN 284263 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_
qual_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1899 MASTER LE NN 284234 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_glue_u/d_refdac_smpl_counter_high_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1900 MASTER LE NN 284916 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1901 MASTER LE NN 284224 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_
u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1902 MASTER LE NN 284153 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_sl
ib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1903 MASTER LE NN 284157 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1904 MASTER LE NN 284055 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1905 MASTER LE NN 284052 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1906 MASTER LE NN 284159 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1907 MASTER LE NN 284163 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1908 MASTER LE NN 284164 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1909 MASTER LE NN 284054 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1910 MASTER LE NN 284162 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1911 MASTER LE NN 284161 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1912 MASTER LE NN 284160 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1913 MASTER LE NN 284416 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1914 MASTER LE NN 284425 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1915 MASTER LE NN 284422 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1916 MASTER LE NN 284411 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1917 MASTER LE NN 284412 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1918 MASTER LE NN 284417 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1919 MASTER LE NN 284438 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1920 MASTER LE NN 284440 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1921 MASTER LE NN 284437 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1922 MASTER LE NN 284444 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1923 MASTER LE NN 284443 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_clear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1924 MASTER LE NN 284442 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1925 MASTER LE NN 284469 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1926 MASTER LE NN 284433 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1927 MASTER LE NN 284434 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1928 MASTER LE NN 284429 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1929 MASTER LE NN 284435 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1930 MASTER LE NN 284470 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 1931 MASTER LE NN 284450 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1932 MASTER LE NN 284430 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1933 MASTER LE NN 284420 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1934 MASTER LE NN 284448 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1935 MASTER LE NN 284424 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1936 MASTER LE NN 284439 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1937 MASTER LE NN 284426 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1938 MASTER LE NN 284474 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_pong_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1939 MASTER LE NN 284475 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_lfrc_req_ping_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1940 MASTER LE NN 284056 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1941 MASTER LE NN 284057 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1942 MASTER LE NN 284058 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1943 MASTER LE NN 284915 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1944 MASTER LE NN 284914 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1945 MASTER LE NN 284239 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_refd
ac_smpl_clk_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1946 MASTER LE NN 284232 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_1st_window_pulse_reg (M31_1P5V6T_SFFRBQX1)
 Chain[2] 1947 MASTER LE NN 284228 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1948 MASTER LE NN 284229 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1949 MASTER LE NN 284226 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1950 MASTER LE NN 284264 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1951 MASTER LE NN 284265 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1952 MASTER LE NN 284267 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1953 MASTER LE NN 284114 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1954 MASTER LE NN 284472 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_ping_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1955 MASTER LE NN 284471 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1956 MASTER LE NN 284199 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1957 MASTER LE NN 284829 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1958 MASTER LE NN 284831 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1959 MASTER LE NN 284820 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1960 MASTER LE NN 284827 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1961 MASTER LE NN 284823 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1962 MASTER LE NN 284181 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_sync_b_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1963 MASTER LE NN 284182 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_load_flag_sync_b_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1964 MASTER LE NN 284041 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1965 MASTER LE NN 284195 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_calc_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1966 MASTER LE NN 284188 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1967 MASTER LE NN 284047 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1968 MASTER LE NN 284085 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[9]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1969 MASTER LE NN 284090 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1970 MASTER LE NN 284088 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1971 MASTER LE NN 284039 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 1972 MASTER LE NN 284087 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 1973 MASTER LE NN 284184 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1974 MASTER LE NN 284200 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1975 MASTER LE NN 284201 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1976 MASTER LE NN 284819 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
 Chain[2] 1977 MASTER LE NN 284230 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1978 MASTER LE NN 284225 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1979 MASTER LE NN 284873 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1980 MASTER LE NN 284875 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/dtmp_reg (M31_1P5V6T_SFFRSBQX1)
Chain[2] 1981 MASTER LE NN 284876 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1982 MASTER LE NN 284877 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1983 MASTER LE NN 284913 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_glue_u/d_refdac_sample_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1984 MASTER LE NN 284152 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_sl
ib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1985 MASTER LE NN 284155 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_en
_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1986 MASTER LE NN 284879 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_slib_sync/sync_d_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 1987 MASTER LE NN 284051 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1988 MASTER LE NN 284158 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1989 MASTER LE NN 284169 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1990 MASTER LE NN 284154 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_en
_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 1991 MASTER LE NN 284156 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/u_vr
eg_fault_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 1992 MASTER LE NN 284167 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_lfrc_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1993 MASTER LE NN 284150 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_clk_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1994 MASTER LE NN 284151 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_clk_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1995 MASTER LE NN 284168 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_lfrc_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1996 MASTER LE NN 284407 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1997 MASTER LE NN 284408 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1998 MASTER LE NN 284427 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 1999 MASTER LE NN 284423 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2000 MASTER LE NN 284419 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2001 MASTER LE NN 284410 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2002 MASTER LE NN 284413 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2003 MASTER LE NN 284409 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2004 MASTER LE NN 284911 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_curr_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2005 MASTER LE NN 284178 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2006 MASTER LE NN 284177 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2007 MASTER LE NN 284241 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2008 MASTER LE NN 284431 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2009 MASTER LE NN 284402 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/slib_sync_u1
/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2010 MASTER LE NN 284403 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/slib_sync_u1
/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2011 MASTER LE NN 284406 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2012 MASTER LE NN 284071 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2013 MASTER LE NN 284073 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2014 MASTER LE NN 284072 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2015 MASTER LE NN 284074 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2016 MASTER LE NN 287036 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2017 MASTER LE NN 284076 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2018 MASTER LE NN 287017 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2019 MASTER LE NN 287035 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2020 MASTER LE NN 287031 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2021 MASTER LE NN 284446 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2022 MASTER LE NN 287033 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2023 MASTER LE NN 287012 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2024 MASTER LE NN 287014 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2025 MASTER LE NN 287106 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2026 MASTER LE NN 287112 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2027 MASTER LE NN 287120 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[7] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2028 MASTER LE NN 287277 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2029 MASTER LE NN 287275 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2030 MASTER LE NN 287263 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2031 MASTER LE NN 287273 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2032 MASTER LE NN 287271 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2033 MASTER LE NN 287269 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2034 MASTER LE NN 287267 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2035 MASTER LE NN 287110 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2036 MASTER LE NN 287116 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2037 MASTER LE NN 287118 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[6] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2038 MASTER LE NN 287015 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2039 MASTER LE NN 287013 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2040 MASTER LE NN 287032 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2041 MASTER LE NN 287034 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2042 MASTER LE NN 284453 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2043 MASTER LE NN 284452 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2044 MASTER LE NN 284451 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2045 MASTER LE NN 284447 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2046 MASTER LE NN 284405 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2047 MASTER LE NN 284421 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_s
tate_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2048 MASTER LE NN 284414 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2049 MASTER LE NN 284468 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2050 MASTER LE NN 284467 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg
(M31_1P5V6T_SFFSBQX1)
 Chain[2] 2051 MASTER LE NN 284418 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2052 MASTER LE NN 284477 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_a2d_comp_out_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2053 MASTER LE NN 284909 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_sync1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2054 MASTER LE NN 284237 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_refdac_sample_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2055 MASTER LE NN 284485 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_comp_out_capture1_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 2056 MASTER LE NN 284176 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_u1/cl
k_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2057 MASTER LE NN 284130 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_lfrc_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2058 MASTER LE NN 284129 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_lfrc_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2059 MASTER LE NN 284880 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2060 MASTER LE NN 284881 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2061 MASTER LE NN 284874 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2062 MASTER LE NN 284135 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2063 MASTER LE NN 284134 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2064 MASTER LE NN 284231 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2065 MASTER LE NN 284106 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_en_rb/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2066 MASTER LE NN 284105 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_en_rb/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2067 MASTER LE NN 284837 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2068 MASTER LE NN 284836 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2069 MASTER LE NN 284118 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_19p2_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2070 MASTER LE NN 284117 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_reg_on_clk_19p2_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2071 MASTER LE NN 284111 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_reg_on_19p2_req_pong_shift_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2072 MASTER LE NN 284196 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_clear_latch_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2073 MASTER LE NN 284834 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_slib_sync/s
ync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2074 MASTER LE NN 284833 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_slib_sync/s
ync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2075 MASTER LE NN 284938 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2076 MASTER LE NN 284046 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2077 MASTER LE NN 284040 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2078 MASTER LE NN 284202 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2079 MASTER LE NN 284089 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2080 MASTER LE NN 284203 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/d_ahc_offset_sat_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2081 MASTER LE NN 284086 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[8]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2082 MASTER LE NN 284091 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2083 MASTER LE NN 284048 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2084 MASTER LE NN 284093 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2085 MASTER LE NN 284921 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2086 MASTER LE NN 284094 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2087 MASTER LE NN 284042 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2088 MASTER LE NN 284083 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[11]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2089 MASTER LE NN 284084 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[10]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2090 MASTER LE NN 284092 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_vset_sync/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2091 MASTER LE NN 284044 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[9] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2092 MASTER LE NN 284045 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[11] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2093 MASTER LE NN 284043 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[10] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2094 MASTER LE NN 284049 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_rlib_ps_reg_ahc_adj_vset_sync/dout
_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2095 MASTER LE NN 284180 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2096 MASTER LE NN 284179 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_ahc_logic_1p0_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2097 MASTER LE NN 284798 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2098 MASTER LE NN 284792 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2099 MASTER LE NN 284799 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2100 MASTER LE NN 284794 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2101 MASTER LE NN 284732 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN1_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2102 MASTER LE NN 284733 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN2_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2103 MASTER LE NN 284728 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2104 MASTER LE NN 284727 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2105 MASTER LE NN 284491 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2106 MASTER LE NN 284494 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2107 MASTER LE NN 284497 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2108 MASTER LE NN 284493 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2109 MASTER LE NN 284495 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
 Chain[2] 2110 MASTER LE NN 284486 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2111 MASTER LE NN 284492 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2112 MASTER LE NN 284735 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_EN_CTL__PERPH_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2113 MASTER LE NN 284726 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2114 MASTER LE NN 284730 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2115 MASTER LE NN 284501 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2116 MASTER LE NN 284608 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2117 MASTER LE NN 284499 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2118 MASTER LE NN 284136 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_en_meas_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2119 MASTER LE NN 284148 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2120 MASTER LE NN 284149 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2121 MASTER LE NN 284878 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_slib_sync/sync_d_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2122 MASTER LE NN 284885 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2123 MASTER LE NN 284597 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 2124 MASTER LE NN 284745 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 2125 MASTER LE NN 284743 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/sync_u0/sync_d_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2126 MASTER LE NN 284715 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_REFSAMPLE_TIMER_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2127 MASTER LE NN 284170 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/u_reg_ocp_logic_2p0_dig_mod/d_vr
eg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2128 MASTER LE NN 284744 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1_bus_sync_en/sync_u0/sync_d_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2129 MASTER LE NN 284606 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2130 MASTER LE NN 284600 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2131 MASTER LE NN 284248 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2132 MASTER LE NN 284912 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_curr_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2133 MASTER LE NN 284238 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_fsm_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2134 MASTER LE NN 284460 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_wake_ctrl_fsm_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 2135 MASTER LE NN 284244 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2136 MASTER LE NN 284243 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2137 MASTER LE NN 284240 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2138 MASTER LE NN 284242 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2139 MASTER LE NN 284400 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/slib_sync_u1
/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2140 MASTER LE NN 284082 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2141 MASTER LE NN 284401 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/slib_sync_u1
/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2142 MASTER LE NN 284081 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2143 MASTER LE NN 284080 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2144 MASTER LE NN 284079 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2145 MASTER LE NN 284078 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2146 MASTER LE NN 284077 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_count_reg[
4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2147 MASTER LE NN 287022 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2148 MASTER LE NN 287024 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2149 MASTER LE NN 284075 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_count_reg[
4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2150 MASTER LE NN 287037 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2151 MASTER LE NN 287038 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2152 MASTER LE NN 287018 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2153 MASTER LE NN 287019 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2154 MASTER LE NN 287026 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2155 MASTER LE NN 287009 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2156 MASTER LE NN 287023 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2157 MASTER LE NN 284297 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2158 MASTER LE NN 284295 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2159 MASTER LE NN 284259 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2160 MASTER LE NN 284258 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2161 MASTER LE NN 284257 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2162 MASTER LE NN 284253 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2163 MASTER LE NN 284255 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/slib_clkreq_gate_1p0_hf_clk_u1
/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2164 MASTER LE NN 284262 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2165 MASTER LE NN 284256 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ctrl_fsm_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2166 MASTER LE NN 284479 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ctrl_fsm_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2167 MASTER LE NN 284478 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2168 MASTER LE NN 284249 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_force_wake_ps_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2169 MASTER LE NN 284246 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2170 MASTER LE NN 284245 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2171 MASTER LE NN 284247 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2172 MASTER LE NN 284602 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2173 MASTER LE NN 284604 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2174 MASTER LE NN 284922 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2175 MASTER LE NN 284598 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2176 MASTER LE NN 284882 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2177 MASTER LE NN 284884 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_slib_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2178 MASTER LE NN 284131 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2179 MASTER LE NN 284599 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2180 MASTER LE NN 284610 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2181 MASTER LE NN 284609 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2182 MASTER LE NN 284498 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2183 MASTER LE NN 284571 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2184 MASTER LE NN 284489 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2185 MASTER LE NN 284487 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2186 MASTER LE NN 284490 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL2__GANG_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2187 MASTER LE NN 284496 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2188 MASTER LE NN 284734 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_AWAKE_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2189 MASTER LE NN 284725 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2190 MASTER LE NN 284731 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN0_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2191 MASTER LE NN 284742 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2192 MASTER LE NN 284793 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2193 MASTER LE NN 284796 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2194 MASTER LE NN 284795 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2195 MASTER LE NN 284790 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2196 MASTER LE NN 284789 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2197 MASTER LE NN 284858 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2198 MASTER LE NN 284859 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
 Chain[2] 2199 MASTER LE NN 284860 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2200 MASTER LE NN 284920 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2201 MASTER LE NN 284814 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2202 MASTER LE NN 284812 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2203 MASTER LE NN 284808 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2204 MASTER LE NN 284806 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2205 MASTER LE NN 284816 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2206 MASTER LE NN 284804 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2207 MASTER LE NN 287071 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL2__GANG_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2208 MASTER LE NN 287042 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2209 MASTER LE NN 287075 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2210 MASTER LE NN 287074 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2211 MASTER LE NN 287077 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2212 MASTER LE NN 287076 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2213 MASTER LE NN 287073 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
 Chain[2] 2214 MASTER LE NN 287251 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2215 MASTER LE NN 287243 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2216 MASTER LE NN 287237 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2217 MASTER LE NN 287244 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2218 MASTER LE NN 287245 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2219 MASTER LE NN 287238 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2220 MASTER LE NN 287256 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2221 MASTER LE NN 287249 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2222 MASTER LE NN 287068 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2223 MASTER LE NN 287072 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2224 MASTER LE NN 287078 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2225 MASTER LE NN 287069 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2226 MASTER LE NN 287043 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2227 MASTER LE NN 287065 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2228 MASTER LE NN 287066 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2229 MASTER LE NN 287064 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2230 MASTER LE NN 287007 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 2231 MASTER LE NN 287006 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2232 MASTER LE NN 287010 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2233 MASTER LE NN 284299 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2234 MASTER LE NN 284261 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2235 MASTER LE NN 284260 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2236 MASTER LE NN 284209 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2237 MASTER LE NN 284291 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2238 MASTER LE NN 284746 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2239 MASTER LE NN 284749 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2240 MASTER LE NN 284747 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2241 MASTER LE NN 284388 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_sync_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2242 MASTER LE NN 284387 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_sync_3p0_trimout_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2243 MASTER LE NN 284480 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_en_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2244 MASTER LE NN 284386 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_sync_3p0_trimout_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2245 MASTER LE NN 284391 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2246 MASTER LE NN 284711 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_2__POWER_BOOST_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2247 MASTER LE NN 284396 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/u_
slib_sync_3p0_trim_cal_act_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2248 MASTER LE NN 284750 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_slib_sync/sy
nc_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2249 MASTER LE NN 284712 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_PS_DLY_reg/dout_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2250 MASTER LE NN 284389 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2251 MASTER LE NN 284107 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_rpm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2252 MASTER LE NN 284251 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2253 MASTER LE NN 284449 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d
_vreg_fault_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2254 MASTER LE NN 284252 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_hf_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2255 MASTER LE NN 284296 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2256 MASTER LE NN 287008 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2257 MASTER LE NN 287011 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2258 MASTER LE NN 287025 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2259 MASTER LE NN 287021 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2260 MASTER LE NN 284289 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2261 MASTER LE NN 284305 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[11] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 2262 MASTER LE NN 284301 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2263 MASTER LE NN 284303 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2264 MASTER LE NN 284254 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_curr_state_hf_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2265 MASTER LE NN 284461 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ctrl_fsm_u1/d_disable_awake_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 2266 MASTER LE NN 284050 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_wake_ps_fsm_reg (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2267 MASTER LE NN 284463 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_enable_toggle_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 2268 MASTER LE NN 284748 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2269 MASTER LE NN 284455 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_npm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2270 MASTER LE NN 284714 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_REFSAMPLE_TIMER_reg/do
ut_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2271 MASTER LE NN 284713 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_PS_DLY_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2272 MASTER LE NN 284394 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_sync_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2273 MASTER LE NN 284395 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/u_
slib_sync_3p0_trim_cal_act_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2274 MASTER LE NN 284716 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AUTO_RETENTION_CTL_1__DIS_RETENTION_MODE_DLY_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2275 MASTER LE NN 284390 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_en_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2276 MASTER LE NN 284605 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2277 MASTER LE NN 284612 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2278 MASTER LE NN 284613 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__OCP_LATCH_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2279 MASTER LE NN 284603 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2280 MASTER LE NN 284611 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2281 MASTER LE NN 284500 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2282 MASTER LE NN 284488 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2283 MASTER LE NN 284709 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2284 MASTER LE NN 284722 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2285 MASTER LE NN 284741 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2286 MASTER LE NN 284809 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2287 MASTER LE NN 284720 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2288 MASTER LE NN 284729 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2289 MASTER LE NN 284847 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2290 MASTER LE NN 284851 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2291 MASTER LE NN 284940 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[2] 2292 MASTER LE NN 284137 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2293 MASTER LE NN 284923 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2294 MASTER LE NN 284872 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2295 MASTER LE NN 284870 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2296 MASTER LE NN 284866 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2297 MASTER LE NN 284864 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2298 MASTER LE NN 284824 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2299 MASTER LE NN 284848 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2300 MASTER LE NN 284740 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2301 MASTER LE NN 284817 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2302 MASTER LE NN 284839 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_M1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2303 MASTER LE NN 284724 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2304 MASTER LE NN 284807 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2305 MASTER LE NN 284846 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_MAX_OFFSET_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2306 MASTER LE NN 284578 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2307 MASTER LE NN 284576 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2308 MASTER LE NN 284710 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2309 MASTER LE NN 284826 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2310 MASTER LE NN 284574 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2311 MASTER LE NN 284573 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2312 MASTER LE NN 284707 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2313 MASTER LE NN 284575 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2314 MASTER LE NN 284717 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2315 MASTER LE NN 284813 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2316 MASTER LE NN 284805 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2317 MASTER LE NN 284721 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2318 MASTER LE NN 284739 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2319 MASTER LE NN 284803 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2320 MASTER LE NN 284850 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2321 MASTER LE NN 284797 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 2322 MASTER LE NN 284861 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2323 MASTER LE NN 284868 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2324 MASTER LE NN 284918 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2325 MASTER LE NN 284818 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2326 MASTER LE NN 284810 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2327 MASTER LE NN 284660 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2328 MASTER LE NN 284616 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2329 MASTER LE NN 284658 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2330 MASTER LE NN 284621 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2331 MASTER LE NN 284619 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2332 MASTER LE NN 284656 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2333 MASTER LE NN 284620 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2334 MASTER LE NN 284653 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2335 MASTER LE NN 284665 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2336 MASTER LE NN 284657 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2337 MASTER LE NN 284862 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2338 MASTER LE NN 284564 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
6] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2339 MASTER LE NN 284738 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2340 MASTER LE NN 284736 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2341 MASTER LE NN 284849 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL1__AHC_RESERVED_HROOM_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2342 MASTER LE NN 284811 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2343 MASTER LE NN 284840 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2344 MASTER LE NN 284843 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2345 MASTER LE NN 284617 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2346 MASTER LE NN 284842 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2347 MASTER LE NN 284719 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2348 MASTER LE NN 284618 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2349 MASTER LE NN 284815 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2350 MASTER LE NN 284844 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
 Chain[2] 2351 MASTER LE NN 284841 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2352 MASTER LE NN 284718 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2353 MASTER LE NN 284503 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2354 MASTER LE NN 284763 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_slib_sync/sync_d
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2355 MASTER LE NN 284762 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2356 MASTER LE NN 284393 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_clkreq_gate_3p0_clk_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2357 MASTER LE NN 284761 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2358 MASTER LE NN 284759 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2359 MASTER LE NN 284398 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_cal_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2360 MASTER LE NN 287048 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2361 MASTER LE NN 287044 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2362 MASTER LE NN 287231 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2363 MASTER LE NN 287253 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2364 MASTER LE NN 287252 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2365 MASTER LE NN 287255 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2366 MASTER LE NN 287233 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2367 MASTER LE NN 287230 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2368 MASTER LE NN 287254 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2369 MASTER LE NN 287239 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2370 MASTER LE NN 287227 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2371 MASTER LE NN 287225 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2372 MASTER LE NN 287241 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2373 MASTER LE NN 287222 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2374 MASTER LE NN 287240 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2375 MASTER LE NN 287242 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2376 MASTER LE NN 287247 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2377 MASTER LE NN 287236 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2378 MASTER LE NN 287246 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2379 MASTER LE NN 287226 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2380 MASTER LE NN 287235 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2381 MASTER LE NN 287234 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2382 MASTER LE NN 287228 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2383 MASTER LE NN 287232 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2384 MASTER LE NN 287050 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2385 MASTER LE NN 287102 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2386 MASTER LE NN 287047 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2387 MASTER LE NN 287046 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2388 MASTER LE NN 287045 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2389 MASTER LE NN 287259 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2390 MASTER LE NN 287049 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2391 MASTER LE NN 284304 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2392 MASTER LE NN 284325 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_stepper_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2393 MASTER LE NN 284397 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_cal_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2394 MASTER LE NN 284302 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2395 MASTER LE NN 284290 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_timer0_exp_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2396 MASTER LE NN 284292 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2397 MASTER LE NN 284298 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2398 MASTER LE NN 284300 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2399 MASTER LE NN 284324 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_stepper_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2400 MASTER LE NN 284288 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_timer1_exp_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2401 MASTER LE NN 284753 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_slib_sync
/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2402 MASTER LE NN 284456 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_npm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2403 MASTER LE NN 284108 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/u_rpm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2404 MASTER LE NN 284505 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2405 MASTER LE NN 284752 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_slib_sync
/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2406 MASTER LE NN 284757 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2407 MASTER LE NN 284756 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2408 MASTER LE NN 284457 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_ocp_logic_ip_wrapper/d_ocp_perph_en_master_reg
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2409 MASTER LE NN 284506 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2410 MASTER LE NN 284758 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 2411 MASTER LE NN 284582 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2412 MASTER LE NN 284504 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX3)
Chain[2] 2413 MASTER LE NN 284607 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPDOWN_READY_CTL__VOUT_EQ_VREF_WAIT_BYPASS_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2414 MASTER LE NN 284392 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
l2r_trim_cal_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2415 MASTER LE NN 284601 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX2J)
Chain[2] 2416 MASTER LE NN 284708 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2417 MASTER LE NN 284572 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 2418 MASTER LE NN 284577 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2419 MASTER LE NN 284540 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PP_PWMBY2_LOOP_EN_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2420 MASTER LE NN 284536 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PWM_F_RIGHT_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX2J)
Chain[2] 2421 MASTER LE NN 284537 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PP_PWMBY2_LOCK_EN_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2422 MASTER LE NN 284541 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PP_PWM_LOOP_EN_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2423 MASTER LE NN 284538 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PP_PWM_LOCK_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2424 MASTER LE NN 284579 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2425 MASTER LE NN 284655 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2426 MASTER LE NN 284615 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2427 MASTER LE NN 284659 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2428 MASTER LE NN 284737 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2429 MASTER LE NN 284832 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2430 MASTER LE NN 284835 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2431 MASTER LE NN 284791 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 2432 MASTER LE NN 284132 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2433 MASTER LE NN 284138 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2434 MASTER LE NN 284133 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2435 MASTER LE NN 284919 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2436 MASTER LE NN 284869 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2437 MASTER LE NN 284614 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2438 MASTER LE NN 284788 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_slib_sync/sync_d_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2439 MASTER LE NN 284787 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_slib_sync/sync_d_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2440 MASTER LE NN 284779 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 2441 MASTER LE NN 284778 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2442 MASTER LE NN 284777 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2443 MASTER LE NN 284783 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2444 MASTER LE NN 284784 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2445 MASTER LE NN 284786 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2446 MASTER LE NN 284785 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2447 MASTER LE NN 284652 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2448 MASTER LE NN 284668 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2449 MASTER LE NN 284650 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2450 MASTER LE NN 284666 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2451 MASTER LE NN 284146 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2452 MASTER LE NN 284865 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2453 MASTER LE NN 284647 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2454 MASTER LE NN 284661 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2455 MASTER LE NN 284645 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2456 MASTER LE NN 284667 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2457 MASTER LE NN 284145 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2458 MASTER LE NN 284551 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2459 MASTER LE NN 284558 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2460 MASTER LE NN 284554 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2461 MASTER LE NN 284556 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__NC_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2462 MASTER LE NN 284557 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2463 MASTER LE NN 284561 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
3] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2464 MASTER LE NN 284549 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__RET_CMP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2465 MASTER LE NN 284649 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2466 MASTER LE NN 284663 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2467 MASTER LE NN 284553 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[2] (M31_1P5V6T_SFFRBQX2J)
Chain[2] 2468 MASTER LE NN 284828 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2469 MASTER LE NN 284830 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2470 MASTER LE NN 284662 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2471 MASTER LE NN 284654 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2472 MASTER LE NN 284539 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PHASE_STAGGERED_LOCK_EN_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2473 MASTER LE NN 284622 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2474 MASTER LE NN 284464 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_power_boost_en_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 2475 MASTER LE NN 284358 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_foldback_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2476 MASTER LE NN 284287 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2477 MASTER LE NN 284208 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_update_fsm_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2478 MASTER LE NN 284103 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_19p2_req_synchro_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2479 MASTER LE NN 284104 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_19p2_req_synchro_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2480 MASTER LE NN 284293 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_timer_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2481 MASTER LE NN 284294 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_timer_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2482 MASTER LE NN 287029 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_cal_act
ivity_en_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2483 MASTER LE NN 287105 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2484 MASTER LE NN 287121 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC3__SENSE_IDAC_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2485 MASTER LE NN 287258 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2486 MASTER LE NN 287224 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2487 MASTER LE NN 287223 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2488 MASTER LE NN 287218 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2489 MASTER LE NN 287217 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2490 MASTER LE NN 287216 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2491 MASTER LE NN 287198 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2492 MASTER LE NN 287250 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2493 MASTER LE NN 287248 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2494 MASTER LE NN 287257 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2495 MASTER LE NN 287067 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2496 MASTER LE NN 287262 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2497 MASTER LE NN 287084 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_MANUAL_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2498 MASTER LE NN 287266 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2499 MASTER LE NN 287260 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2500 MASTER LE NN 287107 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2501 MASTER LE NN 287111 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2502 MASTER LE NN 287109 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2503 MASTER LE NN 287137 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2504 MASTER LE NN 287101 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2505 MASTER LE NN 287041 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_cal_act
ivity_en_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2506 MASTER LE NN 287030 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_l2r_trim_cal
_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2507 MASTER LE NN 284101 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_ps_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2508 MASTER LE NN 284102 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_ps_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2509 MASTER LE NN 284207 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2510 MASTER LE NN 284308 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_mask_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2511 MASTER LE NN 284307 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_mask_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2512 MASTER LE NN 284306 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_update_mask_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2513 MASTER LE NN 284314 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_fsm_mask_en_d2_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2514 MASTER LE NN 284313 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_fsm_mask_en_d1_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2515 MASTER LE NN 284310 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2516 MASTER LE NN 284341 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_buck_en_ret_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2517 MASTER LE NN 284343 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_clk_lfrc_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2518 MASTER LE NN 284328 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_npm_lpm_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2519 MASTER LE NN 284764 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_slib_sync/sync_d
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2520 MASTER LE NN 284883 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2521 MASTER LE NN 284760 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2522 MASTER LE NN 284399 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/d_vreg_ready_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2523 MASTER LE NN 284596 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CTL__MULTIPHASE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2524 MASTER LE NN 284631 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__DACREF_HYST_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2525 MASTER LE NN 284633 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2526 MASTER LE NN 284623 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2527 MASTER LE NN 284629 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2528 MASTER LE NN 284632 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2529 MASTER LE NN 284937 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__DETACH_VREG_READY_CHAIN_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2530 MASTER LE NN 284634 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2531 MASTER LE NN 284801 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2532 MASTER LE NN 284628 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2533 MASTER LE NN 284838 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_M1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2534 MASTER LE NN 284321 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2535 MASTER LE NN 284502 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2536 MASTER LE NN 284643 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__DUTY_GEN_SI_CURRENT_REDUCTION_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2537 MASTER LE NN 284845 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2538 MASTER LE NN 284638 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__VREG_MON_CFG_NPM_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2539 MASTER LE NN 284800 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2540 MASTER LE NN 284535 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PWM_R_RIGHT_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2541 MASTER LE NN 284542 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PHASE_STAGGERED_LOO
P_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2542 MASTER LE NN 284580 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2543 MASTER LE NN 284581 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2544 MASTER LE NN 284583 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2545 MASTER LE NN 284871 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2546 MASTER LE NN 284723 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2547 MASTER LE NN 284552 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2548 MASTER LE NN 284559 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2549 MASTER LE NN 284646 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2550 MASTER LE NN 284592 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2551 MASTER LE NN 284822 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2552 MASTER LE NN 284560 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
2] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2553 MASTER LE NN 284562 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
4] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2554 MASTER LE NN 284563 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
5] (M31_1P5V6T_SFFSBQX1)
 Chain[2] 2555 MASTER LE NN 284139 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2556 MASTER LE NN 284143 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2557 MASTER LE NN 284651 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2558 MASTER LE NN 284917 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2559 MASTER LE NN 284648 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2560 MASTER LE NN 284867 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2561 MASTER LE NN 284119 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_CTLR_MISC4__DUTY_GENERATOR_EN_rifo_del_r
eg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2562 MASTER LE NN 284781 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2563 MASTER LE NN 284782 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2564 MASTER LE NN 284780 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2565 MASTER LE NN 284124 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2566 MASTER LE NN 284123 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2567 MASTER LE NN 284360 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_7_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2568 MASTER LE NN 284361 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_6_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2569 MASTER LE NN 284327 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_mask_pwmcmp_inwarmup_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2570 MASTER LE NN 284204 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2571 MASTER LE NN 284359 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_npm_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2572 MASTER LE NN 284352 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2573 MASTER LE NN 284206 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2574 MASTER LE NN 284354 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2575 MASTER LE NN 284315 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_mode_update_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2576 MASTER LE NN 284357 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2577 MASTER LE NN 284356 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2578 MASTER LE NN 287104 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2579 MASTER LE NN 287083 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_POLARITY_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2580 MASTER LE NN 287134 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2581 MASTER LE NN 287127 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2582 MASTER LE NN 287070 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2583 MASTER LE NN 287119 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2584 MASTER LE NN 287151 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLH_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2585 MASTER LE NN 287261 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2586 MASTER LE NN 287190 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2587 MASTER LE NN 287221 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2588 MASTER LE NN 287220 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2589 MASTER LE NN 287210 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP2_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2590 MASTER LE NN 287199 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2591 MASTER LE NN 287201 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2592 MASTER LE NN 287203 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2593 MASTER LE NN 287202 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2594 MASTER LE NN 287200 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2595 MASTER LE NN 287204 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP3_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2596 MASTER LE NN 287196 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2597 MASTER LE NN 287195 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2598 MASTER LE NN 287219 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2599 MASTER LE NN 287205 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP3_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2600 MASTER LE NN 287192 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2601 MASTER LE NN 287211 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP2_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[2] 2602 MASTER LE NN 287187 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2603 MASTER LE NN 287186 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2604 MASTER LE NN 287168 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2605 MASTER LE NN 287166 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2606 MASTER LE NN 287229 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2607 MASTER LE NN 287153 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__SS_SI_ENABLE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2608 MASTER LE NN 287063 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2609 MASTER LE NN 287138 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2610 MASTER LE NN 287139 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2611 MASTER LE NN 287176 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_SEL_DLY_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2612 MASTER LE NN 287175 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_SEL_DLY_CTRL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2613 MASTER LE NN 287136 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2614 MASTER LE NN 287080 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2615 MASTER LE NN 287081 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2616 MASTER LE NN 287082 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2617 MASTER LE NN 287079 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2618 MASTER LE NN 287103 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2619 MASTER LE NN 287027 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_comp
_fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2620 MASTER LE NN 287020 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_comp_
fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2621 MASTER LE NN 287028 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_fb_latc
h_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2622 MASTER LE NN 284316 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_mode_update_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2623 MASTER LE NN 284355 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2624 MASTER LE NN 284353 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2625 MASTER LE NN 284205 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2626 MASTER LE NN 284312 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2627 MASTER LE NN 284272 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2628 MASTER LE NN 284311 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2629 MASTER LE NN 284309 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2630 MASTER LE NN 284351 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_clk_19p2_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2631 MASTER LE NN 284346 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_smps_clk_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2632 MASTER LE NN 284345 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_smps_clk_buf_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2633 MASTER LE NN 284363 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2634 MASTER LE NN 284342 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_refen_to_bckcmn_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2635 MASTER LE NN 284751 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_slib_sync/sy
nc_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2636 MASTER LE NN 284404 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/d_vreg_error_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2637 MASTER LE NN 284630 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__DACREF_HYST_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2638 MASTER LE NN 284320 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__RETENTION_QUAL_rifi_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2639 MASTER LE NN 284636 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2640 MASTER LE NN 284624 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2641 MASTER LE NN 284685 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_INT_CFG__DUTY_GEN_INT_CAP_CFG_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2642 MASTER LE NN 284692 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_NOTCH_CFG_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2643 MASTER LE NN 284640 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__CAL_FLT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2644 MASTER LE NN 284898 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2645 MASTER LE NN 284147 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_comp_fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2646 MASTER LE NN 284908 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2647 MASTER LE NN 284673 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX3)
Chain[2] 2648 MASTER LE NN 284642 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__PWM_19P2M_CLK_FORCE_ON_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2649 MASTER LE NN 284639 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__VREG_MON_CFG_RM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2650 MASTER LE NN 284644 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__TRAP_GEN_SI_CURRENT_REDUCTION_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2651 MASTER LE NN 284626 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2652 MASTER LE NN 284627 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2653 MASTER LE NN 284637 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2654 MASTER LE NN 284625 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2655 MASTER LE NN 284686 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_INT_CFG__DUTY_GEN_INT_CAP_CFG_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2656 MASTER LE NN 284802 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2657 MASTER LE NN 284641 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__PWM_SMPS_CLK_FORCE_ON_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2658 MASTER LE NN 284939 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2659 MASTER LE NN 284863 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2660 MASTER LE NN 284566 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_POLARITY_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2661 MASTER LE NN 284565 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_MANUAL_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2662 MASTER LE NN 284635 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2663 MASTER LE NN 284584 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2664 MASTER LE NN 284664 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2665 MASTER LE NN 284555 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__NC_TEST_MODE_EN_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2666 MASTER LE NN 284550 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2667 MASTER LE NN 284588 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2668 MASTER LE NN 284595 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2669 MASTER LE NN 284593 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2670 MASTER LE NN 284095 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2671 MASTER LE NN 284590 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2672 MASTER LE NN 284096 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2673 MASTER LE NN 284144 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2674 MASTER LE NN 284140 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2675 MASTER LE NN 284142 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2676 MASTER LE NN 284141 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2677 MASTER LE NN 284773 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 2678 MASTER LE NN 284368 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2679 MASTER LE NN 284334 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2680 MASTER LE NN 284121 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_duty_out_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2681 MASTER LE NN 284120 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_duty_out_half_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2682 MASTER LE NN 284125 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2683 MASTER LE NN 284122 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2684 MASTER LE NN 284126 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2685 MASTER LE NN 284333 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2686 MASTER LE NN 284335 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2687 MASTER LE NN 287128 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2688 MASTER LE NN 287145 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_PRE_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2689 MASTER LE NN 287117 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2690 MASTER LE NN 287150 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLH_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2691 MASTER LE NN 287113 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2692 MASTER LE NN 287115 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2693 MASTER LE NN 287171 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_BLANK_TIME_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2694 MASTER LE NN 287140 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2695 MASTER LE NN 287177 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_SEL_DLY_CTRL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2696 MASTER LE NN 287264 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2697 MASTER LE NN 287123 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2698 MASTER LE NN 287298 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2699 MASTER LE NN 287174 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_BLANK_TIME_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2700 MASTER LE NN 287208 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP1_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2701 MASTER LE NN 287162 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2702 MASTER LE NN 287207 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP2_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2703 MASTER LE NN 287213 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__P_REF2_RATIO_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2704 MASTER LE NN 287212 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP1_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX3)
Chain[2] 2705 MASTER LE NN 287206 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP2_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2706 MASTER LE NN 287197 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2707 MASTER LE NN 287194 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2708 MASTER LE NN 287302 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2709 MASTER LE NN 287209 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP1_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2710 MASTER LE NN 287193 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2711 MASTER LE NN 287191 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2712 MASTER LE NN 287180 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__P_MIN_ON_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2713 MASTER LE NN 287155 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_PRE_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2714 MASTER LE NN 287156 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2715 MASTER LE NN 287270 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2716 MASTER LE NN 287178 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_SEL_DLY_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2717 MASTER LE NN 287141 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2718 MASTER LE NN 287268 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2719 MASTER LE NN 287173 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_BLANK_TIME_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2720 MASTER LE NN 287172 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_BLANK_TIME_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2721 MASTER LE NN 287149 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2722 MASTER LE NN 287148 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2723 MASTER LE NN 287131 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2724 MASTER LE NN 287126 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2725 MASTER LE NN 287147 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__ZX_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2726 MASTER LE NN 287129 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2727 MASTER LE NN 287144 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_PRE_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2728 MASTER LE NN 287135 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2729 MASTER LE NN 287146 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__ZX_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2730 MASTER LE NN 287124 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2731 MASTER LE NN 284068 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2732 MASTER LE NN 284348 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2733 MASTER LE NN 284347 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2734 MASTER LE NN 284210 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_master_
en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2735 MASTER LE NN 284322 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_bypass_
en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2736 MASTER LE NN 284323 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_bypass_
en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2737 MASTER LE NN 284362 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2738 MASTER LE NN 284222 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2739 MASTER LE NN 284522 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2740 MASTER LE NN 284520 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2741 MASTER LE NN 284527 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2742 MASTER LE NN 284671 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2743 MASTER LE NN 284672 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2744 MASTER LE NN 284705 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_EN_COMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2745 MASTER LE NN 284703 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2746 MASTER LE NN 284678 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__BW_PHASE_STAGGER_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2747 MASTER LE NN 284591 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2748 MASTER LE NN 284380 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2749 MASTER LE NN 284371 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2750 MASTER LE NN 284339 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2751 MASTER LE NN 284332 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2752 MASTER LE NN 284336 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2753 MASTER LE NN 284367 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2754 MASTER LE NN 284765 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2755 MASTER LE NN 284772 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2756 MASTER LE NN 284766 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2757 MASTER LE NN 284569 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1J)
Chain[2] 2758 MASTER LE NN 284570 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2759 MASTER LE NN 284326 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2760 MASTER LE NN 284693 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_NOTCH_CFG_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2761 MASTER LE NN 284669 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_RANGE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2762 MASTER LE NN 284687 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CAP_CFG_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2763 MASTER LE NN 284853 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2764 MASTER LE NN 284856 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2765 MASTER LE NN 284852 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2766 MASTER LE NN 284273 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_STEPPER_DONE_d
_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2767 MASTER LE NN 284329 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_en_tx_reg (M31_1P5V6T_SFFRBQX1)
 Chain[2] 2768 MASTER LE NN 284344 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_vreg_comp_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2769 MASTER LE NN 284350 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2770 MASTER LE NN 284349 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2771 MASTER LE NN 284213 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
clk_req_u/d_clk_req_stepper_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2772 MASTER LE NN 284212 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
clk_req_u/d_clk_req_stepper_meta_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2773 MASTER LE NN 284211 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_fts_ctrl_stepper_master_
en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2774 MASTER LE NN 284220 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2775 MASTER LE NN 284221 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2776 MASTER LE NN 284519 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2777 MASTER LE NN 284521 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2778 MASTER LE NN 284319 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__PS_TRUE_rifi_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2779 MASTER LE NN 284070 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_error_debouncer/d_out_reg_re
g (M31_1P5V6T_SFFRBQX1)
Chain[2] 2780 MASTER LE NN 284069 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_flag_logic_3p0_dig_mod/u_vreg_ready_debouncer/d_out_reg_re
g (M31_1P5V6T_SFFRBQX1)
Chain[2] 2781 MASTER LE NN 284534 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 2782 MASTER LE NN 284855 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2783 MASTER LE NN 284318 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2784 MASTER LE NN 284317 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2785 MASTER LE NN 284466 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__MODE_STATE_rifi_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2786 MASTER LE NN 284857 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_SS_CTL__SS_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2787 MASTER LE NN 284854 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_STEPPER_VS_CTL__VS_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2788 MASTER LE NN 284670 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FB_FILT_CFG__FB_FILT_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX2J)
Chain[2] 2789 MASTER LE NN 284586 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2790 MASTER LE NN 284900 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2791 MASTER LE NN 284899 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2792 MASTER LE NN 284567 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2793 MASTER LE NN 284704 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2794 MASTER LE NN 284681 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PHASE_STAGGER_COMP_CAP_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2795 MASTER LE NN 284684 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__OPEN_LOOP_ACTIVE_CFG_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2796 MASTER LE NN 284594 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2797 MASTER LE NN 284589 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2798 MASTER LE NN 284767 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 2799 MASTER LE NN 284771 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2800 MASTER LE NN 284330 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2801 MASTER LE NN 284331 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX2J)
Chain[2] 2802 MASTER LE NN 284381 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2803 MASTER LE NN 284370 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2804 MASTER LE NN 284369 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2805 MASTER LE NN 284338 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2806 MASTER LE NN 284337 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2807 MASTER LE NN 284768 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[0
] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2808 MASTER LE NN 284770 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[2
] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2809 MASTER LE NN 284699 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX2J)
Chain[2] 2810 MASTER LE NN 284547 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_SPARE_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2811 MASTER LE NN 284568 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2812 MASTER LE NN 284385 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2813 MASTER LE NN 284340 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2814 MASTER LE NN 284174 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_toggle_in_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2815 MASTER LE NN 284706 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_EN_DLL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2816 MASTER LE NN 284543 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2817 MASTER LE NN 284907 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2818 MASTER LE NN 284689 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CURRENT_CFG_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2819 MASTER LE NN 284530 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2820 MASTER LE NN 284545 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2821 MASTER LE NN 284675 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_OUT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2822 MASTER LE NN 284524 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2823 MASTER LE NN 284128 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_int_soft_start_done_reg (M31_1P5V6T_SFFRBQX2J)
Chain[2] 2824 MASTER LE NN 284526 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2825 MASTER LE NN 284067 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2826 MASTER LE NN 284223 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2827 MASTER LE NN 287133 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2828 MASTER LE NN 287132 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2829 MASTER LE NN 287130 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2830 MASTER LE NN 287142 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_3__FOLDBACK_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2831 MASTER LE NN 287095 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2832 MASTER LE NN 287094 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2833 MASTER LE NN 287093 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2834 MASTER LE NN 287152 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__RET_WAKE_FREQ_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2835 MASTER LE NN 287154 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_PRE_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2836 MASTER LE NN 287296 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2837 MASTER LE NN 287297 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2838 MASTER LE NN 287157 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2839 MASTER LE NN 287159 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2840 MASTER LE NN 287165 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2841 MASTER LE NN 287303 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2842 MASTER LE NN 287179 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__P_MIN_ON_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX3)
Chain[2] 2843 MASTER LE II 287001 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 2844 MASTER LE NN 287002 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 2845 MASTER LE NN 287167 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2846 MASTER LE NN 287161 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2847 MASTER LE II 287003 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 2848 MASTER LE II 287160 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2849 MASTER LE II 287214 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__P_REF1_RATIO_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2850 MASTER LE II 287286 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2851 MASTER LE NN 287000 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 2852 MASTER LE NN 287299 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2853 MASTER LE NN 287055 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2854 MASTER LE NN 287061 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2855 MASTER LE NN 287051 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2856 MASTER LE NN 287301 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 2857 MASTER LE NN 287300 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2858 MASTER LE NN 287292 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2859 MASTER LE NN 287294 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2860 MASTER LE NN 287057 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2861 MASTER LE NN 287056 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2862 MASTER LE NN 287215 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__CL_TSTMD_MUX_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2863 MASTER LE NN 287062 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2864 MASTER LE NN 287169 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2865 MASTER LE NN 287188 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2866 MASTER LE NN 287282 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2867 MASTER LE NN 287283 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2868 MASTER LE NN 287189 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2869 MASTER LE NN 287182 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__N_MIN_ON_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2870 MASTER LE NN 287272 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2871 MASTER LE NN 287276 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2872 MASTER LE NN 287274 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2873 MASTER LE NN 287143 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_3__FOLDBACK_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2874 MASTER LE NN 287099 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2875 MASTER LE NN 287122 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2876 MASTER LE NN 287125 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2877 MASTER LE NN 284278 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2878 MASTER LE NN 284276 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2879 MASTER LE NN 284270 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_setpoint_eq_vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2880 MASTER LE NN 284271 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2881 MASTER LE NN 284065 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2882 MASTER LE NN 284066 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2883 MASTER LE NN 284754 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2884 MASTER LE NN 284214 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2885 MASTER LE NN 284064 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 2886 MASTER LE NN 284515 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2887 MASTER LE NN 284523 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2888 MASTER LE NN 284525 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2889 MASTER LE NN 284528 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2890 MASTER LE NN 284531 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2891 MASTER LE NN 284529 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST3__CFG_DTEST3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2892 MASTER LE NN 284532 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2893 MASTER LE NN 284533 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST4__CFG_DTEST4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2894 MASTER LE NN 284690 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CURRENT_CFG_reg
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 2895 MASTER LE NN 284698 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2896 MASTER LE NN 284585 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2897 MASTER LE NN 284587 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2898 MASTER LE II 284036 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 2899 MASTER LE II 284902 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2900 MASTER LE II 284458 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_pong_blank_reg
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2901 MASTER LE II 284175 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_blank_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2902 MASTER LE II 284374 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timeout_reg
(M31_1P5V6T_SFFRBQX2J)
Chain[2] 2903 MASTER LE II 284701 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2904 MASTER LE II 284702 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_NC_CFG1__NC_FILT_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2905 MASTER LE II 284683 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PING_PONG_COMP_CAP_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2906 MASTER LE II 284682 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PHASE_STAGGER_COMP_CAP_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2907 MASTER LE II 284679 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__BW_PHASE_STAGGER_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2908 MASTER LE II 284680 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TX_RX_CFG__PING_PONG_CP_CURRNT_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2909 MASTER LE II 284936 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[3
] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 2910 MASTER LE II 284775 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2911 MASTER LE II 284776 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2912 MASTER LE II 284935 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2913 MASTER LE II 284774 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_ID__PHASE_ID_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 2914 MASTER LE II 284364 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync4/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2915 MASTER LE II 284365 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync4/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2916 MASTER LE II 284376 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2917 MASTER LE II 284375 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2918 MASTER LE II 284378 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2919 MASTER LE II 284379 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2920 MASTER LE II 284383 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2921 MASTER LE II 284382 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2922 MASTER LE II 284377 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2923 MASTER LE II 284384 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2924 MASTER LE II 284372 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2925 MASTER LE II 284366 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2926 MASTER LE II 284373 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2927 MASTER LE II 287090 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2928 MASTER LE II 287089 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2929 MASTER LE II 287091 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2930 MASTER LE II 287092 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2931 MASTER LE II 287085 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2932 MASTER LE II 287086 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2933 MASTER LE II 287096 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2934 MASTER LE NN 286999 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 2935 MASTER LE NN 287278 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2936 MASTER LE NN 287279 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2937 MASTER LE NN 287184 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__SKIP_ZX_CMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2938 MASTER LE NN 287181 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__N_MIN_ON_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2939 MASTER LE NN 286982 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2940 MASTER LE NN 287285 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2941 MASTER LE NN 287058 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2942 MASTER LE NN 287288 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2943 MASTER LE NN 287287 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2944 MASTER LE NN 287284 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2945 MASTER LE NN 287293 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2946 MASTER LE NN 287290 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2947 MASTER LE NN 287059 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2948 MASTER LE NN 287053 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2949 MASTER LE NN 287052 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2950 MASTER LE NN 287060 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2951 MASTER LE NN 287054 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2952 MASTER LE NN 287291 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2953 MASTER LE NN 287289 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2954 MASTER LE NN 287163 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2955 MASTER LE NN 287170 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2956 MASTER LE NN 287281 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2957 MASTER LE NN 287280 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2958 MASTER LE NN 287164 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2959 MASTER LE NN 287183 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__D_P_MIN_ON_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2960 MASTER LE NN 287185 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__SKIP_CL_CMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 2961 MASTER LE NN 287158 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLH_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2962 MASTER LE NN 287295 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2963 MASTER LE NN 287304 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2964 MASTER LE II 287004 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 2965 MASTER LE NN 287005 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 2966 MASTER LE NN 287088 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2967 MASTER LE NN 287087 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2968 MASTER LE NN 287097 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2969 MASTER LE NN 287098 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2970 MASTER LE NN 287100 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2971 MASTER LE NN 286979 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2972 MASTER LE NN 284269 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
flags_u/d_setpoint_gt_vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 2973 MASTER LE NN 284282 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2974 MASTER LE NN 284216 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2975 MASTER LE NN 284061 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2976 MASTER LE NN 284215 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2977 MASTER LE NN 284697 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_TON_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
 Chain[2] 2978 MASTER LE NN 284905 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2979 MASTER LE NN 284888 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2980 MASTER LE NN 284891 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2981 MASTER LE NN 284892 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2982 MASTER LE NN 284886 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2983 MASTER LE NN 284894 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2984 MASTER LE NN 284897 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2985 MASTER LE NN 284546 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2986 MASTER LE NN 284903 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2987 MASTER LE NN 284691 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_LP_CFG_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2988 MASTER LE NN 284904 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2989 MASTER LE NN 284544 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2990 MASTER LE NN 284676 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_VOLT_CFG_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2991 MASTER LE NN 284508 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2992 MASTER LE NN 284218 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2993 MASTER LE NN 284219 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2994 MASTER LE NN 284063 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2995 MASTER LE NN 284755 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2996 MASTER LE NN 284127 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2997 MASTER LE NN 284284 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 2998 MASTER LE NN 284062 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 2999 MASTER LE NN 284217 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_v
set_valid_pbuff_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3000 MASTER LE NN 284283 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3001 MASTER LE NN 284274 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3002 MASTER LE NN 284277 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3003 MASTER LE NN 284275 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_
stepper_delay_u/d_delay_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3004 MASTER LE NN 284286 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3005 MASTER LE NN 284281 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3006 MASTER LE NN 284285 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3007 MASTER LE NN 284279 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3008 MASTER LE NN 284280 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3009 MASTER LE NN 284059 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3010 MASTER LE NN 284060 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_voltage_stepper_ip_wrapper/u_reg_voltage_stepper_1p0_
dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage
_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoin
t_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3011 MASTER LE NN 284019 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3012 MASTER LE NN 284020 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3013 MASTER LE NN 284024 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3014 MASTER LE NN 284509 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3015 MASTER LE NN 284510 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3016 MASTER LE NN 284517 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3017 MASTER LE NN 284516 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3018 MASTER LE NN 284518 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3019 MASTER LE NN 284514 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3020 MASTER LE NN 284513 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3021 MASTER LE NN 284507 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3022 MASTER LE NN 284512 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3023 MASTER LE NN 284511 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3024 MASTER LE NN 284674 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_FORCE_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3025 MASTER LE NN 284548 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG2__TRAP_SPARE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3026 MASTER LE NN 284688 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CAP_CFG_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3027 MASTER LE NN 284695 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3028 MASTER LE NN 284694 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3029 MASTER LE II 284038 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 3030 MASTER LE II 284677 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_VOLT_CFG_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3031 MASTER LE II 284906 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3032 MASTER LE II 284901 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3033 MASTER LE II 284696 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_HEIGHT_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3034 MASTER LE II 284700 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRAP_CFG1__TRAP_EN_CFG_VIN_FF_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3035 MASTER LE NN 284037 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[1]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 3036 MASTER LE NN 284896 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3037 MASTER LE NN 284895 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3038 MASTER LE NN 284893 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[0]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3039 MASTER LE NN 284890 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3040 MASTER LE NN 284889 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3041 MASTER LE NN 284887 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[4]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3042 MASTER LE NN 284032 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3043 MASTER LE NN 284025 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3044 MASTER LE NN 284171 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3045 MASTER LE NN 284476 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3046 MASTER LE NN 284769 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PHASE_CNT_MAX__PHASE_CNT_MAX_sync_reg/dout_reg[1
] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3047 MASTER LE NN 286986 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX2J)
Chain[2] 3048 MASTER LE NN 286987 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3049 MASTER LE NN 286978 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3050 MASTER LE NN 286977 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3051 MASTER LE NN 286985 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3052 MASTER LE NN 286984 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3053 MASTER LE NN 286976 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3054 MASTER LE NN 286983 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3055 MASTER LE NN 286980 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3056 MASTER LE NN 286981 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3057 MASTER LE NN 286970 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3058 MASTER LE NN 286969 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3059 MASTER LE NN 286968 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3060 MASTER LE NN 286966 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp7_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3061 MASTER LE NN 286971 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3062 MASTER LE NN 286972 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3063 MASTER LE NN 286967 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3064 MASTER LE NN 286973 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp6_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3065 MASTER LE NN 286974 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3066 MASTER LE NN 284022 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3067 MASTER LE NN 284021 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3068 MASTER LE NN 284017 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3069 MASTER LE NN 284016 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3070 MASTER LE NN 284012 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3071 MASTER LE NN 284027 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3072 MASTER LE NN 284026 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3073 MASTER LE NN 284018 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor16_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3074 MASTER LE NN 284030 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3075 MASTER LE NN 284023 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3076 MASTER LE NN 284028 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3077 MASTER LE NN 284033 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor14_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3078 MASTER LE NN 284029 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3079 MASTER LE NN 284034 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor15_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3080 MASTER LE NN 284014 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3081 MASTER LE NN 284031 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3082 MASTER LE NN 284013 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3083 MASTER LE NN 284015 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3084 MASTER LE NN 284173 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_tgl_counter_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3085 MASTER LE NN 284172 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_tgl_counter_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3086 MASTER LE NN 284465 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[4]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_glitchfree_mux_1p0_c
lk_qual_u/sel0_0_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 3087 MASTER LE NN 286975 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[4]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3088 MASTER LE NN 286833 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
DSLAVE LS NN 257627 - GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX1)
Chain[2] 3089 MASTER LE NN 286848 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP2_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3090 MASTER LE NN 286851 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__P_REF2_RATIO_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3091 MASTER LE NN 286843 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP3_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3092 MASTER LE NN 286842 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP3_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3093 MASTER LE NN 286840 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3094 MASTER LE NN 286838 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3095 MASTER LE NN 286919 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3096 MASTER LE NN 286834 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3097 MASTER LE NN 286857 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3098 MASTER LE NN 286832 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3099 MASTER LE NN 286849 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP2_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3100 MASTER LE NN 286859 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
 Chain[2] 3101 MASTER LE NN 286854 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3102 MASTER LE NN 286855 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3103 MASTER LE NN 286858 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3104 MASTER LE NN 286870 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3105 MASTER LE NN 286869 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3106 MASTER LE NN 286865 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3107 MASTER LE NN 286877 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3108 MASTER LE NN 286864 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3109 MASTER LE NN 286874 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3110 MASTER LE NN 286875 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3111 MASTER LE NN 286866 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3112 MASTER LE NN 286868 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3113 MASTER LE NN 286886 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3114 MASTER LE NN 286888 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3115 MASTER LE NN 286892 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3116 MASTER LE NN 286837 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3117 MASTER LE NN 286893 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3118 MASTER LE NN 286891 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3119 MASTER LE NN 286689 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[2] 3120 MASTER LE NN 286688 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3121 MASTER LE NN 286890 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3122 MASTER LE NN 286887 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3123 MASTER LE NN 286881 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3124 MASTER LE NN 286884 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3125 MASTER LE NN 286880 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3126 MASTER LE NN 286883 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3127 MASTER LE NN 286882 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3128 MASTER LE NN 286876 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3129 MASTER LE NN 286901 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3130 MASTER LE NN 286750 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3131 MASTER LE NN 286909 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3132 MASTER LE NN 286744 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3133 MASTER LE NN 286752 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3134 MASTER LE NN 286748 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3135 MASTER LE NN 286746 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3136 MASTER LE NN 286905 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3137 MASTER LE NN 286907 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3138 MASTER LE NN 286903 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3139 MASTER LE NN 286754 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3140 MASTER LE NN 286756 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[6] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3141 MASTER LE NN 286911 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3142 MASTER LE NN 286913 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3143 MASTER LE NN 286758 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_latched_write_reg/dout_re
g[7] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3144 MASTER LE NN 286915 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3145 MASTER LE NN 286682 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3146 MASTER LE NN 286683 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3147 MASTER LE NN 286684 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3148 MASTER LE NN 286687 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3149 MASTER LE NN 286879 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3150 MASTER LE NN 286885 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3151 MASTER LE NN 286878 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_2__NCLL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3152 MASTER LE NN 286889 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_1__NCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3153 MASTER LE NN 286872 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3154 MASTER LE NN 286873 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_3__PCLL_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3155 MASTER LE NN 286871 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3156 MASTER LE NN 286839 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3157 MASTER LE NN 286863 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3158 MASTER LE NN 286862 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3159 MASTER LE NN 286860 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3160 MASTER LE NN 286841 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3161 MASTER LE NN 286861 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_5__RM_PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3162 MASTER LE NN 286835 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3163 MASTER LE NN 286856 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_6__RM_NCLH_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3164 MASTER LE NN 286850 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__REP1_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3165 MASTER LE NN 286844 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP2_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3166 MASTER LE NN 286845 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP2_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3167 MASTER LE NN 286847 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP1_GATE1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3168 MASTER LE NN 286852 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__P_REF1_RATIO_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3169 MASTER LE NN 286691 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3170 MASTER LE NN 286701 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3171 MASTER LE NN 286696 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3172 MASTER LE NN 286690 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3173 MASTER LE NN 286821 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__D_P_MIN_ON_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3174 MASTER LE NN 286846 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_2__N_REP1_GATE2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3175 MASTER LE NN 286853 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_1__CL_TSTMD_MUX_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3176 MASTER LE NN 286808 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3177 MASTER LE NN 286799 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3178 MASTER LE NN 286805 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3179 MASTER LE NN 286798 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3180 MASTER LE NN 286797 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_OFF_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3181 MASTER LE NN 286817 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__P_MIN_ON_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3182 MASTER LE NN 286803 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3183 MASTER LE NN 286807 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3184 MASTER LE NN 286802 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3185 MASTER LE NN 286800 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3186 MASTER LE NN 286801 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_4__N_DRV_ON_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3187 MASTER LE NN 286699 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3188 MASTER LE NN 286822 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__SKIP_ZX_CMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3189 MASTER LE NN 286820 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__N_MIN_ON_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3190 MASTER LE NN 286827 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3191 MASTER LE NN 286916 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3192 MASTER LE NN 286937 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3193 MASTER LE NN 286826 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3194 MASTER LE NN 286917 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3195 MASTER LE II 286638 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 3196 MASTER LE II 286918 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[3]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3197 MASTER LE II 286818 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__P_MIN_ON_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3198 MASTER LE II 286829 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3199 MASTER LE II 286804 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_OFF_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3200 MASTER LE II 286831 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3201 MASTER LE II 286825 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3202 MASTER LE II 286836 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_3__RM_PCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3203 MASTER LE II 286830 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_4__RM_NCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3204 MASTER LE II 286824 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3205 MASTER LE II 286806 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_3__P_DRV_ON_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3206 MASTER LE II 286828 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_TSTMD_CFG_5__SS_PCLH_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3207 MASTER LE II 286790 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__RET_WAKE_FREQ_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3208 MASTER LE II 286895 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3209 MASTER LE II 286941 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3210 MASTER LE II 286900 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3211 MASTER LE II 286908 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3212 MASTER LE II 286940 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3213 MASTER LE II 286939 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3214 MASTER LE II 286910 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3215 MASTER LE NN 286642 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 3216 MASTER LE NN 286938 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[2]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3217 MASTER LE NN 286920 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3218 MASTER LE NN 286933 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3219 MASTER LE II 286641 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 3220 MASTER LE II 286796 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLH_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3221 MASTER LE NN 286639 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 3222 MASTER LE NN 286795 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3223 MASTER LE NN 286792 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_PRE_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3224 MASTER LE NN 286733 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3225 MASTER LE NN 286749 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3226 MASTER LE NN 286791 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__SS_SI_ENABLE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3227 MASTER LE NN 286731 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3228 MASTER LE NN 286722 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_MANUAL_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3229 MASTER LE NN 286814 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_SEL_DLY_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3230 MASTER LE NN 286813 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_SEL_DLY_CTRL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3231 MASTER LE NN 286793 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_PRE_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3232 MASTER LE NN 286794 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_1__PCLL_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3233 MASTER LE NN 286702 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3234 MASTER LE NN 286751 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3235 MASTER LE NN 286757 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3236 MASTER LE NN 286759 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC3__SENSE_IDAC_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3237 MASTER LE NN 286716 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3238 MASTER LE NN 286681 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3239 MASTER LE NN 286896 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3240 MASTER LE NN 286686 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3241 MASTER LE NN 286897 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3242 MASTER LE NN 286740 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3243 MASTER LE NN 286965 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL2__GANG_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3244 MASTER LE NN 286739 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3245 MASTER LE NN 286775 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3246 MASTER LE NN 286711 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3247 MASTER LE NN 286774 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3248 MASTER LE NN 286710 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3249 MASTER LE NN 286714 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3250 MASTER LE NN 286715 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3251 MASTER LE NN 286713 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3252 MASTER LE NN 286712 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3253 MASTER LE NN 286742 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3254 MASTER LE NN 286741 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_UB__SI_THRES_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3255 MASTER LE NN 286705 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3256 MASTER LE NN 286707 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3257 MASTER LE NN 286765 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3258 MASTER LE NN 286708 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3259 MASTER LE NN 286772 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3260 MASTER LE NN 286703 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3261 MASTER LE NN 286704 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3262 MASTER LE NN 286773 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3263 MASTER LE NN 286745 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3264 MASTER LE NN 286743 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3265 MASTER LE NN 286779 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3266 MASTER LE NN 286747 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3267 MASTER LE NN 286685 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3268 MASTER LE NN 286777 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3269 MASTER LE NN 286894 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_0__PCLH_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3270 MASTER LE NN 286776 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3271 MASTER LE NN 286904 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3272 MASTER LE NN 286898 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3273 MASTER LE NN 286899 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3274 MASTER LE NN 286778 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_GATE_DRV_MUX__GATE_DRV_MUX2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3275 MASTER LE NN 286906 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3276 MASTER LE NN 286902 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3277 MASTER LE NN 286867 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_CL_CTL_4__SS_PCLH_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3278 MASTER LE II 286640 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[1]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 3279 MASTER LE II 286934 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3280 MASTER LE II 286935 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3281 MASTER LE II 286823 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__SKIP_CL_CMP_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3282 MASTER LE II 286936 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[5]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3283 MASTER LE II 286698 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3284 MASTER LE II 286697 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3285 MASTER LE II 286819 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_1__N_MIN_ON_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3286 MASTER LE II 286695 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3287 MASTER LE II 286694 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3288 MASTER LE II 286700 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST34__ATEST3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3289 MASTER LE II 286646 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3290 MASTER LE II 286645 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3291 MASTER LE II 286650 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3292 MASTER LE II 286662 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3293 MASTER LE II 286648 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3294 MASTER LE II 286647 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3295 MASTER LE II 286660 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3296 MASTER LE II 286661 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3297 MASTER LE II 286663 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3298 MASTER LE II 286677 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3299 MASTER LE II 286676 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3300 MASTER LE II 286670 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3301 MASTER LE II 286658 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3302 MASTER LE II 286657 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3303 MASTER LE II 286652 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3304 MASTER LE II 286654 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3305 MASTER LE II 286653 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3306 MASTER LE II 286651 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3307 MASTER LE II 286655 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3308 MASTER LE II 286656 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_meas_
cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3309 MASTER LE II 286671 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3310 MASTER LE II 286672 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3311 MASTER LE II 286673 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3312 MASTER LE II 286675 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3313 MASTER LE II 286674 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_meas
_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3314 MASTER LE II 286665 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3315 MASTER LE II 286649 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/u_slib_
sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3316 MASTER LE II 286664 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/u_slib
_sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3317 MASTER LE II 286669 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_l2r_trim_cal
_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3318 MASTER LE II 286680 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_cal_act
ivity_en_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3319 MASTER LE II 286668 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_cal_act
ivity_en_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3320 MASTER LE II 286667 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_trim_fb_latc
h_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3321 MASTER LE II 286736 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3322 MASTER LE II 286666 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_ret_clk_trim_meas_logic/d_comp
_fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3323 MASTER LE II 286738 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3324 MASTER LE II 286728 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3325 MASTER LE II 286623 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3326 MASTER LE II 286622 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3327 MASTER LE II 286624 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3328 MASTER LE II 286617 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3329 MASTER LE II 286732 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3330 MASTER LE II 286612 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3331 MASTER LE II 286734 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3332 MASTER LE II 286615 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3333 MASTER LE II 286620 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3334 MASTER LE II 286928 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3335 MASTER LE II 286929 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3336 MASTER LE II 286692 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3337 MASTER LE II 286693 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_ATEST12__ATEST1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3338 MASTER LE II 286931 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3339 MASTER LE II 286930 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3340 MASTER LE II 286922 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3341 MASTER LE II 286921 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3342 MASTER LE II 286932 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3343 MASTER LE II 286927 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[0]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3344 MASTER LE II 286923 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3345 MASTER LE NN 286644 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[5] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 3346 MASTER LE NN 286926 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3347 MASTER LE NN 286924 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3348 MASTER LE II 286643 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[6] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 3349 MASTER LE II 286942 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[6]_u
_trim_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3350 MASTER LE II 286914 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3351 MASTER LE II 286735 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3352 MASTER LE II 286912 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[2] 3353 MASTER LE II 286925 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/gen_trims[4]_u
_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3354 MASTER LE II 286812 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_BLANK_TIME_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3355 MASTER LE II 286816 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_SEL_DLY_CTRL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3356 MASTER LE II 286809 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_BLANK_TIME_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3357 MASTER LE II 286811 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_BLANK_TIME_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3358 MASTER LE II 286726 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3359 MASTER LE II 286810 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__N_BLANK_TIME_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3360 MASTER LE II 286725 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3361 MASTER LE II 286717 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3362 MASTER LE II 286718 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3363 MASTER LE II 286719 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3364 MASTER LE II 286720 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3365 MASTER LE II 286706 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3366 MASTER LE II 286753 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3367 MASTER LE II 286709 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3368 MASTER LE II 286815 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_FSM_MINON_CFG_2__P_SEL_DLY_CTRL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3369 MASTER LE II 286727 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3370 MASTER LE II 286730 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3371 MASTER LE II 286761 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3372 MASTER LE II 286764 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3373 MASTER LE II 286782 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_PRE_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3374 MASTER LE II 286785 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__ZX_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3375 MASTER LE II 286770 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3376 MASTER LE II 286788 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLH_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3377 MASTER LE II 286789 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLH_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3378 MASTER LE II 286769 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3379 MASTER LE II 286755 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_SI_THRES_VSET_LB__SI_THRES_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3380 MASTER LE II 286784 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__ZX_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3381 MASTER LE II 286771 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3382 MASTER LE II 286763 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3383 MASTER LE II 286768 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC1__SPARE_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3384 MASTER LE II 286760 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3385 MASTER LE II 286762 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3386 MASTER LE II 286766 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3387 MASTER LE II 286783 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_PRE_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3388 MASTER LE II 286767 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_PS_MISC2__SPARE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3389 MASTER LE II 286787 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_FORCE_HIGH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3390 MASTER LE II 286786 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_2__NCLL_FORCE_LOW_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3391 MASTER LE II 286780 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_3__FOLDBACK_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3392 MASTER LE II 286781 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_EN_OPTIONS_DFT_3__FOLDBACK_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3393 MASTER LE II 286659 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_core/u_fts_ps_trim_cal_cmn_ip_wrapper/u_fts_ctrl_cl_clk_trim_meas_logic/d_comp_
fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3394 MASTER LE II 286721 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_TRIM_CAL_SEL__TRIM_CAL_POLARITY_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3395 MASTER LE II 286737 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST12__DTEST2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3396 MASTER LE II 286729 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3397 MASTER LE II 286723 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3398 MASTER LE II 286724 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/\u_fts_ps_
dig_csr/u_fts_ps_rif/u_DTEST43__DTEST3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3399 MASTER LE II 286619 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3400 MASTER LE II 286621 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3401 MASTER LE II 286618 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3402 MASTER LE II 286614 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3403 MASTER LE II 286616 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3404 MASTER LE II 286605 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3405 MASTER LE II 286604 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp7_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3406 MASTER LE II 286608 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3407 MASTER LE II 286610 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3408 MASTER LE II 286609 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3409 MASTER LE II 284011 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync4/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3410 MASTER LE II 283397 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3411 MASTER LE II 283434 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3412 MASTER LE II 283433 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3413 MASTER LE II 283435 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3414 MASTER LE II 283437 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3415 MASTER LE II 283430 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3416 MASTER LE II 283398 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3417 MASTER LE II 283401 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3418 MASTER LE II 283405 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3419 MASTER LE II 286607 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3420 MASTER LE II 286606 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3421 MASTER LE II 286611 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp6_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3422 MASTER LE II 283402 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3423 MASTER LE II 283399 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3424 MASTER LE II 283404 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3425 MASTER LE II 283406 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 3426 MASTER LE II 283403 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3427 MASTER LE II 283400 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_dll_precharge_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3428 MASTER LE II 283448 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3429 MASTER LE II 283446 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3430 MASTER LE II 283444 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3431 MASTER LE II 283840 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3432 MASTER LE II 283414 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3433 MASTER LE II 283413 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3434 MASTER LE II 286625 + GPIO_07
I_DCORE/\fts_ps_rmod_gen[3]_u_fts_ps_rmod/u_fts_ps_rdig/u_fts_ps_dig_mod/u_fts_ps_d
ig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3435 MASTER LE II 283416 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3436 MASTER LE II 283415 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_smps_clk_req/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3437 MASTER LE II 283849 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3438 MASTER LE II 283850 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_slib_sync/sync_d_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3439 MASTER LE II 283212 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3440 MASTER LE II 283210 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 3441 MASTER LE II 283216 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3442 MASTER LE II 283620 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3443 MASTER LE II 283167 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync4/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3444 MASTER LE II 283173 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_ps_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3445 MASTER LE II 283211 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3446 MASTER LE II 283209 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3447 MASTER LE II 283845 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3448 MASTER LE II 283846 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3449 MASTER LE II 283841 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3450 MASTER LE II 283847 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3451 MASTER LE II 283848 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3452 MASTER LE II 283196 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3453 MASTER LE II 283192 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_duty_out_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3454 MASTER LE II 283197 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3455 MASTER LE II 283195 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3456 MASTER LE II 283190 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_CTLR_MISC4__DUTY_GENERATOR_EN_rifo_del_r
eg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3457 MASTER LE II 283214 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3458 MASTER LE II 283213 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3459 MASTER LE II 283215 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_meas_cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3460 MASTER LE II 283203 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3461 MASTER LE II 283208 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3462 MASTER LE II 283202 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3463 MASTER LE II 283172 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_ps_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3464 MASTER LE II 283207 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3465 MASTER LE II 283554 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3466 MASTER LE II 283556 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3467 MASTER LE II 283557 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3468 MASTER LE II 283558 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3469 MASTER LE II 283559 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3470 MASTER LE II 283292 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_
u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3471 MASTER LE II 283976 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_glue_u/d_refdac_sample_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3472 MASTER LE II 283299 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3473 MASTER LE II 283200 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_lfrc_req_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3474 MASTER LE II 283191 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_duty_out_half_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3475 MASTER LE II 283294 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3476 MASTER LE II 283296 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3477 MASTER LE II 283297 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3478 MASTER LE II 283302 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_glue_u/d_refdac_smpl_counter_high_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3479 MASTER LE II 283298 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3480 MASTER LE II 283300 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_1st_window_pulse_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3481 MASTER LE II 283331 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_clk_
qual_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3482 MASTER LE II 283334 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3483 MASTER LE II 283336 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3484 MASTER LE II 283335 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3485 MASTER LE II 283332 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3486 MASTER LE II 283333 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_thres_counter_u/d_counter_grey_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3487 MASTER LE II 283979 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3488 MASTER LE II 283978 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3489 MASTER LE II 283977 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_refdac_smpl_counter_u/d_counter_grey_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3490 MASTER LE II 283295 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3491 MASTER LE II 283307 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/slib_clkreq_gate_1p0_refd
ac_smpl_clk_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3492 MASTER LE II 283293 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_qual_logic_1p0_dig_mod/reg_retention_qual_logic_
1p0_dig_window_counter_u/d_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3493 MASTER LE II 283199 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_lfrc_req_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3494 MASTER LE II 283193 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3495 MASTER LE II 283194 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_pwm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3496 MASTER LE II 283843 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3497 MASTER LE II 283851 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_slib_sync/sync_d_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3498 MASTER LE II 283844 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3499 MASTER LE II 283842 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 3500 MASTER LE II 283441 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3501 MASTER LE II 283445 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3502 MASTER LE II 283443 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3503 MASTER LE II 283442 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3504 MASTER LE II 283447 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3505 MASTER LE II 283440 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3506 MASTER LE II 283439 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3507 MASTER LE II 283436 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3508 MASTER LE II 283431 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3509 MASTER LE II 283432 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3510 MASTER LE II 283716 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3511 MASTER LE II 283724 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3512 MASTER LE II 283725 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3513 MASTER LE II 283785 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3514 MASTER LE II 283715 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3515 MASTER LE II 283783 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3516 MASTER LE II 283682 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3517 MASTER LE II 283683 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_GENERATOR_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3518 MASTER LE II 283723 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3519 MASTER LE II 283719 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3520 MASTER LE II 283677 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3521 MASTER LE II 283730 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3522 MASTER LE II 283722 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3523 MASTER LE II 283728 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3524 MASTER LE II 283720 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3525 MASTER LE II 283383 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_mode_update_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3526 MASTER LE II 283382 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_mode_update_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3527 MASTER LE II 283429 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/u_slib_sync4/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3528 MASTER LE II 283420 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3529 MASTER LE II 284008 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3530 MASTER LE II 283422 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[4]
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 3531 MASTER LE II 283421 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3532 MASTER LE II 283419 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3533 MASTER LE II 283418 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_from_glue_logic/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3534 MASTER LE II 283276 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3535 MASTER LE II 283986 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3536 MASTER LE II 283360 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_timer_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3537 MASTER LE II 283374 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_mask_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3538 MASTER LE II 283375 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_mask_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3539 MASTER LE II 283275 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3540 MASTER LE II 283361 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_timer_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3541 MASTER LE II 283424 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_npm_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3542 MASTER LE II 283684 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3543 MASTER LE II 283694 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3544 MASTER LE II 283690 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3545 MASTER LE II 283601 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PP_PWM_LOCK_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[2] 3546 MASTER LE II 283718 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3547 MASTER LE II 283689 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3548 MASTER LE II 283905 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3549 MASTER LE II 283685 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3550 MASTER LE II 283717 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3551 MASTER LE II 283600 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PP_PWMBY2_LOCK_EN_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX2J)
Chain[2] 3552 MASTER LE II 283602 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PHASE_STAGGERED_LOCK_EN_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3553 MASTER LE II 283598 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PWM_R_RIGHT_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3554 MASTER LE II 283612 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__RET_CMP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3555 MASTER LE II 283727 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3556 MASTER LE II 283692 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__DACREF_HYST_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3557 MASTER LE II 283617 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3558 MASTER LE II 283680 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3559 MASTER LE II 283678 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3560 MASTER LE II 283605 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PHASE_STAGGERED_LOO
P_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3561 MASTER LE II 283874 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3562 MASTER LE II 283907 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3563 MASTER LE II 283726 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3564 MASTER LE II 283681 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3565 MASTER LE II 283616 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3566 MASTER LE II 283867 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3567 MASTER LE II 283778 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3568 MASTER LE II 283872 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3569 MASTER LE II 283878 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3570 MASTER LE II 283902 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_M1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3571 MASTER LE II 283868 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3572 MASTER LE II 283781 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3573 MASTER LE II 283901 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_M1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3574 MASTER LE II 283729 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG1__PRECHARGE_TIMEOUT_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3575 MASTER LE II 283904 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3576 MASTER LE II 283698 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3577 MASTER LE II 283813 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_slib_sync
/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3578 MASTER LE II 283627 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
6] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3579 MASTER LE II 283640 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__EN_OFF_TO_MPOFF_TRAN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3580 MASTER LE II 283613 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3581 MASTER LE II 283391 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_stepper_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3582 MASTER LE II 283710 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3583 MASTER LE II 283712 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3584 MASTER LE II 283714 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3585 MASTER LE II 283860 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 3586 MASTER LE II 283784 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WIDTH_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3587 MASTER LE II 283779 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3588 MASTER LE II 283903 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P4_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3589 MASTER LE II 283780 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3590 MASTER LE II 283870 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3591 MASTER LE II 283880 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3592 MASTER LE II 283906 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3593 MASTER LE II 283782 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3594 MASTER LE II 283691 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3595 MASTER LE II 283721 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG2__PING_PONG_TIMEOUT_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3596 MASTER LE II 283166 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync4/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3597 MASTER LE II 283852 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3598 MASTER LE II 283858 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3599 MASTER LE II 283859 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3600 MASTER LE II 283392 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_stepper_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3601 MASTER LE II 283862 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3602 MASTER LE II 283462 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_cal_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3603 MASTER LE II 283461 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_cal_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3604 MASTER LE II 283854 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
 Chain[2] 3605 MASTER LE II 283861 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3606 MASTER LE II 283855 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3607 MASTER LE II 283790 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3608 MASTER LE II 283853 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3609 MASTER LE II 283555 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3610 MASTER LE II 283560 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3611 MASTER LE II 283788 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3612 MASTER LE II 283857 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3613 MASTER LE II 283856 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3614 MASTER LE II 283803 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3615 MASTER LE II 283543 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_en_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3616 MASTER LE II 283454 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_en_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3617 MASTER LE II 283458 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_sync_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3618 MASTER LE II 283459 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/u_
slib_sync_3p0_trim_cal_act_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3619 MASTER LE II 283452 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_sync_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3620 MASTER LE II 283451 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_sync_3p0_trimout_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3621 MASTER LE II 283792 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN0_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3622 MASTER LE II 283794 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN2_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3623 MASTER LE II 283460 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/u_
slib_sync_3p0_trim_cal_act_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3624 MASTER LE II 283455 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_cal_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3625 MASTER LE II 283450 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_sync_3p0_trimout_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3626 MASTER LE II 283793 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN1_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3627 MASTER LE II 283175 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_19p2_req_synchro_sync/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3628 MASTER LE II 283709 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3629 MASTER LE II 283174 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_19p2_req_synchro_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3630 MASTER LE II 283811 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_slib_sync/sy
nc_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3631 MASTER LE II 283625 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
4] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3632 MASTER LE II 283639 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3633 MASTER LE II 283800 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3634 MASTER LE II 283623 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
2] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3635 MASTER LE II 283626 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
5] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3636 MASTER LE II 283679 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__PERIOD_CFG_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3637 MASTER LE II 283599 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_PWM_F_RIGHT_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3638 MASTER LE II 283702 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__CAL_FLT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3639 MASTER LE II 283695 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3640 MASTER LE II 283395 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_npm_lpm_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3641 MASTER LE II 283411 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_smps_clk_buf_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3642 MASTER LE II 283274 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_clk_gating/u_clk_req_fsm_sync/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3643 MASTER LE II 283417 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_clk_19p2_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3644 MASTER LE II 283426 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_6_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3645 MASTER LE II 283699 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3646 MASTER LE II 283706 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__TRAP_GEN_SI_CURRENT_REDUCTION_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3647 MASTER LE II 283428 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3648 MASTER LE II 283412 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_smps_clk_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3649 MASTER LE II 284010 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_refen_to_bckcmn_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[2] 3650 MASTER LE II 283408 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_buck_en_ret_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3651 MASTER LE II 283394 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_mask_pwmcmp_inwarmup_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3652 MASTER LE II 283409 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_clk_lfrc_req_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3653 MASTER LE II 283425 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_7_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3654 MASTER LE II 283825 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_slib_sync/sync_d
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3655 MASTER LE II 283380 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_fsm_mask_en_d1_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3656 MASTER LE II 283410 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_vreg_comp_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3657 MASTER LE II 283824 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_slib_sync/sync_d
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3658 MASTER LE II 283581 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3659 MASTER LE II 283579 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3660 MASTER LE II 283572 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3661 MASTER LE II 283571 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3662 MASTER LE II 283576 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3663 MASTER LE II 283575 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3664 MASTER LE II 283573 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3665 MASTER LE II 283580 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST4__CFG_ATEST4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3666 MASTER LE II 283578 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3667 MASTER LE II 283577 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST3__CFG_ATEST3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3668 MASTER LE II 283396 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_en_tx_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3669 MASTER LE II 283427 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_en_1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3670 MASTER LE II 283378 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3671 MASTER LE II 283379 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3672 MASTER LE II 283376 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3673 MASTER LE II 283377 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_fsm_state_mask_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3674 MASTER LE II 283373 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_update_mask_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3675 MASTER LE II 283381 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mode_fsm/d_mode_fsm_mask_en_d2_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3676 MASTER LE II 283817 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3677 MASTER LE II 283820 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3678 MASTER LE II 283822 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3679 MASTER LE II 283821 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3680 MASTER LE II 283823 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_sync_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3681 MASTER LE II 283818 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3682 MASTER LE II 283697 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3683 MASTER LE II 283687 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3684 MASTER LE II 283705 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__DUTY_GEN_SI_CURRENT_REDUCTION_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3685 MASTER LE II 283686 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3686 MASTER LE II 283812 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__STEPPER_BYPASS_EN_slib_sync/sy
nc_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3687 MASTER LE II 283688 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC3__SCRATCH_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3688 MASTER LE II 283603 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PP_PWMBY2_LOOP_EN_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3689 MASTER LE II 283676 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC4__DUTY_CFG_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3690 MASTER LE II 283701 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__VREG_MON_CFG_RM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3691 MASTER LE II 283864 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX2J)
Chain[2] 3692 MASTER LE II 283618 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__NC_TEST_MODE_EN_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3693 MASTER LE II 283604 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_TEST_MODE__TEST_VCTRL_PP_PWM_LOOP_EN_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3694 MASTER LE II 283700 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__VREG_MON_CFG_NPM_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3695 MASTER LE II 283693 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__DACREF_HYST_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3696 MASTER LE II 283819 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 3697 MASTER LE II 283386 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_STATUS1__PS_TRUE_rifi_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3698 MASTER LE II 283703 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__PWM_SMPS_CLK_FORCE_ON_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3699 MASTER LE II 283696 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC2__SPARE_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3700 MASTER LE II 283646 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3701 MASTER LE II 283585 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3702 MASTER LE II 283582 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3703 MASTER LE II 283644 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3704 MASTER LE II 283584 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3705 MASTER LE II 283583 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST1__CFG_DTEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3706 MASTER LE II 283643 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3707 MASTER LE II 283645 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_VALUE_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3708 MASTER LE II 283647 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_MASK__MODE_FSM_MASK_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3709 MASTER LE II 283564 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3710 MASTER LE II 283551 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3711 MASTER LE II 283801 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3712 MASTER LE II 283622 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3713 MASTER LE II 283635 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3714 MASTER LE II 283908 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL2__AHC_VSET_P2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3715 MASTER LE II 283866 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3716 MASTER LE II 283876 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3717 MASTER LE II 283550 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3718 MASTER LE II 283798 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3719 MASTER LE II 283713 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3720 MASTER LE II 283562 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3721 MASTER LE II 283634 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3722 MASTER LE II 283561 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3723 MASTER LE II 283565 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3724 MASTER LE II 283563 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[2] 3725 MASTER LE II 283802 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3726 MASTER LE II 283619 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__NC_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3727 MASTER LE II 283638 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3728 MASTER LE II 283614 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3729 MASTER LE II 283615 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TEST_MODE_CFG__DUTYGEN_TEST_MODE_EN_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3730 MASTER LE II 283637 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T1_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3731 MASTER LE II 283636 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__TIMER_T0_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3732 MASTER LE II 283885 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3733 MASTER LE II 283893 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3734 MASTER LE II 283889 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3735 MASTER LE II 283928 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3736 MASTER LE II 283930 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3737 MASTER LE II 283629 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_POLARITY_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3738 MASTER LE II 283894 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_sync_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3739 MASTER LE II 283786 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3740 MASTER LE II 283891 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3741 MASTER LE II 283898 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3742 MASTER LE II 283217 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_comp_fb_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3743 MASTER LE II 283204 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3744 MASTER LE II 283205 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3745 MASTER LE II 283218 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3746 MASTER LE II 283219 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3747 MASTER LE II 283201 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3748 MASTER LE II 283206 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_fts_ctrl_clk_trim_meas_logi
c/d_en_meas_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3749 MASTER LE II 283453 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
trim_fb_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3750 MASTER LE II 283553 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL2__GANG_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3751 MASTER LE II 283795 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_AWAKE_CFG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3752 MASTER LE II 283789 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3753 MASTER LE II 283457 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/sl
ib_clkreq_gate_3p0_clk_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3754 MASTER LE II 283797 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3755 MASTER LE II 283799 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3756 MASTER LE II 283552 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3757 MASTER LE II 283456 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/d_
l2r_trim_cal_activity_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3758 MASTER LE II 283624 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
3] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3759 MASTER LE II 283621 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_THRESH__CLK_PERIOD_THRESH_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3760 MASTER LE II 283388 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3761 MASTER LE II 283589 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3762 MASTER LE II 283569 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3763 MASTER LE II 283586 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3764 MASTER LE II 283588 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3765 MASTER LE II 283587 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_DTEST2__CFG_DTEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3766 MASTER LE II 283574 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST2__CFG_ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3767 MASTER LE II 283570 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CFG_ATEST1__CFG_ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3768 MASTER LE II 283449 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_speedup_timeout_reg
(M31_1P5V6T_SFFRBQX2J)
Chain[2] 3769 MASTER LE II 283104 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3770 MASTER LE II 283091 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3771 MASTER LE II 283438 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_mphase_dll_logic/d_ping_pong_timeout_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3772 MASTER LE II 283094 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3773 MASTER LE II 283747 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_INT_CFG__DUTY_GEN_INT_CAP_CFG_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3774 MASTER LE II 283384 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3775 MASTER LE II 283962 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3776 MASTER LE II 283971 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3777 MASTER LE NN 283107 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[7] (M31_1P5V6T_SFFSBQBX1)
Chain[2] 3778 MASTER LE NN 283963 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3779 MASTER LE NN 284005 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__DETACH_VREG_READY_CHAIN_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3780 MASTER LE NN 283736 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_CLAMP_CFG__CLAMP_FORCE_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3781 MASTER LE NN 283946 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_OCP__VREG_FOLDBACK_EN_slib_sync/sync_d_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3782 MASTER LE NN 283527 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_retention_logic_1p0_dig_mod/reg_retention_logic_1p0_dig_wa
ke_ps_fsm_u1/d_power_boost_en_reg (M31_1P5V6T_SFFSBQX1)
Chain[2] 3783 MASTER LE NN 283753 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_NOTCH_CFG_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3784 MASTER LE NN 283748 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_VCDL_CFG__DUTY_GEN_VCDL_CAP_CFG_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3785 MASTER LE NN 283754 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_NOTCH_CFG_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3786 MASTER LE NN 283746 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_INT_CFG__DUTY_GEN_INT_CAP_CFG_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3787 MASTER LE NN 283628 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_MANUAL_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3788 MASTER LE NN 283567 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3789 MASTER LE NN 283494 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_v
reg_ack_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3790 MASTER LE NN 283969 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3791 MASTER LE NN 283968 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[2]_u_trim_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3792 MASTER LE NN 283630 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3793 MASTER LE NN 283633 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_TRIM_CAL_SEL__TRIM_CAL_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3794 MASTER LE NN 283926 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3795 MASTER LE NN 283711 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3796 MASTER LE NN 283708 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3797 MASTER LE NN 283887 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_SAMPLE_CTL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3798 MASTER LE NN 283895 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_RES_HROOM_VSET_TRAN_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[2] 3799 MASTER LE NN 283549 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[2] 3800 MASTER LE NN 283566 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3801 MASTER LE NN 283882 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[2] 3802 MASTER LE NN 283892 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_AHC_CTL3__AHC_DEC_DELAY_CTL_sync_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3803 MASTER LE NN 283791 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3804 MASTER LE NN 283787 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3805 MASTER LE NN 283925 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3806 MASTER LE NN 283980 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3807 MASTER LE NN 283707 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MPHASE_DLL_CFG3__PING_PONG_SPEEDUP_THRESH_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3808 MASTER LE NN 283568 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3809 MASTER LE NN 283393 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3810 MASTER LE NN 283641 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[2] 3811 MASTER LE NN 283642 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_MODE_FSM_WAITS_1__SS_CL_THRESH_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3812 MASTER LE NN 283385 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_rif_mode_fsm_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3813 MASTER LE NN 283752 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_DUTY_GEN_FLT_CFG__DUTY_GEN_FLT_LP_CFG_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3814 MASTER LE NN 283961 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_trim_cal_cmn_ip_wrapper/u_trim_cal_cmn_3p0_dig_mod/ge
n_trims[3]_u_trim_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3815 MASTER LE NN 283704 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_csr/u_fts_ctrl_rif/u_CTLR_MISC1__PWM_19P2M_CLK_FORCE_ON_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[2] 3816 MASTER LE NN 283423 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/\u
_fts_ctrl_dig_core/u_fts_ctrl_glue_logic/d_fsm_foldback_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[2] 3817 MASTER LE NN 283090 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3818 MASTER LE NN 283099 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3819 MASTER LE NN 283096 + GPIO_07
I_DCORE/\fts_ctrl_rmod_gen[3]_u_fts_ctrl_rmod/u_fts_ctrl_rdig/u_fts_ctrl_dig_mod/u_
fts_ctrl_dig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[2] 3820 MASTER TE NN 288705 - GPIO_07
I_DCORE/\SNPS_PipeHead_u_waimea_dcore_glue/u_dft_test_ctrl/scan_chain_in[2]_1
(M31_1P5V6T_SFFQX3)
Chain[3] 0 MASTER LE NN 288696 + GPIO_07
I_DCORE/\SNPS_PipeTail_u_waimea_dcore_glue/u_dft_test_ctrl/scan_chain_out[3]_1
(M31_1P5V6T_DFFQX1)
Chain[3] 1 MASTER LE NN 273481 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256608 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP2
(M31_1P5V6T_LOWLATCHX3)
Chain[3] 2 MASTER LE NN 273277 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3 MASTER LE NN 273285 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 4 MASTER LE NN 273310 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 5 MASTER LE NN 273317 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 6 MASTER LE NN 273452 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 7 MASTER LE NN 273454 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 8 MASTER LE NN 273428 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 9 MASTER LE NN 273405 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 10 MASTER LE NN 273423 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 11 MASTER LE NN 273424 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 12 MASTER LE NN 273429 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 13 MASTER LE NN 273406 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 14 MASTER LE NN 273425 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 15 MASTER LE NN 273469 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 16 MASTER LE NN 273449 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 17 MASTER LE NN 273445 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 18 MASTER LE NN 273473 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 19 MASTER LE NN 273447 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 20 MASTER LE NN 273441 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 21 MASTER LE NN 273475 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 22 MASTER LE NN 273455 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 23 MASTER LE NN 273471 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 24 MASTER LE NN 273464 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 25 MASTER LE NN 273451 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 26 MASTER LE NN 273467 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 27 MASTER LE NN 273439 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 28 MASTER LE NN 273443 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 29 MASTER LE NN 273401 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 30 MASTER LE NN 273402 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 31 MASTER LE NN 273440 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 32 MASTER LE NN 273437 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 33 MASTER LE NN 273438 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 34 MASTER LE NN 273478 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 35 MASTER LE NN 273474 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 36 MASTER LE NN 273476 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 37 MASTER LE NN 273472 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 38 MASTER LE NN 273465 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 39 MASTER LE NN 273468 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFSBQX1)
Chain[3] 40 MASTER LE NN 273241 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 41 MASTER LE NN 273380 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[3] 42 MASTER LE NN 273219 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 43 MASTER LE NN 273280 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 44 MASTER LE NN 273281 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 45 MASTER LE NN 273279 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 46 MASTER LE NN 273278 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 47 MASTER LE NN 273282 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 48 MASTER LE NN 273274 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 49 MASTER LE NN 273314 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 50 MASTER LE NN 273382 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 51 MASTER LE NN 273381 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 52 MASTER LE NN 273463 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 53 MASTER LE NN 273462 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 54 MASTER LE NN 273480 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 55 MASTER LE NN 273470 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[3] 56 MASTER LE NN 273460 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 57 MASTER LE NN 273461 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 58 MASTER LE NN 273466 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 59 MASTER LE NN 273420 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 60 MASTER LE NN 273477 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 61 MASTER LE NN 273453 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 62 MASTER LE NN 273422 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 63 MASTER LE NN 273427 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 64 MASTER LE NN 273404 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 65 MASTER LE NN 273403 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 66 MASTER LE NN 273426 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 67 MASTER LE NN 273399 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 68 MASTER LE NN 273331 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 69 MASTER LE NN 273332 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 70 MASTER LE NN 273338 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 71 MASTER LE NN 273304 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 72 MASTER LE NN 273303 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 73 MASTER LE NN 273392 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 74 MASTER LE NN 273394 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 75 MASTER LE NN 273258 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 76 MASTER LE NN 273393 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 77 MASTER LE NN 273383 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 78 MASTER LE NN 273387 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 79 MASTER LE NN 273385 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 80 MASTER LE NN 273479 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX2)
Chain[3] 81 MASTER LE NN 273410 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 82 MASTER LE NN 273134 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 83 MASTER LE NN 273389 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 84 MASTER LE NN 273221 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 85 MASTER LE NN 273135 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 86 MASTER LE NN 273220 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 87 MASTER LE NN 273217 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 88 MASTER LE NN 273218 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 89 MASTER LE NN 273133 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 90 MASTER LE NN 273103 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 91 MASTER LE NN 273104 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 92 MASTER LE NN 273102 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 93 MASTER LE NN 273099 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 94 MASTER LE NN 273101 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 95 MASTER LE NN 273105 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 96 MASTER LE NN 273100 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 97 MASTER LE NN 273098 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 98 MASTER LE NN 273216 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 99 MASTER LE NN 273213 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_meta_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 100 MASTER LE NN 273214 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 101 MASTER LE NN 273224 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 102 MASTER LE NN 273264 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 103 MASTER LE NN 273228 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 104 MASTER LE NN 273231 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 105 MASTER LE NN 273230 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 106 MASTER LE NN 273122 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 107 MASTER LE NN 273239 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 108 MASTER LE NN 273232 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 109 MASTER LE NN 273226 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_eq_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 110 MASTER LE NN 273225 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_gt_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 111 MASTER LE NN 273106 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 112 MASTER LE NN 273227 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 113 MASTER LE NN 273223 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 114 MASTER LE NN 273215 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 115 MASTER LE NN 273229 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_
u/GEN_PBUS_BUFF_STEPPER_DONE_d_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 116 MASTER LE NN 273222 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 117 MASTER LE NN 273155 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 118 MASTER LE NN 273397 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 119 MASTER LE NN 273398 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 120 MASTER LE NN 273195 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 121 MASTER LE NN 273339 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 122 MASTER LE NN 273330 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 123 MASTER LE NN 273430 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 124 MASTER LE NN 273421 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 125 MASTER LE NN 273419 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/BYPASS_CTL1_0_array_u_BYPASS_CTL1_0__SMART_BYPASS_E
NTRY_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 126 MASTER LE NN 273326 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 127 MASTER LE NN 273400 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 128 MASTER LE NN 273433 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 129 MASTER LE NN 273436 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 130 MASTER LE NN 273432 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 131 MASTER LE NN 273435 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 132 MASTER LE NN 273325 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 133 MASTER LE NN 273136 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 134 MASTER LE NN 273391 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC_CTL1__READY_STEPDOWN_QUAL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 135 MASTER LE NN 273327 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 136 MASTER LE NN 273137 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 137 MASTER LE NN 273376 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 138 MASTER LE NN 273375 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 139 MASTER LE NN 273368 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG2_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 140 MASTER LE NN 273329 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 141 MASTER LE NN 273431 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 142 MASTER LE NN 273407 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 143 MASTER LE NN 273373 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 144 MASTER LE NN 273374 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 145 MASTER LE NN 273408 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 146 MASTER LE NN 273434 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 147 MASTER LE NN 273348 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 148 MASTER LE NN 273370 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[1
] (M31_1P5V6T_SFFSBQX1)
Chain[3] 149 MASTER LE NN 273361 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PLOW_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 150 MASTER LE NN 273371 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 151 MASTER LE NN 273366 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PLOW_CLAMP_THR_CONFIG_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 152 MASTER LE NN 273344 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 153 MASTER LE NN 273365 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PUP_CLAMP_THR_CONFIG_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 154 MASTER LE NN 273341 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 155 MASTER LE NN 273362 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD1_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 156 MASTER LE NN 273409 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 157 MASTER LE NN 273328 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 158 MASTER LE NN 273358 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_LPM_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 159 MASTER LE NN 273412 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 160 MASTER LE NN 273350 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 161 MASTER LE NN 273369 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG3_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 162 MASTER LE NN 273340 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 163 MASTER LE NN 273411 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 164 MASTER LE NN 273337 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 165 MASTER LE NN 273171 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 166 MASTER LE NN 273379 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 167 MASTER LE NN 273367 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 168 MASTER LE NN 273333 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 169 MASTER LE NN 273351 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 170 MASTER LE NN 273336 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 171 MASTER LE NN 273334 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 172 MASTER LE NN 273415 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 173 MASTER LE NN 273335 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 174 MASTER LE NN 273378 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 175 MASTER LE NN 273123 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_int_soft_start_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 176 MASTER LE NN 273457 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 177 MASTER LE NN 273138 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 178 MASTER LE NN 273418 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 179 MASTER LE NN 273459 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__VOLTAGE_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 180 MASTER LE NN 273377 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 181 MASTER LE NN 273345 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 182 MASTER LE NN 273363 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD2_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 183 MASTER LE NN 273349 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 184 MASTER LE NN 273353 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 185 MASTER LE NN 273360 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PUP_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 186 MASTER LE NN 273342 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 187 MASTER LE NN 273343 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 188 MASTER LE NN 273359 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_EA_CONFIG_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 189 MASTER LE NN 273355 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 190 MASTER LE NN 273307 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 191 MASTER LE NN 273181 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 192 MASTER LE NN 273159 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 193 MASTER LE NN 273185 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 194 MASTER LE NN 273187 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_narrow_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 195 MASTER LE NN 273183 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 196 MASTER LE NN 273182 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 197 MASTER LE NN 273174 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_wide_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 198 MASTER LE NN 273184 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 199 MASTER LE NN 273347 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 200 MASTER LE NN 273156 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 201 MASTER LE NN 273157 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 202 MASTER LE NN 273083 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 203 MASTER LE NN 273091 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 204 MASTER LE NN 273089 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 205 MASTER LE NN 273090 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 206 MASTER LE NN 273079 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 207 MASTER LE NN 273080 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 208 MASTER LE NN 273180 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 209 MASTER LE NN 273179 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 210 MASTER LE NN 273414 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 211 MASTER LE NN 273416 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 212 MASTER LE NN 273417 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 213 MASTER LE NN 273413 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 214 MASTER LE NN 273458 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 215 MASTER LE NN 273263 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 216 MASTER LE NN 273265 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_stepdn_det_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 217 MASTER LE NN 273233 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 218 MASTER LE NN 273238 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 219 MASTER LE NN 273236 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 220 MASTER LE NN 273237 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 221 MASTER LE NN 273234 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 222 MASTER LE NN 273081 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 223 MASTER LE NN 273085 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 224 MASTER LE NN 273084 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 225 MASTER LE NN 273086 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 226 MASTER LE NN 273087 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 227 MASTER LE NN 273088 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 228 MASTER LE NN 273078 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 229 MASTER LE NN 273082 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 230 MASTER LE NN 273178 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 231 MASTER LE NN 273177 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 232 MASTER LE NN 273235 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 233 MASTER LE NN 273356 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 234 MASTER LE NN 273354 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 235 MASTER LE NN 273306 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 236 MASTER LE NN 273352 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 237 MASTER LE NN 273357 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_BOT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 238 MASTER LE NN 273372 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 239 MASTER LE NN 273364 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__OCP_THR_CONFIG_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 240 MASTER LE NN 273346 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 241 MASTER LE NN 273161 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 242 MASTER LE NN 273259 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 243 MASTER LE NN 273165 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 244 MASTER LE NN 273164 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 245 MASTER LE NN 273096 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 246 MASTER LE NN 273166 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 247 MASTER LE NN 273167 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 248 MASTER LE NN 273189 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 249 MASTER LE NN 273190 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 250 MASTER LE NN 273192 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 251 MASTER LE NN 273169 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 252 MASTER LE NN 273141 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 253 MASTER LE NN 273186 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 254 MASTER LE NN 273188 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 255 MASTER LE NN 273095 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 256 MASTER LE NN 273097 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 257 MASTER LE NN 273260 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 258 MASTER LE NN 273160 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 259 MASTER LE NN 273139 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 260 MASTER LE NN 273143 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 261 MASTER LE NN 273163 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 262 MASTER LE NN 273261 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 263 MASTER LE NN 273262 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 264 MASTER LE NN 273175 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 265 MASTER LE NN 273158 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 266 MASTER LE NN 273176 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 267 MASTER LE NN 273170 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 268 MASTER LE NN 273162 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 269 MASTER LE NN 273144 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_dly_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 270 MASTER LE NN 273142 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 271 MASTER LE NN 273191 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_pfet_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 272 MASTER LE NN 273172 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 273 MASTER LE NN 273302 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 274 MASTER LE NN 273173 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 275 MASTER LE NN 273140 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 276 MASTER LE NN 273193 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 277 MASTER LE NN 273168 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 278 MASTER LE NN 273194 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 279 MASTER LE NN 272848 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256580 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX1)
Chain[3] 280 MASTER LE NN 272808 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 281 MASTER LE NN 272803 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 282 MASTER LE NN 272902 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 283 MASTER LE NN 272853 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 284 MASTER LE NN 272851 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 285 MASTER LE NN 272843 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 286 MASTER LE NN 272841 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 287 MASTER LE NN 272846 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 288 MASTER LE NN 272723 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 289 MASTER LE NN 272839 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 290 MASTER LE NN 272749 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 291 MASTER LE NN 272892 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 292 MASTER LE NN 272917 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 293 MASTER LE NN 272915 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 294 MASTER LE NN 272910 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 295 MASTER LE NN 272909 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 296 MASTER LE NN 272884 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 297 MASTER LE NN 272883 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 298 MASTER LE NN 272881 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 299 MASTER LE NN 272916 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 300 MASTER LE NN 272893 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 301 MASTER LE NN 272891 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 302 MASTER LE NN 272889 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 303 MASTER LE NN 272838 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 304 MASTER LE NN 272722 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 305 MASTER LE NN 273045 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 306 MASTER LE NN 273049 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 307 MASTER LE NN 273051 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 308 MASTER LE NN 272792 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 309 MASTER LE NN 272720 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 310 MASTER LE NN 272721 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 311 MASTER LE NN 272911 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 312 MASTER LE NN 272742 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 313 MASTER LE NN 272743 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 314 MASTER LE NN 272887 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 315 MASTER LE NN 272888 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 316 MASTER LE NN 272908 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 317 MASTER LE NN 272907 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 318 MASTER LE NN 272872 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 319 MASTER LE NN 272873 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 320 MASTER LE NN 272747 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 321 MASTER LE NN 272746 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 322 MASTER LE NN 272706 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 323 MASTER LE NN 272707 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 324 MASTER LE NN 272708 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 325 MASTER LE NN 272709 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 326 MASTER LE NN 272705 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 327 MASTER LE NN 272704 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 328 MASTER LE NN 272703 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 329 MASTER LE NN 272879 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 330 MASTER LE NN 272871 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 331 MASTER LE NN 272882 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 332 MASTER LE NN 272868 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 333 MASTER LE NN 272906 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 334 MASTER LE NN 272875 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 335 MASTER LE NN 272869 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 336 MASTER LE NN 272885 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 337 MASTER LE NN 272870 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 338 MASTER LE NN 272876 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 339 MASTER LE NN 272878 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 340 MASTER LE NN 272877 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 341 MASTER LE NN 272874 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 342 MASTER LE NN 272886 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 343 MASTER LE NN 272894 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 344 MASTER LE NN 272912 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 345 MASTER LE NN 272913 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 346 MASTER LE NN 272914 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 347 MASTER LE NN 272896 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 348 MASTER LE NN 272895 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 349 MASTER LE NN 272880 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 350 MASTER LE NN 272890 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 351 MASTER LE NN 272748 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 352 MASTER LE NN 272844 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 353 MASTER LE NN 272845 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 354 MASTER LE NN 272842 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 355 MASTER LE NN 272850 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 356 MASTER LE NN 272849 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 357 MASTER LE NN 272847 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 358 MASTER LE NN 272750 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 359 MASTER LE NN 272905 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 360 MASTER LE NN 272852 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 361 MASTER LE NN 272840 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 362 MASTER LE NN 272798 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 363 MASTER LE NN 272793 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 364 MASTER LE NN 272800 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
 Chain[3] 365 MASTER LE NN 272807 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 366 MASTER LE NN 272805 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 367 MASTER LE NN 272802 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 368 MASTER LE NN 272996 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 369 MASTER LE NN 273003 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 370 MASTER LE NN 273019 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 371 MASTER LE NN 273021 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 372 MASTER LE NN 273022 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 373 MASTER LE NN 273026 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 374 MASTER LE NN 273020 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 375 MASTER LE NN 273040 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 376 MASTER LE NN 272796 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 377 MASTER LE NN 272795 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 378 MASTER LE NN 272725 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 379 MASTER LE NN 272726 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 380 MASTER LE NN 272898 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
 Chain[3] 381 MASTER LE NN 272804 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 382 MASTER LE NN 272801 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 383 MASTER LE NN 272799 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 384 MASTER LE NN 273043 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 385 MASTER LE NN 272727 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 386 MASTER LE NN 273053 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 387 MASTER LE NN 273042 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 388 MASTER LE NN 273070 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 389 MASTER LE NN 273074 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 390 MASTER LE NN 273052 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 391 MASTER LE NN 273061 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 392 MASTER LE NN 273046 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 393 MASTER LE NN 273036 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 394 MASTER LE NN 273072 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 395 MASTER LE NN 273035 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
 Chain[3] 396 MASTER LE NN 273044 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 397 MASTER LE NN 273038 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 398 MASTER LE NN 273075 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 399 MASTER LE NN 273073 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 400 MASTER LE NN 273063 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 401 MASTER LE NN 273065 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFSBQX1)
Chain[3] 402 MASTER LE NN 273076 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 403 MASTER LE NN 273068 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 404 MASTER LE NN 273048 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 405 MASTER LE NN 273064 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 406 MASTER LE NN 273037 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 407 MASTER LE NN 273066 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 408 MASTER LE NN 272999 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 409 MASTER LE NN 272998 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 410 MASTER LE NN 273058 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 411 MASTER LE NN 273059 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 412 MASTER LE NN 273057 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 413 MASTER LE NN 273034 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 414 MASTER LE NN 272988 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC_CTL1__READY_STEPDOWN_QUAL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 415 MASTER LE NN 273027 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 416 MASTER LE NN 273060 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 417 MASTER LE NN 273016 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/BYPASS_CTL1_0_array_u_BYPASS_CTL1_0__SMART_BYPASS_E
NTRY_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 418 MASTER LE NN 272732 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 419 MASTER LE NN 272731 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 420 MASTER LE NN 272729 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 421 MASTER LE NN 272978 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 422 MASTER LE NN 272744 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 423 MASTER LE NN 272745 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 424 MASTER LE NN 272690 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 425 MASTER LE NN 272836 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 426 MASTER LE NN 272741 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 427 MASTER LE NN 272979 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 428 MASTER LE NN 272837 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 429 MASTER LE NN 272730 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 430 MASTER LE NN 272815 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 431 MASTER LE NN 272814 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 432 MASTER LE NN 272816 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 433 MASTER LE NN 272817 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 434 MASTER LE NN 272812 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 435 MASTER LE NN 272699 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 436 MASTER LE NN 272813 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 437 MASTER LE NN 272791 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 438 MASTER LE NN 272697 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 439 MASTER LE NN 272696 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 440 MASTER LE NN 272695 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 441 MASTER LE NN 272694 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 442 MASTER LE NN 272698 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 443 MASTER LE NN 272701 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 444 MASTER LE NN 272700 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 445 MASTER LE NN 272733 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 446 MASTER LE NN 272809 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_meta_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 447 MASTER LE NN 272992 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 448 MASTER LE NN 272864 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 449 MASTER LE NN 272865 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 450 MASTER LE NN 272863 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 451 MASTER LE NN 272862 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 452 MASTER LE NN 272987 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 453 MASTER LE NN 272985 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 454 MASTER LE NN 272711 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 455 MASTER LE NN 272714 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 456 MASTER LE NN 272819 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 457 MASTER LE NN 272820 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
 Chain[3] 458 MASTER LE NN 272810 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 459 MASTER LE NN 272823 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 460 MASTER LE NN 272861 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_stepdn_det_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 461 MASTER LE NN 272860 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 462 MASTER LE NN 272859 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 463 MASTER LE NN 272713 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 464 MASTER LE NN 272712 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 465 MASTER LE NN 272710 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 466 MASTER LE NN 272688 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 467 MASTER LE NN 272717 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 468 MASTER LE NN 272716 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 469 MASTER LE NN 272715 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 470 MASTER LE NN 272689 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 471 MASTER LE NN 272983 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 472 MASTER LE NN 272981 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 473 MASTER LE NN 272993 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 474 MASTER LE NN 272867 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 475 MASTER LE NN 272866 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 476 MASTER LE NN 273069 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 477 MASTER LE NN 273067 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[3] 478 MASTER LE NN 273041 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 479 MASTER LE NN 273071 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 480 MASTER LE NN 273047 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 481 MASTER LE NN 273039 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 482 MASTER LE NN 272794 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 483 MASTER LE NN 272728 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 484 MASTER LE NN 272724 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 485 MASTER LE NN 272806 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 486 MASTER LE NN 272897 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 487 MASTER LE NN 272797 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 488 MASTER LE NN 273018 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 489 MASTER LE NN 273062 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 490 MASTER LE NN 273017 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 491 MASTER LE NN 273050 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 492 MASTER LE NN 273023 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 493 MASTER LE NN 273002 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 494 MASTER LE NN 273025 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 495 MASTER LE NN 273000 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 496 MASTER LE NN 273024 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 497 MASTER LE NN 273001 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 498 MASTER LE NN 272923 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 499 MASTER LE NN 272997 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 500 MASTER LE NN 272922 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 501 MASTER LE NN 272927 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 502 MASTER LE NN 272928 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 503 MASTER LE NN 272924 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 504 MASTER LE NN 272972 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 505 MASTER LE NN 272929 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 506 MASTER LE NN 272973 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 507 MASTER LE NN 272936 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 508 MASTER LE NN 272937 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 509 MASTER LE NN 272971 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 510 MASTER LE NN 272970 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 511 MASTER LE NN 273032 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 512 MASTER LE NN 272966 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG3_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 513 MASTER LE NN 273010 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 514 MASTER LE NN 272974 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 515 MASTER LE NN 272942 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 516 MASTER LE NN 273012 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 517 MASTER LE NN 272945 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 518 MASTER LE NN 272967 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[1
] (M31_1P5V6T_SFFSBQX1)
Chain[3] 519 MASTER LE NN 272950 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 520 MASTER LE NN 272958 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PLOW_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 521 MASTER LE NN 272948 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 522 MASTER LE NN 272755 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 523 MASTER LE NN 272952 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 524 MASTER LE NN 272831 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 525 MASTER LE NN 272953 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 526 MASTER LE NN 272951 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 527 MASTER LE NN 272949 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 528 MASTER LE NN 272960 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD2_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 529 MASTER LE NN 272954 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_BOT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 530 MASTER LE NN 272946 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 531 MASTER LE NN 273013 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 532 MASTER LE NN 273014 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 533 MASTER LE NN 272932 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 534 MASTER LE NN 273028 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 535 MASTER LE NN 273031 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 536 MASTER LE NN 272935 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 537 MASTER LE NN 273029 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 538 MASTER LE NN 272955 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_LPM_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 539 MASTER LE NN 272925 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 540 MASTER LE NN 272959 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD1_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 541 MASTER LE NN 272975 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 542 MASTER LE NN 272990 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 543 MASTER LE NN 272976 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 544 MASTER LE NN 272995 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 545 MASTER LE NN 272980 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 546 MASTER LE NN 272900 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 547 MASTER LE NN 272982 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 548 MASTER LE NN 272986 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 549 MASTER LE NN 272854 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 550 MASTER LE NN 272984 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 551 MASTER LE NN 272977 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[3] 552 MASTER LE NN 272818 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 553 MASTER LE NN 272811 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 554 MASTER LE NN 272858 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 555 MASTER LE NN 272857 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 556 MASTER LE NN 273007 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 557 MASTER LE NN 272825 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_
u/GEN_PBUS_BUFF_STEPPER_DONE_d_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 558 MASTER LE NN 272991 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 559 MASTER LE NN 272901 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 560 MASTER LE NN 272968 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 561 MASTER LE NN 272965 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG2_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 562 MASTER LE NN 272964 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 563 MASTER LE NN 272989 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 564 MASTER LE NN 273008 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 565 MASTER LE NN 272751 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 566 MASTER LE NN 272994 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 567 MASTER LE NN 272834 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 568 MASTER LE NN 272835 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 569 MASTER LE NN 272718 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 570 MASTER LE NN 272828 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 571 MASTER LE NN 272821 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_gt_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 572 MASTER LE NN 272702 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 573 MASTER LE NN 272822 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_eq_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 574 MASTER LE NN 272826 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 575 MASTER LE NN 272827 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 576 MASTER LE NN 272829 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 577 MASTER LE NN 273077 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 578 MASTER LE NN 273055 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 579 MASTER LE NN 272719 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_int_soft_start_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 580 MASTER LE NN 273054 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 581 MASTER LE NN 272734 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 582 MASTER LE NN 272767 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 583 MASTER LE NN 273056 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__VOLTAGE_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 584 MASTER LE NN 273006 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 585 MASTER LE NN 273009 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 586 MASTER LE NN 272934 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 587 MASTER LE NN 273005 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 588 MASTER LE NN 272832 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 589 MASTER LE NN 272775 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 590 MASTER LE NN 272776 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 591 MASTER LE NN 272830 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 592 MASTER LE NN 272753 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 593 MASTER LE NN 272833 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 594 MASTER LE NN 272752 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 595 MASTER LE NN 272774 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 596 MASTER LE NN 272773 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 597 MASTER LE NN 272903 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 598 MASTER LE NN 272824 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 599 MASTER LE NN 273004 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 600 MASTER LE NN 272931 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 601 MASTER LE NN 272930 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 602 MASTER LE NN 272926 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 603 MASTER LE NN 272933 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 604 MASTER LE NN 273015 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 605 MASTER LE NN 273030 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 606 MASTER LE NN 273033 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 607 MASTER LE NN 273011 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 608 MASTER LE NN 272763 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 609 MASTER LE NN 272762 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 610 MASTER LE NN 272691 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 611 MASTER LE NN 272693 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 612 MASTER LE NN 272963 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PLOW_CLAMP_THR_CONFIG_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 613 MASTER LE NN 272956 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_EA_CONFIG_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 614 MASTER LE NN 272941 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 615 MASTER LE NN 272940 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 616 MASTER LE NN 272957 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PUP_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 617 MASTER LE NN 272939 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 618 MASTER LE NN 272938 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 619 MASTER LE NN 272961 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__OCP_THR_CONFIG_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 620 MASTER LE NN 272943 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 621 MASTER LE NN 272947 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 622 MASTER LE NN 272962 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PUP_CLAMP_THR_CONFIG_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 623 MASTER LE NN 272969 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 624 MASTER LE NN 272779 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 625 MASTER LE NN 272904 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 626 MASTER LE NN 272778 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 627 MASTER LE NN 272777 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 628 MASTER LE NN 272780 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 629 MASTER LE NN 272783 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_narrow_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 630 MASTER LE NN 272781 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 631 MASTER LE NN 272760 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 632 MASTER LE NN 272761 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 633 MASTER LE NN 272855 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 634 MASTER LE NN 272756 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 635 MASTER LE NN 272856 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 636 MASTER LE NN 272757 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 637 MASTER LE NN 272771 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 638 MASTER LE NN 272770 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_wide_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 639 MASTER LE NN 272758 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 640 MASTER LE NN 272944 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 641 MASTER LE NN 272759 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 642 MASTER LE NN 272754 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 643 MASTER LE NN 272738 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 644 MASTER LE NN 272768 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 645 MASTER LE NN 272739 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 646 MASTER LE NN 272735 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 647 MASTER LE NN 272692 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 648 MASTER LE NN 272737 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 649 MASTER LE NN 272736 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 650 MASTER LE NN 272765 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 651 MASTER LE NN 272769 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 652 MASTER LE NN 272785 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 653 MASTER LE NN 272687 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 654 MASTER LE NN 272788 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 655 MASTER LE NN 272899 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 656 MASTER LE NN 272772 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 657 MASTER LE NN 272766 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 658 MASTER LE NN 272787 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_pfet_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 659 MASTER LE NN 272740 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_dly_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 660 MASTER LE NN 272677 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 661 MASTER LE NN 272676 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 662 MASTER LE NN 272678 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 663 MASTER LE NN 272681 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 664 MASTER LE NN 272680 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 665 MASTER LE NN 272679 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 666 MASTER LE NN 272675 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 667 MASTER LE NN 272684 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 668 MASTER LE NN 272790 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 669 MASTER LE NN 272789 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 670 MASTER LE NN 272686 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 671 MASTER LE NN 272683 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 672 MASTER LE NN 272674 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 673 MASTER LE NN 272685 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 674 MASTER LE NN 272682 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 675 MASTER LE NN 272764 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 676 MASTER LE NN 272786 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 677 MASTER LE NN 272784 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 678 MASTER LE NN 272782 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[2]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 679 MASTER LE NN 272279 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256530 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/LOCKUP (M31_1P5V6T_LOWLATCHX2)
Chain[3] 680 MASTER LE NN 272280 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 681 MASTER LE NN 272278 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 682 MASTER LE NN 272277 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 683 MASTER LE NN 272282 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 684 MASTER LE NN 272283 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 685 MASTER LE NN 272271 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 686 MASTER LE NN 272270 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 687 MASTER LE NN 272274 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 688 MASTER LE NN 272275 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 689 MASTER LE NN 272276 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 690 MASTER LE NN 272281 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 691 MASTER LE NN 272272 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 692 MASTER LE NN 272273 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 693 MASTER LE NN 272611 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 694 MASTER LE NN 272612 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 695 MASTER LE NN 272613 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 696 MASTER LE NN 272614 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 697 MASTER LE NN 272616 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 698 MASTER LE NN 272594 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 699 MASTER LE NN 272589 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 700 MASTER LE NN 272617 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 701 MASTER LE NN 272595 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 702 MASTER LE NN 272593 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 703 MASTER LE NN 272596 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 704 MASTER LE NN 272618 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 705 MASTER LE NN 272615 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 706 MASTER LE NN 272531 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 707 MASTER LE NN 272555 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PUP_CLAMP_THR_CONFIG_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 708 MASTER LE NN 272534 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 709 MASTER LE NN 272532 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 710 MASTER LE NN 272533 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 711 MASTER LE NN 272550 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PUP_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 712 MASTER LE NN 272549 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_EA_CONFIG_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 713 MASTER LE NN 272536 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 714 MASTER LE NN 272556 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PLOW_CLAMP_THR_CONFIG_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 715 MASTER LE NN 272554 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__OCP_THR_CONFIG_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 716 MASTER LE NN 272537 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 717 MASTER LE NN 272561 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 718 MASTER LE NN 272543 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 719 MASTER LE NN 272551 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PLOW_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 720 MASTER LE NN 272560 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[1
] (M31_1P5V6T_SFFSBQX1)
Chain[3] 721 MASTER LE NN 272553 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD2_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 722 MASTER LE NN 272562 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 723 MASTER LE NN 272547 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_BOT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 724 MASTER LE NN 272622 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 725 MASTER LE NN 272598 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 726 MASTER LE NN 272564 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 727 MASTER LE NN 272515 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 728 MASTER LE NN 272673 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX2)
Chain[3] 729 MASTER LE NN 272356 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 730 MASTER LE NN 272354 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 731 MASTER LE NN 272289 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 732 MASTER LE NN 272288 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 733 MASTER LE NN 272358 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 734 MASTER LE NN 272357 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 735 MASTER LE NN 272363 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 736 MASTER LE NN 272497 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 737 MASTER LE NN 272335 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 738 MASTER LE NN 272334 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 739 MASTER LE NN 272331 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 740 MASTER LE NN 272287 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 741 MASTER LE NN 272355 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 742 MASTER LE NN 272336 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_dly_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 743 MASTER LE NN 272381 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_pfet_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 744 MASTER LE NN 272361 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 745 MASTER LE NN 272366 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 746 MASTER LE NN 272350 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 747 MASTER LE NN 272353 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 748 MASTER LE NN 272352 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 749 MASTER LE NN 272365 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 750 MASTER LE NN 272370 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 751 MASTER LE NN 272364 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_wide_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 752 MASTER LE NN 272367 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 753 MASTER LE NN 272368 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 754 MASTER LE NN 272501 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 755 MASTER LE NN 272369 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 756 MASTER LE NN 272375 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 757 MASTER LE NN 272351 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 758 MASTER LE NN 272371 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 759 MASTER LE NN 272541 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 760 MASTER LE NN 272540 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 761 MASTER LE NN 272605 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 762 MASTER LE NN 272607 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 763 MASTER LE NN 272606 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 764 MASTER LE NN 272524 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 765 MASTER LE NN 272648 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__VOLTAGE_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 766 MASTER LE NN 272542 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 767 MASTER LE NN 272651 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 768 MASTER LE NN 272664 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 769 MASTER LE NN 272650 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 770 MASTER LE NN 272649 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 771 MASTER LE NN 272629 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 772 MASTER LE NN 272628 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 773 MASTER LE NN 272592 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 774 MASTER LE NN 272591 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 775 MASTER LE NN 272581 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC_CTL1__READY_STEPDOWN_QUAL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 776 MASTER LE NN 272517 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 777 MASTER LE NN 272590 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 778 MASTER LE NN 272516 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 779 MASTER LE NN 272563 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 780 MASTER LE NN 272597 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 781 MASTER LE NN 272625 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 782 MASTER LE NN 272624 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 783 MASTER LE NN 272621 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 784 MASTER LE NN 272623 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 785 MASTER LE NN 272538 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 786 MASTER LE NN 272566 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 787 MASTER LE NN 272599 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 788 MASTER LE NN 272558 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG2_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 789 MASTER LE NN 272620 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 790 MASTER LE NN 272548 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_LPM_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 791 MASTER LE NN 272559 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG3_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 792 MASTER LE NN 272601 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 793 MASTER LE NN 272642 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 794 MASTER LE NN 272619 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 795 MASTER LE NN 272610 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 796 MASTER LE NN 272655 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 797 MASTER LE NN 272530 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 798 MASTER LE NN 272565 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 799 MASTER LE NN 272600 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 800 MASTER LE NN 272518 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 801 MASTER LE NN 272519 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 802 MASTER LE NN 272647 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 803 MASTER LE NN 272557 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 804 MASTER LE NN 272535 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 805 MASTER LE NN 272552 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD1_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 806 MASTER LE NN 272604 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 807 MASTER LE NN 272602 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 808 MASTER LE NN 272499 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 809 MASTER LE NN 272567 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 810 MASTER LE NN 272568 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 811 MASTER LE NN 272587 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 812 MASTER LE NN 272525 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 813 MASTER LE NN 272526 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 814 MASTER LE NN 272579 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX2J)
Chain[3] 815 MASTER LE NN 272646 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 816 MASTER LE NN 272603 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 817 MASTER LE NN 272544 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 818 MASTER LE NN 272546 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 819 MASTER LE NN 272419 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_
u/GEN_PBUS_BUFF_STEPPER_DONE_d_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 820 MASTER LE NN 272608 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/BYPASS_CTL1_0_array_u_BYPASS_CTL1_0__SMART_BYPASS_E
NTRY_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 821 MASTER LE NN 272372 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 822 MASTER LE NN 272502 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 823 MASTER LE NN 272374 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 824 MASTER LE NN 272377 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_narrow_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 825 MASTER LE NN 272539 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 826 MASTER LE NN 272373 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 827 MASTER LE NN 272545 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 828 MASTER LE NN 272569 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[3] 829 MASTER LE NN 272498 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 830 MASTER LE NN 272582 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 831 MASTER LE NN 272588 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 832 MASTER LE NN 272523 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 833 MASTER LE NN 272527 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 834 MASTER LE NN 272577 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 835 MASTER LE NN 272583 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 836 MASTER LE NN 272584 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX3)
Chain[3] 837 MASTER LE NN 272575 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX2J)
Chain[3] 838 MASTER LE NN 272573 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 839 MASTER LE NN 272670 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX2J)
Chain[3] 840 MASTER LE NN 272669 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 841 MASTER LE NN 272529 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 842 MASTER LE NN 272528 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 843 MASTER LE NN 272362 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 844 MASTER LE NN 272520 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 845 MASTER LE NN 272522 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 846 MASTER LE NN 272521 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 847 MASTER LE NN 272609 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 848 MASTER LE NN 272672 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[6]
(M31_1P5V6T_SFFRBQX2)
Chain[3] 849 MASTER LE NN 272332 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 850 MASTER LE NN 272333 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 851 MASTER LE NN 272360 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 852 MASTER LE NN 272450 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 853 MASTER LE NN 272449 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 854 MASTER LE NN 272448 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 855 MASTER LE NN 272570 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[3] 856 MASTER LE NN 272422 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 857 MASTER LE NN 272328 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 858 MASTER LE NN 272330 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 859 MASTER LE NN 272428 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 860 MASTER LE NN 272348 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 861 MASTER LE NN 272429 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 862 MASTER LE NN 272314 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 863 MASTER LE NN 272329 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 864 MASTER LE NN 272416 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_eq_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 865 MASTER LE NN 272315 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_int_soft_start_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 866 MASTER LE NN 272347 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 867 MASTER LE NN 272413 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 868 MASTER LE NN 272657 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFSBQX1)
Chain[3] 869 MASTER LE NN 272668 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 870 MASTER LE NN 272630 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 871 MASTER LE NN 272627 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 872 MASTER LE NN 272636 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 873 MASTER LE NN 272660 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 874 MASTER LE NN 272662 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 875 MASTER LE NN 272638 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 876 MASTER LE NN 272658 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 877 MASTER LE NN 272666 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 878 MASTER LE NN 272652 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 879 MASTER LE NN 272644 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 880 MASTER LE NN 272653 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 881 MASTER LE NN 272640 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 882 MASTER LE NN 272656 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 883 MASTER LE NN 272632 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 884 MASTER LE NN 272634 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 885 MASTER LE NN 272626 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 886 MASTER LE NN 272410 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 887 MASTER LE NN 272411 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 888 MASTER LE NN 272290 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 889 MASTER LE NN 272409 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 890 MASTER LE NN 272292 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 891 MASTER LE NN 272406 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 892 MASTER LE NN 272412 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 893 MASTER LE NN 272421 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 894 MASTER LE NN 272385 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 895 MASTER LE NN 272420 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 896 MASTER LE NN 272423 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 897 MASTER LE NN 272427 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 898 MASTER LE NN 272418 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 899 MASTER LE NN 272425 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 900 MASTER LE NN 272426 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 901 MASTER LE NN 272424 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 902 MASTER LE NN 272415 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_gt_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 903 MASTER LE NN 272408 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 904 MASTER LE NN 272407 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 905 MASTER LE NN 272405 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 906 MASTER LE NN 272296 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 907 MASTER LE NN 272291 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 908 MASTER LE NN 272297 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 909 MASTER LE NN 272294 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 910 MASTER LE NN 272293 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 911 MASTER LE NN 272295 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 912 MASTER LE NN 272654 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 913 MASTER LE NN 272645 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 914 MASTER LE NN 272661 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 915 MASTER LE NN 272665 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 916 MASTER LE NN 272659 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[3] 917 MASTER LE NN 272663 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 918 MASTER LE NN 272633 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 919 MASTER LE NN 272667 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 920 MASTER LE NN 272639 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 921 MASTER LE NN 272641 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 922 MASTER LE NN 272631 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 923 MASTER LE NN 272643 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 924 MASTER LE NN 272483 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 925 MASTER LE NN 272484 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 926 MASTER LE NN 272481 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 927 MASTER LE NN 272325 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 928 MASTER LE NN 272430 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 929 MASTER LE NN 272574 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 930 MASTER LE NN 272576 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 931 MASTER LE NN 272571 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 932 MASTER LE NN 272572 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 933 MASTER LE NN 272585 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 934 MASTER LE NN 272404 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 935 MASTER LE NN 272586 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 936 MASTER LE NN 272403 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_meta_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 937 MASTER LE NN 272414 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 938 MASTER LE NN 272417 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 939 MASTER LE NN 272453 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 940 MASTER LE NN 272298 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 941 MASTER LE NN 272349 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 942 MASTER LE NN 272455 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_stepdn_det_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 943 MASTER LE NN 272454 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 944 MASTER LE NN 272380 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 945 MASTER LE NN 272376 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 946 MASTER LE NN 272452 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 947 MASTER LE NN 272451 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 948 MASTER LE NN 272378 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 949 MASTER LE NN 272379 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 950 MASTER LE NN 272382 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 951 MASTER LE NN 272359 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 952 MASTER LE NN 272300 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 953 MASTER LE NN 272302 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 954 MASTER LE NN 272303 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 955 MASTER LE NN 272384 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 956 MASTER LE NN 272383 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 957 MASTER LE NN 272327 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 958 MASTER LE NN 272326 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 959 MASTER LE NN 272286 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 960 MASTER LE NN 272431 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 961 MASTER LE NN 272337 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 962 MASTER LE NN 272505 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 963 MASTER LE NN 272465 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 964 MASTER LE NN 272509 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 965 MASTER LE NN 272508 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 966 MASTER LE NN 272635 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 967 MASTER LE NN 272637 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 968 MASTER LE NN 272671 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 969 MASTER LE NN 272487 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 970 MASTER LE NN 272488 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 971 MASTER LE NN 272485 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 972 MASTER LE NN 272489 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 973 MASTER LE NN 272486 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 974 MASTER LE NN 272474 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 975 MASTER LE NN 272466 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 976 MASTER LE NN 272467 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 977 MASTER LE NN 272462 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 978 MASTER LE NN 272468 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 979 MASTER LE NN 272463 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 980 MASTER LE NN 272495 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 981 MASTER LE NN 272471 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 982 MASTER LE NN 272472 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 983 MASTER LE NN 272469 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 984 MASTER LE NN 272391 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 985 MASTER LE NN 272400 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 986 MASTER LE NN 272398 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 987 MASTER LE NN 272395 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 988 MASTER LE NN 272397 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 989 MASTER LE NN 272500 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 990 MASTER LE NN 272401 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 991 MASTER LE NN 272393 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 992 MASTER LE NN 272496 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 993 MASTER LE NN 272388 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 994 MASTER LE NN 272320 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 995 MASTER LE NN 272321 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 996 MASTER LE NN 272319 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 997 MASTER LE NN 272318 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 998 MASTER LE NN 272473 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 999 MASTER LE NN 272476 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1000 MASTER LE NN 272475 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1001 MASTER LE NN 272478 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1002 MASTER LE NN 272492 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1003 MASTER LE NN 272493 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1004 MASTER LE NN 272510 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1005 MASTER LE NN 272490 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1006 MASTER LE NN 272491 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1007 MASTER LE NN 272494 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1008 MASTER LE NN 272507 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1009 MASTER LE NN 272482 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1010 MASTER LE NN 272506 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1011 MASTER LE NN 272504 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1012 MASTER LE NN 272480 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1013 MASTER LE NN 272477 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 1014 MASTER LE NN 272479 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1015 MASTER LE NN 272438 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1016 MASTER LE NN 272323 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1017 MASTER LE NN 272435 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1018 MASTER LE NN 272324 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1019 MASTER LE NN 272322 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1020 MASTER LE NN 272444 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1021 MASTER LE NN 272392 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1022 MASTER LE NN 272443 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1023 MASTER LE NN 272445 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1024 MASTER LE NN 272390 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1025 MASTER LE NN 272389 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1026 MASTER LE NN 272436 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1027 MASTER LE NN 272439 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1028 MASTER LE NN 272338 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1029 MASTER LE NN 272339 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1030 MASTER LE NN 272340 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1031 MASTER LE NN 272341 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1032 MASTER LE NN 272460 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1033 MASTER LE NN 272461 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1034 MASTER LE NN 272342 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1035 MASTER LE NN 272299 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1036 MASTER LE NN 272343 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1037 MASTER LE NN 272284 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1038 MASTER LE NN 272313 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1039 MASTER LE NN 272285 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1040 MASTER LE NN 272440 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1041 MASTER LE NN 272316 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1042 MASTER LE NN 272437 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1043 MASTER LE NN 272386 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1044 MASTER LE NN 272432 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1045 MASTER LE NN 272317 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1046 MASTER LE NN 272310 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1047 MASTER LE NN 272312 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1048 MASTER LE NN 272311 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1049 MASTER LE NN 272459 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1050 MASTER LE NN 272458 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1051 MASTER LE NN 272580 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1052 MASTER LE NN 272578 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1053 MASTER LE NN 272456 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1054 MASTER LE NN 272305 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1055 MASTER LE NN 272301 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1056 MASTER LE NN 272304 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1057 MASTER LE NN 272457 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1058 MASTER LE NN 272307 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1059 MASTER LE NN 272306 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1060 MASTER LE NN 272309 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1061 MASTER LE NN 272308 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1062 MASTER LE NN 272433 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1063 MASTER LE NN 272387 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1064 MASTER LE NN 272344 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1065 MASTER LE NN 272345 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1066 MASTER LE NN 272447 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1067 MASTER LE NN 272442 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1068 MASTER LE NN 272503 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1069 MASTER LE NN 272441 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1070 MASTER LE NN 272446 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1071 MASTER LE NN 272434 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1072 MASTER LE NN 272346 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1073 MASTER LE NN 272394 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1074 MASTER LE NN 272399 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1075 MASTER LE NN 272402 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1076 MASTER LE NN 272470 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1077 MASTER LE NN 272396 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1078 MASTER LE NN 272464 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[1]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1079 MASTER LE NN 272265 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_CURRENT_LIM_CTRL_
SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256528 - GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX3)
Chain[3] 1080 MASTER LE NN 272266 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_CURRENT_LIM_CTRL_
SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1081 MASTER LE NN 272188 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__ILIM_DLY_SEL_reg/dout_re
g[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1082 MASTER LE NN 272146 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM2__INZERO_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 1083 MASTER LE NN 272189 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__ILIM_DLY_SEL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1084 MASTER LE NN 272151 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM1__PWM_IPLIM_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1085 MASTER LE NN 272137 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM4__PFM_IPLIM_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1086 MASTER LE NN 272246 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ILIM_SS_CTL__ILIM_SS_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 1087 MASTER LE NN 272244 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ILIM_SS_CTL__ILIM_SS_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 1088 MASTER LE NN 271754 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1089 MASTER LE NN 271069 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1090 MASTER LE NN 271070 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1091 MASTER LE NN 271021 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1092 MASTER LE NN 271017 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1093 MASTER LE NN 271023 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1094 MASTER LE NN 271019 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1095 MASTER LE NN 271137 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1096 MASTER LE NN 271020 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1097 MASTER LE NN 271025 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1098 MASTER LE NN 271018 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1099 MASTER LE NN 271016 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1100 MASTER LE NN 271031 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1101 MASTER LE NN 271032 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1102 MASTER LE NN 271027 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1103 MASTER LE NN 271009 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/fsm_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1104 MASTER LE NN 271026 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/fsm_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1105 MASTER LE NN 271122 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_curr_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1106 MASTER LE NN 271014 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/fsm_state_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1107 MASTER LE NN 271121 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1108 MASTER LE NN 271120 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1109 MASTER LE NN 271124 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_curr_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1110 MASTER LE NN 270953 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1111 MASTER LE NN 271125 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_curr_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1112 MASTER LE NN 271130 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1113 MASTER LE NN 271134 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1114 MASTER LE NN 271136 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1115 MASTER LE NN 271135 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1116 MASTER LE NN 271133 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1117 MASTER LE NN 271129 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1118 MASTER LE NN 271131 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1119 MASTER LE NN 271128 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1120 MASTER LE NN 271203 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1121 MASTER LE NN 271132 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1122 MASTER LE NN 271204 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1123 MASTER LE NN 271206 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1124 MASTER LE NN 271200 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1125 MASTER LE NN 271199 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1126 MASTER LE NN 271108 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1127 MASTER LE NN 271107 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1128 MASTER LE NN 271111 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1129 MASTER LE NN 271109 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1130 MASTER LE NN 271205 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1131 MASTER LE NN 271201 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1132 MASTER LE NN 271198 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_grey_counter_capture_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1133 MASTER LE NN 271197 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_data_ready_hf_sync_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1134 MASTER LE NN 271196 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/u_slib_sync_1p0_freq_data_ready/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1135 MASTER LE NN 271195 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/u_slib_sync_1p0_freq_data_ready/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1136 MASTER LE NN 270957 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1137 MASTER LE NN 270956 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1138 MASTER LE NN 270958 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1139 MASTER LE NN 271208 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1140 MASTER LE NN 270959 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[7] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 1141 MASTER LE NN 270960 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1142 MASTER LE NN 271110 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_data_ready_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1143 MASTER LE NN 271202 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1144 MASTER LE NN 271207 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1145 MASTER LE NN 271214 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_data_ready_hf_sync_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1146 MASTER LE NN 271123 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_wait_timer_start_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1147 MASTER LE NN 271127 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_sqm_timer_start_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1148 MASTER LE NN 271034 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1149 MASTER LE NN 271029 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1150 MASTER LE NN 271067 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1151 MASTER LE NN 271068 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1152 MASTER LE NN 271138 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_sqm_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1153 MASTER LE NN 271022 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1154 MASTER LE NN 271024 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1155 MASTER LE NN 271072 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1156 MASTER LE NN 271071 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1157 MASTER LE NN 271400 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1158 MASTER LE NN 271401 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1159 MASTER LE NN 271383 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1160 MASTER LE NN 271382 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1161 MASTER LE NN 272162 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__ATEST1_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1162 MASTER LE NN 272164 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__DTEST1_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1163 MASTER LE NN 272145 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM2__INZERO_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1164 MASTER LE NN 272165 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__DTEST1_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1165 MASTER LE NN 272152 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM1__PWM_IPLIM_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1166 MASTER LE NN 272147 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM2__INZERO_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1167 MASTER LE NN 272187 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__ILIM_DLY_SEL_reg/dout_re
g[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1168 MASTER LE NN 272247 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ILIM_SS_CTL__ILIM_SS_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 1169 MASTER LE NN 272138 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM4__PFM_IPLIM_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1170 MASTER LE NN 272139 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM4__PFM_IPLIM_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1171 MASTER LE NN 272268 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_CURRENT_LIM_CTRL_
SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1172 MASTER LE NN 272166 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__OPEN_LOOP_TEST_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1173 MASTER LE NN 272157 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_FORCE_FET_TEST__KELVIN_SENSING_TEST_EN_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1174 MASTER LE NN 272191 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__AFSM_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1175 MASTER LE NN 272158 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_FORCE_FET_TEST__FORCE_PFET_NFET_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1176 MASTER LE NN 272163 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__DTEST1_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1177 MASTER LE NN 272269 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_IPLIM_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1178 MASTER LE NN 272167 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__ATEST2_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1179 MASTER LE NN 272159 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_FORCE_FET_TEST__FORCE_PFET_NFET_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1180 MASTER LE NN 272200 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CAL_EN_CTL1__INLIM_TRIM_CAL_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1181 MASTER LE NN 272203 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CAL_EN_CTL1__IPLIM_TRIM_CAL_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1182 MASTER LE NN 272186 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST4__ECM_INPUT_MUX_CTRL_reg/dout
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1183 MASTER LE NN 272184 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST4__ECM_INPUT_MUX_CTRL_reg/dout
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1184 MASTER LE NN 272169 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__ATEST2_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1185 MASTER LE NN 272168 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__ATEST2_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1186 MASTER LE NN 272171 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__DTEST2_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1187 MASTER LE NN 272173 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__IPLIM_TEST_CTRL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1188 MASTER LE NN 272181 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__EN_SENSE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1189 MASTER LE NN 272172 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__DTEST2_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1190 MASTER LE NN 272202 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CAL_EN_CTL1__AUTO_THRES_TRIM_CAL_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1191 MASTER LE NN 272201 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CAL_EN_CTL1__INZERO_TRIM_CAL_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1192 MASTER LE NN 272185 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST4__ECM_INPUT_MUX_CTRL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1193 MASTER LE NN 272161 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__ATEST1_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1194 MASTER LE NN 272170 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__DTEST2_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1195 MASTER LE NN 272174 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__IPLIM_TEST_CTRL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1196 MASTER LE NN 272160 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__ATEST1_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1197 MASTER LE NN 272142 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM3__AUTO_THRS_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1198 MASTER LE NN 272141 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM3__AUTO_THRS_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
 Chain[3] 1199 MASTER LE NN 272143 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM3__AUTO_THRS_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1200 MASTER LE NN 272144 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM3__AUTO_THRS_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1201 MASTER LE NN 272267 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_CURRENT_LIM_CTRL_
SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1202 MASTER LE NN 272148 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM2__INZERO_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1203 MASTER LE NN 272190 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__ILIM_DLY_SEL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1204 MASTER LE NN 272149 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM1__PWM_IPLIM_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1205 MASTER LE NN 272150 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM1__PWM_IPLIM_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1206 MASTER LE NN 272140 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM4__PFM_IPLIM_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1207 MASTER LE NN 272245 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ILIM_SS_CTL__ILIM_SS_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 1208 MASTER LE NN 271763 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_IPLIM_CTRL_
reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1209 MASTER LE NN 271589 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_IPLIM_CTRL_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1210 MASTER LE NN 271588 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__SPARE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1211 MASTER LE NN 271011 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_cal_request_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1212 MASTER LE NN 271375 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1213 MASTER LE NN 271610 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1214 MASTER LE NN 271604 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1215 MASTER LE NN 271608 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1216 MASTER LE NN 271605 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1217 MASTER LE NN 271606 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1218 MASTER LE NN 271607 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1219 MASTER LE NN 271385 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1220 MASTER LE NN 271377 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1221 MASTER LE NN 271387 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1222 MASTER LE NN 271212 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1223 MASTER LE NN 271380 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1224 MASTER LE NN 271392 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1225 MASTER LE NN 271384 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1226 MASTER LE NN 271386 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1227 MASTER LE NN 271390 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1228 MASTER LE NN 271391 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1229 MASTER LE NN 271388 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1230 MASTER LE NN 271397 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1231 MASTER LE NN 271590 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_COMP_PLS_FLTR_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1232 MASTER LE NN 271587 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__SPARE_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1233 MASTER LE NN 271583 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_COMP_PLS_FL
TR_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1234 MASTER LE NN 271213 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1235 MASTER LE NN 271584 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_COMP_HYST_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1236 MASTER LE NN 271445 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__ERR_AMP_TRI
M_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1237 MASTER LE NN 271442 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__PFM_COMP_TR
IM_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1238 MASTER LE NN 271750 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__TRIM_CAL_EN
G_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1239 MASTER LE NN 271334 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1240 MASTER LE NN 271441 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__VDIP_COMP_T
RIM_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1241 MASTER LE NN 271399 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1242 MASTER LE NN 271051 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1243 MASTER LE NN 271055 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1244 MASTER LE NN 271440 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__PWM_RAMP_PE
AK_TRIM_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1245 MASTER LE NN 271443 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__PWM_THRES_T
RIM_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1246 MASTER LE NN 271056 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1247 MASTER LE NN 271405 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM1__PWM_THRES_TRIM_re
g/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1248 MASTER LE NN 271053 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1249 MASTER LE NN 271054 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1250 MASTER LE NN 271333 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1251 MASTER LE NN 271060 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[2][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1252 MASTER LE NN 271335 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[2][3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1253 MASTER LE NN 271063 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[3][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1254 MASTER LE NN 271066 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[4][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1255 MASTER LE NN 271062 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[3][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1256 MASTER LE NN 271047 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1257 MASTER LE NN 271751 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1258 MASTER LE NN 271049 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1259 MASTER LE NN 271048 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1260 MASTER LE NN 271065 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[4][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1261 MASTER LE NN 271061 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[3][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1262 MASTER LE NN 271336 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[3][3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1263 MASTER LE NN 271008 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/slib_sync_trimout_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1264 MASTER LE NN 271015 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/fsm_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1265 MASTER LE NN 271010 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/cal_request_reset_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1266 MASTER LE NN 271045 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1267 MASTER LE NN 271036 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1268 MASTER LE NN 271044 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1269 MASTER LE NN 270955 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1270 MASTER LE NN 270962 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1271 MASTER LE NN 270961 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1272 MASTER LE NN 270952 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1273 MASTER LE NN 270954 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1274 MASTER LE NN 271209 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1275 MASTER LE NN 271043 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1276 MASTER LE NN 271037 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1277 MASTER LE NN 271042 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1278 MASTER LE NN 271041 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1279 MASTER LE NN 271040 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1280 MASTER LE NN 271039 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1281 MASTER LE NN 271038 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1282 MASTER LE NN 271194 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/slib_clkreq_gate_1p0_hf_clk_u1/clk_en
_sync_reg (M31_1P5V6T_SFFRBQX1)
 Chain[3] 1283 MASTER LE NN 271012 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/slib_clkreq_gate_1p0_clk_cal_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1284 MASTER LE NN 271013 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/cal_request_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1285 MASTER LE NN 271007 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/slib_sync_trimout_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1286 MASTER LE NN 271059 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[2][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1287 MASTER LE NN 271337 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[4][3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1288 MASTER LE NN 271058 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[2][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1289 MASTER LE NN 271064 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[4][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1290 MASTER LE NN 271057 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1291 MASTER LE NN 271402 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1292 MASTER LE NN 271050 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1293 MASTER LE NN 271052 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1294 MASTER LE NN 271403 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1295 MASTER LE NN 271395 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 1296 MASTER LE NN 271398 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1297 MASTER LE NN 271394 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1298 MASTER LE NN 271396 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1299 MASTER LE NN 271393 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1300 MASTER LE NN 271389 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1301 MASTER LE NN 271379 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1302 MASTER LE NN 271378 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1303 MASTER LE NN 271381 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1304 MASTER LE NN 271609 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1305 MASTER LE NN 272180 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST4_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1306 MASTER LE NN 272183 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST4__ECM_TEST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1307 MASTER LE NN 272208 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_INZERO_CTL__INZERO_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1308 MASTER LE NN 272206 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_INZERO_CTL__INZERO_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1309 MASTER LE NN 272156 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1310 MASTER LE NN 272205 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_INZERO_CTL__INZERO_FORCE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1311 MASTER LE NN 272131 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_core/hfs_ps_trim_logic/d_l2r_cal_comp_state_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1312 MASTER LE NN 272207 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_INZERO_CTL__INZERO_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1313 MASTER LE NN 272230 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_SWITCH_SIZE_CTL__P_SWITCH_SIZE_reg/dout_re
g[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1314 MASTER LE NN 272182 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__EN_ADC_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1315 MASTER LE NN 272248 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CURRENT_LIM_CTL__RET_PFM_PWM_CURRENT_LIM_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1316 MASTER LE NN 272177 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST3_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1317 MASTER LE NN 272176 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST3_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1318 MASTER LE NN 272228 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_SWITCH_SIZE_CTL__N_SWITCH_SIZE_reg/dout_re
g[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1319 MASTER LE NN 272175 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST3_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1320 MASTER LE NN 272231 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_SWITCH_SIZE_CTL__P_SWITCH_SIZE_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1321 MASTER LE NN 272229 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_SWITCH_SIZE_CTL__N_SWITCH_SIZE_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1322 MASTER LE NN 272179 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST4_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1323 MASTER LE NN 272262 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_AUTOINT_S
EL_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1324 MASTER LE NN 272178 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST4_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1325 MASTER LE NN 272256 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_RET_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1326 MASTER LE NN 272233 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_QM_PS_ENTRY__QMODE_PS_ENTRY_reg/dout_reg[2
] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1327 MASTER LE NN 272154 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1328 MASTER LE NN 271761 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1329 MASTER LE NN 271095 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1330 MASTER LE NN 271616 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1331 MASTER LE NN 271615 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[4] (M31_1P5V6T_SFFSRBQX2J)
Chain[3] 1332 MASTER LE NN 271599 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1333 MASTER LE NN 271612 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1334 MASTER LE NN 271537 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_VRST_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1335 MASTER LE NN 271657 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__AUTO_RANGE_CO
MP_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1336 MASTER LE NN 271654 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__PFM_PWM_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1337 MASTER LE NN 271211 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1338 MASTER LE NN 271536 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_VRST_reg/d
out_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1339 MASTER LE NN 271539 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_VRST_RANGE
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1340 MASTER LE NN 271538 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_VRST_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1341 MASTER LE NN 271035 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1342 MASTER LE NN 271593 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_VOLT_CTL_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1343 MASTER LE NN 271586 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_VOLT_CTL_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1344 MASTER LE NN 271113 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1345 MASTER LE NN 271114 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1346 MASTER LE NN 271444 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__ERR_AMP_TRI
M_CAL_EN_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1347 MASTER LE NN 271404 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM1__PWM_THRES_TRIM_re
g/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1348 MASTER LE NN 271406 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM1__PWM_THRES_TRIM_re
g/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1349 MASTER LE NN 271646 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1350 MASTER LE NN 271648 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1351 MASTER LE NN 271106 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/slib_clkreq_gate_1p0_clk_u1/clk_en_sy
nc_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1352 MASTER LE NN 271447 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1353 MASTER LE NN 271452 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1354 MASTER LE NN 271629 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1355 MASTER LE NN 271647 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1356 MASTER LE NN 271644 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1357 MASTER LE NN 271651 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WID
TH_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1358 MASTER LE NN 271453 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1359 MASTER LE NN 271117 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1360 MASTER LE NN 271119 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1361 MASTER LE NN 271115 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1362 MASTER LE NN 271407 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM1__PWM_THRES_TRIM_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1363 MASTER LE NN 271118 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1364 MASTER LE NN 271112 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1365 MASTER LE NN 271582 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__SPARE_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1366 MASTER LE NN 271591 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_COMP_HYST_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1367 MASTER LE NN 271581 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__SPARE_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1368 MASTER LE NN 271126 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_d2a_pfm_high_sel_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1369 MASTER LE NN 271210 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 1370 MASTER LE NN 271653 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__MODE_SEL_DLY_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1371 MASTER LE NN 271655 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__PFM_PWM_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1372 MASTER LE NN 271376 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1373 MASTER LE NN 271600 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1374 MASTER LE NN 271597 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1375 MASTER LE NN 271652 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__MODE_SEL_DLY_
reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1376 MASTER LE NN 271656 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__PWM_PFM_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1377 MASTER LE NN 271602 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__FOLLOW_F
REQ_CTL_LOGIC_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1378 MASTER LE NN 271598 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1379 MASTER LE NN 271601 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX3)
Chain[3] 1380 MASTER LE NN 271614 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1381 MASTER LE NN 271613 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1382 MASTER LE NN 271611 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1383 MASTER LE NN 270930 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor21_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1384 MASTER LE NN 270925 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor16_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1385 MASTER LE NN 270929 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor20_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1386 MASTER LE NN 270910 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1387 MASTER LE NN 271091 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1388 MASTER LE NN 270932 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor23_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1389 MASTER LE NN 270934 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor25_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1390 MASTER LE NN 270917 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1391 MASTER LE NN 270926 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor17_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1392 MASTER LE NN 270916 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1393 MASTER LE NN 270923 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor14_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1394 MASTER LE NN 270924 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor15_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1395 MASTER LE NN 270928 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor19_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1396 MASTER LE NN 270918 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1397 MASTER LE NN 270920 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1398 MASTER LE NN 270933 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor24_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1399 MASTER LE NN 271294 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pfm_count_logic_u1/d_d2a_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1400 MASTER LE NN 271332 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1401 MASTER LE NN 271099 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1402 MASTER LE NN 271293 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pfm_count_logic_u1/d_sync_flop_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1403 MASTER LE NN 270906 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1404 MASTER LE NN 270904 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1405 MASTER LE NN 270908 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1406 MASTER LE NN 270935 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor26_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1407 MASTER LE NN 270911 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1408 MASTER LE NN 271145 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1409 MASTER LE NN 271001 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1410 MASTER LE NN 271177 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/slib_sync_u2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1411 MASTER LE NN 271178 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/slib_sync_u2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1412 MASTER LE NN 270972 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_fb_count_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1413 MASTER LE NN 271329 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1414 MASTER LE NN 270973 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_fb_count_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1415 MASTER LE NN 270975 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_d2a_fb_cnt_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1416 MASTER LE NN 271328 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1417 MASTER LE NN 270971 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_fb_count_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1418 MASTER LE NN 270974 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_fb_count_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1419 MASTER LE NN 270978 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1420 MASTER LE NN 271094 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1421 MASTER LE NN 271090 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1422 MASTER LE NN 271082 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1423 MASTER LE NN 271330 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1424 MASTER LE NN 271084 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1425 MASTER LE NN 271081 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_first_pass_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1426 MASTER LE NN 271079 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1427 MASTER LE NN 272249 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_PFM_SEL_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1428 MASTER LE NN 272261 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_AUTOINT_S
EL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1429 MASTER LE NN 272232 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_QM_PS_ENTRY__QMODE_PS_ENTRY_reg/dout_reg[3
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1430 MASTER LE NN 272234 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_QM_PS_ENTRY__QMODE_PS_ENTRY_reg/dout_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1431 MASTER LE NN 272155 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1432 MASTER LE NN 272153 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1433 MASTER LE NN 272254 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_RET_SEL_r
eg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
 Chain[3] 1434 MASTER LE NN 272253 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_RET_SEL_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1435 MASTER LE NN 272260 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_PWM_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1436 MASTER LE NN 272259 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_PWM_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1437 MASTER LE NN 272264 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_AUTOINT_S
EL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1438 MASTER LE NN 272257 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_PWM_SEL_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1439 MASTER LE NN 272258 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_PWM_SEL_r
eg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1440 MASTER LE NN 272255 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_RET_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1441 MASTER LE NN 272263 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_AUTOINT_S
EL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1442 MASTER LE NN 272250 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_PFM_SEL_r
eg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1443 MASTER LE NN 272251 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_PFM_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1444 MASTER LE NN 272252 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_PFM_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1445 MASTER LE NN 272235 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_QM_PS_ENTRY__QMODE_PS_ENTRY_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1446 MASTER LE NN 272135 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_re
g/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1447 MASTER LE NN 272136 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1448 MASTER LE NN 271759 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_mode_decoder_u1/d_ps_true_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1449 MASTER LE NN 271101 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1450 MASTER LE NN 271173 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/d_vr
eg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1451 MASTER LE NN 271154 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_STEPPER_DONE_d_stepper_done_pbuf_fla
g_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1452 MASTER LE NN 270931 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor22_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1453 MASTER LE NN 270937 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor28_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1454 MASTER LE NN 271548 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_ILOA
D_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1455 MASTER LE NN 271469 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1456 MASTER LE NN 271672 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_re
g/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1457 MASTER LE NN 271714 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1458 MASTER LE NN 271674 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_re
g/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1459 MASTER LE NN 271500 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FILTER_COEF__SPUR_FILTE
R_COEF_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1460 MASTER LE NN 271592 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_IBOOST_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1461 MASTER LE NN 271542 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_MODE_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1462 MASTER LE NN 271670 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/
dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1463 MASTER LE NN 271503 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_TIMER__WAIT_TIMER_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1464 MASTER LE NN 271498 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FILTER_COEF__SPUR_FILTE
R_COEF_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1465 MASTER LE NN 271030 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1466 MASTER LE NN 271585 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_IBOOST_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1467 MASTER LE NN 271678 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1468 MASTER LE NN 271632 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1469 MASTER LE NN 271449 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1470 MASTER LE NN 271446 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1471 MASTER LE NN 271476 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_3_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1472 MASTER LE NN 271580 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_1
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1473 MASTER LE NN 271577 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_1
_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1474 MASTER LE NN 271479 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_6_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1475 MASTER LE NN 271628 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1476 MASTER LE NN 271477 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_4_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1477 MASTER LE NN 271450 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1478 MASTER LE NN 271451 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1479 MASTER LE NN 271448 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1480 MASTER LE NN 271685 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1481 MASTER LE NN 271529 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1482 MASTER LE NN 271480 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_7_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1483 MASTER LE NN 271516 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1484 MASTER LE NN 271510 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1485 MASTER LE NN 271504 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1486 MASTER LE NN 271520 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1487 MASTER LE NN 271528 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1488 MASTER LE NN 271522 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1489 MASTER LE NN 271515 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1490 MASTER LE NN 271521 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1491 MASTER LE NN 271531 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1492 MASTER LE NN 271513 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1493 MASTER LE NN 271518 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1494 MASTER LE NN 271526 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1495 MASTER LE NN 271506 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1496 MASTER LE NN 271508 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1497 MASTER LE NN 271474 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_1_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1498 MASTER LE NN 271530 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1499 MASTER LE NN 271727 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1500 MASTER LE NN 271512 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1501 MASTER LE NN 271687 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1502 MASTER LE NN 271507 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1503 MASTER LE NN 271650 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WID
TH_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1504 MASTER LE NN 271631 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1505 MASTER LE NN 271649 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WID
TH_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1506 MASTER LE NN 271514 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1507 MASTER LE NN 271645 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 1508 MASTER LE NN 271633 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1509 MASTER LE NN 271720 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1510 MASTER LE NN 271555 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PREC
HG_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1511 MASTER LE NN 271552 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__SPARE1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1512 MASTER LE NN 271729 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1513 MASTER LE NN 271549 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PSKI
P_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1514 MASTER LE NN 271490 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_CLAMP_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1515 MASTER LE NN 271554 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PREC
HG_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1516 MASTER LE NN 271493 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__EN_PWM_TRAN_ASSI
ST_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1517 MASTER LE NN 271415 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__ATEST1_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1518 MASTER LE NN 271499 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FILTER_COEF__SPUR_FILTE
R_COEF_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1519 MASTER LE NN 271501 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_TIMER__SQM_TIMER_SEL_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1520 MASTER LE NN 271046 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/d_cal_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1521 MASTER LE NN 271711 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1522 MASTER LE NN 271669 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/
dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1523 MASTER LE NN 271541 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_FOLLOW_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1524 MASTER LE NN 271540 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_METHOD_reg
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1525 MASTER LE NN 271497 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_CTRL__SPUR_FSM_EN_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1526 MASTER LE NN 271502 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_TIMER__WAIT_TIMER_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1527 MASTER LE NN 271463 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_D
EB_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1528 MASTER LE NN 271006 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_cal_comp_state_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1529 MASTER LE NN 271557 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PULSE_SKIP_CTL__PS_METHOD_re
g/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1530 MASTER LE NN 271558 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PULSE_SKIP_CTL__PS_TIME_HYST
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1531 MASTER LE NN 271560 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PULSE_SKIP_CTL__PS_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1532 MASTER LE NN 271468 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_r
eg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1533 MASTER LE NN 271637 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_RE
FSAMPLE_TIMER_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1534 MASTER LE NN 271559 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PULSE_SKIP_CTL__PS_TIME_HYST
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1535 MASTER LE NN 271546 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_ILOA
D_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1536 MASTER LE NN 270922 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1537 MASTER LE NN 270927 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor18_reg (M31_1P5V6T_SFFRBQX1)
 Chain[3] 1538 MASTER LE NN 270921 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1539 MASTER LE NN 270912 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1540 MASTER LE NN 270913 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1541 MASTER LE NN 270919 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1542 MASTER LE NN 270914 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1543 MASTER LE NN 271103 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1544 MASTER LE NN 271093 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1545 MASTER LE NN 271176 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_dig_glue_u1/slib_clkreq_gate_1p0_clk_u1/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1546 MASTER LE NN 270905 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1547 MASTER LE NN 270907 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1548 MASTER LE NN 271144 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1549 MASTER LE NN 271140 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1550 MASTER LE NN 271142 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1551 MASTER LE NN 270976 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1552 MASTER LE NN 270977 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1553 MASTER LE NN 270979 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1554 MASTER LE NN 271100 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1555 MASTER LE NN 271331 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1556 MASTER LE NN 271092 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1557 MASTER LE NN 271102 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1558 MASTER LE NN 271098 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1559 MASTER LE NN 271089 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1560 MASTER LE NN 271083 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1561 MASTER LE NN 271104 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_pwm_meas_ready_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1562 MASTER LE NN 271080 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1563 MASTER LE NN 271078 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1564 MASTER LE NN 271077 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1565 MASTER LE NN 272130 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_core/hfs_ps_pwm_curr_lim_logic_u1/switch_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1566 MASTER LE NN 272211 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_BLNK_TIME_CTL__MIN_PON_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1567 MASTER LE NN 272210 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_BLNK_TIME_CTL__MIN_PON_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1568 MASTER LE NN 271749 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_ERRAMP_TRIM_
BUF_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX3)
Chain[3] 1569 MASTER LE NN 271489 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_PS_TIMEOUT_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1570 MASTER LE NN 271418 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__DTEST1_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1571 MASTER LE NN 271413 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__ATEST1_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1572 MASTER LE NN 271494 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_RETENTION_MO
DE_DLY_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1573 MASTER LE NN 271487 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_6_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1574 MASTER LE NN 271495 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__SPARE_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1575 MASTER LE NN 271722 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1576 MASTER LE NN 271556 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__SPARE0_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1577 MASTER LE NN 271551 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PSKI
P_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1578 MASTER LE NN 271566 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE2_
reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1579 MASTER LE NN 271491 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_FORCE_PWM_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1580 MASTER LE NN 271567 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE1_
reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1581 MASTER LE NN 271116 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1582 MASTER LE NN 271561 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE4_
reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1583 MASTER LE NN 271563 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE3_
reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1584 MASTER LE NN 271578 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_1
_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1585 MASTER LE NN 271681 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1586 MASTER LE NN 271524 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1587 MASTER LE NN 271666 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN2_CF
G_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1588 MASTER LE NN 271664 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN0_CF
G_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1589 MASTER LE NN 271511 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1590 MASTER LE NN 271525 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1591 MASTER LE NN 271533 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1592 MASTER LE NN 271509 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1593 MASTER LE NN 271517 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1594 MASTER LE NN 271519 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1595 MASTER LE NN 271527 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1596 MASTER LE NN 271534 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1597 MASTER LE NN 271661 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN1
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1598 MASTER LE NN 271473 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_0_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 1599 MASTER LE NN 271523 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1600 MASTER LE NN 271505 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1601 MASTER LE NN 271478 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_5_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1602 MASTER LE NN 271475 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_2_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1603 MASTER LE NN 271630 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1604 MASTER LE NN 271565 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE2_
reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1605 MASTER LE NN 271568 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE1_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1606 MASTER LE NN 271573 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_2
_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1607 MASTER LE NN 271562 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE4_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1608 MASTER LE NN 271550 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PSKI
P_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1609 MASTER LE NN 271553 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PREC
HG_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1610 MASTER LE NN 271484 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_3_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1611 MASTER LE NN 271481 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_0_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1612 MASTER LE NN 271482 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_1_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1613 MASTER LE NN 271492 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_PRECH_EXTEND
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1614 MASTER LE NN 271416 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__DTEST1_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1615 MASTER LE NN 271414 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__ATEST1_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1616 MASTER LE NN 271671 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1617 MASTER LE NN 271713 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1618 MASTER LE NN 271673 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_re
g/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1619 MASTER LE NN 271641 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1620 MASTER LE NN 271411 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INT_TEST_VAL__VREG_ACK_INT_T
EST_VAL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1621 MASTER LE NN 271028 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1622 MASTER LE NN 271710 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1623 MASTER LE NN 271639 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1624 MASTER LE NN 271457 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_D
EB_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1625 MASTER LE NN 271712 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_VS_CTL__VS_STEPPER_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1626 MASTER LE NN 271470 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__FOLDBACK_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1627 MASTER LE NN 271097 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1628 MASTER LE NN 271467 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1629 MASTER LE NN 271545 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_ILOA
D_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1630 MASTER LE NN 271622 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C1_CTRL_
reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1631 MASTER LE NN 271105 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_ready_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1632 MASTER LE NN 271619 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C1_CTRL_
reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1633 MASTER LE NN 271424 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__DTEST2_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1634 MASTER LE NN 271621 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C1_CTRL_
reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1635 MASTER LE NN 271427 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST4_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1636 MASTER LE NN 271715 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_SS_CTL__SS_STEPPER_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1637 MASTER LE NN 271033 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1638 MASTER LE NN 271175 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_vreg_fault
_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1639 MASTER LE NN 271471 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__OCP_LATCH_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1640 MASTER LE NN 271466 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1641 MASTER LE NN 271472 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__VREGOK_BYP_FOLDBACK_EN_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1642 MASTER LE NN 271635 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_P
S_DLY_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1643 MASTER LE NN 271544 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_METHOD_ST
EPPER_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1644 MASTER LE NN 271547 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_ILOA
D_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1645 MASTER LE NN 271429 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST4_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1646 MASTER LE NN 271430 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST3_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1647 MASTER LE NN 270909 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor29_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1648 MASTER LE NN 270936 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor27_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1649 MASTER LE NN 271193 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/d_vr
eg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1650 MASTER LE NN 271350 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_mode_decoder_u1/d_mode_state_flag_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1651 MASTER LE NN 271349 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_mode_decoder_u1/d_mode_state_flag_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1652 MASTER LE NN 271188 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_buck_en_del2_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1653 MASTER LE NN 271351 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_logic_rb_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1654 MASTER LE NN 271170 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1655 MASTER LE NN 271168 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1656 MASTER LE NN 271162 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1657 MASTER LE NN 271169 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1658 MASTER LE NN 271167 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1659 MASTER LE NN 271155 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1660 MASTER LE NN 271002 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_int_soft_sta
rt_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1661 MASTER LE NN 271141 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1662 MASTER LE NN 271143 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1663 MASTER LE NN 271246 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_perph_logic_u1/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1664 MASTER LE NN 271245 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_perph_logic_u1/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1665 MASTER LE NN 270982 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1666 MASTER LE NN 270970 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1667 MASTER LE NN 271184 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/slib_clkreq_gate_1p0_clk_u1/clk_en_sy
nc_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1668 MASTER LE NN 271190 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1669 MASTER LE NN 270981 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1670 MASTER LE NN 270980 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1671 MASTER LE NN 271185 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1672 MASTER LE NN 271229 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1673 MASTER LE NN 271096 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1674 MASTER LE NN 271088 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1675 MASTER LE NN 271087 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1676 MASTER LE NN 271086 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1677 MASTER LE NN 271074 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1678 MASTER LE NN 271075 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1679 MASTER LE NN 271085 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1680 MASTER LE NN 271073 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1681 MASTER LE NN 271076 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1682 MASTER LE NN 272129 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor21_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1683 MASTER LE NN 272104 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1684 MASTER LE NN 272105 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1685 MASTER LE NN 272124 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor16_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1686 MASTER LE NN 272215 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__NSW_DEAD_TIME_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1687 MASTER LE NN 272214 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__NSW_DEAD_TIME_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1688 MASTER LE NN 271161 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1689 MASTER LE NN 271159 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1690 MASTER LE NN 271163 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1691 MASTER LE NN 271166 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1692 MASTER LE NN 271164 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1693 MASTER LE NN 271187 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_buck_en_del1_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1694 MASTER LE NN 271181 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_en_reg_syn
c_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1695 MASTER LE NN 271183 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_vreg_fault
_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1696 MASTER LE NN 271174 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_vreg_fault
_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1697 MASTER LE NN 271428 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST4_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1698 MASTER LE NN 271620 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C1_CTRL_
reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1699 MASTER LE NN 271432 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST3_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1700 MASTER LE NN 271426 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__DTEST2_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1701 MASTER LE NN 271421 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__ATEST2_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1702 MASTER LE NN 271431 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST3_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1703 MASTER LE NN 271425 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__DTEST2_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1704 MASTER LE NN 271422 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__ATEST2_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1705 MASTER LE NN 271638 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_RE
FSAMPLE_TIMER_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1706 MASTER LE NN 271636 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_P
S_DLY_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1707 MASTER LE NN 271658 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1708 MASTER LE NN 271679 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1709 MASTER LE NN 271675 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1710 MASTER LE NN 271677 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1711 MASTER LE NN 271765 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1712 MASTER LE NN 271676 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1713 MASTER LE NN 271725 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
 Chain[3] 1714 MASTER LE NN 271724 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1715 MASTER LE NN 271682 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1716 MASTER LE NN 271665 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN1_CF
G_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1717 MASTER LE NN 271717 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1718 MASTER LE NN 271680 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1719 MASTER LE NN 271730 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1720 MASTER LE NN 271535 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1721 MASTER LE NN 271660 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN0
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1722 MASTER LE NN 271731 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1723 MASTER LE NN 271667 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_AWAKE_CF
G_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1724 MASTER LE NN 271684 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1725 MASTER LE NN 271760 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1726 MASTER LE NN 271662 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN2
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1727 MASTER LE NN 271532 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1728 MASTER LE NN 271575 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_2
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1729 MASTER LE NN 271634 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1730 MASTER LE NN 271564 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE3_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1731 MASTER LE NN 271574 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_2
_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1732 MASTER LE NN 271579 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_1
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1733 MASTER LE NN 271486 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_5_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1734 MASTER LE NN 271576 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_2
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1735 MASTER LE NN 271627 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__POWER_
BOOST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1736 MASTER LE NN 271663 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_
AWAKE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1737 MASTER LE NN 271626 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_
reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1738 MASTER LE NN 271718 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1739 MASTER LE NN 271420 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__OPEN_LOOP_TEST_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1740 MASTER LE NN 271716 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1741 MASTER LE NN 271417 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__DTEST1_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1742 MASTER LE NN 271483 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_2_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1743 MASTER LE NN 271419 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__TRIM_CALIB_EN_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1744 MASTER LE NN 271603 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_BUCK_SNS_CTL__SNS_SEL_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1745 MASTER LE NN 271412 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INT_TEST_VAL__VREG_FAULT_INT
_TEST_VAL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1746 MASTER LE NN 271643 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1747 MASTER LE NN 271640 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1748 MASTER LE NN 271496 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_CTRL__SPUR_SQM_EN_reg/d
out_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1749 MASTER LE NN 271642 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1750 MASTER LE NN 271461 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_D
EB_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1751 MASTER LE NN 271459 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_D
EB_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1752 MASTER LE NN 271436 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__WEAK_PD_PWM_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1753 MASTER LE NN 271435 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1754 MASTER LE NN 271438 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1755 MASTER LE NN 271437 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__WEAK_PD_PFM_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1756 MASTER LE NN 271543 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_RANG
E_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1757 MASTER LE NN 271423 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__ATEST2_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1758 MASTER LE NN 271618 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C2_CTRL_
reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1759 MASTER LE NN 271617 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C2_CTRL_
reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1760 MASTER LE NN 271307 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1761 MASTER LE NN 271301 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1762 MASTER LE NN 271455 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/s
ync_u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1763 MASTER LE NN 271456 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/s
ync_u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1764 MASTER LE NN 271458 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_D
EB_sync_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1765 MASTER LE NN 271464 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_D
EB_sync_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1766 MASTER LE NN 271182 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_en_rise_ed
ge_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1767 MASTER LE NN 271158 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1768 MASTER LE NN 271160 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1769 MASTER LE NN 271165 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1770 MASTER LE NN 271157 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1771 MASTER LE NN 271153 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_done
_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1772 MASTER LE NN 271151 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_eq_
vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1773 MASTER LE NN 271005 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1774 MASTER LE NN 271150 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_gt_
vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1775 MASTER LE NN 271149 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_acti
ve_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1776 MASTER LE NN 271148 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_dela
y_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1777 MASTER LE NN 271139 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_dela
y_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1778 MASTER LE NN 270939 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_wake_ps_fsm_reg (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1779 MASTER LE NN 271340 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_disable_awake_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 1780 MASTER LE NN 271189 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1781 MASTER LE NN 271186 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1782 MASTER LE NN 271344 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_refconn_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 1783 MASTER LE NN 271238 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_wake_ctrl_fsm_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1784 MASTER LE NN 271228 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1785 MASTER LE NN 271230 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1786 MASTER LE NN 271227 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1787 MASTER LE NN 271242 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1788 MASTER LE NN 271243 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1789 MASTER LE NN 271226 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1790 MASTER LE NN 271225 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1791 MASTER LE NN 271223 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1792 MASTER LE NN 271222 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1793 MASTER LE NN 272107 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor22_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1794 MASTER LE NN 272103 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1795 MASTER LE NN 272122 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor14_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1796 MASTER LE NN 272121 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1797 MASTER LE NN 272226 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__P_OFF_DRIVER_SIZE_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1798 MASTER LE NN 272218 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__APT_STEPDOWN_NSW_DEAD_TIME
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1799 MASTER LE NN 272199 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1800 MASTER LE NN 272108 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1801 MASTER LE NN 272111 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1802 MASTER LE NN 272123 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor15_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1803 MASTER LE NN 272221 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__N_ON_DRIVER_SIZE_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1804 MASTER LE NN 272240 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PFM_ENTRY_AUTO_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1805 MASTER LE NN 272224 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__P_ON_DRIVER_SIZE_reg/
dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1806 MASTER LE NN 272209 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_BLNK_TIME_CTL__ISNS_BLNK_TIME_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1807 MASTER LE NN 272134 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1808 MASTER LE NN 272195 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1809 MASTER LE NN 272236 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PS_ENTRY_PWM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1810 MASTER LE NN 272222 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__N_OFF_DRIVER_SIZE_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1811 MASTER LE NN 272117 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1812 MASTER LE NN 272116 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1813 MASTER LE NN 272114 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1814 MASTER LE NN 272113 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1815 MASTER LE NN 272110 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1816 MASTER LE NN 270984 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1817 MASTER LE NN 270966 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1818 MASTER LE NN 270983 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1819 MASTER LE NN 271224 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1820 MASTER LE NN 271191 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1821 MASTER LE NN 271234 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1822 MASTER LE NN 271343 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_power_boost_en_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 1823 MASTER LE NN 271231 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_force_wake_ps_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1824 MASTER LE NN 271354 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_wake_ctrl_fsm_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1825 MASTER LE NN 271147 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_dela
y_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1826 MASTER LE NN 271460 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_D
EB_sync_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1827 MASTER LE NN 271324 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1828 MASTER LE NN 271313 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_clear_latch_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1829 MASTER LE NN 271705 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_MAX_OFFSET_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1830 MASTER LE NN 271706 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_MAX_OFFSET_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1831 MASTER LE NN 271707 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_RESERVED_HROOM_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1832 MASTER LE NN 271701 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P2_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1833 MASTER LE NN 271434 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INT_TEST1__INT_TEST_MODE_EN_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1834 MASTER LE NN 271693 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_RES_HROOM_VSET_TRAN_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1835 MASTER LE NN 271700 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1836 MASTER LE NN 271433 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INT_TEST1__LEGACY_MODE_EN_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1837 MASTER LE NN 271572 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_3_4__PFM_VTHRES_3
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1838 MASTER LE NN 271708 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_RESERVED_HROOM_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1839 MASTER LE NN 271409 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1840 MASTER LE NN 271623 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1841 MASTER LE NN 271365 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT
_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1842 MASTER LE NN 271755 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1843 MASTER LE NN 271728 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1844 MASTER LE NN 271732 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1845 MASTER LE NN 271726 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1846 MASTER LE NN 271368 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1847 MASTER LE NN 271370 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1848 MASTER LE NN 271369 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1849 MASTER LE NN 271371 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1850 MASTER LE NN 271373 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1851 MASTER LE NN 271360 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1852 MASTER LE NN 271372 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1853 MASTER LE NN 271374 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1854 MASTER LE NN 271485 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_4_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1855 MASTER LE NN 271488 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_7_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1856 MASTER LE NN 271762 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1857 MASTER LE NN 271367 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL2__GANG_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1858 MASTER LE NN 271625 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_
reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1859 MASTER LE NN 271624 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1860 MASTER LE NN 271362 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1861 MASTER LE NN 271596 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_DMAX_CTL__DMAX_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1862 MASTER LE NN 271364 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL2__FOLLOW_GLO
BAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1863 MASTER LE NN 271594 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FB_FLT_CFG__FB_RANGE_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1864 MASTER LE NN 271363 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1865 MASTER LE NN 271595 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_DMAX_CTL__DMAX_TIME_SEL_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1866 MASTER LE NN 271696 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_M1_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1867 MASTER LE NN 271695 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_M1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1868 MASTER LE NN 271465 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPDOWN_READY_CTL__VOUT_EQ_
VREF_WAIT_BYPASS_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1869 MASTER LE NN 271704 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_MAX_OFFSET_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1870 MASTER LE NN 271410 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_WAR
M_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1871 MASTER LE NN 271408 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1872 MASTER LE NN 271659 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1873 MASTER LE NN 271439 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__STRONG_PD_EN_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1874 MASTER LE NN 271699 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1875 MASTER LE NN 271570 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_3_4__PFM_VTHRES_3
_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
 Chain[3] 1876 MASTER LE NN 271571 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_3_4__PFM_VTHRES_3
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1877 MASTER LE NN 271569 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_3_4__PFM_VTHRES_3
_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1878 MASTER LE NN 271694 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1879 MASTER LE NN 271703 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_MAX_OFFSET_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1880 MASTER LE NN 271697 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P4_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1881 MASTER LE NN 271689 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_SAMPLE_CTL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1882 MASTER LE NN 271690 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_SAMPLE_CTL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1883 MASTER LE NN 271454 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/d
tmp_reg (M31_1P5V6T_SFFRSBQX1)
Chain[3] 1884 MASTER LE NN 271688 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_SAMPLE_CTL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1885 MASTER LE NN 271306 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1886 MASTER LE NN 271305 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1887 MASTER LE NN 271304 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1888 MASTER LE NN 271323 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1889 MASTER LE NN 271303 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1890 MASTER LE NN 271302 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1891 MASTER LE NN 271462 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_D
EB_sync_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1892 MASTER LE NN 271179 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_slib_sync_
cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1893 MASTER LE NN 271180 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_slib_sync_
cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1894 MASTER LE NN 271156 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[10
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1895 MASTER LE NN 270948 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1896 MASTER LE NN 270963 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_incr
_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1897 MASTER LE NN 271152 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_acti
ve_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1898 MASTER LE NN 271146 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_dela
y_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1899 MASTER LE NN 271237 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/slib_clkreq_gate_1p0_hf_clk_u1/clk_en
_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1900 MASTER LE NN 271218 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_refdac_sample_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1901 MASTER LE NN 271342 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_enable_toggle_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 1902 MASTER LE NN 271219 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_wake_ctrl_fsm_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1903 MASTER LE NN 271236 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_curr_state_hf_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1904 MASTER LE NN 271239 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1905 MASTER LE NN 271240 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1906 MASTER LE NN 271241 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1907 MASTER LE NN 271192 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1908 MASTER LE NN 270989 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1909 MASTER LE NN 272128 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor20_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1910 MASTER LE NN 272106 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1911 MASTER LE NN 272115 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1912 MASTER LE NN 272118 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1913 MASTER LE NN 272225 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__P_ON_DRIVER_SIZE_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1914 MASTER LE NN 272217 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__APT_STEPDOWN_PSW_DEAD_TIME
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1915 MASTER LE NN 272213 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__PSW_DEAD_TIME_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1916 MASTER LE NN 272196 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1917 MASTER LE NN 272243 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PFM_ENTRY_AUTO_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1918 MASTER LE NN 272216 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__APT_STEPDOWN_PSW_DEAD_TIME
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1919 MASTER LE NN 272197 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1920 MASTER LE NN 272242 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PFM_ENTRY_AUTO_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1921 MASTER LE NN 272220 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__N_ON_DRIVER_SIZE_reg/
dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1922 MASTER LE NN 272212 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__PSW_DEAD_TIME_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1923 MASTER LE NN 272192 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1924 MASTER LE NN 272133 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1925 MASTER LE NN 272239 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PS_ENTRY_PWM_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1926 MASTER LE NN 272204 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DIG_FSM_CTL__FSM_LAT_DIS_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1927 MASTER LE NN 272132 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 1928 MASTER LE NN 271767 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1929 MASTER LE NN 270987 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1930 MASTER LE NN 270967 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1931 MASTER LE NN 270965 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1932 MASTER LE NN 271235 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_curr_state_hf_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1933 MASTER LE NN 271244 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_curr_state_hf_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1934 MASTER LE NN 271339 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_wake_ctrl_fsm_reg (M31_1P5V6T_SFFSBQX1)
 Chain[3] 1935 MASTER LE NN 271003 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_st
epper_meta_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1936 MASTER LE NN 270945 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1937 MASTER LE NN 270944 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1938 MASTER LE NN 271000 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1939 MASTER LE NN 271752 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1940 MASTER LE NN 270993 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1941 MASTER LE NN 270995 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1942 MASTER LE NN 270998 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1943 MASTER LE NN 270991 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[10] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1944 MASTER LE NN 270996 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1945 MASTER LE NN 270990 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[11] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1946 MASTER LE NN 270941 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[10] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1947 MASTER LE NN 270940 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[11] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1948 MASTER LE NN 270942 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[9] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1949 MASTER LE NN 271295 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1950 MASTER LE NN 271297 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1951 MASTER LE NN 271298 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1952 MASTER LE NN 271310 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1953 MASTER LE NN 271253 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync7/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1954 MASTER LE NN 271254 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync7/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1955 MASTER LE NN 271250 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1956 MASTER LE NN 271249 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1957 MASTER LE NN 271258 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync9/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1958 MASTER LE NN 271268 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1959 MASTER LE NN 271280 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync6/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1960 MASTER LE NN 271255 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync8/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1961 MASTER LE NN 271259 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync9/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1962 MASTER LE NN 271281 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync6/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1963 MASTER LE NN 271261 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync10/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1964 MASTER LE NN 271267 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1965 MASTER LE NN 271266 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1966 MASTER LE NN 271265 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 1967 MASTER LE NN 271270 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1968 MASTER LE NN 271269 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1969 MASTER LE NN 271311 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1970 MASTER LE NN 271247 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1971 MASTER LE NN 271248 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1972 MASTER LE NN 271309 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_calc_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1973 MASTER LE NN 271300 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_load_flag_sync_b_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1974 MASTER LE NN 271299 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_load_flag_sync_b_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1975 MASTER LE NN 270994 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1976 MASTER LE NN 270997 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1977 MASTER LE NN 270950 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1978 MASTER LE NN 270992 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[9] (M31_1P5V6T_SFFSRBQX1)
 Chain[3] 1979 MASTER LE NN 270999 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1980 MASTER LE NN 271296 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1981 MASTER LE NN 271319 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_4_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 1982 MASTER LE NN 271764 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1983 MASTER LE NN 271723 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1984 MASTER LE NN 271721 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1985 MASTER LE NN 271719 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1986 MASTER LE NN 271757 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1987 MASTER LE NN 271766 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1988 MASTER LE NN 271758 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1989 MASTER LE NN 271686 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1990 MASTER LE NN 271683 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1991 MASTER LE NN 271768 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1992 MASTER LE NN 271756 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1993 MASTER LE NN 271361 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_LOCKBIT_D1_write_once_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 1994 MASTER LE NN 271366 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL1__ENABLE_PRE
SET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1995 MASTER LE NN 271702 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1996 MASTER LE NN 271668 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_EN_CTL__PERPH_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 1997 MASTER LE NN 271691 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_DEC_DELAY_CTL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1998 MASTER LE NN 271698 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 1999 MASTER LE NN 271692 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_DEC_DELAY_CTL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2000 MASTER LE NN 271709 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_RESERVED_HROOM_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2001 MASTER LE NN 271320 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_5_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2002 MASTER LE NN 271318 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_3_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2003 MASTER LE NN 271317 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_2_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2004 MASTER LE NN 271312 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_1_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2005 MASTER LE NN 271316 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2006 MASTER LE NN 271315 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2007 MASTER LE NN 271308 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2008 MASTER LE NN 271327 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2009 MASTER LE NN 271326 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2010 MASTER LE NN 271753 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2011 MASTER LE NN 271325 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2012 MASTER LE NN 271322 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2013 MASTER LE NN 271321 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2014 MASTER LE NN 270951 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2015 MASTER LE NN 270949 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2016 MASTER LE NN 270943 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2017 MASTER LE NN 270947 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2018 MASTER LE NN 270946 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2019 MASTER LE NN 271004 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_st
epper_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2020 MASTER LE NN 271233 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2021 MASTER LE NN 271353 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2022 MASTER LE NN 271352 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_a2d_comp_out_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 2023 MASTER LE NN 270964 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2024 MASTER LE NN 271216 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_comp_out_sync1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2025 MASTER LE NN 271358 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_comp_out_capture1_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 2026 MASTER LE NN 271220 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_curr_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2027 MASTER LE NN 271221 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_curr_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2028 MASTER LE NN 271171 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2029 MASTER LE NN 271172 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2030 MASTER LE NN 270969 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2031 MASTER LE NN 270968 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2032 MASTER LE NN 270986 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2033 MASTER LE NN 270988 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2034 MASTER LE NN 270985 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2035 MASTER LE NN 272112 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2036 MASTER LE NN 272126 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor18_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2037 MASTER LE NN 272125 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor17_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2038 MASTER LE NN 272127 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor19_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2039 MASTER LE NN 272223 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__N_OFF_DRIVER_SIZE_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2040 MASTER LE NN 272219 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__APT_STEPDOWN_NSW_DEAD_TIME
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2041 MASTER LE NN 272227 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__P_OFF_DRIVER_SIZE_reg
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2042 MASTER LE NN 272194 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2043 MASTER LE NN 272237 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PS_ENTRY_PWM_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2044 MASTER LE NN 272198 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2045 MASTER LE NN 272241 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PFM_ENTRY_AUTO_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2046 MASTER LE NN 272193 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2047 MASTER LE NN 272238 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PS_ENTRY_PWM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2048 MASTER LE NN 271285 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2049 MASTER LE NN 271283 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_error_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2050 MASTER LE NN 271282 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_clear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2051 MASTER LE NN 271278 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_s
tate_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2052 MASTER LE NN 271290 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_s
tate_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2053 MASTER LE NN 271292 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2054 MASTER LE NN 271275 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2055 MASTER LE NN 271263 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_sta
te_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2056 MASTER LE NN 271252 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync11/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2057 MASTER LE NN 271279 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2058 MASTER LE NN 271251 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync11/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2059 MASTER LE NN 271346 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vset_valid_sync_reg
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2060 MASTER LE NN 271345 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vset_valid_sync_first_reg
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2061 MASTER LE NN 271257 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_error_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2062 MASTER LE NN 271256 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync8/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2063 MASTER LE NN 271260 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2064 MASTER LE NN 271262 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync10/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2065 MASTER LE NN 271291 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2066 MASTER LE NN 271273 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_sta
te_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2067 MASTER LE NN 271274 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2068 MASTER LE NN 271264 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_sta
te_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2069 MASTER LE NN 271272 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2070 MASTER LE NN 271271 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2071 MASTER LE NN 271347 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2072 MASTER LE NN 271733 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_s
tate_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2073 MASTER LE NN 271284 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_clear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2074 MASTER LE NN 271277 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2075 MASTER LE NN 271276 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2076 MASTER LE NN 271348 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2077 MASTER LE NN 271288 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2078 MASTER LE NN 271286 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2079 MASTER LE NN 271287 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2080 MASTER LE NN 271289 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2081 MASTER LE NN 270938 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2082 MASTER LE NN 270915 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[3]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2083 MASTER LE NN 272109 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2084 MASTER LE NN 272119 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2085 MASTER LE NN 272120 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[3]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2086 MASTER LE NN 270193 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[2][2]
(M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256422 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/LO
CKUP1 (M31_1P5V6T_LOWLATCHX1)
Chain[3] 2087 MASTER LE NN 270201 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[4][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2088 MASTER LE NN 270206 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2089 MASTER LE NN 270159 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2090 MASTER LE NN 270157 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2091 MASTER LE NN 270204 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2092 MASTER LE NN 270203 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2093 MASTER LE NN 270202 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2094 MASTER LE NN 270150 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/fsm_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2095 MASTER LE NN 270158 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2096 MASTER LE NN 270160 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2097 MASTER LE NN 270152 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2098 MASTER LE NN 270156 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2099 MASTER LE NN 270283 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_dela
y_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2100 MASTER LE NN 270276 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_dela
y_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2101 MASTER LE NN 270067 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor22_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2102 MASTER LE NN 270052 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2103 MASTER LE NN 270065 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor20_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2104 MASTER LE NN 270069 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor24_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2105 MASTER LE NN 270060 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor15_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2106 MASTER LE NN 270059 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor14_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2107 MASTER LE NN 270064 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor19_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2108 MASTER LE NN 270043 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2109 MASTER LE NN 270044 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor29_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2110 MASTER LE NN 270073 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor28_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2111 MASTER LE NN 270284 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_dela
y_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2112 MASTER LE NN 270285 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_dela
y_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2113 MASTER LE NN 270154 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2114 MASTER LE NN 270155 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2115 MASTER LE NN 270153 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2116 MASTER LE NN 270151 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2117 MASTER LE NN 270149 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/fsm_state_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2118 MASTER LE NN 270161 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/fsm_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2119 MASTER LE NN 270162 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2120 MASTER LE NN 270144 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/fsm_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2121 MASTER LE NN 270170 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2122 MASTER LE NN 270277 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2123 MASTER LE NN 270045 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2124 MASTER LE NN 270041 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2125 MASTER LE NN 270062 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor17_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2126 MASTER LE NN 270042 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2127 MASTER LE NN 270039 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
 Chain[3] 2128 MASTER LE NN 270053 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2129 MASTER LE NN 270056 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2130 MASTER LE NN 270058 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2131 MASTER LE NN 270048 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2132 MASTER LE NN 270063 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor18_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2133 MASTER LE NN 270040 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2134 MASTER LE NN 270066 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor21_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2135 MASTER LE NN 270071 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor26_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2136 MASTER LE NN 270068 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor23_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2137 MASTER LE NN 270070 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor25_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2138 MASTER LE NN 270055 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2139 MASTER LE NN 270061 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor16_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2140 MASTER LE NN 270049 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2141 MASTER LE NN 270072 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor27_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2142 MASTER LE NN 270051 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2143 MASTER LE NN 270047 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2144 MASTER LE NN 270046 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2145 MASTER LE NN 270057 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2146 MASTER LE NN 270280 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2147 MASTER LE NN 270282 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2148 MASTER LE NN 270281 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2149 MASTER LE NN 270279 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2150 MASTER LE NN 270140 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2151 MASTER LE NN 270136 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2152 MASTER LE NN 270287 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_gt_
vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2153 MASTER LE NN 270278 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2154 MASTER LE NN 270286 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_acti
ve_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2155 MASTER LE NN 270168 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2156 MASTER LE NN 270166 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2157 MASTER LE NN 270164 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2158 MASTER LE NN 270143 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/slib_sync_trimout_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2159 MASTER LE NN 270142 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/slib_sync_trimout_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2160 MASTER LE NN 270205 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2161 MASTER LE NN 270208 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2162 MASTER LE NN 270207 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2163 MASTER LE NN 270145 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/cal_request_reset_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2164 MASTER LE NN 270184 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2165 MASTER LE NN 270183 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2166 MASTER LE NN 270196 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[3][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2167 MASTER LE NN 270894 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2168 MASTER LE NN 270182 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2169 MASTER LE NN 270197 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[3][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2170 MASTER LE NN 270200 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[4][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2171 MASTER LE NN 270198 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[3][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2172 MASTER LE NN 270199 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[4][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2173 MASTER LE NN 270786 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__MODE_SEL_DLY_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2174 MASTER LE NN 270790 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__AUTO_RANGE_CO
MP_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2175 MASTER LE NN 270518 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2176 MASTER LE NN 270575 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__PWM_RAMP_PE
AK_TRIM_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2177 MASTER LE NN 270188 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2178 MASTER LE NN 270742 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2179 MASTER LE NN 270578 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__ERR_AMP_TRI
M_CAL_EN_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2180 MASTER LE NN 270787 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__PFM_PWM_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2181 MASTER LE NN 270743 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2182 MASTER LE NN 270739 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2183 MASTER LE NN 270517 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2184 MASTER LE NN 270576 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__VDIP_COMP_T
RIM_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2185 MASTER LE NN 270514 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2186 MASTER LE NN 270744 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2187 MASTER LE NN 270515 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2188 MASTER LE NN 270577 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__PFM_COMP_TR
IM_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2189 MASTER LE NN 270516 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2190 MASTER LE NN 270169 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2191 MASTER LE NN 270570 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2192 MASTER LE NN 270304 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2193 MASTER LE NN 270678 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_RANG
E_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2194 MASTER LE NN 270511 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2195 MASTER LE NN 270512 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2196 MASTER LE NN 270513 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2197 MASTER LE NN 270566 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST3_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2198 MASTER LE NN 270564 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST4_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2199 MASTER LE NN 270567 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST3_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2200 MASTER LE NN 270891 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__PWM_THRES_T
RIM_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2201 MASTER LE NN 270565 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST3_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2202 MASTER LE NN 270788 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__PFM_PWM_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2203 MASTER LE NN 270525 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2204 MASTER LE NN 270535 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2205 MASTER LE NN 270521 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2206 MASTER LE NN 270520 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2207 MASTER LE NN 270529 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2208 MASTER LE NN 270534 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2209 MASTER LE NN 270526 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2210 MASTER LE NN 270522 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2211 MASTER LE NN 270187 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2212 MASTER LE NN 270539 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2213 MASTER LE NN 270536 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2214 MASTER LE NN 270538 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2215 MASTER LE NN 270192 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2216 MASTER LE NN 270537 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2217 MASTER LE NN 270890 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__TRIM_CAL_EN
G_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2218 MASTER LE NN 270473 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[4][3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2219 MASTER LE NN 270471 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[2][3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2220 MASTER LE NN 270195 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[2][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2221 MASTER LE NN 270194 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[2][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2222 MASTER LE NN 270472 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[3][3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2223 MASTER LE NN 270470 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2224 MASTER LE NN 270469 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2225 MASTER LE NN 270189 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2226 MASTER LE NN 270185 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2227 MASTER LE NN 270190 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2228 MASTER LE NN 270186 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2229 MASTER LE NN 270298 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2230 MASTER LE NN 270191 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2231 MASTER LE NN 270533 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2232 MASTER LE NN 270530 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2233 MASTER LE NN 270896 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2234 MASTER LE NN 270747 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2235 MASTER LE NN 270532 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2236 MASTER LE NN 270749 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2237 MASTER LE NN 270531 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2238 MASTER LE NN 270745 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2239 MASTER LE NN 270748 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2240 MASTER LE NN 270750 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2241 MASTER LE NN 270527 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2242 MASTER LE NN 270524 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[5] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 2243 MASTER LE NN 270519 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2244 MASTER LE NN 270528 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2245 MASTER LE NN 270746 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2246 MASTER LE NN 270523 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2247 MASTER LE NN 270735 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2248 MASTER LE NN 270732 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2249 MASTER LE NN 270733 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2250 MASTER LE NN 270789 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__PWM_PFM_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2251 MASTER LE NN 270785 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__MODE_SEL_DLY_
reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2252 MASTER LE NN 270731 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2253 MASTER LE NN 270736 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__FOLLOW_F
REQ_CTL_LOGIC_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2254 MASTER LE NN 270752 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C2_CTRL_
reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2255 MASTER LE NN 270734 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2256 MASTER LE NN 270753 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C1_CTRL_
reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2257 MASTER LE NN 270751 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C2_CTRL_
reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2258 MASTER LE NN 270756 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C1_CTRL_
reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2259 MASTER LE NN 270755 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C1_CTRL_
reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2260 MASTER LE NN 270557 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__ATEST2_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2261 MASTER LE NN 270558 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__ATEST2_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2262 MASTER LE NN 270754 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C1_CTRL_
reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2263 MASTER LE NN 270562 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST4_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2264 MASTER LE NN 270560 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__DTEST2_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2265 MASTER LE NN 270561 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__DTEST2_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2266 MASTER LE NN 270556 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__ATEST2_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2267 MASTER LE NN 270563 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST4_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2268 MASTER LE NN 270682 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_ILOA
D_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2269 MASTER LE NN 270559 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__DTEST2_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2270 MASTER LE NN 270681 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_ILOA
D_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2271 MASTER LE NN 270305 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 2272 MASTER LE NN 270296 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2273 MASTER LE NN 270299 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2274 MASTER LE NN 270683 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_ILOA
D_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2275 MASTER LE NN 270306 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2276 MASTER LE NN 270679 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_METHOD_ST
EPPER_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2277 MASTER LE NN 270680 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_ILOA
D_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2278 MASTER LE NN 270300 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2279 MASTER LE NN 270294 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2280 MASTER LE NN 270292 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2281 MASTER LE NN 270302 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2282 MASTER LE NN 270301 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2283 MASTER LE NN 270694 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PULSE_SKIP_CTL__PS_TIME_HYST
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2284 MASTER LE NN 270573 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2285 MASTER LE NN 270695 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PULSE_SKIP_CTL__PS_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX3)
Chain[3] 2286 MASTER LE NN 270572 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__WEAK_PD_PFM_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2287 MASTER LE NN 270693 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PULSE_SKIP_CTL__PS_TIME_HYST
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2288 MASTER LE NN 270171 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2289 MASTER LE NN 270346 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2290 MASTER LE NN 270738 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2291 MASTER LE NN 270541 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM1__PWM_THRES_TRIM_re
g/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2292 MASTER LE NN 270741 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2293 MASTER LE NN 270898 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_IPLIM_CTRL_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2294 MASTER LE NN 270725 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_COMP_HYST_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2295 MASTER LE NN 270718 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_COMP_PLS_FL
TR_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2296 MASTER LE NN 270724 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_COMP_PLS_FLTR_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2297 MASTER LE NN 270674 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_VRST_RANGE
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2298 MASTER LE NN 270740 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2299 MASTER LE NN 270671 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_VRST_reg/d
out_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2300 MASTER LE NN 270542 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM1__PWM_THRES_TRIM_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2301 MASTER LE NN 270540 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM1__PWM_THRES_TRIM_re
g/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2302 MASTER LE NN 270252 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2303 MASTER LE NN 270893 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM1__PWM_THRES_TRIM_re
g/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2304 MASTER LE NN 270345 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2305 MASTER LE NN 270601 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2306 MASTER LE NN 270606 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__VREGOK_BYP_FOLDBACK_EN_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2307 MASTER LE NN 270803 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/
dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2308 MASTER LE NN 270251 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2309 MASTER LE NN 270250 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2310 MASTER LE NN 270717 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_IPLIM_CTRL_
reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2311 MASTER LE NN 270722 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__SPARE_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2312 MASTER LE NN 270715 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__SPARE_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 2313 MASTER LE NN 270673 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_VRST_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2314 MASTER LE NN 270723 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__SPARE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2315 MASTER LE NN 270727 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_VOLT_CTL_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2316 MASTER LE NN 270721 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_VOLT_CTL_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2317 MASTER LE NN 270172 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2318 MASTER LE NN 270180 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2319 MASTER LE NN 270255 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2320 MASTER LE NN 270860 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2321 MASTER LE NN 270256 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2322 MASTER LE NN 270728 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FB_FLT_CFG__FB_RANGE_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2323 MASTER LE NN 270550 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__ATEST1_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2324 MASTER LE NN 270719 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_COMP_HYST_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2325 MASTER LE NN 270677 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_MODE_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2326 MASTER LE NN 270720 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_IBOOST_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2327 MASTER LE NN 270676 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_FOLLOW_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2328 MASTER LE NN 270716 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__SPARE_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2329 MASTER LE NN 270726 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_IBOOST_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2330 MASTER LE NN 270675 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_METHOD_reg
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2331 MASTER LE NN 270672 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_VRST_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2332 MASTER LE NN 270249 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2333 MASTER LE NN 270546 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INT_TEST_VAL__VREG_ACK_INT_T
EST_VAL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2334 MASTER LE NN 270547 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INT_TEST_VAL__VREG_FAULT_INT
_TEST_VAL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2335 MASTER LE NN 270805 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_re
g/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2336 MASTER LE NN 270804 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2337 MASTER LE NN 270802 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/
dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2338 MASTER LE NN 270165 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2339 MASTER LE NN 270163 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2340 MASTER LE NN 270600 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2341 MASTER LE NN 270692 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PULSE_SKIP_CTL__PS_METHOD_re
g/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2342 MASTER LE NN 270347 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2343 MASTER LE NN 270181 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/d_cal_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2344 MASTER LE NN 270233 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2345 MASTER LE NN 270231 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2346 MASTER LE NN 270167 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2347 MASTER LE NN 270241 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_ready_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2348 MASTER LE NN 270235 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2349 MASTER LE NN 270229 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2350 MASTER LE NN 270603 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2351 MASTER LE NN 270602 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_r
eg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2352 MASTER LE NN 270237 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2353 MASTER LE NN 270291 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_STEPPER_DONE_d_stepper_done_pbuf_fla
g_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2354 MASTER LE NN 270242 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_mode_decoder_u1/d_ps_true_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2355 MASTER LE NN 270141 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_cal_comp_state_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2356 MASTER LE NN 270146 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_cal_request_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 2357 MASTER LE NN 270293 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[10
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2358 MASTER LE NN 270297 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2359 MASTER LE NN 270604 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__FOLDBACK_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2360 MASTER LE NN 270311 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_vreg_fault
_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2361 MASTER LE NN 270485 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_mode_decoder_u1/d_mode_state_flag_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2362 MASTER LE NN 270849 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2363 MASTER LE NN 270850 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_VS_CTL__VS_STEPPER_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2364 MASTER LE NN 270239 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2365 MASTER LE NN 270848 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2366 MASTER LE NN 270468 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2367 MASTER LE NN 270807 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_re
g/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2368 MASTER LE NN 270227 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2369 MASTER LE NN 270806 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_re
g/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2370 MASTER LE NN 270632 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_CTRL__SPUR_FSM_EN_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2371 MASTER LE NN 270862 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2372 MASTER LE NN 270858 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2373 MASTER LE NN 270737 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_BUCK_SNS_CTL__SNS_SEL_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2374 MASTER LE NN 270729 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_DMAX_CTL__DMAX_TIME_SEL_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2375 MASTER LE NN 270706 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_3_4__PFM_VTHRES_3
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2376 MASTER LE NN 270571 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__WEAK_PD_PWM_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2377 MASTER LE NN 270595 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_D
EB_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2378 MASTER LE NN 270486 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_mode_decoder_u1/d_mode_state_flag_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2379 MASTER LE NN 270593 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_D
EB_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2380 MASTER LE NN 270591 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_D
EB_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2381 MASTER LE NN 270329 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/d_vr
eg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2382 MASTER LE NN 270774 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2383 MASTER LE NN 270605 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__OCP_LATCH_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2384 MASTER LE NN 270348 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2385 MASTER LE NN 270852 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
 Chain[3] 2386 MASTER LE NN 270853 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_SS_CTL__SS_STEPPER_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2387 MASTER LE NN 270137 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_int_soft_sta
rt_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2388 MASTER LE NN 270295 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2389 MASTER LE NN 270290 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_done
_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2390 MASTER LE NN 270303 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2391 MASTER LE NN 270288 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_eq_
vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2392 MASTER LE NN 270289 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_acti
ve_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2393 MASTER LE NN 270097 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_incr
_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2394 MASTER LE NN 270430 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pfm_count_logic_u1/d_d2a_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2395 MASTER LE NN 270429 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pfm_count_logic_u1/d_sync_flop_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2396 MASTER LE NN 270309 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/d_vr
eg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2397 MASTER LE NN 270851 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2398 MASTER LE NN 270636 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_TIMER__SQM_TIMER_SEL_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 2399 MASTER LE NN 270637 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_TIMER__WAIT_TIMER_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2400 MASTER LE NN 270638 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_TIMER__WAIT_TIMER_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2401 MASTER LE NN 270382 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_perph_logic_u1/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2402 MASTER LE NN 270381 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_perph_logic_u1/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2403 MASTER LE NN 270597 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_D
EB_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2404 MASTER LE NN 270772 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2405 MASTER LE NN 270776 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2406 MASTER LE NN 270253 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2407 MASTER LE NN 270254 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2408 MASTER LE NN 270579 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__ERR_AMP_TRI
M_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2409 MASTER LE NN 270870 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2410 MASTER LE NN 270811 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2411 MASTER LE NN 270179 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2412 MASTER LE NN 270178 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2413 MASTER LE NN 270902 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2414 MASTER LE NN 270177 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2415 MASTER LE NN 270173 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2416 MASTER LE NN 270617 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_2_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2417 MASTER LE NN 270616 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_1_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2418 MASTER LE NN 270552 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__DTEST1_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2419 MASTER LE NN 270624 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_PS_TIMEOUT_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2420 MASTER LE NN 270615 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_0_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2421 MASTER LE NN 270623 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_ERRAMP_TRIM_
BUF_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2422 MASTER LE NN 270551 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__DTEST1_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2423 MASTER LE NN 270627 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_PRECH_EXTEND
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2424 MASTER LE NN 270618 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_3_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2425 MASTER LE NN 270553 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__DTEST1_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX2J)
Chain[3] 2426 MASTER LE NN 270548 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__ATEST1_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2427 MASTER LE NN 270630 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__SPARE_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2428 MASTER LE NN 270175 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2429 MASTER LE NN 270628 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__EN_PWM_TRAN_ASSI
ST_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2430 MASTER LE NN 270688 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PREC
HG_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2431 MASTER LE NN 270174 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2432 MASTER LE NN 270621 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_6_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2433 MASTER LE NN 270629 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_RETENTION_MO
DE_DLY_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2434 MASTER LE NN 270176 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2435 MASTER LE NN 270549 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__ATEST1_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2436 MASTER LE NN 270555 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__OPEN_LOOP_TEST_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2437 MASTER LE NN 270685 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PSKI
P_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2438 MASTER LE NN 270757 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2439 MASTER LE NN 270791 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2440 MASTER LE NN 270703 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_3_4__PFM_VTHRES_3
_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2441 MASTER LE NN 270901 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2442 MASTER LE NN 270758 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_
reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2443 MASTER LE NN 270792 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2444 MASTER LE NN 270502 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL1__ENABLE_PRE
SET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2445 MASTER LE NN 270501 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT
_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2446 MASTER LE NN 270499 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2447 MASTER LE NN 270705 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_3_4__PFM_VTHRES_3
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2448 MASTER LE NN 270730 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_DMAX_CTL__DMAX_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2449 MASTER LE NN 270775 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2450 MASTER LE NN 270263 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_d2a_pfm_high_sel_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2451 MASTER LE NN 270631 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_CTRL__SPUR_SQM_EN_reg/d
out_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2452 MASTER LE NN 270574 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__STRONG_PD_EN_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2453 MASTER LE NN 270544 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2454 MASTER LE NN 270773 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2455 MASTER LE NN 270545 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_WAR
M_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2456 MASTER LE NN 270599 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPDOWN_READY_CTL__VOUT_EQ_
VREF_WAIT_BYPASS_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2457 MASTER LE NN 270855 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
 Chain[3] 2458 MASTER LE NN 270148 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/cal_request_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2459 MASTER LE NN 270635 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FILTER_COEF__SPUR_FILTE
R_COEF_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX2J)
Chain[3] 2460 MASTER LE NN 270310 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_vreg_fault
_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2461 MASTER LE NN 270487 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_logic_rb_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2462 MASTER LE NN 270139 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_st
epper_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2463 MASTER LE NN 270768 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_P
S_DLY_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2464 MASTER LE NN 270588 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/d
tmp_reg (M31_1P5V6T_SFFRSBQX1)
Chain[3] 2465 MASTER LE NN 270324 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_buck_en_del2_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2466 MASTER LE NN 270771 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_RE
FSAMPLE_TIMER_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2467 MASTER LE NN 270323 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_buck_en_del1_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2468 MASTER LE NN 270769 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_P
S_DLY_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2469 MASTER LE NN 270759 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_
reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2470 MASTER LE NN 270770 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_RE
FSAMPLE_TIMER_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2471 MASTER LE NN 270634 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FILTER_COEF__SPUR_FILTE
R_COEF_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2472 MASTER LE NN 270590 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/s
ync_u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2473 MASTER LE NN 270489 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2474 MASTER LE NN 270315 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_slib_sync_
cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2475 MASTER LE NN 270321 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2476 MASTER LE NN 270275 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_sqm_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2477 MASTER LE NN 270322 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2478 MASTER LE NN 270104 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2479 MASTER LE NN 270106 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_fb_count_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2480 MASTER LE NN 270109 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_d2a_fb_cnt_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2481 MASTER LE NN 270314 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/slib_sync_u2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2482 MASTER LE NN 270105 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_fb_count_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2483 MASTER LE NN 270107 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_fb_count_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2484 MASTER LE NN 270226 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2485 MASTER LE NN 270465 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2486 MASTER LE NN 270113 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2487 MASTER LE NN 270112 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2488 MASTER LE NN 270108 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_fb_count_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2489 MASTER LE NN 270467 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2490 MASTER LE NN 270232 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2491 MASTER LE NN 270234 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2492 MASTER LE NN 270230 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2493 MASTER LE NN 270236 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2494 MASTER LE NN 270238 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2495 MASTER LE NN 270224 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2496 MASTER LE NN 270222 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2497 MASTER LE NN 270225 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2498 MASTER LE NN 270220 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2499 MASTER LE NN 270228 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2500 MASTER LE NN 270111 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2501 MASTER LE NN 270110 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 2502 MASTER LE NN 270116 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2503 MASTER LE NN 270464 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2504 MASTER LE NN 270326 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2505 MASTER LE NN 270325 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2506 MASTER LE NN 270320 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/slib_clkreq_gate_1p0_clk_u1/clk_en_sy
nc_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2507 MASTER LE NN 270316 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_slib_sync_
cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2508 MASTER LE NN 270317 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_en_reg_syn
c_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2509 MASTER LE NN 270313 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/slib_sync_u2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2510 MASTER LE NN 270318 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_en_rise_ed
ge_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2511 MASTER LE NN 270319 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_vreg_fault
_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2512 MASTER LE NN 270349 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2513 MASTER LE NN 270138 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_st
epper_meta_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2514 MASTER LE NN 270312 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_dig_glue_u1/slib_clkreq_gate_1p0_clk_u1/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2515 MASTER LE NN 270147 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/slib_clkreq_gate_1p0_clk_cal_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2516 MASTER LE NN 270497 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_LOCKBIT_D1_write_once_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2517 MASTER LE NN 270543 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2518 MASTER LE NN 270500 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL2__FOLLOW_GLO
BAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2519 MASTER LE NN 270498 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2520 MASTER LE NN 270837 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2521 MASTER LE NN 270835 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P4_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2522 MASTER LE NN 270689 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PREC
HG_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2523 MASTER LE NN 270625 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_CLAMP_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2524 MASTER LE NN 270684 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PSKI
P_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2525 MASTER LE NN 270626 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_FORCE_PWM_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2526 MASTER LE NN 270554 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__TRIM_CALIB_EN_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2527 MASTER LE NN 270687 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__SPARE1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2528 MASTER LE NN 270833 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_M1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2529 MASTER LE NN 270696 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE4_
reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2530 MASTER LE NN 270834 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_M1_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2531 MASTER LE NN 270686 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PSKI
P_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2532 MASTER LE NN 270691 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__SPARE0_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2533 MASTER LE NN 270900 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE4_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2534 MASTER LE NN 270690 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PREC
HG_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2535 MASTER LE NN 270700 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE2_
reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2536 MASTER LE NN 270701 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE1_
reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2537 MASTER LE NN 270622 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_7_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2538 MASTER LE NN 270619 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_4_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2539 MASTER LE NN 270620 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_5_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2540 MASTER LE NN 270702 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE1_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2541 MASTER LE NN 270713 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_1
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2542 MASTER LE NN 270712 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_1
_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2543 MASTER LE NN 270842 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_MAX_OFFSET_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2544 MASTER LE NN 270698 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE3_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2545 MASTER LE NN 270841 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_MAX_OFFSET_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 2546 MASTER LE NN 270697 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE3_
reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2547 MASTER LE NN 270707 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_2
_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2548 MASTER LE NN 270708 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_2
_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2549 MASTER LE NN 270699 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE2_
reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2550 MASTER LE NN 270760 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__POWER_
BOOST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2551 MASTER LE NN 270582 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2552 MASTER LE NN 270763 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2553 MASTER LE NN 270587 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2554 MASTER LE NN 270781 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2555 MASTER LE NN 270585 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2556 MASTER LE NN 270584 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2557 MASTER LE NN 270610 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_3_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2558 MASTER LE NN 270609 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_2_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2559 MASTER LE NN 270710 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_2
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2560 MASTER LE NN 270612 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_5_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2561 MASTER LE NN 270714 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_1
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2562 MASTER LE NN 270583 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2563 MASTER LE NN 270581 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2564 MASTER LE NN 270762 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2565 MASTER LE NN 270613 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_6_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2566 MASTER LE NN 270780 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2567 MASTER LE NN 270764 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2568 MASTER LE NN 270766 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2569 MASTER LE NN 270779 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2570 MASTER LE NN 270778 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2571 MASTER LE NN 270704 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_3_4__PFM_VTHRES_3
_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2572 MASTER LE NN 270765 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2573 MASTER LE NN 270649 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2574 MASTER LE NN 270784 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WID
TH_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2575 MASTER LE NN 270796 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_
AWAKE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2576 MASTER LE NN 270589 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/s
ync_u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2577 MASTER LE NN 270592 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_D
EB_sync_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2578 MASTER LE NN 270365 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2579 MASTER LE NN 270369 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2580 MASTER LE NN 270363 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2581 MASTER LE NN 270366 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2582 MASTER LE NN 270354 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_refdac_sample_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2583 MASTER LE NN 270367 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_force_wake_ps_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2584 MASTER LE NN 270356 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_curr_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2585 MASTER LE NN 270360 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2586 MASTER LE NN 270267 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2587 MASTER LE NN 270262 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_curr_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2588 MASTER LE NN 270370 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2589 MASTER LE NN 270371 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_curr_state_hf_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2590 MASTER LE NN 270361 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2591 MASTER LE NN 270357 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_curr_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2592 MASTER LE NN 270355 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_wake_ctrl_fsm_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2593 MASTER LE NN 270374 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_wake_ctrl_fsm_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2594 MASTER LE NN 270478 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_enable_toggle_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 2595 MASTER LE NN 270480 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_refconn_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 2596 MASTER LE NN 270479 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_power_boost_en_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 2597 MASTER LE NN 270115 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2598 MASTER LE NN 270114 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2599 MASTER LE NN 270378 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2600 MASTER LE NN 270466 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2601 MASTER LE NN 270218 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2602 MASTER LE NN 270219 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2603 MASTER LE NN 270223 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2604 MASTER LE NN 270221 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 2605 MASTER LE NN 270212 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2606 MASTER LE NN 270213 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2607 MASTER LE NN 270240 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_pwm_meas_ready_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2608 MASTER LE NN 270217 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_first_pass_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2609 MASTER LE NN 270377 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2610 MASTER LE NN 270210 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2611 MASTER LE NN 270209 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2612 MASTER LE NN 270211 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2613 MASTER LE NN 270272 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2614 MASTER LE NN 270274 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2615 MASTER LE NN 270214 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2616 MASTER LE NN 270215 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2617 MASTER LE NN 270216 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2618 MASTER LE NN 270379 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2619 MASTER LE NN 270376 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2620 MASTER LE NN 270375 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2621 MASTER LE NN 270372 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_curr_state_hf_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2622 MASTER LE NN 270380 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_curr_state_hf_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2623 MASTER LE NN 270475 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_wake_ctrl_fsm_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 2624 MASTER LE NN 270074 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_wake_ps_fsm_reg (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2625 MASTER LE NN 270476 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_disable_awake_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 2626 MASTER LE NN 270490 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_wake_ctrl_fsm_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2627 MASTER LE NN 270364 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2628 MASTER LE NN 270373 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/slib_clkreq_gate_1p0_hf_clk_u1/clk_en
_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2629 MASTER LE NN 270594 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_D
EB_sync_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2630 MASTER LE NN 270598 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_D
EB_sync_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2631 MASTER LE NN 270596 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_D
EB_sync_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2632 MASTER LE NN 270633 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FILTER_COEF__SPUR_FILTE
R_COEF_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2633 MASTER LE NN 270568 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INT_TEST1__LEGACY_MODE_EN_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2634 MASTER LE NN 270801 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_EN_CTL__PERPH_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2635 MASTER LE NN 270569 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INT_TEST1__INT_TEST_MODE_EN_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2636 MASTER LE NN 270643 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2637 MASTER LE NN 270648 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2638 MASTER LE NN 270656 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2639 MASTER LE NN 270666 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2640 MASTER LE NN 270651 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2641 MASTER LE NN 270650 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2642 MASTER LE NN 270647 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2643 MASTER LE NN 270824 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2644 MASTER LE NN 270777 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2645 MASTER LE NN 270782 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WID
TH_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2646 MASTER LE NN 270783 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WID
TH_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2647 MASTER LE NN 270761 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2648 MASTER LE NN 270586 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2649 MASTER LE NN 270767 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2650 MASTER LE NN 270709 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_2
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2651 MASTER LE NN 270711 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_1
_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2652 MASTER LE NN 270580 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2653 MASTER LE NN 270903 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2654 MASTER LE NN 270307 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2655 MASTER LE NN 270308 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2656 MASTER LE NN 270327 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2657 MASTER LE NN 270099 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2658 MASTER LE NN 270494 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_comp_out_capture1_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 2659 MASTER LE NN 270352 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_comp_out_sync1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2660 MASTER LE NN 270488 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_a2d_comp_out_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2661 MASTER LE NN 270362 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2662 MASTER LE NN 270261 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_curr_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2663 MASTER LE NN 270243 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/slib_clkreq_gate_1p0_clk_u1/clk_en_sy
nc_reg (M31_1P5V6T_SFFRBQX1)
 Chain[3] 2664 MASTER LE NN 270087 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2665 MASTER LE NN 270095 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2666 MASTER LE NN 270096 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2667 MASTER LE NN 270342 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2668 MASTER LE NN 270344 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2669 MASTER LE NN 270247 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_data_ready_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2670 MASTER LE NN 270246 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2671 MASTER LE NN 270336 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2672 MASTER LE NN 270248 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2673 MASTER LE NN 270265 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2674 MASTER LE NN 270245 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2675 MASTER LE NN 270244 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2676 MASTER LE NN 270273 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2677 MASTER LE NN 270270 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2678 MASTER LE NN 270271 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2679 MASTER LE NN 270266 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2680 MASTER LE NN 270268 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2681 MASTER LE NN 270269 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_timer_u1/d_tim
er_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2682 MASTER LE NN 270260 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_wait_timer_start_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2683 MASTER LE NN 270264 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_sqm_timer_start_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2684 MASTER LE NN 270259 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_curr_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2685 MASTER LE NN 270258 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2686 MASTER LE NN 270257 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2687 MASTER LE NN 270359 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2688 MASTER LE NN 270358 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2689 MASTER LE NN 270123 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2690 MASTER LE NN 270119 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2691 MASTER LE NN 270118 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2692 MASTER LE NN 270328 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2693 MASTER LE NN 270100 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2694 MASTER LE NN 270117 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2695 MASTER LE NN 270122 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2696 MASTER LE NN 270101 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2697 MASTER LE NN 270102 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2698 MASTER LE NN 270098 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2699 MASTER LE NN 270103 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2700 MASTER LE NN 270663 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2701 MASTER LE NN 270660 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2702 MASTER LE NN 270868 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2703 MASTER LE NN 270667 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2704 MASTER LE NN 270856 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2705 MASTER LE NN 270800 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_AWAKE_CF
G_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2706 MASTER LE NN 270822 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2707 MASTER LE NN 270845 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_RESERVED_HROOM_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2708 MASTER LE NN 270828 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_SAMPLE_CTL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2709 MASTER LE NN 270844 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_MAX_OFFSET_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2710 MASTER LE NN 270827 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_SAMPLE_CTL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2711 MASTER LE NN 270843 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_MAX_OFFSET_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2712 MASTER LE NN 270839 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P2_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2713 MASTER LE NN 270836 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2714 MASTER LE NN 270840 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2715 MASTER LE NN 270503 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL2__GANG_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2716 MASTER LE NN 270639 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2717 MASTER LE NN 270611 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_4_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2718 MASTER LE NN 270642 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2719 MASTER LE NN 270614 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_7_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2720 MASTER LE NN 270640 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2721 MASTER LE NN 270799 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN2_CF
G_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2722 MASTER LE NN 270645 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 2723 MASTER LE NN 270658 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2724 MASTER LE NN 270816 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2725 MASTER LE NN 270797 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN0_CF
G_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2726 MASTER LE NN 270659 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2727 MASTER LE NN 270795 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN2
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2728 MASTER LE NN 270809 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2729 MASTER LE NN 270872 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2730 MASTER LE NN 270798 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN1_CF
G_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2731 MASTER LE NN 270820 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2732 MASTER LE NN 270664 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2733 MASTER LE NN 270814 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2734 MASTER LE NN 270866 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2735 MASTER LE NN 270818 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2736 MASTER LE NN 270854 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2737 MASTER LE NN 270808 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2738 MASTER LE NN 270794 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN1
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2739 MASTER LE NN 270669 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2740 MASTER LE NN 270670 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2741 MASTER LE NN 270793 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN0
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2742 MASTER LE NN 270665 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2743 MASTER LE NN 270864 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2744 MASTER LE NN 270857 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2745 MASTER LE NN 270810 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2746 MASTER LE NN 270668 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2747 MASTER LE NN 270655 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2748 MASTER LE NN 270662 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2749 MASTER LE NN 270657 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2750 MASTER LE NN 270641 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2751 MASTER LE NN 270654 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2752 MASTER LE NN 270652 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2753 MASTER LE NN 270644 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2754 MASTER LE NN 270653 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2755 MASTER LE NN 270661 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2756 MASTER LE NN 270646 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2757 MASTER LE NN 270607 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_0_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2758 MASTER LE NN 270608 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_1_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2759 MASTER LE NN 270899 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2760 MASTER LE NN 270813 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2761 MASTER LE NN 270831 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_RES_HROOM_VSET_TRAN_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2762 MASTER LE NN 270832 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2763 MASTER LE NN 270838 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2764 MASTER LE NN 270846 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_RESERVED_HROOM_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2765 MASTER LE NN 270830 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_DEC_DELAY_CTL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2766 MASTER LE NN 270829 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_DEC_DELAY_CTL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2767 MASTER LE NN 270847 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_RESERVED_HROOM_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2768 MASTER LE NN 270510 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2769 MASTER LE NN 270506 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2770 MASTER LE NN 270507 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2771 MASTER LE NN 270505 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2772 MASTER LE NN 270504 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2773 MASTER LE NN 270897 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2774 MASTER LE NN 270092 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2775 MASTER LE NN 270093 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2776 MASTER LE NN 270331 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/u_slib_sync_1p0_freq_data_ready/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2777 MASTER LE NN 270333 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_data_ready_hf_sync_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2778 MASTER LE NN 270334 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_grey_counter_capture_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2779 MASTER LE NN 270332 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/u_slib_sync_1p0_freq_data_ready/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2780 MASTER LE NN 270335 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2781 MASTER LE NN 270339 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[2] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 2782 MASTER LE NN 270341 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2783 MASTER LE NN 270350 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_data_ready_hf_sync_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2784 MASTER LE NN 270094 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2785 MASTER LE NN 270337 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2786 MASTER LE NN 270340 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2787 MASTER LE NN 270338 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync2_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2788 MASTER LE NN 270343 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_freq_capture_grey_sync1_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2789 MASTER LE NN 270089 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2790 MASTER LE NN 270091 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2791 MASTER LE NN 270088 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2792 MASTER LE NN 270090 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_fr
eq_det_filter_sum_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2793 MASTER LE NN 270120 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2794 MASTER LE NN 270121 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2795 MASTER LE NN 270386 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2796 MASTER LE NN 270385 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2797 MASTER LE NN 270873 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2798 MASTER LE NN 270397 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync10/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2799 MASTER LE NN 270871 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2800 MASTER LE NN 270865 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2801 MASTER LE NN 270869 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2802 MASTER LE NN 270867 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2803 MASTER LE NN 270892 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2804 MASTER LE NN 270823 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2805 MASTER LE NN 270825 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2806 MASTER LE NN 270826 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_SAMPLE_CTL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2807 MASTER LE NN 270496 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2808 MASTER LE NN 270509 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2809 MASTER LE NN 270508 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2810 MASTER LE NN 270456 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_5_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2811 MASTER LE NN 270455 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_4_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2812 MASTER LE NN 270454 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_3_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2813 MASTER LE NN 270441 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2814 MASTER LE NN 270442 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2815 MASTER LE NN 270460 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2816 MASTER LE NN 270458 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2817 MASTER LE NN 270461 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2818 MASTER LE NN 270130 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2819 MASTER LE NN 270462 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2820 MASTER LE NN 270459 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2821 MASTER LE NN 270452 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2822 MASTER LE NN 270821 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2823 MASTER LE NN 270819 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2824 MASTER LE NN 270127 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2825 MASTER LE NN 270131 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2826 MASTER LE NN 270128 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2827 MASTER LE NN 270457 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2828 MASTER LE NN 270129 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2829 MASTER LE NN 270085 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2830 MASTER LE NN 270431 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2831 MASTER LE NN 270075 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[11] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2832 MASTER LE NN 270077 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[9] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2833 MASTER LE NN 270433 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2834 MASTER LE NN 270080 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2835 MASTER LE NN 270415 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2836 MASTER LE NN 270427 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2837 MASTER LE NN 270416 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync6/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2838 MASTER LE NN 270406 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2839 MASTER LE NN 270391 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync8/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2840 MASTER LE NN 270390 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync7/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 2841 MASTER LE NN 270389 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync7/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2842 MASTER LE NN 270398 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync10/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2843 MASTER LE NN 270405 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2844 MASTER LE NN 270402 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2845 MASTER LE NN 270403 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2846 MASTER LE NN 270388 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync11/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2847 MASTER LE NN 270481 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vset_valid_sync_first_reg
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2848 MASTER LE NN 270383 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2849 MASTER LE NN 270482 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vset_valid_sync_reg
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2850 MASTER LE NN 270421 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2851 MASTER LE NN 270400 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_sta
te_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2852 MASTER LE NN 270401 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2853 MASTER LE NN 270404 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2854 MASTER LE NN 270392 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync8/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2855 MASTER LE NN 270394 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync9/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2856 MASTER LE NN 270330 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/slib_clkreq_gate_1p0_hf_clk_u1/clk_en
_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2857 MASTER LE NN 270395 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync9/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2858 MASTER LE NN 270393 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_error_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2859 MASTER LE NN 270396 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2860 MASTER LE NN 270410 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2861 MASTER LE NN 270399 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_sta
te_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2862 MASTER LE NN 270407 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2863 MASTER LE NN 270408 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2864 MASTER LE NN 270412 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2865 MASTER LE NN 270413 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2866 MASTER LE NN 270423 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2867 MASTER LE NN 270483 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2868 MASTER LE NN 270419 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_error_req_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2869 MASTER LE NN 270418 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_clear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2870 MASTER LE NN 270411 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2871 MASTER LE NN 270409 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_sta
te_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2872 MASTER LE NN 270417 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync6/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2873 MASTER LE NN 270387 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync11/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2874 MASTER LE NN 270076 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[10] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2875 MASTER LE NN 270863 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2876 MASTER LE NN 270861 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2877 MASTER LE NN 270859 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2878 MASTER LE NN 270436 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_load_flag_sync_b_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2879 MASTER LE NN 270435 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_load_flag_sync_b_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2880 MASTER LE NN 270133 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2881 MASTER LE NN 270817 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2882 MASTER LE NN 270815 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2883 MASTER LE NN 270812 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2884 MASTER LE NN 270125 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[10] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2885 MASTER LE NN 270451 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2886 MASTER LE NN 270449 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_clear_latch_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2887 MASTER LE NN 270453 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_2_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2888 MASTER LE NN 270437 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2889 MASTER LE NN 270448 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_1_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2890 MASTER LE NN 270444 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2891 MASTER LE NN 270439 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2892 MASTER LE NN 270440 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2893 MASTER LE NN 272102 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__P_ON_DRIVER_SIZE_reg/
dout_reg[1] (M31_1P5V6T_SFFRBQX2)
Chain[3] 2894 MASTER LE NN 272048 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__APT_STEPDOWN_PSW_DEAD_TIME
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2895 MASTER LE NN 272057 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__P_OFF_DRIVER_SIZE_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2896 MASTER LE NN 272051 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__APT_STEPDOWN_NSW_DEAD_TIME
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2897 MASTER LE NN 272058 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__P_OFF_DRIVER_SIZE_reg
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2898 MASTER LE NN 272072 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PFM_ENTRY_AUTO_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2899 MASTER LE NN 272031 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 2900 MASTER LE NN 272071 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PFM_ENTRY_AUTO_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2901 MASTER LE NN 272069 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PS_ENTRY_PWM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2902 MASTER LE NN 272026 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2903 MASTER LE NN 272032 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2904 MASTER LE NN 272056 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__P_ON_DRIVER_SIZE_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2905 MASTER LE NN 272030 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2906 MASTER LE NN 272028 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2907 MASTER LE NN 272073 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PFM_ENTRY_AUTO_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2908 MASTER LE NN 272074 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PFM_ENTRY_AUTO_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2909 MASTER LE NN 272029 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2910 MASTER LE NN 272067 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PS_ENTRY_PWM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2911 MASTER LE NN 272027 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2912 MASTER LE NN 272068 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PS_ENTRY_PWM_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2913 MASTER LE NN 272053 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__N_ON_DRIVER_SIZE_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2914 MASTER LE NN 272045 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__PSW_DEAD_TIME_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2915 MASTER LE NN 272088 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_PWM_SEL_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2916 MASTER LE NN 272080 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_PFM_SEL_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2917 MASTER LE NN 272091 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_PWM_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2918 MASTER LE NN 272090 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_PWM_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2919 MASTER LE NN 272010 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST3_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2920 MASTER LE NN 272043 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_BLNK_TIME_CTL__MIN_PON_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2921 MASTER LE NN 272009 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST3_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2922 MASTER LE NN 272019 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST4__ECM_INPUT_MUX_CTRL_reg/dout
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2923 MASTER LE NN 272012 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST4_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2924 MASTER LE NN 272016 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST4__ECM_TEST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2925 MASTER LE NN 271964 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_core/hfs_ps_trim_logic/d_l2r_cal_comp_state_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2926 MASTER LE NN 272014 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__EN_SENSE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2927 MASTER LE NN 272011 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST4_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2928 MASTER LE NN 272006 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__IPLIM_TEST_CTRL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2929 MASTER LE NN 272004 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__DTEST2_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2930 MASTER LE NN 272063 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_QM_PS_ENTRY__QMODE_PS_ENTRY_reg/dout_reg[3
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2931 MASTER LE NN 271994 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__ATEST1_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2932 MASTER LE NN 272061 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_SWITCH_SIZE_CTL__P_SWITCH_SIZE_reg/dout_re
g[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2933 MASTER LE NN 272041 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_BLNK_TIME_CTL__ISNS_BLNK_TIME_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2934 MASTER LE NN 272039 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_INZERO_CTL__INZERO_OFFSET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2935 MASTER LE NN 272062 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_SWITCH_SIZE_CTL__P_SWITCH_SIZE_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2936 MASTER LE NN 272002 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__ATEST2_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2937 MASTER LE NN 272087 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_RET_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2938 MASTER LE NN 272084 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_RET_SEL_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2939 MASTER LE NN 272086 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_RET_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2940 MASTER LE NN 272095 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_AUTOINT_S
EL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2941 MASTER LE NN 272085 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_RET_SEL_r
eg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2942 MASTER LE NN 272092 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_AUTOINT_S
EL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2943 MASTER LE NN 272081 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_PFM_SEL_r
eg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2944 MASTER LE NN 272089 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_PWM_SEL_r
eg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2945 MASTER LE NN 272082 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_PFM_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2946 MASTER LE NN 272083 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_RET_PFM_CURRENT_LIM__CURRENT_LIM_PFM_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 2947 MASTER LE NN 272054 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__N_OFF_DRIVER_SIZE_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2948 MASTER LE NN 272055 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__N_OFF_DRIVER_SIZE_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2949 MASTER LE NN 270445 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_calc_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2950 MASTER LE NN 270438 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2951 MASTER LE NN 270447 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2952 MASTER LE NN 270432 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2953 MASTER LE NN 270443 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2954 MASTER LE NN 270463 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2955 MASTER LE NN 270895 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2956 MASTER LE NN 270126 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[9] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2957 MASTER LE NN 270124 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[11] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2958 MASTER LE NN 270134 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2959 MASTER LE NN 270135 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2960 MASTER LE NN 270132 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2961 MASTER LE NN 270084 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2962 MASTER LE NN 270082 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2963 MASTER LE NN 270446 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2964 MASTER LE NN 270081 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2965 MASTER LE NN 270434 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2966 MASTER LE NN 270414 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_s
tate_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2967 MASTER LE NN 270420 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_clear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2968 MASTER LE NN 270428 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2969 MASTER LE NN 270484 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 2970 MASTER LE NN 270424 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2971 MASTER LE NN 270425 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2972 MASTER LE NN 270422 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_v
reg_fault_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2973 MASTER LE NN 270426 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_s
tate_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 2974 MASTER LE NN 270874 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_fault_fsm/d_s
tate_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 2975 MASTER LE NN 270384 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 2976 MASTER LE NN 270078 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2977 MASTER LE NN 270083 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2978 MASTER LE NN 270079 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2979 MASTER LE NN 270086 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_ahc_adj_vset_syn
c/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 2980 MASTER LE NN 271960 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor20_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2981 MASTER LE NN 271956 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor16_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2982 MASTER LE NN 271957 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor17_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2983 MASTER LE NN 271963 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_core/hfs_ps_pwm_curr_lim_logic_u1/switch_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2984 MASTER LE NN 271938 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2985 MASTER LE NN 271936 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2986 MASTER LE NN 271947 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2987 MASTER LE NN 271946 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2988 MASTER LE NN 271941 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2989 MASTER LE NN 271944 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2990 MASTER LE NN 271943 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2991 MASTER LE NN 271939 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2992 MASTER LE NN 271937 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2993 MASTER LE NN 271945 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2994 MASTER LE NN 271940 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor22_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2995 MASTER LE NN 271961 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor21_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2996 MASTER LE NN 271955 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor15_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2997 MASTER LE NN 271950 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2998 MASTER LE NN 271953 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 2999 MASTER LE NN 271954 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor14_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3000 MASTER LE NN 272059 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_SWITCH_SIZE_CTL__N_SWITCH_SIZE_reg/dout_re
g[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3001 MASTER LE NN 272042 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_BLNK_TIME_CTL__MIN_PON_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3002 MASTER LE NN 272093 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_AUTOINT_S
EL_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3003 MASTER LE NN 272094 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWM_CURRENT_LIM_CTL__CURRENT_LIM_AUTOINT_S
EL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3004 MASTER LE NN 272001 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__ATEST2_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3005 MASTER LE NN 272017 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST4__ECM_INPUT_MUX_CTRL_reg/dout
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3006 MASTER LE NN 272005 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__DTEST2_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3007 MASTER LE NN 272008 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST3_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3008 MASTER LE NN 272013 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__DTEST4_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3009 MASTER LE NN 272046 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__NSW_DEAD_TIME_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3010 MASTER LE NN 272047 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__NSW_DEAD_TIME_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3011 MASTER LE NN 272052 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DRIVER_STRENGTH_CTL__N_ON_DRIVER_SIZE_reg/
dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3012 MASTER LE NN 272050 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__APT_STEPDOWN_NSW_DEAD_TIME
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3013 MASTER LE NN 271962 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3014 MASTER LE NN 271949 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3015 MASTER LE NN 271948 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3016 MASTER LE NN 271958 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor18_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3017 MASTER LE NN 271959 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor19_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3018 MASTER LE NN 272036 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CAL_EN_CTL1__IPLIM_TRIM_CAL_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3019 MASTER LE NN 272060 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_SWITCH_SIZE_CTL__N_SWITCH_SIZE_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3020 MASTER LE NN 272038 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_INZERO_CTL__INZERO_OFFSET_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3021 MASTER LE NN 272065 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_QM_PS_ENTRY__QMODE_PS_ENTRY_reg/dout_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3022 MASTER LE NN 272066 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_QM_PS_ENTRY__QMODE_PS_ENTRY_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3023 MASTER LE NN 271987 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3024 MASTER LE NN 271969 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3025 MASTER LE NN 272049 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__APT_STEPDOWN_PSW_DEAD_TIME
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3026 MASTER LE NN 272070 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ISNS_THRES__PS_ENTRY_PWM_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3027 MASTER LE NN 272044 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DEAD_TIME_CTRL__PSW_DEAD_TIME_reg/dout_reg
[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3028 MASTER LE NN 271966 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3029 MASTER LE NN 272025 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_MISC__SPARE_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3030 MASTER LE NN 271988 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3031 MASTER LE NN 271989 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3032 MASTER LE NN 272076 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ILIM_SS_CTL__ILIM_SS_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 3033 MASTER LE NN 271992 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_FORCE_FET_TEST__FORCE_PFET_NFET_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3034 MASTER LE NN 272024 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__AFSM_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3035 MASTER LE NN 272023 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__ILIM_DLY_SEL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3036 MASTER LE NN 272097 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_CURRENT_LIM_CTRL_
SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3037 MASTER LE NN 272075 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ILIM_SS_CTL__ILIM_SS_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 3038 MASTER LE NN 272021 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__ILIM_DLY_SEL_reg/dout_re
g[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3039 MASTER LE NN 272096 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_CURRENT_LIM_CTRL_
SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3040 MASTER LE NN 272020 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__ILIM_DLY_SEL_reg/dout_re
g[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3041 MASTER LE NN 272022 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_AFSM_CTL__ILIM_DLY_SEL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3042 MASTER LE NN 272078 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ILIM_SS_CTL__ILIM_SS_SEL_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 3043 MASTER LE NN 272099 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_CURRENT_LIM_CTRL_
SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3044 MASTER LE NN 272100 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_IPLIM_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3045 MASTER LE NN 271982 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM1__PWM_IPLIM_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3046 MASTER LE NN 271971 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM4__PFM_IPLIM_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3047 MASTER LE NN 271984 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM1__PWM_IPLIM_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3048 MASTER LE NN 271973 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM4__PFM_IPLIM_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3049 MASTER LE NN 272077 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_ILIM_SS_CTL__ILIM_SS_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[3] 3050 MASTER LE NN 271970 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM4__PFM_IPLIM_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3051 MASTER LE NN 272098 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_NEG_CURRENT_LIM_CTL__NEG_CURRENT_LIM_CTRL_
SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3052 MASTER LE NN 271972 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM4__PFM_IPLIM_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3053 MASTER LE NN 272007 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__IPLIM_TEST_CTRL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 3054 MASTER LE NN 272000 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__ATEST2_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3055 MASTER LE NN 272018 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST4__ECM_INPUT_MUX_CTRL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3056 MASTER LE NN 271993 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__ATEST1_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3057 MASTER LE NN 271991 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_FORCE_FET_TEST__FORCE_PFET_NFET_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3058 MASTER LE NN 271990 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_FORCE_FET_TEST__KELVIN_SENSING_TEST_EN_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3059 MASTER LE NN 271985 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM1__PWM_IPLIM_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3060 MASTER LE NN 271997 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__DTEST1_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3061 MASTER LE NN 271980 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM2__INZERO_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3062 MASTER LE NN 271974 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM3__AUTO_THRS_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3063 MASTER LE NN 271978 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM2__INZERO_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3064 MASTER LE NN 271977 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM3__AUTO_THRS_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3065 MASTER LE NN 271981 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM2__INZERO_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3066 MASTER LE NN 271979 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM2__INZERO_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3067 MASTER LE NN 271983 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM1__PWM_IPLIM_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3068 MASTER LE NN 271976 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM3__AUTO_THRS_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3069 MASTER LE NN 271998 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__DTEST1_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3070 MASTER LE NN 271996 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__DTEST1_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3071 MASTER LE NN 271999 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__OPEN_LOOP_TEST_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3072 MASTER LE NN 271975 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PS_TRIM3__AUTO_THRS_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3073 MASTER LE NN 272040 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_INZERO_CTL__INZERO_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3074 MASTER LE NN 271995 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST1__ATEST1_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3075 MASTER LE NN 272037 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_INZERO_CTL__INZERO_FORCE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3076 MASTER LE NN 272035 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CAL_EN_CTL1__AUTO_THRES_TRIM_CAL_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3077 MASTER LE NN 272034 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CAL_EN_CTL1__INZERO_TRIM_CAL_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3078 MASTER LE NN 272033 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CAL_EN_CTL1__INLIM_TRIM_CAL_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3079 MASTER LE NN 272003 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST2__DTEST2_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3080 MASTER LE NN 272064 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_QM_PS_ENTRY__QMODE_PS_ENTRY_reg/dout_reg[2
] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3081 MASTER LE NN 272079 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_CURRENT_LIM_CTL__RET_PFM_PWM_CURRENT_LIM_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3082 MASTER LE NN 272015 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PWR_STG_TEST3__EN_ADC_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3083 MASTER LE NN 271986 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3084 MASTER LE NN 271968 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_re
g/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3085 MASTER LE NN 272101 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_DIG_FSM_CTL__FSM_LAT_DIS_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX2)
Chain[3] 3086 MASTER LE NN 271967 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3087 MASTER LE NN 271965 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/\u_hfs_ps_
dig_csr/u_hfs_ps_rif_wrap/u_hfs_ps_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3088 MASTER LE NN 270054 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3089 MASTER LE NN 270050 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[2]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3090 MASTER LE NN 271942 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3091 MASTER LE NN 271952 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3092 MASTER LE NN 271951 + GPIO_07
I_DCORE/\hfs_ps_rmod_gen[2]_u_hfs_ps_rmod/u_hfs_ps_rdig/u_hfs_ps_dig_mod/u_hfs_ps_d
ig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3093 MASTER LE NN 269343 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[6]
(M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256360 - GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/LO
CKUP2 (M31_1P5V6T_LOWLATCHX1)
Chain[3] 3094 MASTER LE NN 269344 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3095 MASTER LE NN 269248 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3096 MASTER LE NN 269249 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3097 MASTER LE NN 269250 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3098 MASTER LE NN 269246 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3099 MASTER LE NN 269251 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3100 MASTER LE NN 269245 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3101 MASTER LE NN 269243 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_fb_count_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3102 MASTER LE NN 269240 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_fb_count_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3103 MASTER LE NN 269241 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_fb_count_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3104 MASTER LE NN 269244 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_d2a_fb_cnt_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3105 MASTER LE NN 269601 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3106 MASTER LE NN 269368 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3107 MASTER LE NN 269372 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3108 MASTER LE NN 269599 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3109 MASTER LE NN 269600 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3110 MASTER LE NN 269242 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_fb_count_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3111 MASTER LE NN 269352 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3112 MASTER LE NN 269353 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3113 MASTER LE NN 269374 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_pwm_meas_ready_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3114 MASTER LE NN 269247 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3115 MASTER LE NN 269350 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3116 MASTER LE NN 269349 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3117 MASTER LE NN 269351 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_first_pass_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3118 MASTER LE NN 269355 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3119 MASTER LE NN 269357 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3120 MASTER LE NN 269348 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3121 MASTER LE NN 269345 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3122 MASTER LE NN 269346 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3123 MASTER LE NN 269347 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_sample_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3124 MASTER LE NN 269356 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3125 MASTER LE NN 269358 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3126 MASTER LE NN 269354 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3127 MASTER LE NN 269359 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_meas_cnt_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3128 MASTER LE NN 269366 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3129 MASTER LE NN 269364 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3130 MASTER LE NN 269370 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3131 MASTER LE NN 269505 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3132 MASTER LE NN 269360 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3133 MASTER LE NN 269496 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3134 MASTER LE NN 269362 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_time_spend_pwm_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3135 MASTER LE NN 269598 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3136 MASTER LE NN 269449 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/slib_sync_u2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3137 MASTER LE NN 269461 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3138 MASTER LE NN 269455 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/slib_clkreq_gate_1p0_clk_u1/clk_en_sy
nc_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3139 MASTER LE NN 269622 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_a2d_comp_out_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3140 MASTER LE NN 269487 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_comp_out_sync1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3141 MASTER LE NN 269456 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3142 MASTER LE NN 269457 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 3143 MASTER LE NN 269460 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3144 MASTER LE NN 269239 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_vreg_fault
_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3145 MASTER LE NN 269448 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/slib_sync_u2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3146 MASTER LE NN 269494 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3147 MASTER LE NN 269495 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3148 MASTER LE NN 269493 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3149 MASTER LE NN 269501 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3150 MASTER LE NN 269490 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_wake_ctrl_fsm_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3151 MASTER LE NN 269491 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_curr_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3152 MASTER LE NN 269492 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_curr_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3153 MASTER LE NN 269628 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_comp_out_capture1_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 3154 MASTER LE NN 269489 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_refdac_sample_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3155 MASTER LE NN 269515 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_curr_state_hf_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3156 MASTER LE NN 269610 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_disable_awake_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 3157 MASTER LE NN 269502 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_force_wake_ps_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3158 MASTER LE NN 269609 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_wake_ctrl_fsm_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 3159 MASTER LE NN 269500 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3160 MASTER LE NN 269497 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3161 MASTER LE NN 269513 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3162 MASTER LE NN 269514 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3163 MASTER LE NN 269512 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3164 MASTER LE NN 269511 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3165 MASTER LE NN 269498 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3166 MASTER LE NN 269510 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_hf_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3167 MASTER LE NN 269499 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ctrl
_fsm_u1/d_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3168 MASTER LE NN 269507 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_curr_state_hf_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3169 MASTER LE NN 269506 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_curr_state_hf_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3170 MASTER LE NN 269509 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_wake_ctrl_fsm_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3171 MASTER LE NN 269612 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_enable_toggle_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 3172 MASTER LE NN 269614 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_refconn_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 3173 MASTER LE NN 269624 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_wake_ctrl_fsm_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3174 MASTER LE NN 269504 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/u_slib_sync_1p0_en/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3175 MASTER LE NN 269623 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/u_slib_sync_1p0_en/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3176 MASTER LE NN 269613 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_power_boost_en_reg (M31_1P5V6T_SFFSBQX1)
Chain[3] 3177 MASTER LE NN 269209 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/reg_retention_logic_1p0_dig_wake_ps_f
sm_u1/d_wake_ps_fsm_reg (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3178 MASTER LE NN 269508 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ret_mode_logic_u1/slib_clkreq_gate_1p0_hf_clk_u1/clk_en
_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3179 MASTER LE NN 269564 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pfm_count_logic_u1/d_d2a_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3180 MASTER LE NN 269563 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pfm_count_logic_u1/d_sync_flop_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3181 MASTER LE NN 269174 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp4_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3182 MASTER LE NN 269176 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3183 MASTER LE NN 269175 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3184 MASTER LE NN 269201 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor22_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3185 MASTER LE NN 269178 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3186 MASTER LE NN 269196 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor17_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3187 MASTER LE NN 269181 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3188 MASTER LE NN 269207 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor28_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3189 MASTER LE NN 269183 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3190 MASTER LE NN 269270 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3191 MASTER LE NN 269412 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3192 MASTER LE NN 269273 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3193 MASTER LE NN 269413 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3194 MASTER LE NN 269414 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3195 MASTER LE NN 269415 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3196 MASTER LE NN 269410 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_dela
y_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3197 MASTER LE NN 269189 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3198 MASTER LE NN 269206 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor27_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3199 MASTER LE NN 269205 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor26_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3200 MASTER LE NN 269186 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3201 MASTER LE NN 269190 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3202 MASTER LE NN 269182 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3203 MASTER LE NN 269179 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor29_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3204 MASTER LE NN 269195 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor16_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3205 MASTER LE NN 269194 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor15_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3206 MASTER LE NN 269192 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor13_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3207 MASTER LE NN 269200 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor21_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3208 MASTER LE NN 269193 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor14_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3209 MASTER LE NN 269191 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor12_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3210 MASTER LE NN 269199 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor20_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3211 MASTER LE NN 269198 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor19_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3212 MASTER LE NN 269197 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor18_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3213 MASTER LE NN 269203 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor24_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3214 MASTER LE NN 269202 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor23_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3215 MASTER LE NN 269204 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor25_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3216 MASTER LE NN 269188 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3217 MASTER LE NN 269417 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_dela
y_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3218 MASTER LE NN 269419 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_dela
y_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3219 MASTER LE NN 269418 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_dela
y_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3220 MASTER LE NN 269303 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3221 MASTER LE NN 269299 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3222 MASTER LE NN 269275 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/slib_sync_trimout_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 3223 MASTER LE NN 269187 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3224 MASTER LE NN 269180 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3225 MASTER LE NN 269184 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3226 MASTER LE NN 269177 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/u_
hfs_ctrl_dig_mod_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3227 MASTER LE NN 269295 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3228 MASTER LE NN 269276 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/slib_sync_trimout_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3229 MASTER LE NN 269301 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3230 MASTER LE NN 269340 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3231 MASTER LE NN 269283 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/fsm_state_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3232 MASTER LE NN 269290 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3233 MASTER LE NN 269338 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3234 MASTER LE NN 269336 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3235 MASTER LE NN 269292 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3236 MASTER LE NN 269282 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/fsm_state_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3237 MASTER LE NN 269294 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/fsm_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3238 MASTER LE NN 269277 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/fsm_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3239 MASTER LE NN 269339 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3240 MASTER LE NN 269342 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3241 MASTER LE NN 269288 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3242 MASTER LE NN 269289 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3243 MASTER LE NN 269285 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3244 MASTER LE NN 269291 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3245 MASTER LE NN 269293 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3246 MASTER LE NN 269284 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3247 MASTER LE NN 269287 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/trim_cal_done_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3248 MASTER LE NN 269286 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/auto_trim_cal_on_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3249 MASTER LE NN 269297 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_status_u1/d_trim_cal_fault_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3250 MASTER LE NN 269341 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3251 MASTER LE NN 269606 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[3][3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3252 MASTER LE NN 269607 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[4][3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3253 MASTER LE NN 269232 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_incr
_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3254 MASTER LE NN 269421 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_gt_
vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3255 MASTER LE NN 269411 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3256 MASTER LE NN 269416 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vgu_u/d_setpoint_int_frac_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3257 MASTER LE NN 269420 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_acti
ve_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3258 MASTER LE NN 270032 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C1_CTRL_
reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3259 MASTER LE NN 269690 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__ATEST2_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3260 MASTER LE NN 269692 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__ATEST2_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3261 MASTER LE NN 269691 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__ATEST2_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3262 MASTER LE NN 269887 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C2_CTRL_
reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3263 MASTER LE NN 269699 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST3_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3264 MASTER LE NN 269696 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST4_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3265 MASTER LE NN 269695 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__DTEST2_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3266 MASTER LE NN 269701 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST3_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3267 MASTER LE NN 269905 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_RE
FSAMPLE_TIMER_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3268 MASTER LE NN 269274 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_cal_comp_state_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3269 MASTER LE NN 269698 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST4_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3270 MASTER LE NN 269444 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/d_vr
eg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3271 MASTER LE NN 269447 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_dig_glue_u1/slib_clkreq_gate_1p0_clk_u1/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3272 MASTER LE NN 269737 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3273 MASTER LE NN 269697 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST4_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3274 MASTER LE NN 269811 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_RANG
E_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3275 MASTER LE NN 269739 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__OCP_LATCH_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3276 MASTER LE NN 269815 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_ILOA
D_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3277 MASTER LE NN 269816 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_ILOA
D_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX3)
Chain[3] 3278 MASTER LE NN 269826 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PULSE_SKIP_CTL__PS_TIME_HYST
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3279 MASTER LE NN 269700 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST3__DTEST3_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 3280 MASTER LE NN 269425 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_STEPPER_DONE_d_stepper_done_pbuf_fla
g_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3281 MASTER LE NN 269828 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PULSE_SKIP_CTL__PS_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3282 MASTER LE NN 269376 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_mode_decoder_u1/d_ps_true_flag_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3283 MASTER LE NN 269369 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3284 MASTER LE NN 269363 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3285 MASTER LE NN 269361 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3286 MASTER LE NN 269602 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3287 MASTER LE NN 269371 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3288 MASTER LE NN 269693 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__DTEST2_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3289 MASTER LE NN 269375 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_ready_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3290 MASTER LE NN 269373 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3291 MASTER LE NN 269906 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_1__RET_RE
FSAMPLE_TIMER_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3292 MASTER LE NN 269827 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PULSE_SKIP_CTL__PS_TIME_HYST
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3293 MASTER LE NN 269694 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST2__DTEST2_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3294 MASTER LE NN 269903 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_P
S_DLY_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1J)
Chain[3] 3295 MASTER LE NN 269620 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_mode_decoder_u1/d_mode_state_flag_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3296 MASTER LE NN 269304 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3297 MASTER LE NN 269920 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__MODE_SEL_DLY_
reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3298 MASTER LE NN 269866 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3299 MASTER LE NN 269924 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__PWM_PFM_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3300 MASTER LE NN 269869 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3301 MASTER LE NN 269665 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3302 MASTER LE NN 269659 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3303 MASTER LE NN 269662 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3304 MASTER LE NN 269660 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3305 MASTER LE NN 269663 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3306 MASTER LE NN 269664 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3307 MASTER LE NN 269871 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__FOLLOW_F
REQ_CTL_LOGIC_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3308 MASTER LE NN 269365 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3309 MASTER LE NN 269300 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3310 MASTER LE NN 269880 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3311 MASTER LE NN 269882 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3312 MASTER LE NN 269883 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3313 MASTER LE NN 269867 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3314 MASTER LE NN 269868 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3315 MASTER LE NN 269870 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_RAMP_AMPLITUDE_CTL__PWM_RAMP
AMPLITUDE_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3316 MASTER LE NN 269881 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3317 MASTER LE NN 269326 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3318 MASTER LE NN 269321 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3319 MASTER LE NN 269884 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3320 MASTER LE NN 269885 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C3_CTL__C3_CTRL_reg
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3321 MASTER LE NN 269886 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C2_CTRL_
reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3322 MASTER LE NN 269890 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C1_CTRL_
reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3323 MASTER LE NN 269888 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C1_CTRL_
reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3324 MASTER LE NN 269889 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_COMP_CAP_C1_C2_CTL__C1_CTRL_
reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3325 MASTER LE NN 269424 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_done
_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3326 MASTER LE NN 269423 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_acti
ve_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3327 MASTER LE NN 269422 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_eq_
vset_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3328 MASTER LE NN 269333 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[4][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3329 MASTER LE NN 269329 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[2][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3330 MASTER LE NN 269334 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[4][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3331 MASTER LE NN 269335 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[4][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3332 MASTER LE NN 269327 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[2][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3333 MASTER LE NN 269330 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[3][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3334 MASTER LE NN 269318 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3335 MASTER LE NN 269316 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3336 MASTER LE NN 269317 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3337 MASTER LE NN 270027 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_cal_config_u1/trim_cal_on_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3338 MASTER LE NN 269605 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[2][3]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3339 MASTER LE NN 269332 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[3][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3340 MASTER LE NN 269328 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[2][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3341 MASTER LE NN 269331 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[3][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3342 MASTER LE NN 269337 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_counter_u1/counter_twos_comp_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3343 MASTER LE NN 269278 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/cal_request_reset_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3344 MASTER LE NN 269325 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3345 MASTER LE NN 269672 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3346 MASTER LE NN 269670 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3347 MASTER LE NN 269604 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3348 MASTER LE NN 269323 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3349 MASTER LE NN 269603 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][4]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3350 MASTER LE NN 269319 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3351 MASTER LE NN 269671 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3352 MASTER LE NN 269324 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[0][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3353 MASTER LE NN 269320 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3354 MASTER LE NN 269669 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3355 MASTER LE NN 269667 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3356 MASTER LE NN 269656 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3357 MASTER LE NN 269322 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_trim_cal_mux_u1/trim_cal_val_array_reg[1][3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3358 MASTER LE NN 269652 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3359 MASTER LE NN 269655 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3360 MASTER LE NN 269654 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3361 MASTER LE NN 269653 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3362 MASTER LE NN 269661 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3363 MASTER LE NN 269657 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3364 MASTER LE NN 269709 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__PWM_RAMP_PE
AK_TRIM_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3365 MASTER LE NN 269710 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__VDIP_COMP_T
RIM_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3366 MASTER LE NN 269651 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM3__VDIP_COMP_TRIM_re
g/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3367 MASTER LE NN 269658 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_MANUAL__MAN_CAL_reg/dout
_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3368 MASTER LE NN 269668 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM2__PFM_COMP_TRIM_reg
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3369 MASTER LE NN 269279 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_cal_request_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3370 MASTER LE NN 269922 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__PFM_PWM_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3371 MASTER LE NN 269921 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__MODE_SEL_DLY_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3372 MASTER LE NN 269735 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__OCP_GLOBAL_BROADCAST_EN
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3373 MASTER LE NN 269736 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__INZERO_WAIT_OCP_TIMER_r
eg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3374 MASTER LE NN 269814 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_ILOA
D_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3375 MASTER LE NN 269619 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_mode_decoder_u1/d_mode_state_flag_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3376 MASTER LE NN 269438 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3377 MASTER LE NN 269432 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3378 MASTER LE NN 270038 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_st
epper_meta_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3379 MASTER LE NN 269272 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_st
epper_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3380 MASTER LE NN 269436 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3381 MASTER LE NN 269437 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3382 MASTER LE NN 269459 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_buck_en_del2_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3383 MASTER LE NN 269426 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3384 MASTER LE NN 269452 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_en_reg_syn
c_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3385 MASTER LE NN 269862 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_VOLT_CTL_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3386 MASTER LE NN 269856 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__SPARE_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3387 MASTER LE NN 269765 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_CTRL__SPUR_SQM_EN_reg/d
out_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3388 MASTER LE NN 269731 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_D
EB_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3389 MASTER LE NN 269727 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_D
EB_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3390 MASTER LE NN 269857 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__SPARE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3391 MASTER LE NN 269985 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3392 MASTER LE NN 269808 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_METHOD_reg
/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3393 MASTER LE NN 269766 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_CTRL__SPUR_FSM_EN_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3394 MASTER LE NN 269427 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[10
] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3395 MASTER LE NN 269429 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3396 MASTER LE NN 269454 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_vreg_fault
_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3397 MASTER LE NN 269621 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_logic_rb_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3398 MASTER LE NN 269428 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3399 MASTER LE NN 269440 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3400 MASTER LE NN 269434 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[3]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 3401 MASTER LE NN 269516 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_perph_logic_u1/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3402 MASTER LE NN 269430 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/reg_voltage_st
epper_1p0_dig_vsu_u/VSET_ROUND_UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_
rnd_up_u/reg_voltage_stepper_1p0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3403 MASTER LE NN 269445 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_vreg_fault
_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3404 MASTER LE NN 269271 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_vcu_u/reg_voltage_stepper_1p0_dig_flags_u/d_int_soft_sta
rt_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3405 MASTER LE NN 269706 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__WEAK_PD_PFM_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3406 MASTER LE NN 269435 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3407 MASTER LE NN 269707 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3408 MASTER LE NN 269517 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_perph_logic_u1/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3409 MASTER LE NN 269441 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3410 MASTER LE NN 269433 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3411 MASTER LE NN 269439 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3412 MASTER LE NN 269458 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/d_buck_en_del1_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3413 MASTER LE NN 269464 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/d_vr
eg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
 Chain[3] 3414 MASTER LE NN 269367 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_pwm_mode_meas_u1/d_l2r_time_spend_pwm_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3415 MASTER LE NN 269302 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3416 MASTER LE NN 269740 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__VREGOK_BYP_FOLDBACK_EN_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3417 MASTER LE NN 269813 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_VRST_ILOA
D_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3418 MASTER LE NN 269812 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRES_ILOAD__PS_METHOD_ST
EPPER_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3419 MASTER LE NN 269738 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__FOLDBACK_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3420 MASTER LE NN 269704 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3421 MASTER LE NN 269446 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_vreg_fault
_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3422 MASTER LE NN 269825 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PULSE_SKIP_CTL__PS_METHOD_re
g/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3423 MASTER LE NN 269852 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_COMP_PLS_FL
TR_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3424 MASTER LE NN 269859 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_COMP_PLS_FLTR_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3425 MASTER LE NN 269772 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_TIMER__WAIT_TIMER_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3426 MASTER LE NN 269851 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_IPLIM_CTRL_
reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3427 MASTER LE NN 269858 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_IPLIM_CTRL_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3428 MASTER LE NN 269860 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_COMP_HYST_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3429 MASTER LE NN 269984 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_VS_CTL__VS_STEPPER_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3430 MASTER LE NN 269987 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_SS_CTL__SS_STEPPER_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3431 MASTER LE NN 269296 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3432 MASTER LE NN 269315 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/d_cal_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3433 MASTER LE NN 269385 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3434 MASTER LE NN 269983 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3435 MASTER LE NN 269982 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_VS_CTL__VS_STEP_RATE
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3436 MASTER LE NN 269904 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_1__WAKE_P
S_DLY_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3437 MASTER LE NN 269937 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/
dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3438 MASTER LE NN 269384 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3439 MASTER LE NN 269675 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM1__PWM_THRES_TRIM_re
g/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3440 MASTER LE NN 269942 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_re
g/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3441 MASTER LE NN 269939 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3442 MASTER LE NN 269386 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3443 MASTER LE NN 269298 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/d_l2r_trim_cal_fault_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3444 MASTER LE NN 269482 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3445 MASTER LE NN 269734 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_OCP__OCP_STATUS_CLEAR_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3446 MASTER LE NN 269807 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_VRST_RANGE
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3447 MASTER LE NN 269923 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__PFM_PWM_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3448 MASTER LE NN 269481 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3449 MASTER LE NN 269484 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3450 MASTER LE NN 269713 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__ERR_AMP_TRI
M_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3451 MASTER LE NN 269879 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3452 MASTER LE NN 269644 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3453 MASTER LE NN 269711 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__PFM_COMP_TR
IM_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3454 MASTER LE NN 269878 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3455 MASTER LE NN 269648 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3456 MASTER LE NN 270024 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__PWM_THRES_T
RIM_CAL_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3457 MASTER LE NN 269925 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_MODE_CTL__AUTO_RANGE_CO
MP_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3458 MASTER LE NN 269712 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__ERR_AMP_TRI
M_CAL_EN_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3459 MASTER LE NN 269666 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM4__PWM_RAMP_PEAK_TRI
M_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3460 MASTER LE NN 269646 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3461 MASTER LE NN 269647 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3462 MASTER LE NN 270023 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TRIM_EN_CTL__TRIM_CAL_EN
G_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3463 MASTER LE NN 269645 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3464 MASTER LE NN 269650 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3465 MASTER LE NN 269877 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3466 MASTER LE NN 269874 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3467 MASTER LE NN 269876 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3468 MASTER LE NN 269649 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM5__PWM_TRAN_ASSIST_r
eg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3469 MASTER LE NN 269483 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3470 MASTER LE NN 269938 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL1__MODE_PRIMARY_reg/
dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3471 MASTER LE NN 269875 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3472 MASTER LE NN 269804 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_VRST_reg/d
out_reg[2] (M31_1P5V6T_SFFSBQX1)
 Chain[3] 3473 MASTER LE NN 269676 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM1__PWM_THRES_TRIM_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3474 MASTER LE NN 269674 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM1__PWM_THRES_TRIM_re
g/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3475 MASTER LE NN 269281 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_u1/cal_request_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3476 MASTER LE NN 269673 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTL_TRIM1__PWM_THRES_TRIM_re
g/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3477 MASTER LE NN 269940 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_re
g/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3478 MASTER LE NN 269681 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INT_TEST_VAL__VREG_FAULT_INT
_TEST_VAL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3479 MASTER LE NN 269941 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_MODE_CTL2__MODE_SECONDARY_re
g/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3480 MASTER LE NN 269679 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_WAR
M_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3481 MASTER LE NN 269678 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3482 MASTER LE NN 269677 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3483 MASTER LE NN 269680 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INT_TEST_VAL__VREG_ACK_INT_T
EST_VAL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3484 MASTER LE NN 269873 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_R1_CTL__R1_CTL_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3485 MASTER LE NN 269806 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_VRST_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3486 MASTER LE NN 269986 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPPER_SS_CTL__SS_STEP_RATE
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3487 MASTER LE NN 269849 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__SPARE_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3488 MASTER LE NN 269861 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_CTL__PFM_IBOOST_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3489 MASTER LE NN 269855 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_VOLT_CTL_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3490 MASTER LE NN 269431 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_stepper_lv_hfs_ctrl_reg_voltage_stepper_lv_u1/GEN_SETPOINT_r
eg_voltage_stepper_1p0_dig_smu_u/GEN_PBUS_BUFF_VSET_VALID_d_vset_valid_pbuff_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3491 MASTER LE NN 269771 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_TIMER__WAIT_TIMER_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3492 MASTER LE NN 269453 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/d_en_rise_ed
ge_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3493 MASTER LE NN 269451 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_slib_sync_
cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3494 MASTER LE NN 269450 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_ocp_logic_wrapper_u1/hfs_ctrl_ocp_logic_u1/u_slib_sync_
cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3495 MASTER LE NN 269252 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3496 MASTER LE NN 269463 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3497 MASTER LE NN 269462 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3498 MASTER LE NN 270037 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3499 MASTER LE NN 269256 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3500 MASTER LE NN 269255 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3501 MASTER LE NN 269254 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3502 MASTER LE NN 269726 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_D
EB_sync_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3503 MASTER LE NN 269728 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_D
EB_sync_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3504 MASTER LE NN 269768 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FILTER_COEF__SPUR_FILTE
R_COEF_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3505 MASTER LE NN 269724 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/s
ync_u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3506 MASTER LE NN 269723 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/s
ync_u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3507 MASTER LE NN 269730 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_D
EB_sync_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3508 MASTER LE NN 269253 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3509 MASTER LE NN 269257 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_error_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3510 MASTER LE NN 269397 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_pfm_ctrl_fsm_u
1/d_d2a_pfm_high_sel_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3511 MASTER LE NN 269767 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FILTER_COEF__SPUR_FILTE
R_COEF_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3512 MASTER LE NN 269705 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__WEAK_PD_PWM_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3513 MASTER LE NN 269840 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_3_4__PFM_VTHRES_3
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3514 MASTER LE NN 270004 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3515 MASTER LE NN 269911 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3516 MASTER LE NN 269992 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
 Chain[3] 3517 MASTER LE NN 269909 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3518 MASTER LE NN 269996 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3519 MASTER LE NN 269907 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3520 MASTER LE NN 269722 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL_bus_sync_en/d
tmp_reg (M31_1P5V6T_SFFRSBQX1)
Chain[3] 3521 MASTER LE NN 269936 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_EN_CTL__PERPH_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3522 MASTER LE NN 269769 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FILTER_COEF__SPUR_FILTE
R_COEF_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3523 MASTER LE NN 269732 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_D
EB_sync_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3524 MASTER LE NN 269977 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_MAX_OFFSET_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3525 MASTER LE NN 269961 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_SAMPLE_CTL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3526 MASTER LE NN 269973 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P2_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3527 MASTER LE NN 269979 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_RESERVED_HROOM_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3528 MASTER LE NN 269975 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_MAX_OFFSET_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3529 MASTER LE NN 269965 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_RES_HROOM_VSET_TRAN_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3530 MASTER LE NN 269989 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3531 MASTER LE NN 269910 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3532 MASTER LE NN 269908 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_COUNT_CTL__THRESHOLD_reg
/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3533 MASTER LE NN 269839 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_3_4__PFM_VTHRES_3
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3534 MASTER LE NN 269971 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P4_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3535 MASTER LE NN 269838 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_3_4__PFM_VTHRES_3
_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3536 MASTER LE NN 269686 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__DTEST1_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3537 MASTER LE NN 269751 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_2_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3538 MASTER LE NN 269684 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__ATEST1_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3539 MASTER LE NN 269687 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__DTEST1_SEL_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3540 MASTER LE NN 269758 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_PS_TIMEOUT_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3541 MASTER LE NN 269750 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_1_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3542 MASTER LE NN 269685 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__DTEST1_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3543 MASTER LE NN 269761 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_PRECH_EXTEND
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3544 MASTER LE NN 269757 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_ERRAMP_TRIM_
BUF_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3545 MASTER LE NN 269749 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_0_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3546 MASTER LE NN 269817 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PSKI
P_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3547 MASTER LE NN 269760 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_FORCE_PWM_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3548 MASTER LE NN 269820 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__SPARE1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3549 MASTER LE NN 269824 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__SPARE0_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3550 MASTER LE NN 269835 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE1_
reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3551 MASTER LE NN 269819 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PSKI
P_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3552 MASTER LE NN 269759 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_CLAMP_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3553 MASTER LE NN 269818 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PSKI
P_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3554 MASTER LE NN 269829 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE4_
reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3555 MASTER LE NN 269822 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PREC
HG_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3556 MASTER LE NN 269762 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__EN_PWM_TRAN_ASSI
ST_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3557 MASTER LE NN 269764 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__SPARE_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3558 MASTER LE NN 269682 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__ATEST1_SEL_reg/d
out_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3559 MASTER LE NN 269931 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_
AWAKE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3560 MASTER LE NN 269683 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__ATEST1_SEL_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3561 MASTER LE NN 269914 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3562 MASTER LE NN 269901 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3563 MASTER LE NN 269968 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_M1_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3564 MASTER LE NN 269967 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_M1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3565 MASTER LE NN 269752 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_3_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3566 MASTER LE NN 269969 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P4_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3567 MASTER LE NN 269837 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_3_4__PFM_VTHRES_3
_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3568 MASTER LE NN 269703 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INT_TEST1__INT_TEST_MODE_EN_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3569 MASTER LE NN 269387 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3570 MASTER LE NN 269850 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__SPARE_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3571 MASTER LE NN 269853 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_COMP_HYST_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3572 MASTER LE NN 269770 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_TIMER__SQM_TIMER_SEL_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3573 MASTER LE NN 269810 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_MODE_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3574 MASTER LE NN 269729 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_READY_D
EB_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3575 MASTER LE NN 269854 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_RET_CTL__PFM_IBOOST_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 3576 MASTER LE NN 269383 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3577 MASTER LE NN 269725 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STATUS_DEB_CTL__VREG_ERROR_D
EB_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3578 MASTER LE NN 269389 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3579 MASTER LE NN 269946 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3580 MASTER LE NN 269390 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3581 MASTER LE NN 269994 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3582 MASTER LE NN 269708 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PD_CTL__STRONG_PD_EN_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3583 MASTER LE NN 269702 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INT_TEST1__LEGACY_MODE_EN_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3584 MASTER LE NN 269927 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3585 MASTER LE NN 269733 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_STEPDOWN_READY_CTL__VOUT_EQ_
VREF_WAIT_BYPASS_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3586 MASTER LE NN 269926 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3587 MASTER LE NN 269388 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_filter_u1/d_l2
r_freq_det_filter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3588 MASTER LE NN 269809 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_FOLLOW_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3589 MASTER LE NN 269805 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_QM_PS_EXIT__QM_PS_VRST_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3590 MASTER LE NN 269872 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_BUCK_SNS_CTL__SNS_SEL_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3591 MASTER LE NN 269864 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_DMAX_CTL__DMAX_TIME_SEL_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3592 MASTER LE NN 269863 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FB_FLT_CFG__FB_RANGE_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3593 MASTER LE NN 269632 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3594 MASTER LE NN 269635 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT
_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3595 MASTER LE NN 269631 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_LOCKBIT_D1_write_once_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3596 MASTER LE NN 269633 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3597 MASTER LE NN 269636 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL1__ENABLE_PRE
SET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3598 MASTER LE NN 269634 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PERPH_RESET_CTL2__FOLLOW_GLO
BAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3599 MASTER LE NN 269892 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3600 MASTER LE NN 269894 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_
reg[3] (M31_1P5V6T_SFFSRBQX2J)
Chain[3] 3601 MASTER LE NN 269893 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_
reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3602 MASTER LE NN 269314 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3603 MASTER LE NN 269637 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL2__GANG_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3604 MASTER LE NN 269865 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_DMAX_CTL__DMAX_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3605 MASTER LE NN 269891 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FREQ_CTL__FREQ_CTL_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3606 MASTER LE NN 269689 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__OPEN_LOOP_TEST_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3607 MASTER LE NN 269688 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_TEST1__TRIM_CALIB_EN_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3608 MASTER LE NN 269763 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC1__DIS_RETENTION_MO
DE_DLY_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3609 MASTER LE NN 269821 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PREC
HG_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3610 MASTER LE NN 269755 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_6_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3611 MASTER LE NN 269834 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE2_
reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3612 MASTER LE NN 269823 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PS_THRESH_VSET__PS_VSET_PREC
HG_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3613 MASTER LE NN 269976 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_MAX_OFFSET_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3614 MASTER LE NN 269966 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3615 MASTER LE NN 269964 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_DEC_DELAY_CTL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3616 MASTER LE NN 269970 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P4_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3617 MASTER LE NN 269981 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_RESERVED_HROOM_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3618 MASTER LE NN 270036 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3619 MASTER LE NN 269237 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3620 MASTER LE NN 269236 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3621 MASTER LE NN 269529 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync9/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3622 MASTER LE NN 269530 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync9/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3623 MASTER LE NN 269526 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync8/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3624 MASTER LE NN 269527 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync8/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3625 MASTER LE NN 269524 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync7/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3626 MASTER LE NN 269235 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3627 MASTER LE NN 269234 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3628 MASTER LE NN 269525 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync7/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3629 MASTER LE NN 269528 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_error_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3630 MASTER LE NN 269577 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3631 MASTER LE NN 269532 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync10/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3632 MASTER LE NN 269521 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3633 MASTER LE NN 269238 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3634 MASTER LE NN 269233 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
 Chain[3] 3635 MASTER LE NN 269443 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/slib_sync_u1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3636 MASTER LE NN 269442 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_flag_logic_fast_clk_hfs_ctrl_reg_flag_logic_fast_clk_u1/u_vr
eg_ready_debouncer/slib_sync_u1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3637 MASTER LE NN 269573 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3638 MASTER LE NN 269572 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3639 MASTER LE NN 269520 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3640 MASTER LE NN 269576 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3641 MASTER LE NN 269575 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3642 MASTER LE NN 269580 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3643 MASTER LE NN 269571 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3644 MASTER LE NN 269581 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3645 MASTER LE NN 269589 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_4_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3646 MASTER LE NN 269993 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3647 MASTER LE NN 269997 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3648 MASTER LE NN 269995 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3649 MASTER LE NN 270005 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3650 MASTER LE NN 270007 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3651 MASTER LE NN 269935 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_AWAKE_CF
G_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3652 MASTER LE NN 270006 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3653 MASTER LE NN 269480 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_spur_logic_u1/reg_spur_logic_1p0_dig_freq_detector_
u1/d_l2r_freq_det_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3654 MASTER LE NN 269836 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE1_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3655 MASTER LE NN 269846 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_1
_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3656 MASTER LE NN 269754 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_5_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3657 MASTER LE NN 269915 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3658 MASTER LE NN 269895 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__POWER_
BOOST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3659 MASTER LE NN 269844 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_2
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3660 MASTER LE NN 269916 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3661 MASTER LE NN 269900 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3662 MASTER LE NN 269919 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WID
TH_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3663 MASTER LE NN 269783 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3664 MASTER LE NN 269902 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3665 MASTER LE NN 269898 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3666 MASTER LE NN 269847 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_1
_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3667 MASTER LE NN 269832 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE3_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3668 MASTER LE NN 269842 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_2
_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3669 MASTER LE NN 269831 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE3_
reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3670 MASTER LE NN 269841 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_2
_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3671 MASTER LE NN 269843 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_2
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3672 MASTER LE NN 269833 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE2_
reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3673 MASTER LE NN 269917 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WID
TH_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3674 MASTER LE NN 269918 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__WINDOW_WID
TH_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3675 MASTER LE NN 269912 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3676 MASTER LE NN 269896 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3677 MASTER LE NN 269899 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3678 MASTER LE NN 269714 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3679 MASTER LE NN 269845 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_1
_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3680 MASTER LE NN 269848 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_VTHRES_1_2__PFM_VTHRES_1
_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3681 MASTER LE NN 269717 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3682 MASTER LE NN 269748 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_7_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3683 MASTER LE NN 269773 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3684 MASTER LE NN 269934 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN2_CF
G_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3685 MASTER LE NN 269745 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_4_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3686 MASTER LE NN 269776 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3687 MASTER LE NN 269746 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_5_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3688 MASTER LE NN 269743 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_2_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3689 MASTER LE NN 269719 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3690 MASTER LE NN 269718 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3691 MASTER LE NN 269744 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_3_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3692 MASTER LE NN 269715 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3693 MASTER LE NN 269897 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_AUTO_RETENTION_CTL_2__SPARE_
reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
 Chain[3] 3694 MASTER LE NN 269747 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_6_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3695 MASTER LE NN 269716 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3696 MASTER LE NN 269308 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3697 MASTER LE NN 269643 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3698 MASTER LE NN 269641 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3699 MASTER LE NN 269309 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3700 MASTER LE NN 269310 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3701 MASTER LE NN 269311 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3702 MASTER LE NN 269312 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3703 MASTER LE NN 269306 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3704 MASTER LE NN 269313 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3705 MASTER LE NN 269305 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3706 MASTER LE NN 269307 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/trim_cal_cmn_1p0_dig_fsm_timer_u1/wait_timer_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3707 MASTER LE NN 269280 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_trim_logic_u1/gen_510_trim_cal_trim_cal_cmn_dig_mod_510
_u1/slib_clkreq_gate_1p0_clk_cal_u1/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3708 MASTER LE NN 269756 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_7_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3709 MASTER LE NN 269753 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC2__SPARE_4_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3710 MASTER LE NN 269720 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3711 MASTER LE NN 269721 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CAL_TIMER_CTL__CAL_TIMER_reg
/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3712 MASTER LE NN 269913 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_INZERO_COUNT_CTL__THRESHOLD_
reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3713 MASTER LE NN 269830 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_PFM_TOFF_DELAY__TOFF_RANGE4_
reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3714 MASTER LE NN 269972 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3715 MASTER LE NN 269974 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL2_0_array_u_AHC_CTL2_0_
_AHC_VSET_P2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3716 MASTER LE NN 269980 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_RESERVED_HROOM_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3717 MASTER LE NN 269963 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_DEC_DELAY_CTL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3718 MASTER LE NN 269962 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_SAMPLE_CTL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3719 MASTER LE NN 269978 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL1_0_array_u_AHC_CTL1_0_
_AHC_MAX_OFFSET_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3720 MASTER LE NN 269960 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/AHC_CTL3_0_array_u_AHC_CTL3_0_
_AHC_SAMPLE_CTL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3721 MASTER LE NN 269590 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_5_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3722 MASTER LE NN 269588 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_3_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3723 MASTER LE NN 269587 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_2_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3724 MASTER LE NN 269582 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_1_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3725 MASTER LE NN 269586 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3726 MASTER LE NN 269583 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_clear_latch_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3727 MASTER LE NN 269585 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3728 MASTER LE NN 269578 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_sample_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3729 MASTER LE NN 269579 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_calc_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3730 MASTER LE NN 269574 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_timer_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3731 MASTER LE NN 269541 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync5/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3732 MASTER LE NN 269540 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync5/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3733 MASTER LE NN 269533 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync10/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3734 MASTER LE NN 269545 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_int_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3735 MASTER LE NN 269535 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_sta
te_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3736 MASTER LE NN 269531 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3737 MASTER LE NN 269542 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_cnt_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3738 MASTER LE NN 270029 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3739 MASTER LE NN 269639 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3740 MASTER LE NN 269630 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3741 MASTER LE NN 269642 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3742 MASTER LE NN 269640 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3743 MASTER LE NN 269638 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3744 MASTER LE NN 269774 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3745 MASTER LE NN 269741 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_0_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3746 MASTER LE NN 269742 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_CTLR_MISC3__SCRATCH_1_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3747 MASTER LE NN 269954 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3748 MASTER LE NN 269930 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN2
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3749 MASTER LE NN 269944 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3750 MASTER LE NN 270034 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3751 MASTER LE NN 269998 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3752 MASTER LE NN 269991 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg
/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
 Chain[3] 3753 MASTER LE NN 269947 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3754 MASTER LE NN 269988 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg
/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3755 MASTER LE NN 269990 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg
/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3756 MASTER LE NN 269948 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3757 MASTER LE NN 269943 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3758 MASTER LE NN 269945 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_UB__VSET_UB_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3759 MASTER LE NN 269800 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3760 MASTER LE NN 269956 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[6] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3761 MASTER LE NN 269950 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3762 MASTER LE NN 269797 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3763 MASTER LE NN 269792 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3764 MASTER LE NN 269793 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3765 MASTER LE NN 269795 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3766 MASTER LE NN 269794 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3767 MASTER LE NN 269801 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3768 MASTER LE NN 269787 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3769 MASTER LE NN 269799 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3770 MASTER LE NN 269784 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3771 MASTER LE NN 269788 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3772 MASTER LE NN 269803 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3773 MASTER LE NN 269802 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3774 MASTER LE NN 269928 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN0
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3775 MASTER LE NN 269929 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__EN_FOLLOW_HWEN1
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3776 MASTER LE NN 269780 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3777 MASTER LE NN 269779 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ2_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3778 MASTER LE NN 269933 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN1_CF
G_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3779 MASTER LE NN 269932 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_FOLLOW_HWEN__FOLLOW_HWEN0_CF
G_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3780 MASTER LE NN 269791 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_LOW__FTHRE
SH_LOW_reg/dout_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3781 MASTER LE NN 269798 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_SPUR_FREQ1_THRESH_HIGH__FTHR
ESH_HIGH_reg/dout_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[3] 3782 MASTER LE NN 270002 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3783 MASTER LE NN 269952 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_reg/dout_re
g[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3784 MASTER LE NN 270000 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg
/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3785 MASTER LE NN 270003 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3786 MASTER LE NN 270001 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3787 MASTER LE NN 269999 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_ULS_VSET_LB__ULS_VSET_LB_lat
ched_write_reg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3788 MASTER LE NN 269595 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3789 MASTER LE NN 269596 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3790 MASTER LE NN 269597 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3791 MASTER LE NN 270028 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3792 MASTER LE NN 269566 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg3/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3793 MASTER LE NN 269565 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_slib_sync_cg3/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3794 MASTER LE NN 269547 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3795 MASTER LE NN 269548 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3796 MASTER LE NN 269543 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_cnt_state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3797 MASTER LE NN 269544 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_sta
te_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3798 MASTER LE NN 269534 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_sta
te_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[3] 3799 MASTER LE NN 269536 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_clear_en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3800 MASTER LE NN 269539 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_clear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3801 MASTER LE NN 269518 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3802 MASTER LE NN 269594 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3803 MASTER LE NN 269593 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3804 MASTER LE NN 269592 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_ahc_offset_sat_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3805 MASTER LE NN 270025 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3806 MASTER LE NN 269949 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3807 MASTER LE NN 270026 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_csr/u_hfs_ctrl_rif_wrap/u_hfs_ctrl_rif/u_VSET_LB__VSET_LB_latched_wri
te_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3808 MASTER LE NN 269267 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3809 MASTER LE NN 269268 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3810 MASTER LE NN 269269 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/u_rlib_ps_reg_vset_sync/dout_r
eg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[3] 3811 MASTER LE NN 269570 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_load_flag_sync_b_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[3] 3812 MASTER LE NN 269569 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/gen_ahc_hfs_ctrl_reg_ahc_logic_u1/d_load_flag_sync_b_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3813 MASTER LE NN 269538 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync2/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3814 MASTER LE NN 269537 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync2/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3815 MASTER LE NN 269551 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync6/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3816 MASTER LE NN 269522 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_slib_sync11/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[3] 3817 MASTER LE NN 269546 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/u_reg_int_logic_dig_vreg_ack_fsm/d_vre
g_ack_cnt_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[3] 3818 MASTER LE NN 269617 + GPIO_07
I_DCORE/\hfs_ctrl_rmod_gen[1]_u_hfs_ctrl_rmod/u_hfs_ctrl_rdig/u_hfs_ctrl_dig_mod/\u
_hfs_ctrl_dig_core/hfs_ctrl_reg_int_logic_u1/d_vreg_ack_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[3] 3819 MASTER TE NN 288702 - GPIO_07
I_DCORE/\SNPS_PipeHead_u_waimea_dcore_glue/u_dft_test_ctrl/scan_chain_in[3]_1
(M31_1P5V6T_SFFQX3)
Chain[4] 0 MASTER LE NN 288697 + GPIO_07
I_DCORE/\SNPS_PipeTail_u_waimea_dcore_glue/u_dft_test_ctrl/scan_chain_out[4]_1
(M31_1P5V6T_DFFQX1)
Chain[4] 1 MASTER LE NN 277017 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256858 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/LOCKUP (M31_1P5V6T_LOWLATCHX2)
Chain[4] 2 MASTER LE NN 277007 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3 MASTER LE NN 277015 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 4 MASTER LE NN 277262 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 5 MASTER LE NN 277263 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 6 MASTER LE NN 277302 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 7 MASTER LE NN 277266 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 8 MASTER LE NN 277050 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 9 MASTER LE NN 277297 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 10 MASTER LE NN 277293 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 11 MASTER LE NN 277053 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 12 MASTER LE NN 277142 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 13 MASTER LE NN 277153 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 14 MASTER LE NN 277154 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 15 MASTER LE NN 277216 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 16 MASTER LE NN 277166 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 17 MASTER LE NN 277165 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 18 MASTER LE NN 277169 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 19 MASTER LE NN 277159 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 20 MASTER LE NN 277167 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 21 MASTER LE NN 277172 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 22 MASTER LE NN 277168 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 23 MASTER LE NN 277162 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 24 MASTER LE NN 277158 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 25 MASTER LE NN 277174 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 26 MASTER LE NN 277149 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 27 MASTER LE NN 277146 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 28 MASTER LE NN 277155 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 29 MASTER LE NN 277052 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 30 MASTER LE NN 277018 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 31 MASTER LE NN 277072 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 32 MASTER LE NN 277384 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 33 MASTER LE NN 277298 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 34 MASTER LE NN 277291 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 35 MASTER LE NN 277074 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 36 MASTER LE NN 277269 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 37 MASTER LE NN 277213 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 38 MASTER LE NN 277075 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 39 MASTER LE NN 277344 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 40 MASTER LE NN 277343 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
 Chain[4] 41 MASTER LE NN 277342 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 42 MASTER LE NN 277077 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 43 MASTER LE NN 277340 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 44 MASTER LE NN 277285 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 45 MASTER LE NN 277299 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 46 MASTER LE NN 277212 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 47 MASTER LE NN 277324 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[4] 48 MASTER LE NN 277141 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 49 MASTER LE NN 277070 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 50 MASTER LE NN 277283 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 51 MASTER LE NN 277316 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 52 MASTER LE NN 277325 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 53 MASTER LE NN 277239 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 54 MASTER LE NN 277317 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 55 MASTER LE NN 277314 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 56 MASTER LE NN 277122 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
 Chain[4] 57 MASTER LE NN 277281 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 58 MASTER LE NN 277328 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 59 MASTER LE NN 277253 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 60 MASTER LE NN 277329 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 61 MASTER LE NN 277320 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 62 MASTER LE NN 277078 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 63 MASTER LE NN 277341 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 64 MASTER LE NN 277254 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 65 MASTER LE NN 277251 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 66 MASTER LE NN 277265 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 67 MASTER LE NN 277264 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 68 MASTER LE NN 277326 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 69 MASTER LE NN 277322 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 70 MASTER LE NN 277260 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 71 MASTER LE NN 277237 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
 Chain[4] 72 MASTER LE NN 277252 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 73 MASTER LE NN 277273 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 74 MASTER LE NN 277272 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 75 MASTER LE NN 277244 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 76 MASTER LE NN 277257 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 77 MASTER LE NN 277275 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 78 MASTER LE NN 277274 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 79 MASTER LE NN 277318 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 80 MASTER LE NN 277313 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 81 MASTER LE NN 277259 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 82 MASTER LE NN 277321 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 83 MASTER LE NN 277319 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 84 MASTER LE NN 277312 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 85 MASTER LE NN 277261 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 86 MASTER LE NN 277238 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 87 MASTER LE NN 277240 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 88 MASTER LE NN 277323 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 89 MASTER LE NN 277327 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 90 MASTER LE NN 277242 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 91 MASTER LE NN 277284 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 92 MASTER LE NN 277268 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 93 MASTER LE NN 277289 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 94 MASTER LE NN 277051 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 95 MASTER LE NN 277295 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 96 MASTER LE NN 277071 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 97 MASTER LE NN 277143 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 98 MASTER LE NN 277148 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 99 MASTER LE NN 277145 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 100 MASTER LE NN 277144 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 101 MASTER LE NN 277157 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 102 MASTER LE NN 277160 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 103 MASTER LE NN 277173 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 104 MASTER LE NN 277215 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 105 MASTER LE NN 277214 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 106 MASTER LE NN 277387 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 107 MASTER LE NN 277164 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 108 MASTER LE NN 277182 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 109 MASTER LE NN 277161 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 110 MASTER LE NN 277163 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 111 MASTER LE NN 277156 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 112 MASTER LE NN 277128 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 113 MASTER LE NN 277130 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 114 MASTER LE NN 277129 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 115 MASTER LE NN 277061 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 116 MASTER LE NN 277066 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 117 MASTER LE NN 277065 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 118 MASTER LE NN 277131 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 119 MASTER LE NN 277132 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 120 MASTER LE NN 277064 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 121 MASTER LE NN 277094 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 122 MASTER LE NN 277133 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 123 MASTER LE NN 277063 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 124 MASTER LE NN 277062 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 125 MASTER LE NN 277069 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 126 MASTER LE NN 277088 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 127 MASTER LE NN 277067 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 128 MASTER LE NN 277084 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 129 MASTER LE NN 277068 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 130 MASTER LE NN 277201 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 131 MASTER LE NN 277085 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 132 MASTER LE NN 277202 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 133 MASTER LE NN 277087 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 134 MASTER LE NN 277093 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 135 MASTER LE NN 277083 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 136 MASTER LE NN 277383 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 137 MASTER LE NN 277379 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 138 MASTER LE NN 277377 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFSBQX1)
Chain[4] 139 MASTER LE NN 277381 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 140 MASTER LE NN 277370 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFSBQX1)
Chain[4] 141 MASTER LE NN 277386 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 142 MASTER LE NN 277367 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 143 MASTER LE NN 277375 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[4] 144 MASTER LE NN 277346 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 145 MASTER LE NN 277372 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFSBQX1)
Chain[4] 146 MASTER LE NN 277366 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 147 MASTER LE NN 277347 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 148 MASTER LE NN 277345 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 149 MASTER LE NN 277382 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 150 MASTER LE NN 277349 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 151 MASTER LE NN 277376 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 152 MASTER LE NN 277348 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 153 MASTER LE NN 277353 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 154 MASTER LE NN 277361 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 155 MASTER LE NN 277378 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 156 MASTER LE NN 277371 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 157 MASTER LE NN 277351 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 158 MASTER LE NN 277368 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 159 MASTER LE NN 277380 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 160 MASTER LE NN 277365 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 161 MASTER LE NN 277369 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 162 MASTER LE NN 277282 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 163 MASTER LE NN 277338 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 164 MASTER LE NN 277315 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 165 MASTER LE NN 277385 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 166 MASTER LE NN 277339 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 167 MASTER LE NN 277073 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 168 MASTER LE NN 277279 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 169 MASTER LE NN 277280 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 170 MASTER LE NN 277241 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 171 MASTER LE NN 277076 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 172 MASTER LE NN 277243 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 173 MASTER LE NN 277270 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 174 MASTER LE NN 277250 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 175 MASTER LE NN 277276 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 176 MASTER LE NN 277277 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 177 MASTER LE NN 277255 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 178 MASTER LE NN 277256 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 179 MASTER LE NN 277271 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 180 MASTER LE NN 277258 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 181 MASTER LE NN 277278 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 182 MASTER LE NN 277245 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 183 MASTER LE NN 277247 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 184 MASTER LE NN 277249 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 185 MASTER LE NN 277248 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 186 MASTER LE NN 277235 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 187 MASTER LE NN 277246 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 188 MASTER LE NN 277236 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 189 MASTER LE NN 277234 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 190 MASTER LE NN 277363 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 191 MASTER LE NN 277334 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 192 MASTER LE NN 277308 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 193 MASTER LE NN 277373 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 194 MASTER LE NN 277359 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 195 MASTER LE NN 277374 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 196 MASTER LE NN 277306 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 197 MASTER LE NN 277305 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 198 MASTER LE NN 277311 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 199 MASTER LE NN 277337 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 200 MASTER LE NN 277335 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 201 MASTER LE NN 277309 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 202 MASTER LE NN 277331 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 203 MASTER LE NN 277330 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 204 MASTER LE NN 277333 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 205 MASTER LE NN 277332 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 206 MASTER LE NN 277336 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 207 MASTER LE NN 277310 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 208 MASTER LE NN 277307 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 209 MASTER LE NN 277304 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 210 MASTER LE NN 277357 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 211 MASTER LE NN 277355 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 212 MASTER LE NN 277358 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 213 MASTER LE NN 277360 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 214 MASTER LE NN 277362 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 215 MASTER LE NN 277364 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 216 MASTER LE NN 277356 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 217 MASTER LE NN 277354 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 218 MASTER LE NN 277205 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 219 MASTER LE NN 277092 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 220 MASTER LE NN 277204 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 221 MASTER LE NN 277095 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 222 MASTER LE NN 277206 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 223 MASTER LE NN 277082 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 224 MASTER LE NN 277086 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 225 MASTER LE NN 277203 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 226 MASTER LE NN 277096 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 227 MASTER LE NN 277080 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 228 MASTER LE NN 277079 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 229 MASTER LE NN 277352 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 230 MASTER LE NN 277350 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 231 MASTER LE NN 277091 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 232 MASTER LE NN 277090 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 233 MASTER LE NN 277089 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 234 MASTER LE NN 277207 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 235 MASTER LE NN 277200 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 236 MASTER LE NN 277081 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 237 MASTER LE NN 276802 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256853 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX1)
Chain[4] 238 MASTER LE NN 276796 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 239 MASTER LE NN 276788 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 240 MASTER LE NN 276792 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 241 MASTER LE NN 276801 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 242 MASTER LE NN 276797 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 243 MASTER LE NN 276800 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 244 MASTER LE NN 276798 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 245 MASTER LE NN 276835 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 246 MASTER LE NN 276833 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 247 MASTER LE NN 276793 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 248 MASTER LE NN 276763 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 249 MASTER LE NN 276795 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 250 MASTER LE NN 276784 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 251 MASTER LE NN 276782 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 252 MASTER LE NN 276775 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 253 MASTER LE NN 276762 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 254 MASTER LE NN 276759 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 255 MASTER LE NN 276758 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 256 MASTER LE NN 276785 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 257 MASTER LE NN 276783 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 258 MASTER LE NN 276766 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 259 MASTER LE NN 276789 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 260 MASTER LE NN 276768 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 261 MASTER LE NN 276699 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 262 MASTER LE NN 276819 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 263 MASTER LE NN 276697 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 264 MASTER LE NN 276832 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 265 MASTER LE NN 276700 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 266 MASTER LE NN 276820 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 267 MASTER LE NN 276698 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 268 MASTER LE NN 276694 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 269 MASTER LE NN 276821 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 270 MASTER LE NN 276701 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 271 MASTER LE NN 276695 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 272 MASTER LE NN 276696 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 273 MASTER LE NN 276711 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 274 MASTER LE NN 276824 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 275 MASTER LE NN 276818 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 276 MASTER LE NN 276710 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 277 MASTER LE NN 276823 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 278 MASTER LE NN 276707 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 279 MASTER LE NN 276708 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 280 MASTER LE NN 276702 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 281 MASTER LE NN 276683 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 282 MASTER LE NN 276822 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 283 MASTER LE NN 276825 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 284 MASTER LE NN 276706 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 285 MASTER LE NN 276704 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 286 MASTER LE NN 276705 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 287 MASTER LE NN 276993 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 288 MASTER LE NN 276965 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 289 MASTER LE NN 276962 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 290 MASTER LE NN 276960 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 291 MASTER LE NN 276992 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 292 MASTER LE NN 276972 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 293 MASTER LE NN 276969 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 294 MASTER LE NN 276985 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFSBQX1)
Chain[4] 295 MASTER LE NN 276957 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 296 MASTER LE NN 276956 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 297 MASTER LE NN 276955 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 298 MASTER LE NN 276974 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 299 MASTER LE NN 276975 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 300 MASTER LE NN 276976 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 301 MASTER LE NN 276980 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFSBQX1)
Chain[4] 302 MASTER LE NN 276984 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 303 MASTER LE NN 276958 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 304 MASTER LE NN 276967 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 305 MASTER LE NN 276991 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 306 MASTER LE NN 276989 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 307 MASTER LE NN 276961 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 308 MASTER LE NN 276987 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 309 MASTER LE NN 276988 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 310 MASTER LE NN 276986 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 311 MASTER LE NN 276963 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 312 MASTER LE NN 276959 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 313 MASTER LE NN 276964 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 314 MASTER LE NN 276983 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[4] 315 MASTER LE NN 276966 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 316 MASTER LE NN 276970 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 317 MASTER LE NN 276990 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 318 MASTER LE NN 276982 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 319 MASTER LE NN 276979 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 320 MASTER LE NN 277000 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 321 MASTER LE NN 276968 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 322 MASTER LE NN 276981 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 323 MASTER LE NN 276915 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 324 MASTER LE NN 276942 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 325 MASTER LE NN 276940 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 326 MASTER LE NN 276941 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 327 MASTER LE NN 276945 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 328 MASTER LE NN 276918 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 329 MASTER LE NN 276947 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 330 MASTER LE NN 276944 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 331 MASTER LE NN 276917 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 332 MASTER LE NN 276943 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 333 MASTER LE NN 276916 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 334 MASTER LE NN 276919 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 335 MASTER LE NN 276913 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 336 MASTER LE NN 276946 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 337 MASTER LE NN 276914 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 338 MASTER LE NN 276978 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFSBQX1)
Chain[4] 339 MASTER LE NN 276682 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 340 MASTER LE NN 276799 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 341 MASTER LE NN 276767 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 342 MASTER LE NN 276787 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 343 MASTER LE NN 276834 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 344 MASTER LE NN 276786 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 345 MASTER LE NN 276794 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 346 MASTER LE NN 276774 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 347 MASTER LE NN 276776 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 348 MASTER LE NN 276771 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 349 MASTER LE NN 276770 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 350 MASTER LE NN 276773 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 351 MASTER LE NN 276772 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 352 MASTER LE NN 276769 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 353 MASTER LE NN 276761 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 354 MASTER LE NN 276760 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 355 MASTER LE NN 276765 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 356 MASTER LE NN 276764 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 357 MASTER LE NN 276634 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 358 MASTER LE NN 276633 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 359 MASTER LE NN 276635 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 360 MASTER LE NN 276640 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 361 MASTER LE NN 276909 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 362 MASTER LE NN 276910 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 363 MASTER LE NN 276902 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 364 MASTER LE NN 276904 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 365 MASTER LE NN 276668 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 366 MASTER LE NN 276952 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 367 MASTER LE NN 276954 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 368 MASTER LE NN 276889 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 369 MASTER LE NN 276688 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 370 MASTER LE NN 276888 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 371 MASTER LE NN 276953 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 372 MASTER LE NN 276890 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 373 MASTER LE NN 276950 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 374 MASTER LE NN 276907 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 375 MASTER LE NN 276951 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 376 MASTER LE NN 276906 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 377 MASTER LE NN 276924 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 378 MASTER LE NN 276908 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 379 MASTER LE NN 276892 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 380 MASTER LE NN 276926 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 381 MASTER LE NN 276928 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 382 MASTER LE NN 276927 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 383 MASTER LE NN 276930 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 384 MASTER LE NN 276737 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 385 MASTER LE NN 276689 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 386 MASTER LE NN 276949 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 387 MASTER LE NN 276925 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 388 MASTER LE NN 276894 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 389 MASTER LE NN 276685 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 390 MASTER LE NN 276757 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 391 MASTER LE NN 276692 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 392 MASTER LE NN 276939 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 393 MASTER LE NN 276690 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 394 MASTER LE NN 276887 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 395 MASTER LE NN 276691 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 396 MASTER LE NN 276920 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 397 MASTER LE NN 276971 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 398 MASTER LE NN 276977 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 399 MASTER LE NN 276973 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 400 MASTER LE NN 276948 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 401 MASTER LE NN 276854 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 402 MASTER LE NN 276855 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 403 MASTER LE NN 276858 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 404 MASTER LE NN 276891 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 405 MASTER LE NN 276856 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 406 MASTER LE NN 276857 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 407 MASTER LE NN 276844 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 408 MASTER LE NN 276843 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 409 MASTER LE NN 276845 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 410 MASTER LE NN 276852 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 411 MASTER LE NN 276853 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 412 MASTER LE NN 276693 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 413 MASTER LE NN 276867 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 414 MASTER LE NN 276938 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 415 MASTER LE NN 276862 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 416 MASTER LE NN 276886 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 417 MASTER LE NN 276885 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 418 MASTER LE NN 276868 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 419 MASTER LE NN 276880 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 420 MASTER LE NN 276879 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 421 MASTER LE NN 276859 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 422 MASTER LE NN 276884 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 423 MASTER LE NN 276866 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 424 MASTER LE NN 276865 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 425 MASTER LE NN 276883 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 426 MASTER LE NN 276869 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 427 MASTER LE NN 276937 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 428 MASTER LE NN 276932 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 429 MASTER LE NN 276923 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 430 MASTER LE NN 276931 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 431 MASTER LE NN 276929 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 432 MASTER LE NN 276743 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 433 MASTER LE NN 276687 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 434 MASTER LE NN 276686 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 435 MASTER LE NN 276658 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 436 MASTER LE NN 276636 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 437 MASTER LE NN 276667 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 438 MASTER LE NN 276791 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 439 MASTER LE NN 276790 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 440 MASTER LE NN 276779 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 441 MASTER LE NN 276778 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 442 MASTER LE NN 276777 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 443 MASTER LE NN 276781 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 444 MASTER LE NN 276681 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 445 MASTER LE NN 276780 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 446 MASTER LE NN 276677 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 447 MASTER LE NN 276747 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 448 MASTER LE NN 276678 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 449 MASTER LE NN 276680 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 450 MASTER LE NN 276684 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 451 MASTER LE NN 276703 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 452 MASTER LE NN 276744 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 453 MASTER LE NN 276748 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 454 MASTER LE NN 276709 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 455 MASTER LE NN 276679 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 456 MASTER LE NN 276749 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 457 MASTER LE NN 276746 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 458 MASTER LE NN 276745 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 459 MASTER LE NN 276676 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 460 MASTER LE NN 276670 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 461 MASTER LE NN 276669 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 462 MASTER LE NN 276662 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 463 MASTER LE NN 276661 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 464 MASTER LE NN 276660 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 465 MASTER LE NN 276659 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 466 MASTER LE NN 276753 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 467 MASTER LE NN 276671 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 468 MASTER LE NN 276673 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 469 MASTER LE NN 276672 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 470 MASTER LE NN 276649 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 471 MASTER LE NN 276657 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 472 MASTER LE NN 276648 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 473 MASTER LE NN 276735 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 474 MASTER LE NN 276756 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 475 MASTER LE NN 276755 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 476 MASTER LE NN 276804 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 477 MASTER LE NN 276654 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 478 MASTER LE NN 276653 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 479 MASTER LE NN 276655 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 480 MASTER LE NN 276651 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 481 MASTER LE NN 276652 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 482 MASTER LE NN 276639 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 483 MASTER LE NN 276638 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 484 MASTER LE NN 276664 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 485 MASTER LE NN 276663 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 486 MASTER LE NN 276899 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 487 MASTER LE NN 276896 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 488 MASTER LE NN 276903 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 489 MASTER LE NN 276905 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 490 MASTER LE NN 276742 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 491 MASTER LE NN 276712 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 492 MASTER LE NN 276803 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 493 MASTER LE NN 276736 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 494 MASTER LE NN 276645 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 495 MASTER LE NN 276650 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 496 MASTER LE NN 276646 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 497 MASTER LE NN 276675 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 498 MASTER LE NN 276812 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 499 MASTER LE NN 276811 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 500 MASTER LE NN 276809 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 501 MASTER LE NN 276808 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 502 MASTER LE NN 276807 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 503 MASTER LE NN 276836 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 504 MASTER LE NN 276837 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 505 MASTER LE NN 276666 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 506 MASTER LE NN 276839 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 507 MASTER LE NN 276895 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[4] 508 MASTER LE NN 276897 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 509 MASTER LE NN 276901 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 510 MASTER LE NN 276637 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 511 MASTER LE NN 276912 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 512 MASTER LE NN 276933 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 513 MASTER LE NN 276900 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 514 MASTER LE NN 276878 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 515 MASTER LE NN 276877 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 516 MASTER LE NN 276898 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 517 MASTER LE NN 276935 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 518 MASTER LE NN 276849 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 519 MASTER LE NN 276622 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 520 MASTER LE NN 276623 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 521 MASTER LE NN 276624 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 522 MASTER LE NN 276625 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 523 MASTER LE NN 276632 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 524 MASTER LE NN 276627 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 525 MASTER LE NN 276630 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 526 MASTER LE NN 276629 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
 Chain[4] 527 MASTER LE NN 276631 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 528 MASTER LE NN 276619 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 529 MASTER LE NN 276620 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 530 MASTER LE NN 276621 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 531 MASTER LE NN 276628 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 532 MASTER LE NN 276626 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 533 MASTER LE NN 276873 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 534 MASTER LE NN 276871 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 535 MASTER LE NN 276813 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[4] 536 MASTER LE NN 276814 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 537 MASTER LE NN 276734 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 538 MASTER LE NN 276876 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 539 MASTER LE NN 276875 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 540 MASTER LE NN 276934 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[4] 541 MASTER LE NN 276893 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 542 MASTER LE NN 276911 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 543 MASTER LE NN 276830 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
 Chain[4] 544 MASTER LE NN 276936 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 545 MASTER LE NN 276921 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 546 MASTER LE NN 276860 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 547 MASTER LE NN 276665 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 548 MASTER LE NN 276831 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 549 MASTER LE NN 276922 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 550 MASTER LE NN 276881 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 551 MASTER LE NN 276882 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 552 MASTER LE NN 276864 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 553 MASTER LE NN 276848 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 554 MASTER LE NN 276863 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 555 MASTER LE NN 276861 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 556 MASTER LE NN 276846 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 557 MASTER LE NN 276847 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 558 MASTER LE NN 276850 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 559 MASTER LE NN 276851 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 560 MASTER LE NN 276870 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 561 MASTER LE NN 276874 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 562 MASTER LE NN 276872 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 563 MASTER LE NN 276815 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 564 MASTER LE NN 276656 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 565 MASTER LE NN 276724 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 566 MASTER LE NN 276750 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 567 MASTER LE NN 276817 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[4] 568 MASTER LE NN 276751 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 569 MASTER LE NN 276674 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 570 MASTER LE NN 276816 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[4] 571 MASTER LE NN 276752 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 572 MASTER LE NN 276641 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 573 MASTER LE NN 276647 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 574 MASTER LE NN 276810 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 575 MASTER LE NN 276741 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 576 MASTER LE NN 276806 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 577 MASTER LE NN 276805 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 578 MASTER LE NN 276720 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 579 MASTER LE NN 276714 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 580 MASTER LE NN 276713 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 581 MASTER LE NN 276719 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 582 MASTER LE NN 276725 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 583 MASTER LE NN 276754 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 584 MASTER LE NN 276739 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 585 MASTER LE NN 276738 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 586 MASTER LE NN 276729 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 587 MASTER LE NN 276728 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 588 MASTER LE NN 276726 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 589 MASTER LE NN 276826 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 590 MASTER LE NN 276827 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[4] 591 MASTER LE NN 276717 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 592 MASTER LE NN 276727 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 593 MASTER LE NN 276829 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 594 MASTER LE NN 276828 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[4] 595 MASTER LE NN 276721 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 596 MASTER LE NN 276722 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 597 MASTER LE NN 276643 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 598 MASTER LE NN 276644 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 599 MASTER LE NN 276718 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 600 MASTER LE NN 276642 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 601 MASTER LE NN 276716 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 602 MASTER LE NN 276715 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 603 MASTER LE NN 276723 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 604 MASTER LE NN 276740 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 605 MASTER LE NN 276733 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 606 MASTER LE NN 276732 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 607 MASTER LE NN 276731 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 608 MASTER LE NN 276730 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[3]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 609 MASTER LE NN 276234 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256800 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/LOCKUP (M31_1P5V6T_LOWLATCHX1)
Chain[4] 610 MASTER LE NN 276235 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 611 MASTER LE NN 276236 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 612 MASTER LE NN 276246 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 613 MASTER LE NN 276245 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 614 MASTER LE NN 276247 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 615 MASTER LE NN 276240 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 616 MASTER LE NN 276432 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[4] 617 MASTER LE NN 276366 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX2J)
Chain[4] 618 MASTER LE NN 276430 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX3)
Chain[4] 619 MASTER LE NN 276271 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 620 MASTER LE NN 276256 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 621 MASTER LE NN 276262 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 622 MASTER LE NN 276422 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 623 MASTER LE NN 276288 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 624 MASTER LE NN 276369 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 625 MASTER LE NN 276403 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 626 MASTER LE NN 276449 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 627 MASTER LE NN 276409 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 628 MASTER LE NN 276415 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 629 MASTER LE NN 276411 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 630 MASTER LE NN 276412 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 631 MASTER LE NN 276416 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 632 MASTER LE NN 276450 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 633 MASTER LE NN 276383 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 634 MASTER LE NN 276408 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 635 MASTER LE NN 276407 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 636 MASTER LE NN 276410 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 637 MASTER LE NN 276378 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 638 MASTER LE NN 276448 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 639 MASTER LE NN 276406 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 640 MASTER LE NN 276377 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 641 MASTER LE NN 276344 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 642 MASTER LE NN 276382 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 643 MASTER LE NN 276381 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 644 MASTER LE NN 276347 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 645 MASTER LE NN 276343 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 646 MASTER LE NN 276443 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[4] 647 MASTER LE NN 276268 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 648 MASTER LE NN 276269 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 649 MASTER LE NN 276405 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 650 MASTER LE NN 276522 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 651 MASTER LE NN 276524 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 652 MASTER LE NN 276350 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 653 MASTER LE NN 276266 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 654 MASTER LE NN 276353 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 655 MASTER LE NN 276336 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 656 MASTER LE NN 276442 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[4] 657 MASTER LE NN 276345 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 658 MASTER LE NN 276346 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 659 MASTER LE NN 276441 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 660 MASTER LE NN 276341 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 661 MASTER LE NN 276444 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 662 MASTER LE NN 276342 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 663 MASTER LE NN 276354 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 664 MASTER LE NN 276337 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 665 MASTER LE NN 276286 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 666 MASTER LE NN 276287 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 667 MASTER LE NN 276290 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 668 MASTER LE NN 276272 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 669 MASTER LE NN 276259 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 670 MASTER LE NN 276355 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 671 MASTER LE NN 276348 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 672 MASTER LE NN 276338 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 673 MASTER LE NN 276335 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 674 MASTER LE NN 276334 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 675 MASTER LE NN 276331 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 676 MASTER LE NN 276257 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 677 MASTER LE NN 276332 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 678 MASTER LE NN 276356 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 679 MASTER LE NN 276421 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 680 MASTER LE NN 276420 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 681 MASTER LE NN 276333 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 682 MASTER LE NN 276330 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 683 MASTER LE NN 276340 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 684 MASTER LE NN 276329 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 685 MASTER LE NN 276328 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 686 MASTER LE NN 276423 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 687 MASTER LE NN 276425 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX2J)
Chain[4] 688 MASTER LE NN 276451 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 689 MASTER LE NN 276452 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 690 MASTER LE NN 276424 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 691 MASTER LE NN 276427 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 692 MASTER LE NN 276426 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 693 MASTER LE NN 276258 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 694 MASTER LE NN 276368 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 695 MASTER LE NN 276370 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 696 MASTER LE NN 276371 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 697 MASTER LE NN 276267 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 698 MASTER LE NN 276379 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 699 MASTER LE NN 276380 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 700 MASTER LE NN 276404 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 701 MASTER LE NN 276413 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 702 MASTER LE NN 276417 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 703 MASTER LE NN 276402 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 704 MASTER LE NN 276398 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 705 MASTER LE NN 276401 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 706 MASTER LE NN 276397 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 707 MASTER LE NN 276399 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 708 MASTER LE NN 276390 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 709 MASTER LE NN 276389 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 710 MASTER LE NN 276391 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 711 MASTER LE NN 276447 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 712 MASTER LE NN 276396 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 713 MASTER LE NN 276376 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 714 MASTER LE NN 276392 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 715 MASTER LE NN 276393 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 716 MASTER LE NN 276270 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 717 MASTER LE NN 276373 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 718 MASTER LE NN 276374 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 719 MASTER LE NN 276279 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 720 MASTER LE NN 276250 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 721 MASTER LE NN 276255 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 722 MASTER LE NN 276254 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 723 MASTER LE NN 276253 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 724 MASTER LE NN 276274 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 725 MASTER LE NN 276264 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 726 MASTER LE NN 276265 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 727 MASTER LE NN 276263 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 728 MASTER LE NN 276261 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 729 MASTER LE NN 276351 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 730 MASTER LE NN 276260 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 731 MASTER LE NN 276526 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 732 MASTER LE NN 276528 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 733 MASTER LE NN 276277 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 734 MASTER LE NN 276533 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 735 MASTER LE NN 276532 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 736 MASTER LE NN 276285 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 737 MASTER LE NN 276282 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 738 MASTER LE NN 276327 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 739 MASTER LE NN 276418 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 740 MASTER LE NN 276419 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 741 MASTER LE NN 276357 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 742 MASTER LE NN 276372 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 743 MASTER LE NN 276273 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 744 MASTER LE NN 276521 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 745 MASTER LE NN 276554 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 746 MASTER LE NN 276535 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 747 MASTER LE NN 276553 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
 Chain[4] 748 MASTER LE NN 276527 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 749 MASTER LE NN 276552 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 750 MASTER LE NN 276302 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 751 MASTER LE NN 276525 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 752 MASTER LE NN 276530 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 753 MASTER LE NN 276301 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 754 MASTER LE NN 276550 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 755 MASTER LE NN 276548 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 756 MASTER LE NN 276546 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 757 MASTER LE NN 276529 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 758 MASTER LE NN 276551 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 759 MASTER LE NN 276557 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 760 MASTER LE NN 276498 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 761 MASTER LE NN 276499 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 762 MASTER LE NN 276473 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 763 MASTER LE NN 276474 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 764 MASTER LE NN 276280 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 765 MASTER LE NN 276556 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 766 MASTER LE NN 276483 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 767 MASTER LE NN 276512 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 768 MASTER LE NN 276544 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 769 MASTER LE NN 276445 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 770 MASTER LE NN 276505 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 771 MASTER LE NN 276516 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 772 MASTER LE NN 276517 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 773 MASTER LE NN 276484 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 774 MASTER LE NN 276493 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 775 MASTER LE NN 276486 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 776 MASTER LE NN 276469 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 777 MASTER LE NN 276497 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 778 MASTER LE NN 276495 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 779 MASTER LE NN 276349 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX2J)
Chain[4] 780 MASTER LE NN 276431 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[4] 781 MASTER LE NN 276367 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX2J)
Chain[4] 782 MASTER LE NN 276429 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 783 MASTER LE NN 276428 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[4] 784 MASTER LE NN 276365 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 785 MASTER LE NN 276339 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 786 MASTER LE NN 276289 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 787 MASTER LE NN 276241 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 788 MASTER LE NN 276243 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 789 MASTER LE NN 276242 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 790 MASTER LE NN 276244 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 791 MASTER LE NN 276237 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 792 MASTER LE NN 276239 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 793 MASTER LE NN 276238 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 794 MASTER LE NN 276496 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 795 MASTER LE NN 276492 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 796 MASTER LE NN 276515 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 797 MASTER LE NN 276471 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 798 MASTER LE NN 276472 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 799 MASTER LE NN 276534 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 800 MASTER LE NN 276558 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 801 MASTER LE NN 276501 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 802 MASTER LE NN 276545 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 803 MASTER LE NN 276531 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 804 MASTER LE NN 276352 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 805 MASTER LE NN 276281 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 806 MASTER LE NN 276462 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX2J)
Chain[4] 807 MASTER LE NN 276518 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[4] 808 MASTER LE NN 276520 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 809 MASTER LE NN 276519 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 810 MASTER LE NN 276248 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 811 MASTER LE NN 276284 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 812 MASTER LE NN 276278 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 813 MASTER LE NN 276249 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 814 MASTER LE NN 276276 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 815 MASTER LE NN 276275 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 816 MASTER LE NN 276375 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 817 MASTER LE NN 276384 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 818 MASTER LE NN 276395 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 819 MASTER LE NN 276386 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 820 MASTER LE NN 276394 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 821 MASTER LE NN 276400 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 822 MASTER LE NN 276385 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 823 MASTER LE NN 276388 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 824 MASTER LE NN 276414 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 825 MASTER LE NN 276387 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 826 MASTER LE NN 276602 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFSBQX1)
Chain[4] 827 MASTER LE NN 276607 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFSBQX1)
Chain[4] 828 MASTER LE NN 276605 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
 Chain[4] 829 MASTER LE NN 276578 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 830 MASTER LE NN 276596 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 831 MASTER LE NN 276597 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 832 MASTER LE NN 276598 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 833 MASTER LE NN 276322 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 834 MASTER LE NN 276325 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 835 MASTER LE NN 276316 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 836 MASTER LE NN 276310 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 837 MASTER LE NN 276313 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 838 MASTER LE NN 276315 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 839 MASTER LE NN 276295 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 840 MASTER LE NN 276296 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 841 MASTER LE NN 276292 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 842 MASTER LE NN 276361 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 843 MASTER LE NN 276362 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 844 MASTER LE NN 276299 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 845 MASTER LE NN 276318 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 846 MASTER LE NN 276297 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 847 MASTER LE NN 276435 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 848 MASTER LE NN 276311 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 849 MASTER LE NN 276433 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 850 MASTER LE NN 276312 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 851 MASTER LE NN 276440 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 852 MASTER LE NN 276323 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 853 MASTER LE NN 276436 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 854 MASTER LE NN 276314 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 855 MASTER LE NN 276434 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 856 MASTER LE NN 276359 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 857 MASTER LE NN 276363 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 858 MASTER LE NN 276293 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 859 MASTER LE NN 276291 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 860 MASTER LE NN 276251 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 861 MASTER LE NN 276252 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 862 MASTER LE NN 276360 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 863 MASTER LE NN 276364 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 864 MASTER LE NN 276324 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 865 MASTER LE NN 276616 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 866 MASTER LE NN 276615 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 867 MASTER LE NN 276294 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 868 MASTER LE NN 276283 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 869 MASTER LE NN 276358 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 870 MASTER LE NN 276510 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 871 MASTER LE NN 276549 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 872 MASTER LE NN 276304 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 873 MASTER LE NN 276547 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 874 MASTER LE NN 276303 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 875 MASTER LE NN 276308 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 876 MASTER LE NN 276300 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 877 MASTER LE NN 276511 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 878 MASTER LE NN 276570 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 879 MASTER LE NN 276523 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 880 MASTER LE NN 276571 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 881 MASTER LE NN 276569 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 882 MASTER LE NN 276477 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 883 MASTER LE NN 276478 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 884 MASTER LE NN 276600 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFSBQX1)
Chain[4] 885 MASTER LE NN 276590 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 886 MASTER LE NN 276606 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 887 MASTER LE NN 276588 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 888 MASTER LE NN 276540 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 889 MASTER LE NN 276541 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 890 MASTER LE NN 276594 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 891 MASTER LE NN 276599 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 892 MASTER LE NN 276514 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 893 MASTER LE NN 276481 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 894 MASTER LE NN 276479 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 895 MASTER LE NN 276573 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 896 MASTER LE NN 276307 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 897 MASTER LE NN 276305 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 898 MASTER LE NN 276572 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 899 MASTER LE NN 276500 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 900 MASTER LE NN 276306 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 901 MASTER LE NN 276513 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 902 MASTER LE NN 276555 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[4] 903 MASTER LE NN 276446 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 904 MASTER LE NN 276508 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 905 MASTER LE NN 276475 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 906 MASTER LE NN 276476 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 907 MASTER LE NN 276507 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 908 MASTER LE NN 276489 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 909 MASTER LE NN 276491 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 910 MASTER LE NN 276504 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 911 MASTER LE NN 276490 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 912 MASTER LE NN 276470 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 913 MASTER LE NN 276506 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 914 MASTER LE NN 276494 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 915 MASTER LE NN 276482 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 916 MASTER LE NN 276502 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 917 MASTER LE NN 276487 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 918 MASTER LE NN 276509 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 919 MASTER LE NN 276503 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 920 MASTER LE NN 276485 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 921 MASTER LE NN 276559 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 922 MASTER LE NN 276488 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 923 MASTER LE NN 276575 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 924 MASTER LE NN 276574 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 925 MASTER LE NN 276560 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 926 MASTER LE NN 276480 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 927 MASTER LE NN 276467 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 928 MASTER LE NN 276468 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 929 MASTER LE NN 276466 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 930 MASTER LE NN 276568 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 931 MASTER LE NN 276543 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 932 MASTER LE NN 276565 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 933 MASTER LE NN 276566 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 934 MASTER LE NN 276604 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
 Chain[4] 935 MASTER LE NN 276603 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 936 MASTER LE NN 276617 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 937 MASTER LE NN 276618 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 938 MASTER LE NN 276579 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 939 MASTER LE NN 276577 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 940 MASTER LE NN 276576 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 941 MASTER LE NN 276437 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 942 MASTER LE NN 276438 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 943 MASTER LE NN 276439 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 944 MASTER LE NN 276326 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 945 MASTER LE NN 276309 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 946 MASTER LE NN 276317 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 947 MASTER LE NN 276321 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 948 MASTER LE NN 276298 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 949 MASTER LE NN 276595 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
 Chain[4] 950 MASTER LE NN 276593 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 951 MASTER LE NN 276591 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 952 MASTER LE NN 276609 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 953 MASTER LE NN 276580 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 954 MASTER LE NN 276608 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 955 MASTER LE NN 276582 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 956 MASTER LE NN 276592 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 957 MASTER LE NN 276584 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 958 MASTER LE NN 276586 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 959 MASTER LE NN 276536 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 960 MASTER LE NN 276561 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 961 MASTER LE NN 276562 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 962 MASTER LE NN 276564 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 963 MASTER LE NN 276539 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 964 MASTER LE NN 276542 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 965 MASTER LE NN 276567 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 966 MASTER LE NN 276563 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 967 MASTER LE NN 276537 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 968 MASTER LE NN 276538 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 969 MASTER LE NN 276601 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 970 MASTER LE NN 276610 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 971 MASTER LE NN 276612 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 972 MASTER LE NN 276613 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 973 MASTER LE NN 276611 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 974 MASTER LE NN 276581 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 975 MASTER LE NN 276583 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 976 MASTER LE NN 276585 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 977 MASTER LE NN 276587 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 978 MASTER LE NN 276589 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 979 MASTER LE NN 276320 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 980 MASTER LE NN 276319 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[2]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 981 MASTER LE NN 276054 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256799 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX2)
Chain[4] 982 MASTER LE NN 276040 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 983 MASTER LE NN 276050 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 984 MASTER LE NN 276052 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 985 MASTER LE NN 276048 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 986 MASTER LE NN 276044 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 987 MASTER LE NN 276053 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 988 MASTER LE NN 276049 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 989 MASTER LE NN 276076 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 990 MASTER LE NN 276046 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 991 MASTER LE NN 276038 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 992 MASTER LE NN 276045 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 993 MASTER LE NN 276047 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 994 MASTER LE NN 276015 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 995 MASTER LE NN 276036 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 996 MASTER LE NN 276051 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 997 MASTER LE NN 276074 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 998 MASTER LE NN 276041 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 999 MASTER LE NN 276028 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1000 MASTER LE NN 276031 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1001 MASTER LE NN 276201 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1002 MASTER LE NN 276211 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1003 MASTER LE NN 276032 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1004 MASTER LE NN 276024 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1005 MASTER LE NN 276033 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1006 MASTER LE NN 276029 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1007 MASTER LE NN 276026 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1008 MASTER LE NN 276034 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1009 MASTER LE NN 276039 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1010 MASTER LE NN 276035 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1011 MASTER LE NN 276020 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1012 MASTER LE NN 276018 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1013 MASTER LE NN 276075 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1014 MASTER LE NN 276027 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1015 MASTER LE NN 275933 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1016 MASTER LE NN 276037 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1017 MASTER LE NN 276014 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1018 MASTER LE NN 276017 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1019 MASTER LE NN 276013 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1020 MASTER LE NN 275946 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1021 MASTER LE NN 275949 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1022 MASTER LE NN 275965 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1023 MASTER LE NN 275993 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1024 MASTER LE NN 276007 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1025 MASTER LE NN 275932 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1026 MASTER LE NN 275935 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1027 MASTER LE NN 275934 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1028 MASTER LE NN 276021 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1029 MASTER LE NN 276022 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 1030 MASTER LE NN 276023 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1031 MASTER LE NN 276019 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1032 MASTER LE NN 275940 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1033 MASTER LE NN 275939 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1034 MASTER LE NN 275938 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1035 MASTER LE NN 275937 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1036 MASTER LE NN 276150 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1037 MASTER LE NN 276152 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1038 MASTER LE NN 276008 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1039 MASTER LE NN 275924 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1040 MASTER LE NN 275927 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1041 MASTER LE NN 275936 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1042 MASTER LE NN 275926 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1043 MASTER LE NN 275922 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1044 MASTER LE NN 275925 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1045 MASTER LE NN 275923 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1046 MASTER LE NN 275921 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1047 MASTER LE NN 275931 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1048 MASTER LE NN 275994 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1049 MASTER LE NN 275951 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1050 MASTER LE NN 275950 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1051 MASTER LE NN 276154 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1052 MASTER LE NN 275952 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1053 MASTER LE NN 275963 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1054 MASTER LE NN 276148 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1055 MASTER LE NN 276156 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1056 MASTER LE NN 275920 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1057 MASTER LE NN 275945 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1058 MASTER LE NN 275966 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1059 MASTER LE NN 275948 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1060 MASTER LE NN 275947 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1061 MASTER LE NN 276025 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1062 MASTER LE NN 276030 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1063 MASTER LE NN 276043 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1064 MASTER LE NN 276042 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1065 MASTER LE NN 276073 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
 Chain[4] 1066 MASTER LE NN 276203 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1067 MASTER LE NN 276199 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1068 MASTER LE NN 276209 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1069 MASTER LE NN 276205 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1070 MASTER LE NN 276207 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1071 MASTER LE NN 276226 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1072 MASTER LE NN 276200 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1073 MASTER LE NN 276225 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1074 MASTER LE NN 276198 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1075 MASTER LE NN 276206 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1076 MASTER LE NN 276222 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1077 MASTER LE NN 276224 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1078 MASTER LE NN 276228 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1079 MASTER LE NN 276194 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1080 MASTER LE NN 276215 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1081 MASTER LE NN 276213 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1082 MASTER LE NN 276195 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1083 MASTER LE NN 276230 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1084 MASTER LE NN 276193 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1085 MASTER LE NN 276231 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1086 MASTER LE NN 276197 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1087 MASTER LE NN 276189 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1088 MASTER LE NN 276142 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1089 MASTER LE NN 276096 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1090 MASTER LE NN 276098 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1091 MASTER LE NN 276107 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1092 MASTER LE NN 276010 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1093 MASTER LE NN 276016 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1094 MASTER LE NN 276012 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1095 MASTER LE NN 276011 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1096 MASTER LE NN 276009 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1097 MASTER LE NN 276141 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1098 MASTER LE NN 276110 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1099 MASTER LE NN 276108 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1100 MASTER LE NN 276140 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1101 MASTER LE NN 276174 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1102 MASTER LE NN 276109 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1103 MASTER LE NN 276071 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1104 MASTER LE NN 275959 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1105 MASTER LE NN 276117 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1106 MASTER LE NN 276191 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1107 MASTER LE NN 275960 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1108 MASTER LE NN 275962 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1109 MASTER LE NN 275961 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1110 MASTER LE NN 276134 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1111 MASTER LE NN 276161 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1112 MASTER LE NN 276113 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1113 MASTER LE NN 276173 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1114 MASTER LE NN 276100 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1115 MASTER LE NN 276162 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1116 MASTER LE NN 276102 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1117 MASTER LE NN 276105 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1118 MASTER LE NN 276172 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1119 MASTER LE NN 276157 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1120 MASTER LE NN 276158 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1121 MASTER LE NN 275953 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1122 MASTER LE NN 276159 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1123 MASTER LE NN 276151 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1124 MASTER LE NN 276149 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1125 MASTER LE NN 275964 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1126 MASTER LE NN 276147 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1127 MASTER LE NN 276146 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
 Chain[4] 1128 MASTER LE NN 276153 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1129 MASTER LE NN 276155 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1130 MASTER LE NN 276092 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1131 MASTER LE NN 276000 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1132 MASTER LE NN 275971 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1133 MASTER LE NN 276056 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1134 MASTER LE NN 276055 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1135 MASTER LE NN 276061 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1136 MASTER LE NN 276059 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1137 MASTER LE NN 276077 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1138 MASTER LE NN 276078 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1139 MASTER LE NN 276057 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1140 MASTER LE NN 276060 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1141 MASTER LE NN 276062 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1142 MASTER LE NN 276065 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1143 MASTER LE NN 275944 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1144 MASTER LE NN 275968 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1145 MASTER LE NN 275967 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1146 MASTER LE NN 275915 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1147 MASTER LE NN 275916 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1148 MASTER LE NN 275911 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1149 MASTER LE NN 275913 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1150 MASTER LE NN 275917 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1151 MASTER LE NN 275910 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1152 MASTER LE NN 275969 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1153 MASTER LE NN 275942 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1154 MASTER LE NN 276064 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1155 MASTER LE NN 275941 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1156 MASTER LE NN 276063 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1157 MASTER LE NN 275999 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1158 MASTER LE NN 276001 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1159 MASTER LE NN 276129 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1160 MASTER LE NN 276104 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1161 MASTER LE NN 276103 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1162 MASTER LE NN 276160 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1163 MASTER LE NN 276163 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[4] 1164 MASTER LE NN 275995 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1165 MASTER LE NN 276188 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1166 MASTER LE NN 276058 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1167 MASTER LE NN 276006 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1168 MASTER LE NN 276005 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1169 MASTER LE NN 276101 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1170 MASTER LE NN 276128 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1171 MASTER LE NN 276130 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1172 MASTER LE NN 276192 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1173 MASTER LE NN 276187 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1174 MASTER LE NN 276097 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1175 MASTER LE NN 276139 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1176 MASTER LE NN 276106 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1177 MASTER LE NN 276186 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1178 MASTER LE NN 276099 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1179 MASTER LE NN 276229 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1180 MASTER LE NN 276196 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1181 MASTER LE NN 276212 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1182 MASTER LE NN 276214 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1183 MASTER LE NN 276232 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1184 MASTER LE NN 276204 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1185 MASTER LE NN 276227 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1186 MASTER LE NN 276208 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1187 MASTER LE NN 276202 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1188 MASTER LE NN 276220 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1189 MASTER LE NN 276218 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1190 MASTER LE NN 276223 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1191 MASTER LE NN 276167 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1192 MASTER LE NN 276165 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1193 MASTER LE NN 276184 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 1194 MASTER LE NN 276168 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1195 MASTER LE NN 276166 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1196 MASTER LE NN 276170 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1197 MASTER LE NN 276182 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1198 MASTER LE NN 276179 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1199 MASTER LE NN 276221 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1200 MASTER LE NN 276219 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1201 MASTER LE NN 276164 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1202 MASTER LE NN 276210 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1203 MASTER LE NN 276216 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1204 MASTER LE NN 276217 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1205 MASTER LE NN 276169 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1206 MASTER LE NN 276183 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1207 MASTER LE NN 276171 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1208 MASTER LE NN 276185 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1209 MASTER LE NN 276181 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1210 MASTER LE NN 276180 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1211 MASTER LE NN 276178 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1212 MASTER LE NN 275988 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1213 MASTER LE NN 275987 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1214 MASTER LE NN 276070 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 1215 MASTER LE NN 276068 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1216 MASTER LE NN 275975 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1217 MASTER LE NN 275974 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1218 MASTER LE NN 275996 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1219 MASTER LE NN 275997 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1220 MASTER LE NN 275929 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1221 MASTER LE NN 275930 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1222 MASTER LE NN 275977 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1223 MASTER LE NN 275976 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1224 MASTER LE NN 276177 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 1225 MASTER LE NN 275958 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1226 MASTER LE NN 275955 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1227 MASTER LE NN 276138 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1228 MASTER LE NN 276190 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1229 MASTER LE NN 276072 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1230 MASTER LE NN 276175 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1231 MASTER LE NN 276137 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1232 MASTER LE NN 275954 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1233 MASTER LE NN 276111 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1234 MASTER LE NN 276176 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1235 MASTER LE NN 276131 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1236 MASTER LE NN 276119 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1237 MASTER LE NN 276121 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1238 MASTER LE NN 276133 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1239 MASTER LE NN 276136 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1240 MASTER LE NN 276132 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1241 MASTER LE NN 276118 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1242 MASTER LE NN 276120 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1243 MASTER LE NN 276112 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1244 MASTER LE NN 276115 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1245 MASTER LE NN 276122 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1246 MASTER LE NN 276123 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1247 MASTER LE NN 276116 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1248 MASTER LE NN 276125 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1249 MASTER LE NN 276066 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1250 MASTER LE NN 276124 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1251 MASTER LE NN 275983 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1252 MASTER LE NN 275972 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1253 MASTER LE NN 275943 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1254 MASTER LE NN 276080 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1255 MASTER LE NN 276082 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1256 MASTER LE NN 276081 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
 Chain[4] 1257 MASTER LE NN 276003 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1258 MASTER LE NN 276004 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1259 MASTER LE NN 276002 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1260 MASTER LE NN 275992 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1261 MASTER LE NN 275984 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1262 MASTER LE NN 275979 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1263 MASTER LE NN 275978 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1264 MASTER LE NN 275906 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1265 MASTER LE NN 275919 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1266 MASTER LE NN 275908 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1267 MASTER LE NN 275914 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1268 MASTER LE NN 275907 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1269 MASTER LE NN 275918 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1270 MASTER LE NN 275912 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1271 MASTER LE NN 275909 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1272 MASTER LE NN 275973 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1273 MASTER LE NN 275970 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1274 MASTER LE NN 276079 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1275 MASTER LE NN 276126 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1276 MASTER LE NN 276145 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1277 MASTER LE NN 276127 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1278 MASTER LE NN 276143 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1279 MASTER LE NN 276144 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1280 MASTER LE NN 276135 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1281 MASTER LE NN 275956 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1282 MASTER LE NN 275957 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1283 MASTER LE NN 276114 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1284 MASTER LE NN 275986 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1285 MASTER LE NN 276067 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1286 MASTER LE NN 275998 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1287 MASTER LE NN 275982 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1288 MASTER LE NN 276233 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1289 MASTER LE NN 275985 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1290 MASTER LE NN 275928 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1291 MASTER LE NN 275981 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1292 MASTER LE NN 275980 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1293 MASTER LE NN 276069 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1294 MASTER LE NN 275991 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1295 MASTER LE NN 275990 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1296 MASTER LE NN 275989 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[1]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1297 MASTER LE NN 275711 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256771 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX3)
Chain[4] 1298 MASTER LE NN 275667 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1299 MASTER LE NN 275669 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1300 MASTER LE NN 275674 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1301 MASTER LE NN 275678 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1302 MASTER LE NN 275679 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1303 MASTER LE NN 275675 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1304 MASTER LE NN 275668 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1305 MASTER LE NN 275680 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1306 MASTER LE NN 275905 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1307 MASTER LE NN 275864 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1308 MASTER LE NN 275873 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1309 MASTER LE NN 275877 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1310 MASTER LE NN 275548 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1311 MASTER LE NN 275624 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1312 MASTER LE NN 275623 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1313 MASTER LE NN 275622 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1314 MASTER LE NN 275681 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1315 MASTER LE NN 275676 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1316 MASTER LE NN 275736 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1317 MASTER LE NN 275625 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1318 MASTER LE NN 275733 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1319 MASTER LE NN 275631 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1320 MASTER LE NN 275630 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1321 MASTER LE NN 275629 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 1322 MASTER LE NN 275632 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1323 MASTER LE NN 275633 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1324 MASTER LE NN 275635 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1325 MASTER LE NN 275577 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1326 MASTER LE NN 275728 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 1327 MASTER LE NN 275578 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1328 MASTER LE NN 275627 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1329 MASTER LE NN 275636 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1330 MASTER LE NN 275626 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1331 MASTER LE NN 275628 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1332 MASTER LE NN 275621 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1333 MASTER LE NN 275677 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1334 MASTER LE NN 275672 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1335 MASTER LE NN 275673 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1336 MASTER LE NN 275670 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1337 MASTER LE NN 275671 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1338 MASTER LE NN 275666 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1339 MASTER LE NN 275865 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1340 MASTER LE NN 275879 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1341 MASTER LE NN 275867 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1342 MASTER LE NN 275550 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1343 MASTER LE NN 275551 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1344 MASTER LE NN 275871 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1345 MASTER LE NN 275718 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1346 MASTER LE NN 275869 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1347 MASTER LE NN 275721 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1348 MASTER LE NN 275720 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1349 MASTER LE NN 275725 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1350 MASTER LE NN 275722 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1351 MASTER LE NN 275709 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1352 MASTER LE NN 275743 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1353 MASTER LE NN 275726 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1354 MASTER LE NN 275708 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1355 MASTER LE NN 275719 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1356 MASTER LE NN 275898 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1357 MASTER LE NN 275892 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1358 MASTER LE NN 275868 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1359 MASTER LE NN 275895 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1360 MASTER LE NN 275874 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1361 MASTER LE NN 275893 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1362 MASTER LE NN 275878 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1363 MASTER LE NN 275887 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1364 MASTER LE NN 275891 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1365 MASTER LE NN 275872 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1366 MASTER LE NN 275870 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1367 MASTER LE NN 275889 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1368 MASTER LE NN 275902 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1369 MASTER LE NN 275888 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1370 MASTER LE NN 275894 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1371 MASTER LE NN 275890 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1372 MASTER LE NN 275710 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1373 MASTER LE NN 275571 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1374 MASTER LE NN 275570 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1375 MASTER LE NN 275741 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1376 MASTER LE NN 275723 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1377 MASTER LE NN 275744 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1378 MASTER LE NN 275739 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1379 MASTER LE NN 275737 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1380 MASTER LE NN 275900 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1381 MASTER LE NN 275712 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1382 MASTER LE NN 275713 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1383 MASTER LE NN 275715 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1384 MASTER LE NN 275740 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1385 MASTER LE NN 275717 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1386 MASTER LE NN 275697 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1387 MASTER LE NN 275698 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1388 MASTER LE NN 275702 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1389 MASTER LE NN 275696 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1390 MASTER LE NN 275701 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1391 MASTER LE NN 275572 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1392 MASTER LE NN 275700 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1393 MASTER LE NN 275707 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1394 MASTER LE NN 275807 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1395 MASTER LE NN 275809 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1396 MASTER LE NN 275543 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1397 MASTER LE NN 275538 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1398 MASTER LE NN 275618 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1399 MASTER LE NN 275542 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1400 MASTER LE NN 275540 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 1401 MASTER LE NN 275541 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1402 MASTER LE NN 275516 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1403 MASTER LE NN 275544 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1404 MASTER LE NN 275545 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1405 MASTER LE NN 275705 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1406 MASTER LE NN 275706 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1407 MASTER LE NN 275704 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1408 MASTER LE NN 275703 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1409 MASTER LE NN 275738 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1410 MASTER LE NN 275714 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1411 MASTER LE NN 275716 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1412 MASTER LE NN 275724 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1413 MASTER LE NN 275742 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1414 MASTER LE NN 275727 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1415 MASTER LE NN 275896 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1416 MASTER LE NN 275899 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1417 MASTER LE NN 275875 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1418 MASTER LE NN 275549 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1419 MASTER LE NN 275555 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1420 MASTER LE NN 275620 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1421 MASTER LE NN 275556 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1422 MASTER LE NN 275554 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1423 MASTER LE NN 275729 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 1424 MASTER LE NN 275553 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1425 MASTER LE NN 275552 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1426 MASTER LE NN 275904 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1427 MASTER LE NN 275876 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1428 MASTER LE NN 275843 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1429 MASTER LE NN 275886 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1430 MASTER LE NN 275823 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1431 MASTER LE NN 275750 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1432 MASTER LE NN 275749 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1433 MASTER LE NN 275754 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1434 MASTER LE NN 275755 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1435 MASTER LE NN 275751 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1436 MASTER LE NN 275842 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/BYPASS_CTL1_0_array_u_BYPASS_CTL1_0__SMART_BYPASS_E
NTRY_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1437 MASTER LE NN 275682 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1438 MASTER LE NN 275529 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1439 MASTER LE NN 275527 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1440 MASTER LE NN 275665 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1441 MASTER LE NN 275518 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1442 MASTER LE NN 275557 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1443 MASTER LE NN 275573 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1444 MASTER LE NN 275694 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1445 MASTER LE NN 275531 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1446 MASTER LE NN 275699 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1447 MASTER LE NN 275695 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1448 MASTER LE NN 275575 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1449 MASTER LE NN 275569 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
 Chain[4] 1450 MASTER LE NN 275559 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1451 MASTER LE NN 275819 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1452 MASTER LE NN 275818 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1453 MASTER LE NN 275523 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1454 MASTER LE NN 275526 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1455 MASTER LE NN 275524 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1456 MASTER LE NN 275525 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1457 MASTER LE NN 275522 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1458 MASTER LE NN 275528 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1459 MASTER LE NN 275640 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1460 MASTER LE NN 275619 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1461 MASTER LE NN 275641 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1462 MASTER LE NN 275644 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1463 MASTER LE NN 275651 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1464 MASTER LE NN 275648 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1465 MASTER LE NN 275805 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1466 MASTER LE NN 275804 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1467 MASTER LE NN 275560 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1468 MASTER LE NN 275561 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1469 MASTER LE NN 275591 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1470 MASTER LE NN 275590 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1471 MASTER LE NN 275521 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1472 MASTER LE NN 275647 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1473 MASTER LE NN 275519 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1474 MASTER LE NN 275596 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1475 MASTER LE NN 275615 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_pfet_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1476 MASTER LE NN 275730 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1477 MASTER LE NN 275566 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1478 MASTER LE NN 275689 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_stepdn_det_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1479 MASTER LE NN 275687 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1480 MASTER LE NN 275688 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1481 MASTER LE NN 275637 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_meta_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1482 MASTER LE NN 275638 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1483 MASTER LE NN 275534 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1484 MASTER LE NN 275685 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1485 MASTER LE NN 275535 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1486 MASTER LE NN 275692 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1487 MASTER LE NN 275811 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1488 MASTER LE NN 275813 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1489 MASTER LE NN 275693 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1490 MASTER LE NN 275536 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1491 MASTER LE NN 275537 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1492 MASTER LE NN 275517 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1493 MASTER LE NN 275539 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1494 MASTER LE NN 275617 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1495 MASTER LE NN 275592 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1496 MASTER LE NN 275612 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 1497 MASTER LE NN 275613 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1498 MASTER LE NN 275616 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1499 MASTER LE NN 275610 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1500 MASTER LE NN 275691 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1501 MASTER LE NN 275690 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1502 MASTER LE NN 275684 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1503 MASTER LE NN 275593 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1504 MASTER LE NN 275565 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1505 MASTER LE NN 275563 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1506 MASTER LE NN 275597 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1507 MASTER LE NN 275567 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1508 MASTER LE NN 275614 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1509 MASTER LE NN 275564 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1510 MASTER LE NN 275686 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1511 MASTER LE NN 275683 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1512 MASTER LE NN 275533 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1513 MASTER LE NN 275532 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1514 MASTER LE NN 275558 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1515 MASTER LE NN 275574 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1516 MASTER LE NN 275664 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1517 MASTER LE NN 275853 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1518 MASTER LE NN 275844 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1519 MASTER LE NN 275814 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC_CTL1__READY_STEPDOWN_QUAL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1520 MASTER LE NN 275860 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1521 MASTER LE NN 275822 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1522 MASTER LE NN 275849 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1523 MASTER LE NN 275826 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1524 MASTER LE NN 275845 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1525 MASTER LE NN 275852 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1526 MASTER LE NN 275846 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1527 MASTER LE NN 275829 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1528 MASTER LE NN 275851 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 1529 MASTER LE NN 275850 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1530 MASTER LE NN 275828 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1531 MASTER LE NN 275827 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1532 MASTER LE NN 275847 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1533 MASTER LE NN 275884 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1534 MASTER LE NN 275885 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1535 MASTER LE NN 275848 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1536 MASTER LE NN 275883 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1537 MASTER LE NN 275897 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1538 MASTER LE NN 275862 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1539 MASTER LE NN 275824 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1540 MASTER LE NN 275861 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1541 MASTER LE NN 275866 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1542 MASTER LE NN 275863 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1543 MASTER LE NN 275825 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1544 MASTER LE NN 275634 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1545 MASTER LE NN 275576 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1546 MASTER LE NN 275796 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1547 MASTER LE NN 275759 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1548 MASTER LE NN 275764 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1549 MASTER LE NN 275761 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1550 MASTER LE NN 275760 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1551 MASTER LE NN 275837 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 1552 MASTER LE NN 275762 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1553 MASTER LE NN 275776 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1554 MASTER LE NN 275795 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1555 MASTER LE NN 275784 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PLOW_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1556 MASTER LE NN 275840 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 1557 MASTER LE NN 275767 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1558 MASTER LE NN 275789 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PLOW_CLAMP_THR_CONFIG_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1559 MASTER LE NN 275757 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1560 MASTER LE NN 275752 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1561 MASTER LE NN 275763 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1562 MASTER LE NN 275797 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1563 MASTER LE NN 275799 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1564 MASTER LE NN 275798 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1565 MASTER LE NN 275817 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1566 MASTER LE NN 275816 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1567 MASTER LE NN 275756 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1568 MASTER LE NN 275645 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1569 MASTER LE NN 275639 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1570 MASTER LE NN 275643 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1571 MASTER LE NN 275642 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1572 MASTER LE NN 275803 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[4] 1573 MASTER LE NN 275812 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1574 MASTER LE NN 275810 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1575 MASTER LE NN 275646 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1576 MASTER LE NN 275821 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1577 MASTER LE NN 275820 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1578 MASTER LE NN 275731 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1579 MASTER LE NN 275808 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1580 MASTER LE NN 275854 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1581 MASTER LE NN 275857 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1582 MASTER LE NN 275753 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1583 MASTER LE NN 275781 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_LPM_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1584 MASTER LE NN 275790 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1585 MASTER LE NN 275794 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1586 MASTER LE NN 275802 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1587 MASTER LE NN 275856 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1588 MASTER LE NN 275859 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1589 MASTER LE NN 275732 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
 Chain[4] 1590 MASTER LE NN 275579 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1591 MASTER LE NN 275801 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1592 MASTER LE NN 275831 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1593 MASTER LE NN 275832 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1594 MASTER LE NN 275858 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1595 MASTER LE NN 275834 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1596 MASTER LE NN 275773 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1597 MASTER LE NN 275793 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[1
] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1598 MASTER LE NN 275785 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD1_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1599 MASTER LE NN 275758 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1600 MASTER LE NN 275841 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 1601 MASTER LE NN 275791 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG2_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1602 MASTER LE NN 275792 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG3_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1603 MASTER LE NN 275882 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__VOLTAGE_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1604 MASTER LE NN 275881 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[4] 1605 MASTER LE NN 275780 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_BOT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1606 MASTER LE NN 275772 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1607 MASTER LE NN 275786 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD2_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1608 MASTER LE NN 275880 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1609 MASTER LE NN 275607 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1610 MASTER LE NN 275735 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1611 MASTER LE NN 275779 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1612 MASTER LE NN 275777 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1613 MASTER LE NN 275830 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1614 MASTER LE NN 275652 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1615 MASTER LE NN 275734 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1616 MASTER LE NN 275653 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_
u/GEN_PBUS_BUFF_STEPPER_DONE_d_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1617 MASTER LE NN 275835 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1618 MASTER LE NN 275855 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1619 MASTER LE NN 275815 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1620 MASTER LE NN 275595 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1621 MASTER LE NN 275806 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1622 MASTER LE NN 275833 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1623 MASTER LE NN 275547 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_int_soft_start_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1624 MASTER LE NN 275581 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1625 MASTER LE NN 275562 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1626 MASTER LE NN 275903 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1627 MASTER LE NN 275650 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_eq_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1628 MASTER LE NN 275520 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1629 MASTER LE NN 275530 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1630 MASTER LE NN 275588 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1631 MASTER LE NN 275580 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1632 MASTER LE NN 275603 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1633 MASTER LE NN 275601 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1634 MASTER LE NN 275602 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1635 MASTER LE NN 275600 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 1636 MASTER LE NN 275604 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1637 MASTER LE NN 275582 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1638 MASTER LE NN 275584 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1639 MASTER LE NN 275589 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1640 MASTER LE NN 275568 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_dly_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1641 MASTER LE NN 275585 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1642 MASTER LE NN 275594 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1643 MASTER LE NN 275599 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1644 MASTER LE NN 275587 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1645 MASTER LE NN 275586 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1646 MASTER LE NN 275608 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1647 MASTER LE NN 275605 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1648 MASTER LE NN 275611 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_narrow_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1649 MASTER LE NN 275598 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_wide_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1650 MASTER LE NN 275609 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1651 MASTER LE NN 275583 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1652 MASTER LE NN 275649 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_gt_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1653 MASTER LE NN 275606 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1654 MASTER LE NN 275659 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1655 MASTER LE NN 275774 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1656 MASTER LE NN 275778 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1657 MASTER LE NN 275775 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1658 MASTER LE NN 275657 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1659 MASTER LE NN 275787 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__OCP_THR_CONFIG_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1660 MASTER LE NN 275788 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PUP_CLAMP_THR_CONFIG_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1661 MASTER LE NN 275783 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PUP_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1662 MASTER LE NN 275800 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1663 MASTER LE NN 275838 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 1664 MASTER LE NN 275839 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 1665 MASTER LE NN 275836 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 1666 MASTER LE NN 275901 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX2)
Chain[4] 1667 MASTER LE NN 275771 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1668 MASTER LE NN 275768 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1669 MASTER LE NN 275765 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1670 MASTER LE NN 275769 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1671 MASTER LE NN 275766 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1672 MASTER LE NN 275782 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_EA_CONFIG_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1673 MASTER LE NN 275660 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1674 MASTER LE NN 275654 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1675 MASTER LE NN 275656 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1676 MASTER LE NN 275663 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1677 MASTER LE NN 275504 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1678 MASTER LE NN 275502 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1679 MASTER LE NN 275507 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1680 MASTER LE NN 275508 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
 Chain[4] 1681 MASTER LE NN 275503 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1682 MASTER LE NN 275510 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1683 MASTER LE NN 275512 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1684 MASTER LE NN 275511 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1685 MASTER LE NN 275513 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1686 MASTER LE NN 275509 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1687 MASTER LE NN 275506 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1688 MASTER LE NN 275514 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1689 MASTER LE NN 275505 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1690 MASTER LE NN 275515 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1691 MASTER LE NN 275658 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1692 MASTER LE NN 275661 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1693 MASTER LE NN 275662 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1694 MASTER LE NN 275546 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1695 MASTER LE NN 275655 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1696 MASTER LE NN 275770 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[9]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1697 MASTER LE NN 275309 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
 DSLAVE LS NN 256746 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX1)
Chain[4] 1698 MASTER LE NN 275308 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1699 MASTER LE NN 275312 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1700 MASTER LE NN 275334 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1701 MASTER LE NN 275296 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1702 MASTER LE NN 275297 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1703 MASTER LE NN 275299 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1704 MASTER LE NN 275306 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1705 MASTER LE NN 275300 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1706 MASTER LE NN 275293 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1707 MASTER LE NN 275151 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1708 MASTER LE NN 275219 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1709 MASTER LE NN 275269 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1710 MASTER LE NN 275270 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1711 MASTER LE NN 275267 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1712 MASTER LE NN 275266 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1713 MASTER LE NN 275268 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1714 MASTER LE NN 275265 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1715 MASTER LE NN 275275 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1716 MASTER LE NN 275230 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1717 MASTER LE NN 275325 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 1718 MASTER LE NN 275218 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1719 MASTER LE NN 275272 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1720 MASTER LE NN 275276 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1721 MASTER LE NN 275264 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1722 MASTER LE NN 275274 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1723 MASTER LE NN 275148 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1724 MASTER LE NN 275220 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1725 MASTER LE NN 275152 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1726 MASTER LE NN 275147 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1727 MASTER LE NN 275167 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1728 MASTER LE NN 275409 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1729 MASTER LE NN 275169 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1730 MASTER LE NN 275129 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1731 MASTER LE NN 275131 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1732 MASTER LE NN 275145 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1733 MASTER LE NN 275273 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1734 MASTER LE NN 275149 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1735 MASTER LE NN 275222 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1736 MASTER LE NN 275217 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1737 MASTER LE NN 275326 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 1738 MASTER LE NN 275225 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1739 MASTER LE NN 275333 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1740 MASTER LE NN 275277 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1741 MASTER LE NN 275271 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1742 MASTER LE NN 275221 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1743 MASTER LE NN 275228 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1744 MASTER LE NN 275227 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1745 MASTER LE NN 275226 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1746 MASTER LE NN 275232 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1747 MASTER LE NN 275330 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
 Chain[4] 1748 MASTER LE NN 275223 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1749 MASTER LE NN 275229 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1750 MASTER LE NN 275224 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1751 MASTER LE NN 275172 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1752 MASTER LE NN 275150 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1753 MASTER LE NN 275140 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1754 MASTER LE NN 275133 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1755 MASTER LE NN 275407 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1756 MASTER LE NN 275405 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1757 MASTER LE NN 275113 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1758 MASTER LE NN 275134 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1759 MASTER LE NN 275136 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1760 MASTER LE NN 275139 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1761 MASTER LE NN 275137 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1762 MASTER LE NN 275216 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1763 MASTER LE NN 275173 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1764 MASTER LE NN 275231 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1765 MASTER LE NN 275174 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1766 MASTER LE NN 275263 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1767 MASTER LE NN 275262 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1768 MASTER LE NN 275138 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1769 MASTER LE NN 275112 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1770 MASTER LE NN 275141 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1771 MASTER LE NN 275132 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1772 MASTER LE NN 275128 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1773 MASTER LE NN 275144 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1774 MASTER LE NN 275168 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1775 MASTER LE NN 275146 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1776 MASTER LE NN 275166 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1777 MASTER LE NN 275294 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1778 MASTER LE NN 275302 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1779 MASTER LE NN 275301 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1780 MASTER LE NN 275292 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1781 MASTER LE NN 275311 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1782 MASTER LE NN 275314 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1783 MASTER LE NN 275305 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1784 MASTER LE NN 275307 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1785 MASTER LE NN 275335 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1786 MASTER LE NN 275500 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1787 MASTER LE NN 275471 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1788 MASTER LE NN 275318 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1789 MASTER LE NN 275317 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1790 MASTER LE NN 275319 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1791 MASTER LE NN 275324 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1792 MASTER LE NN 275341 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1793 MASTER LE NN 275340 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1794 MASTER LE NN 275323 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1795 MASTER LE NN 275322 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1796 MASTER LE NN 275320 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1797 MASTER LE NN 275338 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFSBQX1)
 Chain[4] 1798 MASTER LE NN 275315 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1799 MASTER LE NN 275339 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1800 MASTER LE NN 275321 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1801 MASTER LE NN 275313 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1802 MASTER LE NN 275336 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1803 MASTER LE NN 275337 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1804 MASTER LE NN 275298 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1805 MASTER LE NN 275310 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1806 MASTER LE NN 275303 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1807 MASTER LE NN 275304 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1808 MASTER LE NN 275316 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1809 MASTER LE NN 275295 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1810 MASTER LE NN 275401 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[4] 1811 MASTER LE NN 275239 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1812 MASTER LE NN 275124 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 1813 MASTER LE NN 275402 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1814 MASTER LE NN 275403 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1815 MASTER LE NN 275411 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1816 MASTER LE NN 275165 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1817 MASTER LE NN 275291 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1818 MASTER LE NN 275290 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1819 MASTER LE NN 275120 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1820 MASTER LE NN 275121 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1821 MASTER LE NN 275119 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1822 MASTER LE NN 275118 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1823 MASTER LE NN 275122 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1824 MASTER LE NN 275125 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1825 MASTER LE NN 275123 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1826 MASTER LE NN 275236 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 1827 MASTER LE NN 275238 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1828 MASTER LE NN 275235 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1829 MASTER LE NN 275215 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1830 MASTER LE NN 275261 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1831 MASTER LE NN 275237 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1832 MASTER LE NN 275175 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1833 MASTER LE NN 275260 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1834 MASTER LE NN 275114 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1835 MASTER LE NN 275416 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1836 MASTER LE NN 275417 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1837 MASTER LE NN 275170 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1838 MASTER LE NN 275130 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1839 MASTER LE NN 275289 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1840 MASTER LE NN 275127 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1841 MASTER LE NN 275288 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1842 MASTER LE NN 275171 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1843 MASTER LE NN 275154 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1844 MASTER LE NN 275153 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1845 MASTER LE NN 275155 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1846 MASTER LE NN 275251 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1847 MASTER LE NN 275250 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1848 MASTER LE NN 275252 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1849 MASTER LE NN 275253 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1850 MASTER LE NN 275284 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1851 MASTER LE NN 275244 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1852 MASTER LE NN 275143 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_int_soft_start_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1853 MASTER LE NN 275243 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1854 MASTER LE NN 275247 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1855 MASTER LE NN 275286 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1856 MASTER LE NN 275135 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1857 MASTER LE NN 275287 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1858 MASTER LE NN 275126 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
 Chain[4] 1859 MASTER LE NN 275246 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_eq_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1860 MASTER LE NN 275233 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_meta_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1861 MASTER LE NN 275234 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1862 MASTER LE NN 275245 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_gt_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1863 MASTER LE NN 275282 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1864 MASTER LE NN 275279 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1865 MASTER LE NN 275280 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1866 MASTER LE NN 275187 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1867 MASTER LE NN 275186 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1868 MASTER LE NN 275210 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1869 MASTER LE NN 275213 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1870 MASTER LE NN 275188 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1871 MASTER LE NN 275214 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1872 MASTER LE NN 275209 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1873 MASTER LE NN 275208 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1874 MASTER LE NN 275206 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 1875 MASTER LE NN 275281 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1876 MASTER LE NN 275258 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1877 MASTER LE NN 275259 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1878 MASTER LE NN 275142 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1879 MASTER LE NN 275285 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_stepdn_det_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1880 MASTER LE NN 275283 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1881 MASTER LE NN 275157 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1882 MASTER LE NN 275156 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1883 MASTER LE NN 275249 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_
u/GEN_PBUS_BUFF_STEPPER_DONE_d_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1884 MASTER LE NN 275475 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1885 MASTER LE NN 275476 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1886 MASTER LE NN 275419 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1887 MASTER LE NN 275415 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1888 MASTER LE NN 275408 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1889 MASTER LE NN 275410 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1890 MASTER LE NN 275242 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 1891 MASTER LE NN 275241 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1892 MASTER LE NN 275240 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1893 MASTER LE NN 275498 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1894 MASTER LE NN 275497 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1895 MASTER LE NN 275395 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1896 MASTER LE NN 275406 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1897 MASTER LE NN 275450 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1898 MASTER LE NN 275496 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1899 MASTER LE NN 275466 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1900 MASTER LE NN 275474 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1901 MASTER LE NN 275488 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1902 MASTER LE NN 275462 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1903 MASTER LE NN 275469 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1904 MASTER LE NN 275467 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1905 MASTER LE NN 275464 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1906 MASTER LE NN 275501 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1907 MASTER LE NN 275487 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1908 MASTER LE NN 275468 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1909 MASTER LE NN 275465 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1910 MASTER LE NN 275489 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1911 MASTER LE NN 275491 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1912 MASTER LE NN 275495 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1913 MASTER LE NN 275492 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1914 MASTER LE NN 275484 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1915 MASTER LE NN 275499 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1916 MASTER LE NN 275490 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1917 MASTER LE NN 275458 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1918 MASTER LE NN 275494 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1919 MASTER LE NN 275461 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1920 MASTER LE NN 275493 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 1921 MASTER LE NN 275459 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1922 MASTER LE NN 275473 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1923 MASTER LE NN 275485 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1924 MASTER LE NN 275423 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1925 MASTER LE NN 275351 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1926 MASTER LE NN 275348 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1927 MASTER LE NN 275439 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/BYPASS_CTL1_0_array_u_BYPASS_CTL1_0__SMART_BYPASS_E
NTRY_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1928 MASTER LE NN 275481 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1929 MASTER LE NN 275486 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1930 MASTER LE NN 275412 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC_CTL1__READY_STEPDOWN_QUAL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1931 MASTER LE NN 275457 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 1932 MASTER LE NN 275397 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1933 MASTER LE NN 275359 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1934 MASTER LE NN 275361 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1935 MASTER LE NN 275191 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1936 MASTER LE NN 275396 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1937 MASTER LE NN 275399 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1938 MASTER LE NN 275394 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1939 MASTER LE NN 275358 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1940 MASTER LE NN 275414 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1941 MASTER LE NN 275357 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1942 MASTER LE NN 275452 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1943 MASTER LE NN 275404 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1944 MASTER LE NN 275398 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1945 MASTER LE NN 275354 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1946 MASTER LE NN 275477 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__VOLTAGE_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1947 MASTER LE NN 275433 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 1948 MASTER LE NN 275456 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1949 MASTER LE NN 275429 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1950 MASTER LE NN 275432 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1951 MASTER LE NN 275373 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1952 MASTER LE NN 275356 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1953 MASTER LE NN 275453 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1954 MASTER LE NN 275418 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1955 MASTER LE NN 275278 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1956 MASTER LE NN 275355 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1957 MASTER LE NN 275413 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1958 MASTER LE NN 275400 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1959 MASTER LE NN 275370 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1960 MASTER LE NN 275248 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1961 MASTER LE NN 275197 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1962 MASTER LE NN 275198 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1963 MASTER LE NN 275331 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1964 MASTER LE NN 275256 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1965 MASTER LE NN 275199 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1966 MASTER LE NN 275254 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1967 MASTER LE NN 275200 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1968 MASTER LE NN 275257 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1969 MASTER LE NN 275158 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 1970 MASTER LE NN 275177 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1971 MASTER LE NN 275181 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1972 MASTER LE NN 275182 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1973 MASTER LE NN 275190 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1974 MASTER LE NN 275183 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1975 MASTER LE NN 275115 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1976 MASTER LE NN 275117 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1977 MASTER LE NN 275116 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1978 MASTER LE NN 275212 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1979 MASTER LE NN 275162 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1980 MASTER LE NN 275161 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1981 MASTER LE NN 275189 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1982 MASTER LE NN 275159 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1983 MASTER LE NN 275193 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1984 MASTER LE NN 275160 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1985 MASTER LE NN 275163 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1986 MASTER LE NN 275192 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1987 MASTER LE NN 275327 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 1988 MASTER LE NN 275196 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1989 MASTER LE NN 275178 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1990 MASTER LE NN 275185 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1991 MASTER LE NN 275184 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1992 MASTER LE NN 275176 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1993 MASTER LE NN 275179 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1994 MASTER LE NN 275255 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 1995 MASTER LE NN 275332 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 1996 MASTER LE NN 275201 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1997 MASTER LE NN 275180 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 1998 MASTER LE NN 275194 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_wide_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 1999 MASTER LE NN 275205 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2000 MASTER LE NN 275376 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2001 MASTER LE NN 275377 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2002 MASTER LE NN 275435 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2003 MASTER LE NN 275436 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2004 MASTER LE NN 275438 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2005 MASTER LE NN 275455 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2006 MASTER LE NN 275434 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2007 MASTER LE NN 275454 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2008 MASTER LE NN 275451 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2009 MASTER LE NN 275431 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2010 MASTER LE NN 275350 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2011 MASTER LE NN 275328 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2012 MASTER LE NN 275360 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
 Chain[4] 2013 MASTER LE NN 275353 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2014 MASTER LE NN 275352 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2015 MASTER LE NN 275441 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2016 MASTER LE NN 275479 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2017 MASTER LE NN 275483 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2018 MASTER LE NN 275440 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2019 MASTER LE NN 275480 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2020 MASTER LE NN 275460 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2021 MASTER LE NN 275478 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2022 MASTER LE NN 275422 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2023 MASTER LE NN 275482 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2024 MASTER LE NN 275470 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2025 MASTER LE NN 275463 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2026 MASTER LE NN 275111 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2027 MASTER LE NN 275100 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2028 MASTER LE NN 275110 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2029 MASTER LE NN 275380 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_EA_CONFIG_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2030 MASTER LE NN 275363 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2031 MASTER LE NN 275384 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD2_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2032 MASTER LE NN 275386 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PUP_CLAMP_THR_CONFIG_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2033 MASTER LE NN 275362 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2034 MASTER LE NN 275365 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2035 MASTER LE NN 275387 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PLOW_CLAMP_THR_CONFIG_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2036 MASTER LE NN 275374 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2037 MASTER LE NN 275382 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PLOW_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2038 MASTER LE NN 275366 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2039 MASTER LE NN 275393 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2040 MASTER LE NN 275378 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_BOT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2041 MASTER LE NN 275385 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__OCP_THR_CONFIG_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2042 MASTER LE NN 275367 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2043 MASTER LE NN 275430 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2044 MASTER LE NN 275329 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2045 MASTER LE NN 275389 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG2_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2046 MASTER LE NN 275383 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD1_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2047 MASTER LE NN 275437 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2048 MASTER LE NN 275391 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[1
] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2049 MASTER LE NN 275369 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2050 MASTER LE NN 275428 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2051 MASTER LE NN 275364 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2052 MASTER LE NN 275381 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PUP_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2053 MASTER LE NN 275368 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2054 MASTER LE NN 275101 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2055 MASTER LE NN 275102 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2056 MASTER LE NN 275195 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2057 MASTER LE NN 275108 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2058 MASTER LE NN 275164 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_dly_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 2059 MASTER LE NN 275211 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_pfet_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2060 MASTER LE NN 275106 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2061 MASTER LE NN 275107 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2062 MASTER LE NN 275103 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2063 MASTER LE NN 275105 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2064 MASTER LE NN 275109 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2065 MASTER LE NN 275104 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2066 MASTER LE NN 275099 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2067 MASTER LE NN 275098 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2068 MASTER LE NN 275207 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_narrow_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2069 MASTER LE NN 275204 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2070 MASTER LE NN 275203 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2071 MASTER LE NN 275202 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2072 MASTER LE NN 275375 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2073 MASTER LE NN 275372 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2074 MASTER LE NN 275371 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2075 MASTER LE NN 275388 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2076 MASTER LE NN 275392 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2077 MASTER LE NN 275390 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG3_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2078 MASTER LE NN 275379 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_LPM_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2079 MASTER LE NN 275349 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2080 MASTER LE NN 275346 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2081 MASTER LE NN 275421 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2082 MASTER LE NN 275347 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2083 MASTER LE NN 275472 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2084 MASTER LE NN 275420 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2085 MASTER LE NN 275426 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2086 MASTER LE NN 275427 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2087 MASTER LE NN 275425 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2088 MASTER LE NN 275444 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2089 MASTER LE NN 275445 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2090 MASTER LE NN 275447 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2091 MASTER LE NN 275443 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2092 MASTER LE NN 275449 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2093 MASTER LE NN 275448 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2094 MASTER LE NN 275424 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2095 MASTER LE NN 275446 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2096 MASTER LE NN 275442 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[8]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2097 MASTER LE NN 274694 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256695 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/LOCKUP (M31_1P5V6T_LOWLATCHX2)
Chain[4] 2098 MASTER LE NN 274701 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2099 MASTER LE NN 274698 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2100 MASTER LE NN 274699 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2101 MASTER LE NN 274702 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2102 MASTER LE NN 274704 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2103 MASTER LE NN 274703 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2104 MASTER LE NN 274705 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2105 MASTER LE NN 274706 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2106 MASTER LE NN 274696 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
 Chain[4] 2107 MASTER LE NN 274707 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2108 MASTER LE NN 274695 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2109 MASTER LE NN 274697 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2110 MASTER LE NN 274700 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2111 MASTER LE NN 274961 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2112 MASTER LE NN 274973 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_EA_CONFIG_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2113 MASTER LE NN 274957 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2114 MASTER LE NN 274970 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2115 MASTER LE NN 274925 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2116 MASTER LE NN 274969 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2117 MASTER LE NN 274793 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2118 MASTER LE NN 274772 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2119 MASTER LE NN 274785 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2120 MASTER LE NN 274779 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2121 MASTER LE NN 274756 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2122 MASTER LE NN 274778 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2123 MASTER LE NN 274760 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_dly_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2124 MASTER LE NN 274806 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_pfet_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2125 MASTER LE NN 274790 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2126 MASTER LE NN 274854 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2127 MASTER LE NN 274738 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2128 MASTER LE NN 274849 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2129 MASTER LE NN 274852 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2130 MASTER LE NN 274796 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2131 MASTER LE NN 274802 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_narrow_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2132 MASTER LE NN 274851 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2133 MASTER LE NN 274850 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2134 MASTER LE NN 274798 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2135 MASTER LE NN 274968 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2136 MASTER LE NN 274797 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2137 MASTER LE NN 274800 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2138 MASTER LE NN 274799 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2139 MASTER LE NN 274789 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_wide_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2140 MASTER LE NN 274853 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2141 MASTER LE NN 274840 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_gt_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2142 MASTER LE NN 274920 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2143 MASTER LE NN 274788 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2144 MASTER LE NN 274784 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2145 MASTER LE NN 274801 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2146 MASTER LE NN 275096 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2147 MASTER LE NN 274782 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2148 MASTER LE NN 274712 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2149 MASTER LE NN 274881 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2150 MASTER LE NN 274882 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2151 MASTER LE NN 274713 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2152 MASTER LE NN 274809 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2153 MASTER LE NN 274711 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2154 MASTER LE NN 274783 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2155 MASTER LE NN 274807 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2156 MASTER LE NN 274803 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2157 MASTER LE NN 274804 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2158 MASTER LE NN 274757 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2159 MASTER LE NN 274805 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2160 MASTER LE NN 274755 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2161 MASTER LE NN 274808 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2162 MASTER LE NN 274787 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2163 MASTER LE NN 274759 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2164 MASTER LE NN 274876 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2165 MASTER LE NN 274875 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2166 MASTER LE NN 274874 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2167 MASTER LE NN 274828 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_meta_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2168 MASTER LE NN 274845 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2169 MASTER LE NN 274838 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2170 MASTER LE NN 274877 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2171 MASTER LE NN 274758 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2172 MASTER LE NN 274722 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2173 MASTER LE NN 274841 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_eq_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2174 MASTER LE NN 274774 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2175 MASTER LE NN 274791 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2176 MASTER LE NN 274776 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2177 MASTER LE NN 274777 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2178 MASTER LE NN 274781 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2179 MASTER LE NN 274780 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2180 MASTER LE NN 274880 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_stepdn_det_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2181 MASTER LE NN 274842 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2182 MASTER LE NN 274878 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2183 MASTER LE NN 274879 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2184 MASTER LE NN 274839 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2185 MASTER LE NN 275071 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2186 MASTER LE NN 275050 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2187 MASTER LE NN 275047 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2188 MASTER LE NN 275072 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2189 MASTER LE NN 274739 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_int_soft_start_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2190 MASTER LE NN 274754 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2191 MASTER LE NN 274794 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2192 MASTER LE NN 274773 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2193 MASTER LE NN 274792 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2194 MASTER LE NN 274775 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2195 MASTER LE NN 274795 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2196 MASTER LE NN 274843 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2197 MASTER LE NN 274924 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2198 MASTER LE NN 275030 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2199 MASTER LE NN 275031 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2200 MASTER LE NN 275032 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2201 MASTER LE NN 275073 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__VOLTAGE_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2202 MASTER LE NN 274993 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2203 MASTER LE NN 274844 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_
u/GEN_PBUS_BUFF_STEPPER_DONE_d_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2204 MASTER LE NN 274947 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2205 MASTER LE NN 275049 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2206 MASTER LE NN 274949 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2207 MASTER LE NN 274950 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2208 MASTER LE NN 274951 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2209 MASTER LE NN 275028 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2210 MASTER LE NN 274786 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2211 MASTER LE NN 275027 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2212 MASTER LE NN 274966 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2213 MASTER LE NN 275029 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2214 MASTER LE NN 274967 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2215 MASTER LE NN 274964 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 2216 MASTER LE NN 274956 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2217 MASTER LE NN 274960 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2218 MASTER LE NN 274978 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__OCP_THR_CONFIG_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2219 MASTER LE NN 274955 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2220 MASTER LE NN 274979 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PUP_CLAMP_THR_CONFIG_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2221 MASTER LE NN 274958 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2222 MASTER LE NN 274980 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PLOW_CLAMP_THR_CONFIG_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2223 MASTER LE NN 274974 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PUP_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2224 MASTER LE NN 274986 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2225 MASTER LE NN 274971 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_BOT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2226 MASTER LE NN 274963 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2227 MASTER LE NN 274975 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PLOW_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2228 MASTER LE NN 274984 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[1
] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2229 MASTER LE NN 274962 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2230 MASTER LE NN 274977 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD2_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2231 MASTER LE NN 275033 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/BYPASS_CTL1_0_array_u_BYPASS_CTL1_0__SMART_BYPASS_E
NTRY_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2232 MASTER LE NN 275021 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2233 MASTER LE NN 275023 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2234 MASTER LE NN 274959 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2235 MASTER LE NN 275026 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2236 MASTER LE NN 274991 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2237 MASTER LE NN 274965 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2238 MASTER LE NN 275022 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2239 MASTER LE NN 274983 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG3_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2240 MASTER LE NN 274976 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD1_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2241 MASTER LE NN 274972 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_LPM_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2242 MASTER LE NN 275025 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2243 MASTER LE NN 274981 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2244 MASTER LE NN 274942 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2245 MASTER LE NN 274943 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2246 MASTER LE NN 274985 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2247 MASTER LE NN 274922 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2248 MASTER LE NN 274982 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG2_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2249 MASTER LE NN 274921 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2250 MASTER LE NN 274948 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2251 MASTER LE NN 274987 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2252 MASTER LE NN 274992 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2253 MASTER LE NN 275048 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2254 MASTER LE NN 275045 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2255 MASTER LE NN 275046 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2256 MASTER LE NN 274752 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2257 MASTER LE NN 274753 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2258 MASTER LE NN 274848 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2259 MASTER LE NN 274847 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2260 MASTER LE NN 274846 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2261 MASTER LE NN 275002 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2262 MASTER LE NN 274829 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2263 MASTER LE NN 274731 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2264 MASTER LE NN 274732 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2265 MASTER LE NN 274733 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2266 MASTER LE NN 275097 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2267 MASTER LE NN 274734 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2268 MASTER LE NN 274730 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2269 MASTER LE NN 275004 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2270 MASTER LE NN 274766 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2271 MASTER LE NN 274883 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2272 MASTER LE NN 275009 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2273 MASTER LE NN 274726 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2274 MASTER LE NN 274725 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2275 MASTER LE NN 274727 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2276 MASTER LE NN 274728 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2277 MASTER LE NN 274729 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2278 MASTER LE NN 275000 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2279 MASTER LE NN 274708 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2280 MASTER LE NN 274737 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2281 MASTER LE NN 274736 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2282 MASTER LE NN 274763 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2283 MASTER LE NN 274762 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2284 MASTER LE NN 274884 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2285 MASTER LE NN 274885 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2286 MASTER LE NN 274761 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2287 MASTER LE NN 274750 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2288 MASTER LE NN 274998 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2289 MASTER LE NN 274723 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2290 MASTER LE NN 274724 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2291 MASTER LE NN 275010 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2292 MASTER LE NN 274767 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2293 MASTER LE NN 274856 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2294 MASTER LE NN 274855 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2295 MASTER LE NN 274710 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2296 MASTER LE NN 274996 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2297 MASTER LE NN 274995 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2298 MASTER LE NN 274994 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[4] 2299 MASTER LE NN 274997 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2300 MASTER LE NN 275001 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2301 MASTER LE NN 275003 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2302 MASTER LE NN 275006 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2303 MASTER LE NN 275012 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2304 MASTER LE NN 274999 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2305 MASTER LE NN 274832 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2306 MASTER LE NN 274831 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2307 MASTER LE NN 274715 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2308 MASTER LE NN 274716 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2309 MASTER LE NN 274718 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2310 MASTER LE NN 274717 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2311 MASTER LE NN 274719 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2312 MASTER LE NN 274893 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2313 MASTER LE NN 274887 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2314 MASTER LE NN 274894 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2315 MASTER LE NN 274888 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2316 MASTER LE NN 274896 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2317 MASTER LE NN 274895 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2318 MASTER LE NN 274886 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2319 MASTER LE NN 274834 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2320 MASTER LE NN 274833 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2321 MASTER LE NN 274836 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2322 MASTER LE NN 275008 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2323 MASTER LE NN 274830 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2324 MASTER LE NN 275007 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2325 MASTER LE NN 274952 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2326 MASTER LE NN 274988 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2327 MASTER LE NN 274953 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2328 MASTER LE NN 274954 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2329 MASTER LE NN 274873 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2330 MASTER LE NN 275024 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2331 MASTER LE NN 274945 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2332 MASTER LE NN 274944 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2333 MASTER LE NN 274990 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2334 MASTER LE NN 274940 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2335 MASTER LE NN 274939 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2336 MASTER LE NN 274889 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2337 MASTER LE NN 274897 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2338 MASTER LE NN 274900 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2339 MASTER LE NN 274891 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2340 MASTER LE NN 274890 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2341 MASTER LE NN 274907 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2342 MASTER LE NN 274930 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2343 MASTER LE NN 274740 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2344 MASTER LE NN 274741 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2345 MASTER LE NN 275005 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC_CTL1__READY_STEPDOWN_QUAL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2346 MASTER LE NN 274909 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2347 MASTER LE NN 275051 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2348 MASTER LE NN 275018 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2349 MASTER LE NN 275041 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2350 MASTER LE NN 275037 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2351 MASTER LE NN 274858 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2352 MASTER LE NN 274857 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2353 MASTER LE NN 275044 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2354 MASTER LE NN 275036 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2355 MASTER LE NN 275042 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2356 MASTER LE NN 275019 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2357 MASTER LE NN 275040 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2358 MASTER LE NN 275017 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2359 MASTER LE NN 275076 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2360 MASTER LE NN 275080 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2361 MASTER LE NN 275013 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2362 MASTER LE NN 275077 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2363 MASTER LE NN 275035 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2364 MASTER LE NN 275034 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2365 MASTER LE NN 275014 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2366 MASTER LE NN 275067 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2367 MASTER LE NN 274989 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2368 MASTER LE NN 274946 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2369 MASTER LE NN 275093 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX2)
Chain[4] 2370 MASTER LE NN 274941 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 2371 MASTER LE NN 274771 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2372 MASTER LE NN 275011 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2373 MASTER LE NN 274837 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2374 MASTER LE NN 274835 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2375 MASTER LE NN 274810 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2376 MASTER LE NN 274892 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2377 MASTER LE NN 274749 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2378 MASTER LE NN 274721 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2379 MASTER LE NN 274720 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2380 MASTER LE NN 274714 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2381 MASTER LE NN 274751 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2382 MASTER LE NN 274765 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2383 MASTER LE NN 274764 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2384 MASTER LE NN 274709 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2385 MASTER LE NN 274735 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2386 MASTER LE NN 275095 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFRSBQX1)
Chain[4] 2387 MASTER LE NN 274906 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2388 MASTER LE NN 274905 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2389 MASTER LE NN 274929 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2390 MASTER LE NN 274927 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2391 MASTER LE NN 274931 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2392 MASTER LE NN 274903 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2393 MASTER LE NN 274934 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2394 MASTER LE NN 274910 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2395 MASTER LE NN 274912 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2396 MASTER LE NN 274916 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2397 MASTER LE NN 274917 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2398 MASTER LE NN 274915 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2399 MASTER LE NN 274913 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2400 MASTER LE NN 274928 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2401 MASTER LE NN 274904 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2402 MASTER LE NN 274898 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2403 MASTER LE NN 274932 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2404 MASTER LE NN 275094 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2405 MASTER LE NN 274899 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2406 MASTER LE NN 275057 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2407 MASTER LE NN 275020 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2408 MASTER LE NN 275043 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2409 MASTER LE NN 275075 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2410 MASTER LE NN 275089 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2411 MASTER LE NN 275074 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2412 MASTER LE NN 275053 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2413 MASTER LE NN 275015 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2414 MASTER LE NN 275016 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2415 MASTER LE NN 275052 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2416 MASTER LE NN 275082 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFSBQX1)
 Chain[4] 2417 MASTER LE NN 275054 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2418 MASTER LE NN 275081 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2419 MASTER LE NN 275065 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2420 MASTER LE NN 275063 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2421 MASTER LE NN 275059 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2422 MASTER LE NN 275083 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2423 MASTER LE NN 275078 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2424 MASTER LE NN 275069 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2425 MASTER LE NN 275085 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2426 MASTER LE NN 275091 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2427 MASTER LE NN 275061 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2428 MASTER LE NN 275092 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2429 MASTER LE NN 275088 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2430 MASTER LE NN 275086 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2431 MASTER LE NN 275079 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2432 MASTER LE NN 275039 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2433 MASTER LE NN 275038 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2434 MASTER LE NN 274742 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2435 MASTER LE NN 274863 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2436 MASTER LE NN 274860 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2437 MASTER LE NN 274814 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2438 MASTER LE NN 275066 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2439 MASTER LE NN 274768 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2440 MASTER LE NN 275062 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2441 MASTER LE NN 275056 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2442 MASTER LE NN 275058 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2443 MASTER LE NN 275064 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2444 MASTER LE NN 275068 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2445 MASTER LE NN 274918 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 2446 MASTER LE NN 274825 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2447 MASTER LE NN 274744 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2448 MASTER LE NN 275070 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2449 MASTER LE NN 274746 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2450 MASTER LE NN 274815 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2451 MASTER LE NN 274870 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2452 MASTER LE NN 274811 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2453 MASTER LE NN 274864 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2454 MASTER LE NN 274861 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2455 MASTER LE NN 274865 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2456 MASTER LE NN 274862 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2457 MASTER LE NN 274868 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2458 MASTER LE NN 274866 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2459 MASTER LE NN 274859 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2460 MASTER LE NN 274871 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2461 MASTER LE NN 274769 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2462 MASTER LE NN 274812 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2463 MASTER LE NN 274745 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2464 MASTER LE NN 274817 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2465 MASTER LE NN 274819 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2466 MASTER LE NN 274824 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2467 MASTER LE NN 274823 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2468 MASTER LE NN 274919 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 2469 MASTER LE NN 274813 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2470 MASTER LE NN 275060 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2471 MASTER LE NN 274816 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2472 MASTER LE NN 274820 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2473 MASTER LE NN 274818 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2474 MASTER LE NN 274827 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2475 MASTER LE NN 274822 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2476 MASTER LE NN 274923 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2477 MASTER LE NN 274821 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2478 MASTER LE NN 274826 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2479 MASTER LE NN 274770 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2480 MASTER LE NN 274926 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2481 MASTER LE NN 274867 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2482 MASTER LE NN 274872 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2483 MASTER LE NN 274869 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2484 MASTER LE NN 274748 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2485 MASTER LE NN 274743 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2486 MASTER LE NN 274747 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2487 MASTER LE NN 275090 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2488 MASTER LE NN 275055 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2489 MASTER LE NN 275087 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2490 MASTER LE NN 275084 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2491 MASTER LE NN 274911 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2492 MASTER LE NN 274908 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2493 MASTER LE NN 274933 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2494 MASTER LE NN 274914 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFRSBQX1)
Chain[4] 2495 MASTER LE NN 274902 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2496 MASTER LE NN 274901 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[7]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2497 MASTER LE NN 274331 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
 DSLAVE LS NN 256690 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX3)
Chain[4] 2498 MASTER LE NN 274332 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2499 MASTER LE NN 274304 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2500 MASTER LE NN 274333 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2501 MASTER LE NN 274481 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2502 MASTER LE NN 274483 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2503 MASTER LE NN 274482 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2504 MASTER LE NN 274510 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2505 MASTER LE NN 274655 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2506 MASTER LE NN 274664 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2507 MASTER LE NN 274682 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2508 MASTER LE NN 274680 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2509 MASTER LE NN 274667 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2510 MASTER LE NN 274657 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2511 MASTER LE NN 274661 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2512 MASTER LE NN 274659 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2513 MASTER LE NN 274663 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2514 MASTER LE NN 274665 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2515 MASTER LE NN 274669 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2516 MASTER LE NN 274658 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2517 MASTER LE NN 274662 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2518 MASTER LE NN 274686 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2519 MASTER LE NN 274691 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2520 MASTER LE NN 274689 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2521 MASTER LE NN 274687 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2522 MASTER LE NN 274512 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2523 MASTER LE NN 274511 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2524 MASTER LE NN 274514 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2525 MASTER LE NN 274533 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2526 MASTER LE NN 274509 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2527 MASTER LE NN 274513 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 2528 MASTER LE NN 274530 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2529 MASTER LE NN 274678 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2530 MASTER LE NN 274692 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2531 MASTER LE NN 274676 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2532 MASTER LE NN 274508 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2533 MASTER LE NN 274496 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2534 MASTER LE NN 274505 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2535 MASTER LE NN 274527 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2536 MASTER LE NN 274516 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2537 MASTER LE NN 274532 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2538 MASTER LE NN 274515 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2539 MASTER LE NN 274500 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2540 MASTER LE NN 274501 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2541 MASTER LE NN 274499 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2542 MASTER LE NN 274502 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2543 MASTER LE NN 274323 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2544 MASTER LE NN 274504 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2545 MASTER LE NN 274529 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2546 MASTER LE NN 274506 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2547 MASTER LE NN 274503 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2548 MASTER LE NN 274609 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2549 MASTER LE NN 274359 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2550 MASTER LE NN 274363 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2551 MASTER LE NN 274362 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2552 MASTER LE NN 274357 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2553 MASTER LE NN 274306 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2554 MASTER LE NN 274358 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2555 MASTER LE NN 274360 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2556 MASTER LE NN 274337 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2557 MASTER LE NN 274338 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2558 MASTER LE NN 274327 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2559 MASTER LE NN 274319 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 2560 MASTER LE NN 274325 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2561 MASTER LE NN 274324 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2562 MASTER LE NN 274478 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2563 MASTER LE NN 274480 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2564 MASTER LE NN 274597 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2565 MASTER LE NN 274599 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2566 MASTER LE NN 274479 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2567 MASTER LE NN 274329 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2568 MASTER LE NN 274305 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2569 MASTER LE NN 274415 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2570 MASTER LE NN 274413 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2571 MASTER LE NN 274341 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2572 MASTER LE NN 274340 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2573 MASTER LE NN 274328 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2574 MASTER LE NN 274410 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2575 MASTER LE NN 274460 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2576 MASTER LE NN 274364 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2577 MASTER LE NN 274457 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2578 MASTER LE NN 274339 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2579 MASTER LE NN 274461 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2580 MASTER LE NN 274462 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2581 MASTER LE NN 274517 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 2582 MASTER LE NN 274518 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 2583 MASTER LE NN 274421 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2584 MASTER LE NN 274468 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2585 MASTER LE NN 274525 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2586 MASTER LE NN 274423 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2587 MASTER LE NN 274522 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2588 MASTER LE NN 274420 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2589 MASTER LE NN 274418 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2590 MASTER LE NN 274414 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2591 MASTER LE NN 274424 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2592 MASTER LE NN 274419 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2593 MASTER LE NN 274416 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2594 MASTER LE NN 274342 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2595 MASTER LE NN 274417 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2596 MASTER LE NN 274366 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2597 MASTER LE NN 274409 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2598 MASTER LE NN 274365 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2599 MASTER LE NN 274412 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2600 MASTER LE NN 274411 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2601 MASTER LE NN 274326 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2602 MASTER LE NN 274330 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2603 MASTER LE NN 274320 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2604 MASTER LE NN 274321 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2605 MASTER LE NN 274322 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2606 MASTER LE NN 274528 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2607 MASTER LE NN 274526 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2608 MASTER LE NN 274497 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2609 MASTER LE NN 274531 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2610 MASTER LE NN 274507 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2611 MASTER LE NN 274685 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2612 MASTER LE NN 274681 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2613 MASTER LE NN 274683 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2614 MASTER LE NN 274650 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2615 MASTER LE NN 274654 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2616 MASTER LE NN 274684 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2617 MASTER LE NN 274660 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2618 MASTER LE NN 274677 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2619 MASTER LE NN 274668 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2620 MASTER LE NN 274651 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2621 MASTER LE NN 274656 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2622 MASTER LE NN 274674 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2623 MASTER LE NN 274652 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2624 MASTER LE NN 274617 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2625 MASTER LE NN 274640 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2626 MASTER LE NN 274616 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2627 MASTER LE NN 274639 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2628 MASTER LE NN 274636 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2629 MASTER LE NN 274637 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2630 MASTER LE NN 274638 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2631 MASTER LE NN 274635 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2632 MASTER LE NN 274641 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2633 MASTER LE NN 274619 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2634 MASTER LE NN 274642 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2635 MASTER LE NN 274690 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2636 MASTER LE NN 274615 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2637 MASTER LE NN 274688 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2638 MASTER LE NN 274653 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2639 MASTER LE NN 274673 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2640 MASTER LE NN 274614 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2641 MASTER LE NN 274675 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2642 MASTER LE NN 274493 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2643 MASTER LE NN 274495 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2644 MASTER LE NN 274643 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2645 MASTER LE NN 274544 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2646 MASTER LE NN 274545 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2647 MASTER LE NN 274543 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2648 MASTER LE NN 274551 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2649 MASTER LE NN 274552 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2650 MASTER LE NN 274553 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2651 MASTER LE NN 274598 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2652 MASTER LE NN 274596 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2653 MASTER LE NN 274594 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2654 MASTER LE NN 274490 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2655 MASTER LE NN 274491 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 2656 MASTER LE NN 274492 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2657 MASTER LE NN 274494 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2658 MASTER LE NN 274608 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2659 MASTER LE NN 274498 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2660 MASTER LE NN 274489 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2661 MASTER LE NN 274488 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2662 MASTER LE NN 274486 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2663 MASTER LE NN 274595 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2664 MASTER LE NN 274593 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[4] 2665 MASTER LE NN 274607 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2666 MASTER LE NN 274610 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2667 MASTER LE NN 274606 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2668 MASTER LE NN 274428 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2669 MASTER LE NN 274433 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2670 MASTER LE NN 274312 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 2671 MASTER LE NN 274311 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2672 MASTER LE NN 274310 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2673 MASTER LE NN 274431 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2674 MASTER LE NN 274430 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2675 MASTER LE NN 274427 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2676 MASTER LE NN 274407 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2677 MASTER LE NN 274436 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2678 MASTER LE NN 274453 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2679 MASTER LE NN 274435 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2680 MASTER LE NN 274452 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2681 MASTER LE NN 274346 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2682 MASTER LE NN 274345 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2683 MASTER LE NN 274336 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2684 MASTER LE NN 274361 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2685 MASTER LE NN 274459 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2686 MASTER LE NN 274458 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2687 MASTER LE NN 274408 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2688 MASTER LE NN 274343 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 2689 MASTER LE NN 274455 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2690 MASTER LE NN 274473 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2691 MASTER LE NN 274451 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2692 MASTER LE NN 274450 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2693 MASTER LE NN 274471 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2694 MASTER LE NN 274398 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2695 MASTER LE NN 274474 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2696 MASTER LE NN 274401 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2697 MASTER LE NN 274467 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2698 MASTER LE NN 274456 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2699 MASTER LE NN 274469 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2700 MASTER LE NN 274463 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2701 MASTER LE NN 274400 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2702 MASTER LE NN 274402 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2703 MASTER LE NN 274472 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2704 MASTER LE NN 274353 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2705 MASTER LE NN 274404 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 2706 MASTER LE NN 274405 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2707 MASTER LE NN 274380 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2708 MASTER LE NN 274406 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2709 MASTER LE NN 274464 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2710 MASTER LE NN 274422 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2711 MASTER LE NN 274466 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2712 MASTER LE NN 274465 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2713 MASTER LE NN 274344 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2714 MASTER LE NN 274454 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2715 MASTER LE NN 274334 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[5] (M31_1P5V6T_SFFRBQX2J)
Chain[4] 2716 MASTER LE NN 274426 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2717 MASTER LE NN 274347 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2718 MASTER LE NN 274425 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_meta_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2719 MASTER LE NN 274437 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_gt_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2720 MASTER LE NN 274318 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2721 MASTER LE NN 274438 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_eq_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2722 MASTER LE NN 274439 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2723 MASTER LE NN 274350 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2724 MASTER LE NN 274335 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_int_soft_start_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2725 MASTER LE NN 274316 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2726 MASTER LE NN 274313 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2727 MASTER LE NN 274603 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2728 MASTER LE NN 274314 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2729 MASTER LE NN 274317 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2730 MASTER LE NN 274315 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2731 MASTER LE NN 274601 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2732 MASTER LE NN 274485 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2733 MASTER LE NN 274484 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2734 MASTER LE NN 274487 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2735 MASTER LE NN 274632 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/BYPASS_CTL1_0_array_u_BYPASS_CTL1_0__SMART_BYPASS_E
NTRY_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2736 MASTER LE NN 274634 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2737 MASTER LE NN 274679 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2738 MASTER LE NN 274633 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2739 MASTER LE NN 274612 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2740 MASTER LE NN 274618 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2741 MASTER LE NN 274666 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 2742 MASTER LE NN 274613 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2743 MASTER LE NN 274604 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC_CTL1__READY_STEPDOWN_QUAL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2744 MASTER LE NN 274540 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2745 MASTER LE NN 274539 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2746 MASTER LE NN 274538 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2747 MASTER LE NN 274589 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2748 MASTER LE NN 274581 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG2_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2749 MASTER LE NN 274541 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2750 MASTER LE NN 274580 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2751 MASTER LE NN 274558 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2752 MASTER LE NN 274575 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD1_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2753 MASTER LE NN 274571 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_LPM_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2754 MASTER LE NN 274582 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG3_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2755 MASTER LE NN 274588 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2756 MASTER LE NN 274548 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2757 MASTER LE NN 274600 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2758 MASTER LE NN 274602 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2759 MASTER LE NN 274623 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2760 MASTER LE NN 274693 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2761 MASTER LE NN 274549 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2762 MASTER LE NN 274550 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2763 MASTER LE NN 274546 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2764 MASTER LE NN 274624 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2765 MASTER LE NN 274565 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2766 MASTER LE NN 274629 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2767 MASTER LE NN 274670 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2768 MASTER LE NN 274631 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2769 MASTER LE NN 274672 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__VOLTAGE_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2770 MASTER LE NN 274383 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2771 MASTER LE NN 274591 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2772 MASTER LE NN 274564 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2773 MASTER LE NN 274590 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2774 MASTER LE NN 274547 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2775 MASTER LE NN 274521 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2776 MASTER LE NN 274470 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2777 MASTER LE NN 274611 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2778 MASTER LE NN 274367 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2779 MASTER LE NN 274520 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
 Chain[4] 2780 MASTER LE NN 274605 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2781 MASTER LE NN 274447 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2782 MASTER LE NN 274562 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2783 MASTER LE NN 274394 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2784 MASTER LE NN 274567 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2785 MASTER LE NN 274569 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2786 MASTER LE NN 274386 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_wide_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2787 MASTER LE NN 274432 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2788 MASTER LE NN 274434 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2789 MASTER LE NN 274348 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2790 MASTER LE NN 274349 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2791 MASTER LE NN 274443 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2792 MASTER LE NN 274429 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2793 MASTER LE NN 274445 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2794 MASTER LE NN 274441 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_
u/GEN_PBUS_BUFF_STEPPER_DONE_d_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2795 MASTER LE NN 274440 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2796 MASTER LE NN 274371 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2797 MASTER LE NN 274568 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2798 MASTER LE NN 274393 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2799 MASTER LE NN 274397 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2800 MASTER LE NN 274399 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_narrow_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2801 MASTER LE NN 274396 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2802 MASTER LE NN 274389 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2803 MASTER LE NN 274390 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2804 MASTER LE NN 274392 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2805 MASTER LE NN 274382 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2806 MASTER LE NN 274387 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2807 MASTER LE NN 274372 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2808 MASTER LE NN 274376 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2809 MASTER LE NN 274444 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2810 MASTER LE NN 274442 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2811 MASTER LE NN 274477 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_stepdn_det_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2812 MASTER LE NN 274476 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2813 MASTER LE NN 274446 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2814 MASTER LE NN 274449 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2815 MASTER LE NN 274448 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2816 MASTER LE NN 274475 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2817 MASTER LE NN 274377 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2818 MASTER LE NN 274368 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2819 MASTER LE NN 274369 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2820 MASTER LE NN 274307 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2821 MASTER LE NN 274308 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2822 MASTER LE NN 274309 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2823 MASTER LE NN 274403 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_pfet_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2824 MASTER LE NN 274379 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2825 MASTER LE NN 274356 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_dly_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2826 MASTER LE NN 274381 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2827 MASTER LE NN 274354 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2828 MASTER LE NN 274352 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2829 MASTER LE NN 274385 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2830 MASTER LE NN 274355 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2831 MASTER LE NN 274351 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2832 MASTER LE NN 274519 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2833 MASTER LE NN 274384 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2834 MASTER LE NN 274378 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2835 MASTER LE NN 274375 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2836 MASTER LE NN 274374 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2837 MASTER LE NN 274388 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2838 MASTER LE NN 274373 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2839 MASTER LE NN 274370 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2840 MASTER LE NN 274523 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2841 MASTER LE NN 274391 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2842 MASTER LE NN 274395 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2843 MASTER LE NN 274524 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2844 MASTER LE NN 274592 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2845 MASTER LE NN 274671 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2846 MASTER LE NN 274563 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2847 MASTER LE NN 274630 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2848 MASTER LE NN 274625 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2849 MASTER LE NN 274542 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2850 MASTER LE NN 274627 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2851 MASTER LE NN 274626 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2852 MASTER LE NN 274622 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2853 MASTER LE NN 274644 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2854 MASTER LE NN 274628 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 2855 MASTER LE NN 274587 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2856 MASTER LE NN 274586 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2857 MASTER LE NN 274648 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2858 MASTER LE NN 274621 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2859 MASTER LE NN 274620 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2860 MASTER LE NN 274645 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2861 MASTER LE NN 274647 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2862 MASTER LE NN 274646 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2863 MASTER LE NN 274561 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2864 MASTER LE NN 274585 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2865 MASTER LE NN 274649 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2866 MASTER LE NN 274570 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_BOT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2867 MASTER LE NN 274566 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2868 MASTER LE NN 274576 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD2_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2869 MASTER LE NN 274574 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PLOW_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2870 MASTER LE NN 274583 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[1
] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2871 MASTER LE NN 274584 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 2872 MASTER LE NN 274560 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2873 MASTER LE NN 274559 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2874 MASTER LE NN 274556 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2875 MASTER LE NN 274577 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__OCP_THR_CONFIG_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2876 MASTER LE NN 274554 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2877 MASTER LE NN 274579 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PLOW_CLAMP_THR_CONFIG_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2878 MASTER LE NN 274557 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2879 MASTER LE NN 274555 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2880 MASTER LE NN 274572 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_EA_CONFIG_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2881 MASTER LE NN 274573 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PUP_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2882 MASTER LE NN 274578 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PUP_CLAMP_THR_CONFIG_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2883 MASTER LE NN 274296 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2884 MASTER LE NN 274290 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2885 MASTER LE NN 274292 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2886 MASTER LE NN 274298 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2887 MASTER LE NN 274303 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
 Chain[4] 2888 MASTER LE NN 274300 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2889 MASTER LE NN 274302 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2890 MASTER LE NN 274293 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2891 MASTER LE NN 274295 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2892 MASTER LE NN 274294 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2893 MASTER LE NN 274297 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2894 MASTER LE NN 274291 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2895 MASTER LE NN 274301 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2896 MASTER LE NN 274299 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[6]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2897 MASTER LE NN 273891 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256640 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/LOCKUP (M31_1P5V6T_LOWLATCHX3)
Chain[4] 2898 MASTER LE NN 273893 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2899 MASTER LE NN 273897 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2900 MASTER LE NN 273887 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2901 MASTER LE NN 273899 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2902 MASTER LE NN 273892 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2903 MASTER LE NN 273979 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2904 MASTER LE NN 274083 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2905 MASTER LE NN 274091 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2906 MASTER LE NN 273888 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2907 MASTER LE NN 273890 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2908 MASTER LE NN 273896 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2909 MASTER LE NN 273889 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2910 MASTER LE NN 273895 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2911 MASTER LE NN 274082 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2912 MASTER LE NN 274081 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2913 MASTER LE NN 274089 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2914 MASTER LE NN 274086 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2915 MASTER LE NN 273924 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2916 MASTER LE NN 273925 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2917 MASTER LE NN 274090 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2918 MASTER LE NN 274088 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2919 MASTER LE NN 274087 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2920 MASTER LE NN 274080 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2921 MASTER LE NN 273894 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2922 MASTER LE NN 273886 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2923 MASTER LE NN 273898 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2924 MASTER LE NN 273986 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2925 MASTER LE NN 274118 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2926 MASTER LE NN 273985 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2927 MASTER LE NN 273988 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2928 MASTER LE NN 273987 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2929 MASTER LE NN 273993 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2930 MASTER LE NN 273967 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2931 MASTER LE NN 273973 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2932 MASTER LE NN 273966 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2933 MASTER LE NN 273971 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2934 MASTER LE NN 273970 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2935 MASTER LE NN 274067 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2936 MASTER LE NN 273974 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2937 MASTER LE NN 273975 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2938 MASTER LE NN 273905 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2939 MASTER LE NN 273904 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2940 MASTER LE NN 273903 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2941 MASTER LE NN 274114 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 2942 MASTER LE NN 274000 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2943 MASTER LE NN 274001 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2944 MASTER LE NN 274002 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2945 MASTER LE NN 273976 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2946 MASTER LE NN 273997 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2947 MASTER LE NN 273996 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2948 MASTER LE NN 273994 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2949 MASTER LE NN 273998 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2950 MASTER LE NN 273981 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2951 MASTER LE NN 273949 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2952 MASTER LE NN 273948 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2953 MASTER LE NN 273977 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2954 MASTER LE NN 273980 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2955 MASTER LE NN 273951 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[8]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 2956 MASTER LE NN 273947 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2957 MASTER LE NN 273950 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2958 MASTER LE NN 273982 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_wide_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2959 MASTER LE NN 273999 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_pfet_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2960 MASTER LE NN 273952 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_dly_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2961 MASTER LE NN 273984 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2962 MASTER LE NN 274068 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2963 MASTER LE NN 273983 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2964 MASTER LE NN 273978 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2965 MASTER LE NN 273969 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2966 MASTER LE NN 273968 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2967 MASTER LE NN 274071 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2968 MASTER LE NN 274072 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2969 MASTER LE NN 273992 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2970 MASTER LE NN 273995 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_narrow_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2971 MASTER LE NN 273989 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 2972 MASTER LE NN 273990 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2973 MASTER LE NN 274119 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 2974 MASTER LE NN 274043 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2975 MASTER LE NN 273991 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2976 MASTER LE NN 274073 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_stepdn_det_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2977 MASTER LE NN 273972 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2978 MASTER LE NN 273914 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2979 MASTER LE NN 274033 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_gt_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2980 MASTER LE NN 274044 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2981 MASTER LE NN 274042 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2982 MASTER LE NN 274045 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2983 MASTER LE NN 274047 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2984 MASTER LE NN 273930 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2985 MASTER LE NN 274046 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2986 MASTER LE NN 274040 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2987 MASTER LE NN 274039 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2988 MASTER LE NN 274038 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2989 MASTER LE NN 273907 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2990 MASTER LE NN 273908 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2991 MASTER LE NN 273906 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2992 MASTER LE NN 273912 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 2993 MASTER LE NN 274035 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2994 MASTER LE NN 274031 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 2995 MASTER LE NN 274022 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2996 MASTER LE NN 274069 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2997 MASTER LE NN 274021 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_meta_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 2998 MASTER LE NN 274041 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 2999 MASTER LE NN 274034 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_eq_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3000 MASTER LE NN 274032 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3001 MASTER LE NN 273965 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3002 MASTER LE NN 273964 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3003 MASTER LE NN 274070 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3004 MASTER LE NN 273931 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_int_soft_start_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3005 MASTER LE NN 273946 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3006 MASTER LE NN 274023 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3007 MASTER LE NN 274027 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3008 MASTER LE NN 274066 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3009 MASTER LE NN 274026 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3010 MASTER LE NN 274028 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3011 MASTER LE NN 274037 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_
u/GEN_PBUS_BUFF_STEPPER_DONE_d_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3012 MASTER LE NN 274158 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3013 MASTER LE NN 274036 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3014 MASTER LE NN 274162 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3015 MASTER LE NN 274164 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3016 MASTER LE NN 274174 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PLOW_CLAMP_THR_CONFIG_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3017 MASTER LE NN 274161 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3018 MASTER LE NN 274177 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG3_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3019 MASTER LE NN 274178 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[1
] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3020 MASTER LE NN 274157 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3021 MASTER LE NN 274185 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3022 MASTER LE NN 274187 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3023 MASTER LE NN 274186 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3024 MASTER LE NN 274170 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD1_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3025 MASTER LE NN 274166 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_LPM_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3026 MASTER LE NN 274167 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_EA_CONFIG_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3027 MASTER LE NN 274169 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PLOW_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3028 MASTER LE NN 274179 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3029 MASTER LE NN 274156 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3030 MASTER LE NN 274155 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3031 MASTER LE NN 274149 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3032 MASTER LE NN 274144 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3033 MASTER LE NN 274143 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3034 MASTER LE NN 274175 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3035 MASTER LE NN 274141 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3036 MASTER LE NN 274152 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3037 MASTER LE NN 274151 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3038 MASTER LE NN 274150 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3039 MASTER LE NN 274221 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3040 MASTER LE NN 274142 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3041 MASTER LE NN 274145 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3042 MASTER LE NN 274266 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3043 MASTER LE NN 274168 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PUP_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3044 MASTER LE NN 274217 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 3045 MASTER LE NN 274241 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3046 MASTER LE NN 274244 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3047 MASTER LE NN 274227 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 3048 MASTER LE NN 274115 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3049 MASTER LE NN 274180 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3050 MASTER LE NN 274267 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__VOLTAGE_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3051 MASTER LE NN 274172 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__OCP_THR_CONFIG_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3052 MASTER LE NN 274243 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3053 MASTER LE NN 274245 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3054 MASTER LE NN 274116 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3055 MASTER LE NN 274220 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3056 MASTER LE NN 274206 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3057 MASTER LE NN 274224 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 3058 MASTER LE NN 274226 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 3059 MASTER LE NN 274200 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3060 MASTER LE NN 274240 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3061 MASTER LE NN 274242 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3062 MASTER LE NN 274216 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3063 MASTER LE NN 274215 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3064 MASTER LE NN 274223 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 3065 MASTER LE NN 274197 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3066 MASTER LE NN 274193 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3067 MASTER LE NN 274195 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3068 MASTER LE NN 274194 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3069 MASTER LE NN 274192 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3070 MASTER LE NN 274189 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3071 MASTER LE NN 274188 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[4] 3072 MASTER LE NN 273901 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3073 MASTER LE NN 273900 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3074 MASTER LE NN 273928 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3075 MASTER LE NN 273929 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 3076 MASTER LE NN 273923 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3077 MASTER LE NN 274075 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3078 MASTER LE NN 274074 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3079 MASTER LE NN 273926 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3080 MASTER LE NN 273922 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3081 MASTER LE NN 273927 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3082 MASTER LE NN 274077 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3083 MASTER LE NN 274076 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3084 MASTER LE NN 274198 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3085 MASTER LE NN 274196 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3086 MASTER LE NN 274225 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 3087 MASTER LE NN 274219 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3088 MASTER LE NN 274218 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3089 MASTER LE NN 274222 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 3090 MASTER LE NN 274265 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3091 MASTER LE NN 274171 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD2_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3092 MASTER LE NN 274176 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG2_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3093 MASTER LE NN 274165 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_BOT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3094 MASTER LE NN 274173 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PUP_CLAMP_THR_CONFIG_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3095 MASTER LE NN 274153 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3096 MASTER LE NN 274154 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3097 MASTER LE NN 274159 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3098 MASTER LE NN 274163 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3099 MASTER LE NN 274160 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3100 MASTER LE NN 274025 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3101 MASTER LE NN 274024 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3102 MASTER LE NN 273911 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3103 MASTER LE NN 273913 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3104 MASTER LE NN 273910 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3105 MASTER LE NN 273909 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 3106 MASTER LE NN 274287 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFRBQX2)
Chain[4] 3107 MASTER LE NN 274099 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3108 MASTER LE NN 274100 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3109 MASTER LE NN 274122 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3110 MASTER LE NN 274095 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3111 MASTER LE NN 274096 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3112 MASTER LE NN 274097 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3113 MASTER LE NN 274109 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3114 MASTER LE NN 274108 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3115 MASTER LE NN 274104 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3116 MASTER LE NN 274106 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3117 MASTER LE NN 274105 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3118 MASTER LE NN 274110 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3119 MASTER LE NN 274278 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3120 MASTER LE NN 274273 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3121 MASTER LE NN 274252 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3122 MASTER LE NN 274247 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3123 MASTER LE NN 274280 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3124 MASTER LE NN 274107 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3125 MASTER LE NN 274111 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3126 MASTER LE NN 274128 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3127 MASTER LE NN 274125 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3128 MASTER LE NN 274127 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3129 MASTER LE NN 274126 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3130 MASTER LE NN 274121 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3131 MASTER LE NN 274124 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3132 MASTER LE NN 274098 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3133 MASTER LE NN 274123 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3134 MASTER LE NN 274101 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3135 MASTER LE NN 274030 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3136 MASTER LE NN 274029 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3137 MASTER LE NN 274003 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3138 MASTER LE NN 273945 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3139 MASTER LE NN 273944 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3140 MASTER LE NN 274103 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3141 MASTER LE NN 274093 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3142 MASTER LE NN 274102 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3143 MASTER LE NN 274228 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/BYPASS_CTL1_0_array_u_BYPASS_CTL1_0__SMART_BYPASS_E
NTRY_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3144 MASTER LE NN 274092 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3145 MASTER LE NN 274271 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3146 MASTER LE NN 274199 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC_CTL1__READY_STEPDOWN_QUAL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3147 MASTER LE NN 274246 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3148 MASTER LE NN 274276 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3149 MASTER LE NN 274250 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3150 MASTER LE NN 274279 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3151 MASTER LE NN 274255 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3152 MASTER LE NN 274277 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3153 MASTER LE NN 274281 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3154 MASTER LE NN 274259 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3155 MASTER LE NN 274275 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3156 MASTER LE NN 274207 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3157 MASTER LE NN 274209 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3158 MASTER LE NN 274283 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3159 MASTER LE NN 274248 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3160 MASTER LE NN 274230 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3161 MASTER LE NN 274239 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3162 MASTER LE NN 274268 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3163 MASTER LE NN 274288 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFRBQX2)
Chain[4] 3164 MASTER LE NN 274184 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3165 MASTER LE NN 273963 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3166 MASTER LE NN 274183 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3167 MASTER LE NN 274137 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3168 MASTER LE NN 274148 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3169 MASTER LE NN 274136 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3170 MASTER LE NN 274205 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3171 MASTER LE NN 274201 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3172 MASTER LE NN 274181 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3173 MASTER LE NN 274182 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3174 MASTER LE NN 274139 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3175 MASTER LE NN 274049 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3176 MASTER LE NN 273943 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3177 MASTER LE NN 274202 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3178 MASTER LE NN 273942 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3179 MASTER LE NN 274191 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3180 MASTER LE NN 274094 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3181 MASTER LE NN 273958 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3182 MASTER LE NN 274084 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3183 MASTER LE NN 274085 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3184 MASTER LE NN 273941 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3185 MASTER LE NN 273955 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3186 MASTER LE NN 273954 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3187 MASTER LE NN 273953 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3188 MASTER LE NN 273921 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3189 MASTER LE NN 273915 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3190 MASTER LE NN 273959 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3191 MASTER LE NN 274203 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3192 MASTER LE NN 274204 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3193 MASTER LE NN 274190 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3194 MASTER LE NN 273918 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3195 MASTER LE NN 273917 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3196 MASTER LE NN 273919 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3197 MASTER LE NN 273916 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3198 MASTER LE NN 273920 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3199 MASTER LE NN 274079 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 3200 MASTER LE NN 274078 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3201 MASTER LE NN 273956 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3202 MASTER LE NN 273957 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3203 MASTER LE NN 273902 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3204 MASTER LE NN 274048 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3205 MASTER LE NN 274146 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3206 MASTER LE NN 274147 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3207 MASTER LE NN 274140 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3208 MASTER LE NN 274138 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3209 MASTER LE NN 274135 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3210 MASTER LE NN 274133 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3211 MASTER LE NN 274134 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3212 MASTER LE NN 274208 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3213 MASTER LE NN 274229 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3214 MASTER LE NN 274274 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3215 MASTER LE NN 274270 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 3216 MASTER LE NN 274269 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3217 MASTER LE NN 274210 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3218 MASTER LE NN 274249 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3219 MASTER LE NN 274285 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3220 MASTER LE NN 274286 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3221 MASTER LE NN 274282 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3222 MASTER LE NN 274284 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3223 MASTER LE NN 274260 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3224 MASTER LE NN 274256 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3225 MASTER LE NN 274251 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3226 MASTER LE NN 274289 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3227 MASTER LE NN 274254 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3228 MASTER LE NN 274253 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3229 MASTER LE NN 274272 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3230 MASTER LE NN 274263 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3231 MASTER LE NN 274257 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3232 MASTER LE NN 274262 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3233 MASTER LE NN 274258 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3234 MASTER LE NN 274264 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3235 MASTER LE NN 274053 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3236 MASTER LE NN 274056 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3237 MASTER LE NN 274050 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3238 MASTER LE NN 274051 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3239 MASTER LE NN 274062 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3240 MASTER LE NN 274063 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3241 MASTER LE NN 274059 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3242 MASTER LE NN 274052 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3243 MASTER LE NN 274064 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3244 MASTER LE NN 274065 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3245 MASTER LE NN 274112 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 3246 MASTER LE NN 274061 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3247 MASTER LE NN 274055 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3248 MASTER LE NN 274058 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3249 MASTER LE NN 274057 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3250 MASTER LE NN 274054 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3251 MASTER LE NN 274007 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3252 MASTER LE NN 274231 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3253 MASTER LE NN 274214 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3254 MASTER LE NN 274235 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3255 MASTER LE NN 274211 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3256 MASTER LE NN 274261 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3257 MASTER LE NN 274236 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3258 MASTER LE NN 274212 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3259 MASTER LE NN 274213 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3260 MASTER LE NN 274238 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3261 MASTER LE NN 274237 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3262 MASTER LE NN 274234 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3263 MASTER LE NN 274232 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3264 MASTER LE NN 274233 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3265 MASTER LE NN 273932 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3266 MASTER LE NN 274008 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3267 MASTER LE NN 274004 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3268 MASTER LE NN 274010 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3269 MASTER LE NN 274005 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3270 MASTER LE NN 274113 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 3271 MASTER LE NN 274006 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3272 MASTER LE NN 274120 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3273 MASTER LE NN 274014 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3274 MASTER LE NN 274011 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3275 MASTER LE NN 274020 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3276 MASTER LE NN 274117 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3277 MASTER LE NN 274015 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3278 MASTER LE NN 273962 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3279 MASTER LE NN 274016 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3280 MASTER LE NN 273961 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3281 MASTER LE NN 274018 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3282 MASTER LE NN 273936 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3283 MASTER LE NN 273935 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3284 MASTER LE NN 273933 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3285 MASTER LE NN 273934 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3286 MASTER LE NN 273939 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3287 MASTER LE NN 273940 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3288 MASTER LE NN 273960 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3289 MASTER LE NN 273937 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3290 MASTER LE NN 273938 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3291 MASTER LE NN 274012 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3292 MASTER LE NN 274017 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3293 MASTER LE NN 274019 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3294 MASTER LE NN 274009 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3295 MASTER LE NN 274013 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3296 MASTER LE NN 274060 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[5]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3297 MASTER LE NN 273844 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
DSLAVE LS NN 256635 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX2)
Chain[4] 3298 MASTER LE NN 273850 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3299 MASTER LE NN 273846 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3300 MASTER LE NN 273848 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3301 MASTER LE NN 273724 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3302 MASTER LE NN 273707 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3303 MASTER LE NN 273701 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3304 MASTER LE NN 273723 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3305 MASTER LE NN 273725 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3306 MASTER LE NN 273703 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3307 MASTER LE NN 273697 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3308 MASTER LE NN 273720 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3309 MASTER LE NN 273691 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3310 MASTER LE NN 273694 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3311 MASTER LE NN 273653 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3312 MASTER LE NN 273654 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3313 MASTER LE NN 273709 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 3314 MASTER LE NN 273659 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3315 MASTER LE NN 273648 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3316 MASTER LE NN 273612 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3317 MASTER LE NN 273615 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3318 MASTER LE NN 273613 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3319 MASTER LE NN 273610 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3320 MASTER LE NN 273616 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3321 MASTER LE NN 273611 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3322 MASTER LE NN 273714 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3323 MASTER LE NN 273606 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3324 MASTER LE NN 273534 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3325 MASTER LE NN 273608 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3326 MASTER LE NN 273607 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3327 MASTER LE NN 273605 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3328 MASTER LE NN 273710 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 3329 MASTER LE NN 273614 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3330 MASTER LE NN 273609 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3331 MASTER LE NN 273604 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3332 MASTER LE NN 273602 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3333 MASTER LE NN 273603 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3334 MASTER LE NN 273693 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3335 MASTER LE NN 273692 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3336 MASTER LE NN 273695 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3337 MASTER LE NN 273719 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3338 MASTER LE NN 273698 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3339 MASTER LE NN 273708 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3340 MASTER LE NN 273702 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3341 MASTER LE NN 273706 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3342 MASTER LE NN 273704 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3343 MASTER LE NN 273858 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
 Chain[4] 3344 MASTER LE NN 273854 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3345 MASTER LE NN 273856 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3346 MASTER LE NN 273884 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX2)
Chain[4] 3347 MASTER LE NN 273810 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3348 MASTER LE NN 273803 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3349 MASTER LE NN 273826 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3350 MASTER LE NN 273868 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3351 MASTER LE NN 273824 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3352 MASTER LE NN 273862 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3353 MASTER LE NN 273863 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3354 MASTER LE NN 273842 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3355 MASTER LE NN 273806 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3356 MASTER LE NN 273805 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3357 MASTER LE NN 273871 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3358 MASTER LE NN 273853 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3359 MASTER LE NN 273849 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3360 MASTER LE NN 273879 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3361 MASTER LE NN 273841 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3362 MASTER LE NN 273866 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3363 MASTER LE NN 273847 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3364 MASTER LE NN 273875 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3365 MASTER LE NN 273873 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3366 MASTER LE NN 273857 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3367 MASTER LE NN 273845 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3368 MASTER LE NN 273840 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3369 MASTER LE NN 273869 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3370 MASTER LE NN 273851 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3371 MASTER LE NN 273843 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3372 MASTER LE NN 273872 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3373 MASTER LE NN 273880 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3374 MASTER LE NN 273852 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3375 MASTER LE NN 273876 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3376 MASTER LE NN 273878 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3377 MASTER LE NN 273874 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3378 MASTER LE NN 273883 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3379 MASTER LE NN 273687 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3380 MASTER LE NN 273679 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3381 MASTER LE NN 273682 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3382 MASTER LE NN 273676 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3383 MASTER LE NN 273718 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3384 MASTER LE NN 273696 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3385 MASTER LE NN 273688 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3386 MASTER LE NN 273683 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3387 MASTER LE NN 273684 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3388 MASTER LE NN 273685 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3389 MASTER LE NN 273690 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3390 MASTER LE NN 273785 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3391 MASTER LE NN 273790 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3392 MASTER LE NN 273549 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3393 MASTER LE NN 273788 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3394 MASTER LE NN 273680 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3395 MASTER LE NN 273681 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3396 MASTER LE NN 273530 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3397 MASTER LE NN 273529 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3398 MASTER LE NN 273678 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3399 MASTER LE NN 273689 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3400 MASTER LE NN 273652 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3401 MASTER LE NN 273649 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3402 MASTER LE NN 273651 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3403 MASTER LE NN 273650 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3404 MASTER LE NN 273531 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3405 MASTER LE NN 273600 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3406 MASTER LE NN 273550 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3407 MASTER LE NN 273674 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3408 MASTER LE NN 273675 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3409 MASTER LE NN 273553 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3410 MASTER LE NN 273515 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3411 MASTER LE NN 273552 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3412 MASTER LE NN 273551 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3413 MASTER LE NN 273646 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3414 MASTER LE NN 273517 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3415 MASTER LE NN 273516 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3416 MASTER LE NN 273532 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3417 MASTER LE NN 273647 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3418 MASTER LE NN 273655 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3419 MASTER LE NN 273656 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3420 MASTER LE NN 273660 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3421 MASTER LE NN 273558 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3422 MASTER LE NN 273717 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
 Chain[4] 3423 MASTER LE NN 273661 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3424 MASTER LE NN 273533 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3425 MASTER LE NN 273497 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3426 MASTER LE NN 273523 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3427 MASTER LE NN 273496 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3428 MASTER LE NN 273673 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3429 MASTER LE NN 273518 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3430 MASTER LE NN 273520 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3431 MASTER LE NN 273525 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3432 MASTER LE NN 273524 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3433 MASTER LE NN 273557 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3434 MASTER LE NN 273556 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3435 MASTER LE NN 273657 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3436 MASTER LE NN 273658 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3437 MASTER LE NN 273601 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3438 MASTER LE NN 273536 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3439 MASTER LE NN 273535 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3440 MASTER LE NN 273528 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3441 MASTER LE NN 273686 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3442 MASTER LE NN 273677 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3443 MASTER LE NN 273700 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3444 MASTER LE NN 273721 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3445 MASTER LE NN 273699 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3446 MASTER LE NN 273722 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3447 MASTER LE NN 273705 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3448 MASTER LE NN 273870 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3449 MASTER LE NN 273867 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3450 MASTER LE NN 273795 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC_CTL1__READY_STEPDOWN_QUAL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3451 MASTER LE NN 273865 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3452 MASTER LE NN 273823 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/BYPASS_CTL1_0_array_u_BYPASS_CTL1_0__SMART_BYPASS_E
NTRY_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3453 MASTER LE NN 273839 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3454 MASTER LE NN 273833 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3455 MASTER LE NN 273825 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3456 MASTER LE NN 273864 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3457 MASTER LE NN 273877 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3458 MASTER LE NN 273827 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3459 MASTER LE NN 273829 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3460 MASTER LE NN 273828 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3461 MASTER LE NN 273831 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3462 MASTER LE NN 273809 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3463 MASTER LE NN 273832 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3464 MASTER LE NN 273830 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3465 MASTER LE NN 273808 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3466 MASTER LE NN 273885 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3467 MASTER LE NN 273836 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3468 MASTER LE NN 273743 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3469 MASTER LE NN 273835 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3470 MASTER LE NN 273838 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3471 MASTER LE NN 273745 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3472 MASTER LE NN 273837 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3473 MASTER LE NN 273778 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3474 MASTER LE NN 273802 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3475 MASTER LE NN 273662 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3476 MASTER LE NN 273859 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3477 MASTER LE NN 273882 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3478 MASTER LE NN 273814 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3479 MASTER LE NN 273798 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3480 MASTER LE NN 273791 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3481 MASTER LE NN 273834 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3482 MASTER LE NN 273779 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3483 MASTER LE NN 273787 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3484 MASTER LE NN 273784 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[4] 3485 MASTER LE NN 273506 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 3486 MASTER LE NN 273503 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3487 MASTER LE NN 273507 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3488 MASTER LE NN 273505 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3489 MASTER LE NN 273540 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3490 MASTER LE NN 273504 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3491 MASTER LE NN 273623 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3492 MASTER LE NN 273502 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3493 MASTER LE NN 273625 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3494 MASTER LE NN 273624 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3495 MASTER LE NN 273619 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3496 MASTER LE NN 273526 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3497 MASTER LE NN 273642 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3498 MASTER LE NN 273637 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3499 MASTER LE NN 273799 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3500 MASTER LE NN 273541 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_stepdn_qual_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3501 MASTER LE NN 273794 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3502 MASTER LE NN 273786 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3503 MASTER LE NN 273792 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3504 MASTER LE NN 273559 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3505 MASTER LE NN 273644 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3506 MASTER LE NN 273498 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3507 MASTER LE NN 273645 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3508 MASTER LE NN 273537 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3509 MASTER LE NN 273634 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3510 MASTER LE NN 273510 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_incr_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3511 MASTER LE NN 273630 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_eq_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3512 MASTER LE NN 273635 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3513 MASTER LE NN 273669 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_stepdn_det_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3514 MASTER LE NN 273565 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3515 MASTER LE NN 273560 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3516 MASTER LE NN 273561 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[4] 3517 MASTER LE NN 273568 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3518 MASTER LE NN 273569 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3519 MASTER LE NN 273548 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_dly_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3520 MASTER LE NN 273567 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3521 MASTER LE NN 273499 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3522 MASTER LE NN 273666 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3523 MASTER LE NN 273665 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3524 MASTER LE NN 273668 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3525 MASTER LE NN 273539 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3526 MASTER LE NN 273800 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3527 MASTER LE NN 273538 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3528 MASTER LE NN 273512 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3529 MASTER LE NN 273554 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3530 MASTER LE NN 273555 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3531 MASTER LE NN 273514 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3532 MASTER LE NN 273513 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3533 MASTER LE NN 273511 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3534 MASTER LE NN 273672 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3535 MASTER LE NN 273671 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3536 MASTER LE NN 273670 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3537 MASTER LE NN 273519 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3538 MASTER LE NN 273593 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3539 MASTER LE NN 273571 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3540 MASTER LE NN 273664 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3541 MASTER LE NN 273501 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3542 MASTER LE NN 273576 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3543 MASTER LE NN 273594 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3544 MASTER LE NN 273596 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3545 MASTER LE NN 273546 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3546 MASTER LE NN 273547 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3547 MASTER LE NN 273573 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3548 MASTER LE NN 273545 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3549 MASTER LE NN 273572 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3550 MASTER LE NN 273597 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3551 MASTER LE NN 273598 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3552 MASTER LE NN 273522 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3553 MASTER LE NN 273521 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3554 MASTER LE NN 273592 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3555 MASTER LE NN 273590 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_fsm_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3556 MASTER LE NN 273500 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3557 MASTER LE NN 273570 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3558 MASTER LE NN 273663 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3559 MASTER LE NN 273618 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3560 MASTER LE NN 273617 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_clk_req_u/d_clk_req_stepper_meta_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3561 MASTER LE NN 273667 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_vreg_ready_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3562 MASTER LE NN 273628 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_stepper_active_delay_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3563 MASTER LE NN 273631 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3564 MASTER LE NN 273627 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_active_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3565 MASTER LE NN 273626 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3566 MASTER LE NN 273509 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3567 MASTER LE NN 273508 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/reg_voltage_stepper_1p0_dig_vsu_u/VSET_ROUND_
UP_PROCESS_ENABLED_reg_voltage_stepper_1p0_dig_vset_rnd_up_u/reg_voltage_stepper_1p
0_dig_vset_sync_u/d_sw_setpoint_sat_sync_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3568 MASTER LE NN 273620 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3569 MASTER LE NN 273622 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3570 MASTER LE NN 273621 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3571 MASTER LE NN 273793 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3572 MASTER LE NN 273797 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3573 MASTER LE NN 273789 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3574 MASTER LE NN 273744 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3575 MASTER LE NN 273712 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3576 MASTER LE NN 273818 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 3577 MASTER LE NN 273732 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3578 MASTER LE NN 273737 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3579 MASTER LE NN 273736 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3580 MASTER LE NN 273735 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3581 MASTER LE NN 273855 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3582 MASTER LE NN 273807 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3583 MASTER LE NN 273804 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3584 MASTER LE NN 273731 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3585 MASTER LE NN 273730 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3586 MASTER LE NN 273881 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX2)
Chain[4] 3587 MASTER LE NN 273817 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 3588 MASTER LE NN 273775 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3589 MASTER LE NN 273772 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG2_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3590 MASTER LE NN 273821 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 3591 MASTER LE NN 273822 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 3592 MASTER LE NN 273767 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD1_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3593 MASTER LE NN 273819 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 3594 MASTER LE NN 273820 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[4] 3595 MASTER LE NN 273753 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3596 MASTER LE NN 273756 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3597 MASTER LE NN 273763 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_LPM_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3598 MASTER LE NN 273811 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3599 MASTER LE NN 273768 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__GATE_PD2_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3600 MASTER LE NN 273774 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__RTIA_CONFIG_reg/dout_reg[1
] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3601 MASTER LE NN 273770 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PUP_CLAMP_THR_CONFIG_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3602 MASTER LE NN 273749 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3603 MASTER LE NN 273746 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3604 MASTER LE NN 273776 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3605 MASTER LE NN 273766 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PLOW_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3606 MASTER LE NN 273769 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__OCP_THR_CONFIG_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3607 MASTER LE NN 273484 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor11_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3608 MASTER LE NN 273495 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3609 MASTER LE NN 273492 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3610 MASTER LE NN 273491 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3611 MASTER LE NN 273482 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3612 MASTER LE NN 273493 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3613 MASTER LE NN 273485 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3614 MASTER LE NN 273752 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3615 MASTER LE NN 273751 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3616 MASTER LE NN 273748 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3617 MASTER LE NN 273764 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_EA_CONFIG_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3618 MASTER LE NN 273765 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__PUP_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3619 MASTER LE NN 273747 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3620 MASTER LE NN 273771 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__PLOW_CLAMP_THR_CONFIG_reg/
dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3621 MASTER LE NN 273762 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST4_0_array_u_TEST4_0__IB_BOT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3622 MASTER LE NN 273750 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3623 MASTER LE NN 273781 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3624 MASTER LE NN 273773 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TEST5_0_array_u_TEST5_0__STB_CONFIG3_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3625 MASTER LE NN 273813 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3626 MASTER LE NN 273757 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3627 MASTER LE NN 273812 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3628 MASTER LE NN 273861 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__VOLTAGE_STEPPER_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3629 MASTER LE NN 273780 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3630 MASTER LE NN 273777 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3631 MASTER LE NN 273713 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3632 MASTER LE NN 273733 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3633 MASTER LE NN 273782 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3634 MASTER LE NN 273599 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3635 MASTER LE NN 273739 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3636 MASTER LE NN 273734 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/TRIM_CTRL3_0_array_u_TRIM_CTRL3_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3637 MASTER LE NN 273815 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3638 MASTER LE NN 273755 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3639 MASTER LE NN 273758 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3640 MASTER LE NN 273760 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3641 MASTER LE NN 273585 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3642 MASTER LE NN 273716 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
 Chain[4] 3643 MASTER LE NN 273586 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3644 MASTER LE NN 273589 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3645 MASTER LE NN 273761 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3646 MASTER LE NN 273759 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3647 MASTER LE NN 273591 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_narrow_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3648 MASTER LE NN 273588 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3649 MASTER LE NN 273563 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3650 MASTER LE NN 273754 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3651 MASTER LE NN 273632 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_stepper_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3652 MASTER LE NN 273801 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3653 MASTER LE NN 273783 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3654 MASTER LE NN 273816 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3655 MASTER LE NN 273741 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3656 MASTER LE NN 273742 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3657 MASTER LE NN 273740 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3658 MASTER LE NN 273860 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STEPPER_CTL__STEP_RATE_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3659 MASTER LE NN 273796 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3660 MASTER LE NN 273738 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3661 MASTER LE NN 273640 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3662 MASTER LE NN 273633 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_smu_
u/GEN_PBUS_BUFF_STEPPER_DONE_d_stepper_done_pbuf_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3663 MASTER LE NN 273641 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3664 MASTER LE NN 273636 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_stepper_delay_u/d_delay_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3665 MASTER LE NN 273577 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3666 MASTER LE NN 273544 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3667 MASTER LE NN 273543 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3668 MASTER LE NN 273711 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3669 MASTER LE NN 273566 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3670 MASTER LE NN 273595 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_lpm_en_pfet_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3671 MASTER LE NN 273562 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3672 MASTER LE NN 273564 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3673 MASTER LE NN 273542 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3674 MASTER LE NN 273629 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_setpoint_gt_vset_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3675 MASTER LE NN 273643 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3676 MASTER LE NN 273527 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vcu_
u/reg_voltage_stepper_1p0_dig_flags_u/d_int_soft_start_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3677 MASTER LE NN 273580 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3678 MASTER LE NN 273575 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3679 MASTER LE NN 273638 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3680 MASTER LE NN 273578 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_pulse_wide_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3681 MASTER LE NN 273583 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3682 MASTER LE NN 273584 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3683 MASTER LE NN 273582 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3684 MASTER LE NN 273581 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3685 MASTER LE NN 273587 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3686 MASTER LE NN 273639 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_voltage_stepper_1p0_dig_mod/GEN_SETPOINT_reg_voltage_stepper_1p0_dig_vgu_
u/d_setpoint_int_frac_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3687 MASTER LE NN 273579 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_buff_en_delay_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 3688 MASTER LE NN 273574 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_mode_ctrl/u_ldo_n_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3689 MASTER LE NN 273715 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3690 MASTER LE NN 273488 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3691 MASTER LE NN 273489 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3692 MASTER LE NN 273487 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3693 MASTER LE NN 273483 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3694 MASTER LE NN 273490 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3695 MASTER LE NN 273486 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3696 MASTER LE NN 273494 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[4]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/u_ldo_n_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3697 MASTER LE NN 273153 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256607 - GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX3)
Chain[4] 3698 MASTER LE NN 273152 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3699 MASTER LE NN 273154 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3700 MASTER LE NN 273129 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3701 MASTER LE NN 273204 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3702 MASTER LE NN 273203 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3703 MASTER LE NN 273201 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3704 MASTER LE NN 273212 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3705 MASTER LE NN 273207 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3706 MASTER LE NN 273448 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3707 MASTER LE NN 273442 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3708 MASTER LE NN 273446 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3709 MASTER LE NN 273444 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3710 MASTER LE NN 273110 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3711 MASTER LE NN 273111 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3712 MASTER LE NN 273113 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3713 MASTER LE NN 273108 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3714 MASTER LE NN 273112 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3715 MASTER LE NN 273148 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3716 MASTER LE NN 273147 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3717 MASTER LE NN 273146 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3718 MASTER LE NN 273126 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3719 MASTER LE NN 273131 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3720 MASTER LE NN 273249 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3721 MASTER LE NN 273242 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3722 MASTER LE NN 273199 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3723 MASTER LE NN 273127 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3724 MASTER LE NN 273243 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3725 MASTER LE NN 273250 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3726 MASTER LE NN 273132 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3727 MASTER LE NN 273200 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3728 MASTER LE NN 273198 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3729 MASTER LE NN 273210 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3730 MASTER LE NN 273300 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 3731 MASTER LE NN 273254 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3732 MASTER LE NN 273301 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[4] 3733 MASTER LE NN 273305 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3734 MASTER LE NN 273209 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3735 MASTER LE NN 273208 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3736 MASTER LE NN 273128 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3737 MASTER LE NN 273211 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3738 MASTER LE NN 273205 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3739 MASTER LE NN 273206 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3740 MASTER LE NN 273202 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3741 MASTER LE NN 273130 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3742 MASTER LE NN 273256 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3743 MASTER LE NN 273308 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[4] 3744 MASTER LE NN 273257 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3745 MASTER LE NN 273251 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3746 MASTER LE NN 273244 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3747 MASTER LE NN 273253 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3748 MASTER LE NN 273255 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3749 MASTER LE NN 273247 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3750 MASTER LE NN 273246 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3751 MASTER LE NN 273248 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3752 MASTER LE NN 273245 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3753 MASTER LE NN 273149 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3754 MASTER LE NN 273151 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3755 MASTER LE NN 273107 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3756 MASTER LE NN 273109 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3757 MASTER LE NN 273395 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3758 MASTER LE NN 273396 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3759 MASTER LE NN 273296 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3760 MASTER LE NN 273292 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3761 MASTER LE NN 273294 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3762 MASTER LE NN 273293 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3763 MASTER LE NN 273299 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3764 MASTER LE NN 273298 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3765 MASTER LE NN 273320 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3766 MASTER LE NN 273318 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3767 MASTER LE NN 273297 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3768 MASTER LE NN 273316 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3769 MASTER LE NN 273284 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3770 MASTER LE NN 273283 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3771 MASTER LE NN 273240 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3772 MASTER LE NN 273094 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
 Chain[4] 3773 MASTER LE NN 273150 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3774 MASTER LE NN 273270 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3775 MASTER LE NN 273384 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3776 MASTER LE NN 273390 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3777 MASTER LE NN 273386 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3778 MASTER LE NN 273287 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3779 MASTER LE NN 273288 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3780 MASTER LE NN 273388 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3781 MASTER LE NN 273271 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3782 MASTER LE NN 273118 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3783 MASTER LE NN 273117 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3784 MASTER LE NN 273116 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3785 MASTER LE NN 273266 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3786 MASTER LE NN 273268 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3787 MASTER LE NN 273121 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3788 MASTER LE NN 273196 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3789 MASTER LE NN 273252 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3790 MASTER LE NN 273197 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3791 MASTER LE NN 273120 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3792 MASTER LE NN 273119 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3793 MASTER LE NN 273092 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3794 MASTER LE NN 273093 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3795 MASTER LE NN 273269 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3796 MASTER LE NN 273267 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3797 MASTER LE NN 273115 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3798 MASTER LE NN 273114 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3799 MASTER LE NN 273124 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3800 MASTER LE NN 273125 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[4] 3801 MASTER LE NN 273145 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/u_ldo_n_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[4] 3802 MASTER LE NN 273309 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3803 MASTER LE NN 273311 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3804 MASTER LE NN 273290 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3805 MASTER LE NN 273291 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3806 MASTER LE NN 273273 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[4] 3807 MASTER LE NN 273272 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3808 MASTER LE NN 273275 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3809 MASTER LE NN 273276 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3810 MASTER LE NN 273312 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3811 MASTER LE NN 273286 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3812 MASTER LE NN 273289 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3813 MASTER LE NN 273313 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3814 MASTER LE NN 273315 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3815 MASTER LE NN 273319 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[4] 3816 MASTER LE NN 273295 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[4] 3817 MASTER LE NN 273456 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3818 MASTER LE NN 273450 + GPIO_07
I_DCORE/\ldo_n_rmod_gen[3]_u_ldo_n_rmod/u_ldo_n_rdig/u_ldo_n_dig_mod/\u_ldo_n_dig_c
sr/u_ldo_n_rif_wrap/u_ldo_n_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[4] 3819 MASTER TE NN 288703 - GPIO_07
I_DCORE/\SNPS_PipeHead_u_waimea_dcore_glue/u_dft_test_ctrl/scan_chain_in[4]_1
(M31_1P5V6T_SFFQX3)
Chain[5] 0 MASTER LE NN 288698 + GPIO_07
I_DCORE/\SNPS_PipeTail_u_waimea_dcore_glue/u_dft_test_ctrl/scan_chain_out[5]_1
(M31_1P5V6T_DFFQX1)
Chain[5] 1 MASTER LE NN 281039 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cn
t_clear_reg (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 257165 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX2)
Chain[5] 2 MASTER LE NN 281040 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3 MASTER LE NN 281044 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 4 MASTER LE NN 281067 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 5 MASTER LE NN 281036 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 6 MASTER LE NN 281011 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 7 MASTER LE NN 281012 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 8 MASTER LE NN 281013 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 9 MASTER LE NN 280929 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 10 MASTER LE NN 280999 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 11 MASTER LE NN 281005 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 12 MASTER LE NN 280913 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 13 MASTER LE NN 280918 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[5] 14 MASTER LE NN 280998 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 15 MASTER LE NN 280915 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 16 MASTER LE NN 280933 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 17 MASTER LE NN 281073 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 18 MASTER LE NN 280994 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 19 MASTER LE NN 280993 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 20 MASTER LE NN 281070 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 21 MASTER LE NN 280995 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX3)
Chain[5] 22 MASTER LE NN 281072 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[5] 23 MASTER LE NN 280934 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 24 MASTER LE NN 281115 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 25 MASTER LE NN 281116 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 26 MASTER LE NN 281057 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 27 MASTER LE NN 281113 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 28 MASTER LE NN 281114 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 29 MASTER LE NN 281112 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 30 MASTER LE NN 281092 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 31 MASTER LE NN 281164 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 32 MASTER LE NN 281094 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 33 MASTER LE NN 281111 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 34 MASTER LE NN 281127 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 35 MASTER LE NN 281119 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 36 MASTER LE NN 281135 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 37 MASTER LE NN 281125 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 38 MASTER LE NN 281148 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 39 MASTER LE NN 280946 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 40 MASTER LE NN 280947 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 41 MASTER LE NN 281134 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 42 MASTER LE NN 281123 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 43 MASTER LE NN 281103 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 44 MASTER LE NN 281108 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 45 MASTER LE NN 281109 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 46 MASTER LE NN 281095 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 47 MASTER LE NN 281093 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 48 MASTER LE NN 281104 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 49 MASTER LE NN 281106 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 50 MASTER LE NN 281124 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 51 MASTER LE NN 281105 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 52 MASTER LE NN 281166 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 53 MASTER LE NN 281126 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dou
t_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 54 MASTER LE NN 281096 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 55 MASTER LE NN 280950 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 56 MASTER LE NN 280945 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 57 MASTER LE NN 280953 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 58 MASTER LE NN 281151 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 59 MASTER LE NN 280948 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 60 MASTER LE NN 281129 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 61 MASTER LE NN 281152 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 62 MASTER LE NN 280983 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 63 MASTER LE NN 280944 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 64 MASTER LE NN 281153 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 65 MASTER LE NN 280974 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 66 MASTER LE NN 280943 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 67 MASTER LE NN 280932 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 68 MASTER LE NN 281051 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 69 MASTER LE NN 281054 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 70 MASTER LE NN 281055 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 71 MASTER LE NN 280935 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 72 MASTER LE NN 281056 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 73 MASTER LE NN 280914 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 74 MASTER LE NN 280917 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 75 MASTER LE NN 280916 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 76 MASTER LE NN 280928 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 77 MASTER LE NN 280930 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 78 MASTER LE NN 281006 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 79 MASTER LE NN 281010 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 80 MASTER LE NN 281009 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 81 MASTER LE NN 281014 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 82 MASTER LE NN 281038 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 83 MASTER LE NN 281043 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cn
t_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 84 MASTER LE NN 281035 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 85 MASTER LE NN 281041 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 86 MASTER LE NN 281031 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 87 MASTER LE NN 281037 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 88 MASTER LE NN 281032 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 89 MASTER LE NN 281045 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 90 MASTER LE NN 281027 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 91 MASTER LE NN 281025 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cl
ear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 92 MASTER LE NN 281017 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 93 MASTER LE NN 281020 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 94 MASTER LE NN 281019 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_
en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 95 MASTER LE NN 281028 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_re
g (M31_1P5V6T_SFFRBQX1)
Chain[5] 96 MASTER LE NN 281064 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 97 MASTER LE NN 281065 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 98 MASTER LE NN 281042 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_in
t_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 99 MASTER LE NN 281034 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 100 MASTER LE NN 281033 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 101 MASTER LE NN 281016 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 102 MASTER LE NN 281008 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 103 MASTER LE NN 280931 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 104 MASTER LE NN 280927 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 105 MASTER LE NN 281007 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 106 MASTER LE NN 280984 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 107 MASTER LE NN 280912 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 108 MASTER LE NN 280941 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 109 MASTER LE NN 280942 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 110 MASTER LE NN 281141 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 111 MASTER LE NN 280985 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 112 MASTER LE NN 281002 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 113 MASTER LE NN 280924 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 114 MASTER LE NN 280925 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 115 MASTER LE NN 280937 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 116 MASTER LE NN 280957 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 117 MASTER LE NN 280938 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 118 MASTER LE NN 280939 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 119 MASTER LE NN 280959 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 120 MASTER LE NN 281145 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 121 MASTER LE NN 280958 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 122 MASTER LE NN 280911 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 123 MASTER LE NN 280954 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 124 MASTER LE NN 281052 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 125 MASTER LE NN 281053 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 126 MASTER LE NN 281050 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 127 MASTER LE NN 281147 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 128 MASTER LE NN 280960 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 129 MASTER LE NN 280936 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 130 MASTER LE NN 281046 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 131 MASTER LE NN 280962 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 132 MASTER LE NN 281047 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 133 MASTER LE NN 280967 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 134 MASTER LE NN 281049 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 135 MASTER LE NN 280970 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 136 MASTER LE NN 280991 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 137 MASTER LE NN 280969 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 138 MASTER LE NN 280963 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 139 MASTER LE NN 280964 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 140 MASTER LE NN 280961 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 141 MASTER LE NN 281068 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 142 MASTER LE NN 281069 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 143 MASTER LE NN 281154 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 144 MASTER LE NN 280955 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 145 MASTER LE NN 281000 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 146 MASTER LE NN 281063 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 147 MASTER LE NN 281140 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 148 MASTER LE NN 281144 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 149 MASTER LE NN 280949 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 150 MASTER LE NN 281150 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 151 MASTER LE NN 281149 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 152 MASTER LE NN 281167 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 153 MASTER LE NN 281146 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 154 MASTER LE NN 281136 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 155 MASTER LE NN 281107 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 156 MASTER LE NN 281122 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 157 MASTER LE NN 281165 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 158 MASTER LE NN 280986 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 159 MASTER LE NN 281102 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 160 MASTER LE NN 280951 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 161 MASTER LE NN 281132 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 162 MASTER LE NN 281142 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 163 MASTER LE NN 281180 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 164 MASTER LE NN 281120 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 165 MASTER LE NN 281213 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 166 MASTER LE NN 281209 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[7] (M31_1P5V6T_SFFSBQX1)
Chain[5] 167 MASTER LE NN 281097 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 168 MASTER LE NN 281089 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 169 MASTER LE NN 281098 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 170 MASTER LE NN 281168 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 171 MASTER LE NN 281110 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 172 MASTER LE NN 280952 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 173 MASTER LE NN 281101 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 174 MASTER LE NN 281100 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 175 MASTER LE NN 281099 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 176 MASTER LE NN 281133 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 177 MASTER LE NN 281130 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 178 MASTER LE NN 281131 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 179 MASTER LE NN 281118 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 180 MASTER LE NN 281163 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 181 MASTER LE NN 281062 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 182 MASTER LE NN 281137 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[5] 183 MASTER LE NN 281083 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 184 MASTER LE NN 280990 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 185 MASTER LE NN 280992 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 186 MASTER LE NN 281139 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 187 MASTER LE NN 281138 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 188 MASTER LE NN 280940 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 189 MASTER LE NN 281143 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 190 MASTER LE NN 280923 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 191 MASTER LE NN 281003 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 192 MASTER LE NN 281023 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 193 MASTER LE NN 281015 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 194 MASTER LE NN 281001 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 195 MASTER LE NN 281004 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 196 MASTER LE NN 281024 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 197 MASTER LE NN 281021 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 198 MASTER LE NN 281022 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_
vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 199 MASTER LE NN 281018 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 200 MASTER LE NN 281029 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en
_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 201 MASTER LE NN 281030 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 202 MASTER LE NN 281066 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 203 MASTER LE NN 281026 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 204 MASTER LE NN 281058 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 205 MASTER LE NN 280989 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 206 MASTER LE NN 280976 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 207 MASTER LE NN 281224 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 208 MASTER LE NN 280978 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 209 MASTER LE NN 280980 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 210 MASTER LE NN 280981 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 211 MASTER LE NN 280979 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 212 MASTER LE NN 280982 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 213 MASTER LE NN 280973 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 214 MASTER LE NN 280977 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 215 MASTER LE NN 280965 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 216 MASTER LE NN 280966 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 217 MASTER LE NN 280972 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 218 MASTER LE NN 280971 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 219 MASTER LE NN 281061 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 220 MASTER LE NN 280920 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 221 MASTER LE NN 281059 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 222 MASTER LE NN 281060 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[5] 223 MASTER LE NN 280919 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 224 MASTER LE NN 280921 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 225 MASTER LE NN 281179 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 226 MASTER LE NN 281181 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 227 MASTER LE NN 281216 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 228 MASTER LE NN 281207 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 229 MASTER LE NN 281204 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 230 MASTER LE NN 281087 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 231 MASTER LE NN 281090 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 232 MASTER LE NN 281208 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 233 MASTER LE NN 281177 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX2J)
Chain[5] 234 MASTER LE NN 281160 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 235 MASTER LE NN 281161 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 236 MASTER LE NN 281174 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 237 MASTER LE NN 281175 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 238 MASTER LE NN 281162 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 239 MASTER LE NN 281176 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 240 MASTER LE NN 281220 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 241 MASTER LE NN 281170 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 242 MASTER LE NN 281156 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 243 MASTER LE NN 281173 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 244 MASTER LE NN 281159 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 245 MASTER LE NN 281169 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 246 MASTER LE NN 281155 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 247 MASTER LE NN 281171 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 248 MASTER LE NN 281172 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 249 MASTER LE NN 281157 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 250 MASTER LE NN 281218 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 251 MASTER LE NN 281196 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 252 MASTER LE NN 281200 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 253 MASTER LE NN 281198 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 254 MASTER LE NN 281212 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 255 MASTER LE NN 281222 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 256 MASTER LE NN 281194 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 257 MASTER LE NN 281187 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 258 MASTER LE NN 281217 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 259 MASTER LE NN 281185 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 260 MASTER LE NN 281192 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 261 MASTER LE NN 281190 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 262 MASTER LE NN 281210 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 263 MASTER LE NN 281219 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 264 MASTER LE NN 281223 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 265 MASTER LE NN 281221 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 266 MASTER LE NN 281191 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 267 MASTER LE NN 281189 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 268 MASTER LE NN 281193 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 269 MASTER LE NN 281197 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 270 MASTER LE NN 281201 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 271 MASTER LE NN 281199 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 272 MASTER LE NN 281195 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 273 MASTER LE NN 281203 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 274 MASTER LE NN 281215 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 275 MASTER LE NN 281211 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 276 MASTER LE NN 281186 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 277 MASTER LE NN 281184 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
 Chain[5] 278 MASTER LE NN 281214 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 279 MASTER LE NN 281158 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 280 MASTER LE NN 281188 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 281 MASTER LE NN 281205 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 282 MASTER LE NN 281206 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 283 MASTER LE NN 281202 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 284 MASTER LE NN 281088 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 285 MASTER LE NN 281178 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 286 MASTER LE NN 281182 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 287 MASTER LE NN 281121 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/d
out_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 288 MASTER LE NN 281183 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 289 MASTER LE NN 280968 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 290 MASTER LE NN 281048 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 291 MASTER LE NN 280975 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 292 MASTER LE NN 280988 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 293 MASTER LE NN 280997 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 294 MASTER LE NN 280996 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 295 MASTER LE NN 280987 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 296 MASTER LE NN 280956 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 297 MASTER LE NN 280922 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 298 MASTER LE NN 280926 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[15]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 299 MASTER LE NN 280653 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 257139 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX1)
Chain[5] 300 MASTER LE NN 280652 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 301 MASTER LE NN 280650 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 302 MASTER LE NN 280632 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 303 MASTER LE NN 280645 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 304 MASTER LE NN 280631 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 305 MASTER LE NN 280630 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 306 MASTER LE NN 280641 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 307 MASTER LE NN 280607 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 308 MASTER LE NN 280728 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 309 MASTER LE NN 280636 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 310 MASTER LE NN 280633 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 311 MASTER LE NN 280605 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 312 MASTER LE NN 280666 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 313 MASTER LE NN 280744 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[5] 314 MASTER LE NN 280667 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 315 MASTER LE NN 280745 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 316 MASTER LE NN 280743 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 317 MASTER LE NN 280575 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 318 MASTER LE NN 280576 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 319 MASTER LE NN 280582 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 320 MASTER LE NN 280571 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 321 MASTER LE NN 280581 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 322 MASTER LE NN 280570 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 323 MASTER LE NN 280569 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 324 MASTER LE NN 280577 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 325 MASTER LE NN 280579 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 326 MASTER LE NN 280573 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 327 MASTER LE NN 280580 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 328 MASTER LE NN 280574 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 329 MASTER LE NN 280729 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 330 MASTER LE NN 280606 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 331 MASTER LE NN 280788 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 332 MASTER LE NN 280572 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 333 MASTER LE NN 280742 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 334 MASTER LE NN 280783 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 335 MASTER LE NN 280578 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 336 MASTER LE NN 280787 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 337 MASTER LE NN 280785 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 338 MASTER LE NN 280765 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 339 MASTER LE NN 280798 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dou
t_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 340 MASTER LE NN 280786 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 341 MASTER LE NN 280779 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 342 MASTER LE NN 280796 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 343 MASTER LE NN 280795 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 344 MASTER LE NN 280774 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 345 MASTER LE NN 280621 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 346 MASTER LE NN 280776 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 347 MASTER LE NN 280784 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 348 MASTER LE NN 280778 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 349 MASTER LE NN 280781 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 350 MASTER LE NN 280775 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 351 MASTER LE NN 280777 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 352 MASTER LE NN 280790 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 353 MASTER LE NN 280799 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 354 MASTER LE NN 280794 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 355 MASTER LE NN 280806 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 356 MASTER LE NN 280808 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 357 MASTER LE NN 280797 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 358 MASTER LE NN 280838 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 359 MASTER LE NN 280764 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 360 MASTER LE NN 280763 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 361 MASTER LE NN 280618 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 362 MASTER LE NN 280620 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 363 MASTER LE NN 280836 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 364 MASTER LE NN 280837 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 365 MASTER LE NN 280791 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 366 MASTER LE NN 280807 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 367 MASTER LE NN 280768 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 368 MASTER LE NN 280665 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 369 MASTER LE NN 280615 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 370 MASTER LE NN 280789 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 371 MASTER LE NN 280655 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 372 MASTER LE NN 280646 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 373 MASTER LE NN 280604 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 374 MASTER LE NN 280792 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 375 MASTER LE NN 280825 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 376 MASTER LE NN 280835 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 377 MASTER LE NN 280818 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 378 MASTER LE NN 280823 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 379 MASTER LE NN 280658 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 380 MASTER LE NN 280826 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 381 MASTER LE NN 280724 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 382 MASTER LE NN 280725 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 383 MASTER LE NN 280722 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 384 MASTER LE NN 280664 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 385 MASTER LE NN 280723 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 386 MASTER LE NN 280635 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 387 MASTER LE NN 280662 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 388 MASTER LE NN 280647 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 389 MASTER LE NN 280649 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 390 MASTER LE NN 280726 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 391 MASTER LE NN 280720 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 392 MASTER LE NN 280741 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 393 MASTER LE NN 280740 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 394 MASTER LE NN 280663 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 395 MASTER LE NN 280811 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 396 MASTER LE NN 280819 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 397 MASTER LE NN 280634 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 398 MASTER LE NN 280614 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 399 MASTER LE NN 280613 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 400 MASTER LE NN 280718 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 401 MASTER LE NN 280727 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 402 MASTER LE NN 280639 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 403 MASTER LE NN 280640 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 404 MASTER LE NN 280721 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 405 MASTER LE NN 280648 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 406 MASTER LE NN 280638 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 407 MASTER LE NN 280637 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 408 MASTER LE NN 280642 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 409 MASTER LE NN 280730 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 410 MASTER LE NN 280651 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 411 MASTER LE NN 280661 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 412 MASTER LE NN 280896 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 413 MASTER LE NN 280643 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 414 MASTER LE NN 280593 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 415 MASTER LE NN 280659 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 416 MASTER LE NN 280644 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 417 MASTER LE NN 280733 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 418 MASTER LE NN 280654 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 419 MASTER LE NN 280732 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[5] 420 MASTER LE NN 280731 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 421 MASTER LE NN 280660 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 422 MASTER LE NN 280668 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 423 MASTER LE NN 280669 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 424 MASTER LE NN 280588 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 425 MASTER LE NN 280585 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 426 MASTER LE NN 280589 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 427 MASTER LE NN 280590 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[5] 428 MASTER LE NN 280586 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 429 MASTER LE NN 280591 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 430 MASTER LE NN 280587 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 431 MASTER LE NN 280592 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 432 MASTER LE NN 280719 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 433 MASTER LE NN 280810 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 434 MASTER LE NN 280809 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[5] 435 MASTER LE NN 280824 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 436 MASTER LE NN 280820 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 437 MASTER LE NN 280793 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/d
out_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 438 MASTER LE NN 280816 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 439 MASTER LE NN 280617 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 440 MASTER LE NN 280625 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 441 MASTER LE NN 280619 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 442 MASTER LE NN 280782 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 443 MASTER LE NN 280839 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 444 MASTER LE NN 280828 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 445 MASTER LE NN 280830 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 446 MASTER LE NN 280831 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 447 MASTER LE NN 280833 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 448 MASTER LE NN 280846 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 449 MASTER LE NN 280834 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 450 MASTER LE NN 280848 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 451 MASTER LE NN 280802 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 452 MASTER LE NN 280805 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 453 MASTER LE NN 280852 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 454 MASTER LE NN 280804 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 455 MASTER LE NN 280767 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 456 MASTER LE NN 280850 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 457 MASTER LE NN 280780 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 458 MASTER LE NN 280800 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 459 MASTER LE NN 280623 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 460 MASTER LE NN 280801 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 461 MASTER LE NN 280851 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 462 MASTER LE NN 280766 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 463 MASTER LE NN 280624 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 464 MASTER LE NN 280812 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 465 MASTER LE NN 280814 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 466 MASTER LE NN 280853 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 467 MASTER LE NN 280622 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 468 MASTER LE NN 280855 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 469 MASTER LE NN 280854 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 470 MASTER LE NN 280672 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 471 MASTER LE NN 280760 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 472 MASTER LE NN 280803 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 473 MASTER LE NN 280840 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 474 MASTER LE NN 280880 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 475 MASTER LE NN 280841 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 476 MASTER LE NN 280843 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 477 MASTER LE NN 280844 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 478 MASTER LE NN 280842 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 479 MASTER LE NN 280874 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 480 MASTER LE NN 280771 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 481 MASTER LE NN 280734 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 482 MASTER LE NN 280822 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 483 MASTER LE NN 280821 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 484 MASTER LE NN 280616 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 485 MASTER LE NN 280626 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 486 MASTER LE NN 280608 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 487 MASTER LE NN 280628 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 488 MASTER LE NN 280629 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 489 MASTER LE NN 280609 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 490 MASTER LE NN 280673 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 491 MASTER LE NN 280674 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 492 MASTER LE NN 280675 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 493 MASTER LE NN 280687 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 494 MASTER LE NN 280695 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 495 MASTER LE NN 280693 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 496 MASTER LE NN 280696 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 497 MASTER LE NN 280688 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 498 MASTER LE NN 280676 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 499 MASTER LE NN 280680 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 500 MASTER LE NN 280677 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 501 MASTER LE NN 280610 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 502 MASTER LE NN 280612 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 503 MASTER LE NN 280813 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 504 MASTER LE NN 280656 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 505 MASTER LE NN 280584 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 506 MASTER LE NN 280594 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 507 MASTER LE NN 280598 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 508 MASTER LE NN 280597 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 509 MASTER LE NN 280671 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 510 MASTER LE NN 280611 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 511 MASTER LE NN 280600 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 512 MASTER LE NN 280679 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 513 MASTER LE NN 280603 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 514 MASTER LE NN 280678 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 515 MASTER LE NN 280684 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 516 MASTER LE NN 280681 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 517 MASTER LE NN 280694 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_
vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 518 MASTER LE NN 280691 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_
en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 519 MASTER LE NN 280686 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 520 MASTER LE NN 280690 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 521 MASTER LE NN 280683 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 522 MASTER LE NN 280689 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 523 MASTER LE NN 280697 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cl
ear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 524 MASTER LE NN 280700 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_re
g (M31_1P5V6T_SFFRBQX1)
Chain[5] 525 MASTER LE NN 280682 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 526 MASTER LE NN 280685 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 527 MASTER LE NN 280602 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 528 MASTER LE NN 280601 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 529 MASTER LE NN 280599 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 530 MASTER LE NN 280596 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 531 MASTER LE NN 280595 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 532 MASTER LE NN 280657 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 533 MASTER LE NN 280670 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 534 MASTER LE NN 280815 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 535 MASTER LE NN 280817 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 536 MASTER LE NN 280627 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 537 MASTER LE NN 280583 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 538 MASTER LE NN 280755 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 539 MASTER LE NN 280773 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 540 MASTER LE NN 280735 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 541 MASTER LE NN 280772 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 542 MASTER LE NN 280761 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 543 MASTER LE NN 280849 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 544 MASTER LE NN 280762 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 545 MASTER LE NN 280770 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 546 MASTER LE NN 280769 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 547 MASTER LE NN 280759 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 548 MASTER LE NN 280881 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[7] (M31_1P5V6T_SFFSBQX1)
Chain[5] 549 MASTER LE NN 280878 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 550 MASTER LE NN 280876 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 551 MASTER LE NN 280692 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 552 MASTER LE NN 280710 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 553 MASTER LE NN 280706 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 554 MASTER LE NN 280705 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 555 MASTER LE NN 280877 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 556 MASTER LE NN 280859 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 557 MASTER LE NN 280885 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 558 MASTER LE NN 280884 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 559 MASTER LE NN 280829 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 560 MASTER LE NN 280827 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 561 MASTER LE NN 280845 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 562 MASTER LE NN 280847 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 563 MASTER LE NN 280832 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 564 MASTER LE NN 280870 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 565 MASTER LE NN 280882 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 566 MASTER LE NN 280860 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 567 MASTER LE NN 280872 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 568 MASTER LE NN 280894 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 569 MASTER LE NN 280892 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 570 MASTER LE NN 280862 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 571 MASTER LE NN 280890 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 572 MASTER LE NN 280888 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 573 MASTER LE NN 280865 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 574 MASTER LE NN 280861 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 575 MASTER LE NN 280863 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 576 MASTER LE NN 280871 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 577 MASTER LE NN 280739 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 578 MASTER LE NN 280712 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 579 MASTER LE NN 280715 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cn
t_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 580 MASTER LE NN 280713 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 581 MASTER LE NN 280703 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 582 MASTER LE NN 280875 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 583 MASTER LE NN 280714 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_in
t_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 584 MASTER LE NN 280736 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 585 MASTER LE NN 280709 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 586 MASTER LE NN 280737 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 587 MASTER LE NN 280707 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 588 MASTER LE NN 280708 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 589 MASTER LE NN 280699 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 590 MASTER LE NN 280702 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 591 MASTER LE NN 280701 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en
_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 592 MASTER LE NN 280698 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 593 MASTER LE NN 280738 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 594 MASTER LE NN 280716 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 595 MASTER LE NN 280711 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cn
t_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 596 MASTER LE NN 280717 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 597 MASTER LE NN 280704 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 598 MASTER LE NN 280869 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 599 MASTER LE NN 280867 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 600 MASTER LE NN 280873 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 601 MASTER LE NN 280893 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 602 MASTER LE NN 280889 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 603 MASTER LE NN 280857 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 604 MASTER LE NN 280858 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 605 MASTER LE NN 280879 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 606 MASTER LE NN 280883 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 607 MASTER LE NN 280856 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 608 MASTER LE NN 280887 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 609 MASTER LE NN 280891 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 610 MASTER LE NN 280895 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 611 MASTER LE NN 280864 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 612 MASTER LE NN 280866 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 613 MASTER LE NN 280868 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 614 MASTER LE NN 280886 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[14]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 615 MASTER LE NN 280536 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
DSLAVE LS NN 257115 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX2)
Chain[5] 616 MASTER LE NN 280561 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 617 MASTER LE NN 280534 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 618 MASTER LE NN 280563 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 619 MASTER LE NN 280532 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 620 MASTER LE NN 280565 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 621 MASTER LE NN 280562 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 622 MASTER LE NN 280530 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 623 MASTER LE NN 280550 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 624 MASTER LE NN 280553 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[7] (M31_1P5V6T_SFFSBQX1)
Chain[5] 625 MASTER LE NN 280531 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 626 MASTER LE NN 280541 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 627 MASTER LE NN 280547 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 628 MASTER LE NN 280364 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 629 MASTER LE NN 280378 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 630 MASTER LE NN 280366 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_
vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 631 MASTER LE NN 280363 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_
en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 632 MASTER LE NN 280377 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 633 MASTER LE NN 280408 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 634 MASTER LE NN 280409 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 635 MASTER LE NN 280369 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cl
ear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 636 MASTER LE NN 280362 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 637 MASTER LE NN 280410 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 638 MASTER LE NN 280385 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 639 MASTER LE NN 280387 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cn
t_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 640 MASTER LE NN 280389 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 641 MASTER LE NN 280383 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cn
t_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 642 MASTER LE NN 280411 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 643 MASTER LE NN 280388 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 644 MASTER LE NN 280384 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 645 MASTER LE NN 280370 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 646 MASTER LE NN 280374 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 647 MASTER LE NN 280373 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en
_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 648 MASTER LE NN 280371 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 649 MASTER LE NN 280361 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 650 MASTER LE NN 280365 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 651 MASTER LE NN 280368 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 652 MASTER LE NN 280367 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 653 MASTER LE NN 280372 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_re
g (M31_1P5V6T_SFFRBQX1)
Chain[5] 654 MASTER LE NN 280348 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 655 MASTER LE NN 280386 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_in
t_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 656 MASTER LE NN 280346 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 657 MASTER LE NN 280545 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 658 MASTER LE NN 280539 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 659 MASTER LE NN 280537 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 660 MASTER LE NN 280535 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 661 MASTER LE NN 280533 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 662 MASTER LE NN 280566 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 663 MASTER LE NN 280564 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 664 MASTER LE NN 280528 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 665 MASTER LE NN 280549 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 666 MASTER LE NN 280551 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 667 MASTER LE NN 280529 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 668 MASTER LE NN 280560 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 669 MASTER LE NN 280555 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 670 MASTER LE NN 280538 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 671 MASTER LE NN 280554 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 672 MASTER LE NN 280434 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 673 MASTER LE NN 280546 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 674 MASTER LE NN 280559 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 675 MASTER LE NN 280544 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 676 MASTER LE NN 280442 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 677 MASTER LE NN 280433 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 678 MASTER LE NN 280431 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 679 MASTER LE NN 280512 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 680 MASTER LE NN 280552 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
 Chain[5] 681 MASTER LE NN 280501 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 682 MASTER LE NN 280513 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 683 MASTER LE NN 280515 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 684 MASTER LE NN 280391 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 685 MASTER LE NN 280390 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 686 MASTER LE NN 280306 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 687 MASTER LE NN 280300 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 688 MASTER LE NN 280301 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 689 MASTER LE NN 280543 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 690 MASTER LE NN 280347 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 691 MASTER LE NN 280282 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 692 MASTER LE NN 280283 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 693 MASTER LE NN 280284 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 694 MASTER LE NN 280285 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 695 MASTER LE NN 280340 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 696 MASTER LE NN 280331 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 697 MASTER LE NN 280341 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 698 MASTER LE NN 280258 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 699 MASTER LE NN 280259 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 700 MASTER LE NN 280286 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 701 MASTER LE NN 280349 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 702 MASTER LE NN 280351 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 703 MASTER LE NN 280352 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 704 MASTER LE NN 280376 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 705 MASTER LE NN 280256 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 706 MASTER LE NN 280257 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 707 MASTER LE NN 280260 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 708 MASTER LE NN 280343 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 709 MASTER LE NN 280261 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 710 MASTER LE NN 280262 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[5] 711 MASTER LE NN 280379 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 712 MASTER LE NN 280355 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 713 MASTER LE NN 280358 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 714 MASTER LE NN 280356 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 715 MASTER LE NN 280272 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 716 MASTER LE NN 280271 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 717 MASTER LE NN 280274 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 718 MASTER LE NN 280273 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 719 MASTER LE NN 280357 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 720 MASTER LE NN 280354 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 721 MASTER LE NN 280353 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 722 MASTER LE NN 280381 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 723 MASTER LE NN 280350 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 724 MASTER LE NN 280382 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 725 MASTER LE NN 280380 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 726 MASTER LE NN 280375 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 727 MASTER LE NN 280360 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 728 MASTER LE NN 280359 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 729 MASTER LE NN 280281 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 730 MASTER LE NN 280345 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 731 MASTER LE NN 280280 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 732 MASTER LE NN 280548 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 733 MASTER LE NN 280557 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 734 MASTER LE NN 280521 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 735 MASTER LE NN 280558 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 736 MASTER LE NN 280432 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 737 MASTER LE NN 280475 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 738 MASTER LE NN 280502 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 739 MASTER LE NN 280519 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 740 MASTER LE NN 280518 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 741 MASTER LE NN 280503 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 742 MASTER LE NN 280454 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 743 MASTER LE NN 280477 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 744 MASTER LE NN 280511 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 745 MASTER LE NN 280446 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 746 MASTER LE NN 280293 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 747 MASTER LE NN 280467 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 748 MASTER LE NN 280455 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 749 MASTER LE NN 280439 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 750 MASTER LE NN 280468 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 751 MASTER LE NN 280435 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 752 MASTER LE NN 280466 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 753 MASTER LE NN 280480 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 754 MASTER LE NN 280291 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 755 MASTER LE NN 280476 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 756 MASTER LE NN 280524 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 757 MASTER LE NN 280451 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 758 MASTER LE NN 280527 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 759 MASTER LE NN 280472 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 760 MASTER LE NN 280452 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 761 MASTER LE NN 280522 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 762 MASTER LE NN 280484 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 763 MASTER LE NN 280523 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 764 MASTER LE NN 280295 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 765 MASTER LE NN 280526 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 766 MASTER LE NN 280493 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 767 MASTER LE NN 280525 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 768 MASTER LE NN 280494 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 769 MASTER LE NN 280406 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 770 MASTER LE NN 280443 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 771 MASTER LE NN 280407 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 772 MASTER LE NN 280441 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 773 MASTER LE NN 280540 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 774 MASTER LE NN 280542 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 775 MASTER LE NN 280556 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 776 MASTER LE NN 280567 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 777 MASTER LE NN 280344 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 778 MASTER LE NN 280255 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 779 MASTER LE NN 280298 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 780 MASTER LE NN 280299 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
 Chain[5] 781 MASTER LE NN 280396 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 782 MASTER LE NN 280427 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 783 MASTER LE NN 280287 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 784 MASTER LE NN 280288 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 785 MASTER LE NN 280496 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 786 MASTER LE NN 280495 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 787 MASTER LE NN 280498 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 788 MASTER LE NN 280330 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 789 MASTER LE NN 280445 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 790 MASTER LE NN 280444 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 791 MASTER LE NN 280492 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 792 MASTER LE NN 280294 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 793 MASTER LE NN 280474 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 794 MASTER LE NN 280473 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 795 MASTER LE NN 280499 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 796 MASTER LE NN 280500 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 797 MASTER LE NN 280514 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 798 MASTER LE NN 280505 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 799 MASTER LE NN 280516 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 800 MASTER LE NN 280520 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 801 MASTER LE NN 280517 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 802 MASTER LE NN 280506 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 803 MASTER LE NN 280504 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 804 MASTER LE NN 280254 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 805 MASTER LE NN 280247 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 806 MASTER LE NN 280246 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 807 MASTER LE NN 280327 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 808 MASTER LE NN 280414 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 809 MASTER LE NN 280440 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 810 MASTER LE NN 280464 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 811 MASTER LE NN 280447 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 812 MASTER LE NN 280450 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 813 MASTER LE NN 280456 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 814 MASTER LE NN 280470 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dou
t_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 815 MASTER LE NN 280448 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 816 MASTER LE NN 280438 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 817 MASTER LE NN 280510 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 818 MASTER LE NN 280479 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 819 MASTER LE NN 280453 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 820 MASTER LE NN 280478 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 821 MASTER LE NN 280457 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 822 MASTER LE NN 280462 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 823 MASTER LE NN 280449 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 824 MASTER LE NN 280436 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 825 MASTER LE NN 280290 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 826 MASTER LE NN 280471 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 827 MASTER LE NN 280292 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 828 MASTER LE NN 280469 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 829 MASTER LE NN 280289 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 830 MASTER LE NN 280297 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 831 MASTER LE NN 280296 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 832 MASTER LE NN 280488 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 833 MASTER LE NN 280497 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 834 MASTER LE NN 280486 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 835 MASTER LE NN 280465 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/d
out_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 836 MASTER LE NN 280458 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 837 MASTER LE NN 280463 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 838 MASTER LE NN 280459 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 839 MASTER LE NN 280337 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 840 MASTER LE NN 280416 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[5] 841 MASTER LE NN 280415 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 842 MASTER LE NN 280417 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 843 MASTER LE NN 280338 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 844 MASTER LE NN 280339 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 845 MASTER LE NN 280277 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 846 MASTER LE NN 280305 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 847 MASTER LE NN 280334 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 848 MASTER LE NN 280307 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 849 MASTER LE NN 280308 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 850 MASTER LE NN 280336 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 851 MASTER LE NN 280413 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 852 MASTER LE NN 280397 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 853 MASTER LE NN 280487 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 854 MASTER LE NN 280319 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 855 MASTER LE NN 280393 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 856 MASTER LE NN 280400 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 857 MASTER LE NN 280313 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 858 MASTER LE NN 280279 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 859 MASTER LE NN 280309 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 860 MASTER LE NN 280310 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 861 MASTER LE NN 280314 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 862 MASTER LE NN 280311 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 863 MASTER LE NN 280485 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 864 MASTER LE NN 280335 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 865 MASTER LE NN 280263 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 866 MASTER LE NN 280332 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 867 MASTER LE NN 280316 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 868 MASTER LE NN 280264 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 869 MASTER LE NN 280399 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 870 MASTER LE NN 280398 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 871 MASTER LE NN 280402 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 872 MASTER LE NN 280568 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 873 MASTER LE NN 280317 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 874 MASTER LE NN 280328 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 875 MASTER LE NN 280489 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 876 MASTER LE NN 280491 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 877 MASTER LE NN 280269 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 878 MASTER LE NN 280268 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 879 MASTER LE NN 280342 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 880 MASTER LE NN 280329 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 881 MASTER LE NN 280302 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 882 MASTER LE NN 280303 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 883 MASTER LE NN 280405 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 884 MASTER LE NN 280270 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 885 MASTER LE NN 280404 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[5] 886 MASTER LE NN 280275 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 887 MASTER LE NN 280403 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 888 MASTER LE NN 280323 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 889 MASTER LE NN 280326 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 890 MASTER LE NN 280304 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 891 MASTER LE NN 280324 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 892 MASTER LE NN 280325 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 893 MASTER LE NN 280322 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 894 MASTER LE NN 280266 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 895 MASTER LE NN 280267 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
 Chain[5] 896 MASTER LE NN 280321 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX2J)
Chain[5] 897 MASTER LE NN 280333 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 898 MASTER LE NN 280320 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 899 MASTER LE NN 280315 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 900 MASTER LE NN 280265 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 901 MASTER LE NN 280312 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 902 MASTER LE NN 280392 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 903 MASTER LE NN 280483 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 904 MASTER LE NN 280482 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 905 MASTER LE NN 280412 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 906 MASTER LE NN 280395 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 907 MASTER LE NN 280394 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 908 MASTER LE NN 280278 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 909 MASTER LE NN 280481 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[5] 910 MASTER LE NN 280276 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 911 MASTER LE NN 280318 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 912 MASTER LE NN 280490 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 913 MASTER LE NN 280461 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 914 MASTER LE NN 280401 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 915 MASTER LE NN 280509 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 916 MASTER LE NN 280507 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 917 MASTER LE NN 280508 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 918 MASTER LE NN 280437 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 919 MASTER LE NN 280460 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 920 MASTER LE NN 280244 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 921 MASTER LE NN 280253 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 922 MASTER LE NN 280243 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 923 MASTER LE NN 280242 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 924 MASTER LE NN 280249 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 925 MASTER LE NN 280248 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 926 MASTER LE NN 280252 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 927 MASTER LE NN 280245 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 928 MASTER LE NN 280241 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 929 MASTER LE NN 280250 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 930 MASTER LE NN 280251 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[13]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 931 MASTER LE NN 280173 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 257091 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX1)
Chain[5] 932 MASTER LE NN 280187 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 933 MASTER LE NN 280183 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 934 MASTER LE NN 280226 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 935 MASTER LE NN 280237 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 936 MASTER LE NN 280236 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 937 MASTER LE NN 280202 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 938 MASTER LE NN 280235 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 939 MASTER LE NN 280228 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 940 MASTER LE NN 280210 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 941 MASTER LE NN 280234 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 942 MASTER LE NN 280232 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 943 MASTER LE NN 280233 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[2] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 944 MASTER LE NN 280204 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 945 MASTER LE NN 280203 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 946 MASTER LE NN 280206 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 947 MASTER LE NN 280227 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 948 MASTER LE NN 280208 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 949 MASTER LE NN 280220 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 950 MASTER LE NN 280230 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 951 MASTER LE NN 280214 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 952 MASTER LE NN 280224 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 953 MASTER LE NN 280189 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 954 MASTER LE NN 280175 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 955 MASTER LE NN 280169 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 956 MASTER LE NN 280184 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 957 MASTER LE NN 280185 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 958 MASTER LE NN 280170 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 959 MASTER LE NN 280188 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 960 MASTER LE NN 280174 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 961 MASTER LE NN 280172 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 962 MASTER LE NN 280186 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 963 MASTER LE NN 280171 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 964 MASTER LE NN 280176 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 965 MASTER LE NN 280190 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 966 MASTER LE NN 280105 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 967 MASTER LE NN 280102 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 968 MASTER LE NN 280222 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 969 MASTER LE NN 280217 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 970 MASTER LE NN 279968 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 971 MASTER LE NN 279961 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 972 MASTER LE NN 279969 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 973 MASTER LE NN 279964 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 974 MASTER LE NN 280141 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dou
t_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 975 MASTER LE NN 279963 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 976 MASTER LE NN 279962 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 977 MASTER LE NN 280126 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 978 MASTER LE NN 279965 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 979 MASTER LE NN 279967 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 980 MASTER LE NN 279966 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 981 MASTER LE NN 280103 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 982 MASTER LE NN 280112 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 983 MASTER LE NN 280113 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 984 MASTER LE NN 280115 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 985 MASTER LE NN 280116 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 986 MASTER LE NN 280182 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 987 MASTER LE NN 280181 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 988 MASTER LE NN 280145 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 989 MASTER LE NN 280150 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 990 MASTER LE NN 280196 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 991 MASTER LE NN 280147 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 992 MASTER LE NN 280077 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 993 MASTER LE NN 280197 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 994 MASTER LE NN 280168 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 995 MASTER LE NN 280144 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 996 MASTER LE NN 280149 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 997 MASTER LE NN 280133 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 998 MASTER LE NN 280108 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 999 MASTER LE NN 280120 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1000 MASTER LE NN 280159 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1001 MASTER LE NN 280122 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1002 MASTER LE NN 280146 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1003 MASTER LE NN 280135 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1004 MASTER LE NN 280078 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1005 MASTER LE NN 280110 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1006 MASTER LE NN 280194 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1007 MASTER LE NN 280111 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1008 MASTER LE NN 280136 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/d
out_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1009 MASTER LE NN 280163 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1010 MASTER LE NN 280109 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1011 MASTER LE NN 280165 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1012 MASTER LE NN 280161 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1013 MASTER LE NN 280107 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1014 MASTER LE NN 280157 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1015 MASTER LE NN 280177 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1016 MASTER LE NN 280164 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1017 MASTER LE NN 280155 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1018 MASTER LE NN 280179 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1019 MASTER LE NN 280193 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1020 MASTER LE NN 280180 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1021 MASTER LE NN 280192 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1022 MASTER LE NN 280195 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1023 MASTER LE NN 280178 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1024 MASTER LE NN 280148 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1025 MASTER LE NN 280114 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1026 MASTER LE NN 280104 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1027 MASTER LE NN 280191 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1028 MASTER LE NN 280216 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1029 MASTER LE NN 280223 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[7] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1030 MASTER LE NN 280225 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1031 MASTER LE NN 280198 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1032 MASTER LE NN 280221 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1033 MASTER LE NN 280218 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1034 MASTER LE NN 280199 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1035 MASTER LE NN 280219 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1036 MASTER LE NN 280231 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1037 MASTER LE NN 280201 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1038 MASTER LE NN 280200 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1039 MASTER LE NN 280205 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1040 MASTER LE NN 280229 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1041 MASTER LE NN 280207 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1042 MASTER LE NN 280213 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1043 MASTER LE NN 280212 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1044 MASTER LE NN 280239 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1045 MASTER LE NN 280106 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1046 MASTER LE NN 280166 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1047 MASTER LE NN 280151 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1048 MASTER LE NN 280152 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[5] 1049 MASTER LE NN 279916 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1050 MASTER LE NN 279926 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1051 MASTER LE NN 279921 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1052 MASTER LE NN 279925 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1053 MASTER LE NN 280011 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1054 MASTER LE NN 280009 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1055 MASTER LE NN 280088 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1056 MASTER LE NN 280086 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1057 MASTER LE NN 280010 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1058 MASTER LE NN 279960 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1059 MASTER LE NN 279950 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX2J)
Chain[5] 1060 MASTER LE NN 280007 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1061 MASTER LE NN 279970 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1062 MASTER LE NN 280083 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1063 MASTER LE NN 280067 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1064 MASTER LE NN 279952 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1065 MASTER LE NN 279972 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1066 MASTER LE NN 280162 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1067 MASTER LE NN 280065 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1068 MASTER LE NN 280068 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1069 MASTER LE NN 280084 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1070 MASTER LE NN 279927 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1071 MASTER LE NN 279979 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1072 MASTER LE NN 279980 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1073 MASTER LE NN 280066 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1074 MASTER LE NN 280061 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1075 MASTER LE NN 280062 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1076 MASTER LE NN 279978 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1077 MASTER LE NN 279974 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1078 MASTER LE NN 280160 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1079 MASTER LE NN 279973 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1080 MASTER LE NN 280016 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1081 MASTER LE NN 280063 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1082 MASTER LE NN 280071 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1083 MASTER LE NN 280008 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1084 MASTER LE NN 279931 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1085 MASTER LE NN 279930 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1086 MASTER LE NN 279929 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1087 MASTER LE NN 279991 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1088 MASTER LE NN 280064 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1089 MASTER LE NN 279951 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1090 MASTER LE NN 280017 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1091 MASTER LE NN 279975 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1092 MASTER LE NN 279976 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1093 MASTER LE NN 280070 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1094 MASTER LE NN 280069 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1095 MASTER LE NN 279985 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1096 MASTER LE NN 279934 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1097 MASTER LE NN 279933 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1098 MASTER LE NN 279987 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1099 MASTER LE NN 279981 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1100 MASTER LE NN 279986 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1101 MASTER LE NN 279983 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1102 MASTER LE NN 279984 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1103 MASTER LE NN 279982 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1104 MASTER LE NN 279989 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1105 MASTER LE NN 279992 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1106 MASTER LE NN 279937 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1107 MASTER LE NN 279988 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1108 MASTER LE NN 279935 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1109 MASTER LE NN 279936 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1110 MASTER LE NN 279928 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1111 MASTER LE NN 279932 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1112 MASTER LE NN 279958 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1113 MASTER LE NN 279957 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1114 MASTER LE NN 280006 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1115 MASTER LE NN 279977 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3]
(M31_1P5V6T_SFFRBQX2J)
Chain[5] 1116 MASTER LE NN 279971 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1117 MASTER LE NN 280015 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1118 MASTER LE NN 280154 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1119 MASTER LE NN 279948 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1120 MASTER LE NN 280153 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1121 MASTER LE NN 279949 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1122 MASTER LE NN 280098 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1123 MASTER LE NN 279914 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1124 MASTER LE NN 279919 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1125 MASTER LE NN 279920 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1126 MASTER LE NN 279917 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1127 MASTER LE NN 279923 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1128 MASTER LE NN 279924 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1129 MASTER LE NN 279922 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1130 MASTER LE NN 279918 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1131 MASTER LE NN 279913 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1132 MASTER LE NN 279915 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1133 MASTER LE NN 279999 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1134 MASTER LE NN 280087 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1135 MASTER LE NN 279990 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1136 MASTER LE NN 280132 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1137 MASTER LE NN 280130 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1138 MASTER LE NN 280085 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1139 MASTER LE NN 280072 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1140 MASTER LE NN 280131 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1141 MASTER LE NN 279959 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1142 MASTER LE NN 280123 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1143 MASTER LE NN 280142 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1144 MASTER LE NN 280138 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1145 MASTER LE NN 280125 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1146 MASTER LE NN 280137 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1147 MASTER LE NN 280128 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1148 MASTER LE NN 280140 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1149 MASTER LE NN 280117 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1150 MASTER LE NN 280002 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1151 MASTER LE NN 280118 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1152 MASTER LE NN 280119 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1153 MASTER LE NN 280167 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[5] 1154 MASTER LE NN 280134 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1155 MASTER LE NN 280139 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1156 MASTER LE NN 280127 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1157 MASTER LE NN 280129 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1158 MASTER LE NN 280121 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1159 MASTER LE NN 280124 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1160 MASTER LE NN 280143 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1161 MASTER LE NN 280215 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1162 MASTER LE NN 280209 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1163 MASTER LE NN 280211 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1164 MASTER LE NN 280240 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1165 MASTER LE NN 279956 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1166 MASTER LE NN 279955 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1167 MASTER LE NN 279953 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1168 MASTER LE NN 279954 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1169 MASTER LE NN 279939 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
 Chain[5] 1170 MASTER LE NN 280000 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1171 MASTER LE NN 280156 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1172 MASTER LE NN 280001 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1173 MASTER LE NN 280013 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1174 MASTER LE NN 279942 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1175 MASTER LE NN 280014 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1176 MASTER LE NN 280158 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1177 MASTER LE NN 279947 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1178 MASTER LE NN 279944 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1179 MASTER LE NN 280018 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1180 MASTER LE NN 280019 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1181 MASTER LE NN 280020 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1182 MASTER LE NN 280038 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1183 MASTER LE NN 280035 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1184 MASTER LE NN 280049 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1185 MASTER LE NN 280048 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1186 MASTER LE NN 280057 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_in
t_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1187 MASTER LE NN 280047 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1188 MASTER LE NN 280060 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1189 MASTER LE NN 280024 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1190 MASTER LE NN 280046 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1191 MASTER LE NN 280025 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1192 MASTER LE NN 280027 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1193 MASTER LE NN 280028 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1194 MASTER LE NN 280050 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1195 MASTER LE NN 280029 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1196 MASTER LE NN 280054 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cn
t_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1197 MASTER LE NN 280052 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1198 MASTER LE NN 280053 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1199 MASTER LE NN 280058 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cn
t_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1200 MASTER LE NN 280056 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1201 MASTER LE NN 280080 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 1202 MASTER LE NN 280079 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 1203 MASTER LE NN 280036 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 1204 MASTER LE NN 280039 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1205 MASTER LE NN 279943 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1206 MASTER LE NN 279938 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1207 MASTER LE NN 280004 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1208 MASTER LE NN 280003 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1209 MASTER LE NN 280076 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 1210 MASTER LE NN 280012 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1211 MASTER LE NN 280005 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1212 MASTER LE NN 280073 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1213 MASTER LE NN 279993 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1214 MASTER LE NN 280238 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX2)
Chain[5] 1215 MASTER LE NN 280075 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1216 MASTER LE NN 280074 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1217 MASTER LE NN 279998 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1218 MASTER LE NN 279995 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1219 MASTER LE NN 279994 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1220 MASTER LE NN 279997 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1221 MASTER LE NN 279996 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 1222 MASTER LE NN 279941 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1223 MASTER LE NN 279940 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1224 MASTER LE NN 279945 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1225 MASTER LE NN 279946 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1226 MASTER LE NN 280022 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1227 MASTER LE NN 280023 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1228 MASTER LE NN 280034 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_
en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1229 MASTER LE NN 280037 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_
vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1230 MASTER LE NN 280030 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1231 MASTER LE NN 280021 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1232 MASTER LE NN 280031 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1233 MASTER LE NN 280043 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_re
g (M31_1P5V6T_SFFRBQX1)
Chain[5] 1234 MASTER LE NN 280032 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1235 MASTER LE NN 280033 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1236 MASTER LE NN 280040 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cl
ear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1237 MASTER LE NN 280042 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1238 MASTER LE NN 280044 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en
_reg (M31_1P5V6T_SFFRBQX1)
 Chain[5] 1239 MASTER LE NN 280045 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1240 MASTER LE NN 280081 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1241 MASTER LE NN 280041 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1242 MASTER LE NN 280059 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1243 MASTER LE NN 280055 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1244 MASTER LE NN 280082 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1245 MASTER LE NN 280051 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1246 MASTER LE NN 280026 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[12]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1247 MASTER LE NN 279696 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 257070 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX2)
Chain[5] 1248 MASTER LE NN 279719 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1249 MASTER LE NN 279709 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_
vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1250 MASTER LE NN 279705 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1251 MASTER LE NN 279751 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 1252 MASTER LE NN 279697 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1253 MASTER LE NN 279700 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1254 MASTER LE NN 279729 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_in
t_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1255 MASTER LE NN 279699 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1256 MASTER LE NN 279714 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1257 MASTER LE NN 279716 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en
_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1258 MASTER LE NN 279713 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1259 MASTER LE NN 279753 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1260 MASTER LE NN 279712 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cl
ear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1261 MASTER LE NN 279717 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1262 MASTER LE NN 279726 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cn
t_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1263 MASTER LE NN 279732 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1264 MASTER LE NN 279701 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1265 MASTER LE NN 279718 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1266 MASTER LE NN 279752 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 1267 MASTER LE NN 279728 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1268 MASTER LE NN 279730 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cn
t_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1269 MASTER LE NN 279754 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1270 MASTER LE NN 279731 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1271 MASTER LE NN 279727 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1272 MASTER LE NN 279698 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1273 MASTER LE NN 279722 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1274 MASTER LE NN 279693 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1275 MASTER LE NN 279688 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1276 MASTER LE NN 279723 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1277 MASTER LE NN 279725 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1278 MASTER LE NN 279724 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1279 MASTER LE NN 279704 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1280 MASTER LE NN 279715 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_re
g (M31_1P5V6T_SFFRBQX1)
Chain[5] 1281 MASTER LE NN 279721 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1282 MASTER LE NN 279720 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1283 MASTER LE NN 279706 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_
en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1284 MASTER LE NN 279861 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1285 MASTER LE NN 279847 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1286 MASTER LE NN 279863 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1287 MASTER LE NN 279849 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1288 MASTER LE NN 279856 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1289 MASTER LE NN 279862 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1290 MASTER LE NN 279848 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1291 MASTER LE NN 279842 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1292 MASTER LE NN 279857 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1293 MASTER LE NN 279889 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1294 MASTER LE NN 279785 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1295 MASTER LE NN 279854 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1296 MASTER LE NN 279817 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1297 MASTER LE NN 279869 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1298 MASTER LE NN 279865 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1299 MASTER LE NN 279687 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1300 MASTER LE NN 279750 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1301 MASTER LE NN 279781 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1302 MASTER LE NN 279808 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/d
out_reg[0] (M31_1P5V6T_SFFSBQX1)
 Chain[5] 1303 MASTER LE NN 279779 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1304 MASTER LE NN 279778 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1305 MASTER LE NN 279630 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1306 MASTER LE NN 279840 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1307 MASTER LE NN 279829 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1308 MASTER LE NN 279841 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1309 MASTER LE NN 279673 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1310 MASTER LE NN 279749 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1311 MASTER LE NN 279798 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1312 MASTER LE NN 279835 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1313 MASTER LE NN 279807 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1314 MASTER LE NN 279801 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1315 MASTER LE NN 279631 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1316 MASTER LE NN 279642 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1317 MASTER LE NN 279770 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1318 MASTER LE NN 279641 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1319 MASTER LE NN 279602 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1320 MASTER LE NN 279604 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1321 MASTER LE NN 279601 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1322 MASTER LE NN 279600 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1323 MASTER LE NN 279605 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1324 MASTER LE NN 279710 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1325 MASTER LE NN 279708 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1326 MASTER LE NN 279707 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1327 MASTER LE NN 279711 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1328 MASTER LE NN 279703 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1329 MASTER LE NN 279694 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1330 MASTER LE NN 279691 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1331 MASTER LE NN 279692 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1332 MASTER LE NN 279695 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1333 MASTER LE NN 279678 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1334 MASTER LE NN 279627 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1335 MASTER LE NN 279825 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1336 MASTER LE NN 279623 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1337 MASTER LE NN 279643 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1338 MASTER LE NN 279644 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1339 MASTER LE NN 279689 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1340 MASTER LE NN 279616 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1341 MASTER LE NN 279619 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1342 MASTER LE NN 279617 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1343 MASTER LE NN 279614 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1344 MASTER LE NN 279618 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1345 MASTER LE NN 279615 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1346 MASTER LE NN 279832 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1347 MASTER LE NN 279834 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1348 MASTER LE NN 279649 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1349 MASTER LE NN 279671 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1350 MASTER LE NN 279685 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1351 MASTER LE NN 279734 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1352 MASTER LE NN 279733 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1353 MASTER LE NN 279683 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1354 MASTER LE NN 279684 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1355 MASTER LE NN 279672 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 1356 MASTER LE NN 279611 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1357 MASTER LE NN 279610 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1358 MASTER LE NN 279612 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1359 MASTER LE NN 279613 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1360 MASTER LE NN 279686 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1361 MASTER LE NN 279828 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1362 MASTER LE NN 279830 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1363 MASTER LE NN 279826 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1364 MASTER LE NN 279626 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1365 MASTER LE NN 279625 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1366 MASTER LE NN 279624 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1367 MASTER LE NN 279690 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1368 MASTER LE NN 279702 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1369 MASTER LE NN 279629 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1370 MASTER LE NN 279628 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1371 MASTER LE NN 279606 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1372 MASTER LE NN 279599 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1373 MASTER LE NN 279603 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1374 MASTER LE NN 279824 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[5] 1375 MASTER LE NN 279838 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1376 MASTER LE NN 279839 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1377 MASTER LE NN 279836 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1378 MASTER LE NN 279833 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1379 MASTER LE NN 279831 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1380 MASTER LE NN 279837 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1381 MASTER LE NN 279827 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1382 MASTER LE NN 279788 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1383 MASTER LE NN 279787 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1384 MASTER LE NN 279868 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1385 MASTER LE NN 279870 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1386 MASTER LE NN 279818 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1387 MASTER LE NN 279855 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1388 MASTER LE NN 279786 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1389 MASTER LE NN 279864 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1390 MASTER LE NN 279866 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1391 MASTER LE NN 279867 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1392 MASTER LE NN 279819 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1393 MASTER LE NN 279820 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1394 MASTER LE NN 279784 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1395 MASTER LE NN 279777 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1396 MASTER LE NN 279859 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1397 MASTER LE NN 279858 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1398 MASTER LE NN 279860 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1399 MASTER LE NN 279846 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1400 MASTER LE NN 279843 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1401 MASTER LE NN 279878 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1402 MASTER LE NN 279877 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1403 MASTER LE NN 279876 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1404 MASTER LE NN 279906 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1405 MASTER LE NN 279882 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1406 MASTER LE NN 279910 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1407 MASTER LE NN 279908 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1408 MASTER LE NN 279899 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1409 MASTER LE NN 279905 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1410 MASTER LE NN 279880 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1411 MASTER LE NN 279909 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1412 MASTER LE NN 279885 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1413 MASTER LE NN 279875 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1414 MASTER LE NN 279897 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1415 MASTER LE NN 279881 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1416 MASTER LE NN 279903 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1417 MASTER LE NN 279879 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
 Chain[5] 1418 MASTER LE NN 279901 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1419 MASTER LE NN 279887 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1420 MASTER LE NN 279907 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1421 MASTER LE NN 279884 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1422 MASTER LE NN 279883 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1423 MASTER LE NN 279895 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1424 MASTER LE NN 279844 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1425 MASTER LE NN 279845 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1426 MASTER LE NN 279890 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1427 MASTER LE NN 279871 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1428 MASTER LE NN 279874 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1429 MASTER LE NN 279904 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1430 MASTER LE NN 279894 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1431 MASTER LE NN 279891 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1432 MASTER LE NN 279632 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 1433 MASTER LE NN 279640 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1434 MASTER LE NN 279638 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1435 MASTER LE NN 279637 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1436 MASTER LE NN 279776 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1437 MASTER LE NN 279853 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1438 MASTER LE NN 279635 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1439 MASTER LE NN 279789 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1440 MASTER LE NN 279636 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1441 MASTER LE NN 279814 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1442 MASTER LE NN 279796 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1443 MASTER LE NN 279813 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dou
t_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1444 MASTER LE NN 279793 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1445 MASTER LE NN 279850 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1446 MASTER LE NN 279783 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1447 MASTER LE NN 279810 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1448 MASTER LE NN 279797 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 1449 MASTER LE NN 279815 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1450 MASTER LE NN 279809 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1451 MASTER LE NN 279805 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1452 MASTER LE NN 279795 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1453 MASTER LE NN 279782 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1454 MASTER LE NN 279851 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1455 MASTER LE NN 279780 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1456 MASTER LE NN 279799 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1457 MASTER LE NN 279811 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1458 MASTER LE NN 279816 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1459 MASTER LE NN 279794 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1460 MASTER LE NN 279741 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1461 MASTER LE NN 279738 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1462 MASTER LE NN 279911 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX3)
Chain[5] 1463 MASTER LE NN 279739 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1464 MASTER LE NN 279740 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 1465 MASTER LE NN 279737 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1466 MASTER LE NN 279608 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1467 MASTER LE NN 279735 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1468 MASTER LE NN 279742 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1469 MASTER LE NN 279679 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1470 MASTER LE NN 279662 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1471 MASTER LE NN 279757 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1472 MASTER LE NN 279760 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1473 MASTER LE NN 279677 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1474 MASTER LE NN 279758 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1475 MASTER LE NN 279655 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1476 MASTER LE NN 279654 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1477 MASTER LE NN 279744 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1478 MASTER LE NN 279621 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1479 MASTER LE NN 279663 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1480 MASTER LE NN 279660 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1481 MASTER LE NN 279676 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1482 MASTER LE NN 279736 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1483 MASTER LE NN 279658 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1484 MASTER LE NN 279659 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1485 MASTER LE NN 279609 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1486 MASTER LE NN 279607 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1487 MASTER LE NN 279675 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1488 MASTER LE NN 279674 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1489 MASTER LE NN 279756 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1490 MASTER LE NN 279755 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1491 MASTER LE NN 279759 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1492 MASTER LE NN 279681 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1493 MASTER LE NN 279680 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1494 MASTER LE NN 279661 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1495 MASTER LE NN 279670 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1496 MASTER LE NN 279803 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1497 MASTER LE NN 279804 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 1498 MASTER LE NN 279802 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1499 MASTER LE NN 279800 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1500 MASTER LE NN 279823 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1501 MASTER LE NN 279822 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1502 MASTER LE NN 279812 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1503 MASTER LE NN 279806 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1504 MASTER LE NN 279791 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1505 MASTER LE NN 279790 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1506 MASTER LE NN 279852 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1507 MASTER LE NN 279821 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1508 MASTER LE NN 279792 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1509 MASTER LE NN 279634 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1510 MASTER LE NN 279633 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1511 MASTER LE NN 279639 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1512 MASTER LE NN 279775 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1513 MASTER LE NN 279774 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1514 MASTER LE NN 279896 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[7] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1515 MASTER LE NN 279892 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1516 MASTER LE NN 279873 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1517 MASTER LE NN 279893 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1518 MASTER LE NN 279872 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1519 MASTER LE NN 279886 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1520 MASTER LE NN 279888 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1521 MASTER LE NN 279902 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1522 MASTER LE NN 279900 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1523 MASTER LE NN 279898 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1524 MASTER LE NN 279588 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1525 MASTER LE NN 279593 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1526 MASTER LE NN 279592 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1527 MASTER LE NN 279746 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1528 MASTER LE NN 279747 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1529 MASTER LE NN 279748 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 1530 MASTER LE NN 279651 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1531 MASTER LE NN 279650 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1532 MASTER LE NN 279648 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1533 MASTER LE NN 279682 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1534 MASTER LE NN 279620 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1535 MASTER LE NN 279645 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1536 MASTER LE NN 279622 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1537 MASTER LE NN 279743 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1538 MASTER LE NN 279745 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1539 MASTER LE NN 279912 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1540 MASTER LE NN 279647 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1541 MASTER LE NN 279646 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1542 MASTER LE NN 279664 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1543 MASTER LE NN 279653 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1544 MASTER LE NN 279652 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1545 MASTER LE NN 279657 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1546 MASTER LE NN 279656 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1547 MASTER LE NN 279666 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1548 MASTER LE NN 279668 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1549 MASTER LE NN 279669 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1550 MASTER LE NN 279665 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1551 MASTER LE NN 279667 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1552 MASTER LE NN 279594 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1553 MASTER LE NN 279590 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1554 MASTER LE NN 279591 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1555 MASTER LE NN 279595 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1556 MASTER LE NN 279596 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1557 MASTER LE NN 279597 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1558 MASTER LE NN 279598 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1559 MASTER LE NN 279589 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1560 MASTER LE NN 279585 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1561 MASTER LE NN 279586 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1562 MASTER LE NN 279587 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[11]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1563 MASTER LE NN 279378 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 257043 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX1)
Chain[5] 1564 MASTER LE NN 279373 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 1565 MASTER LE NN 279370 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1566 MASTER LE NN 279387 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1567 MASTER LE NN 279374 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1568 MASTER LE NN 279389 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en
_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1569 MASTER LE NN 279371 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1570 MASTER LE NN 279395 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1571 MASTER LE NN 279399 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cn
t_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1572 MASTER LE NN 279391 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1573 MASTER LE NN 279397 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1574 MASTER LE NN 279427 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1575 MASTER LE NN 279405 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1576 MASTER LE NN 279396 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1577 MASTER LE NN 279366 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1578 MASTER LE NN 279398 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1579 MASTER LE NN 279425 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 1580 MASTER LE NN 279404 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1581 MASTER LE NN 279400 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1582 MASTER LE NN 279403 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cn
t_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1583 MASTER LE NN 279401 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1584 MASTER LE NN 279426 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1585 MASTER LE NN 279424 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 1586 MASTER LE NN 279386 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1587 MASTER LE NN 279390 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1588 MASTER LE NN 279392 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cl
ear_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1589 MASTER LE NN 279385 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cl
ear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1590 MASTER LE NN 279393 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1591 MASTER LE NN 279394 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1592 MASTER LE NN 279533 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1593 MASTER LE NN 279535 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1594 MASTER LE NN 279570 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1595 MASTER LE NN 279560 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1596 MASTER LE NN 279516 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1597 MASTER LE NN 279548 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1598 MASTER LE NN 279550 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1599 MASTER LE NN 279515 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1600 MASTER LE NN 279556 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1601 MASTER LE NN 279521 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1602 MASTER LE NN 279519 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1603 MASTER LE NN 279552 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1604 MASTER LE NN 279517 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1605 MASTER LE NN 279558 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1606 MASTER LE NN 279520 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1607 MASTER LE NN 279554 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1608 MASTER LE NN 279576 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1609 MASTER LE NN 279580 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1610 MASTER LE NN 279544 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1611 MASTER LE NN 279578 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1612 MASTER LE NN 279567 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1613 MASTER LE NN 279582 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1614 MASTER LE NN 279575 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1615 MASTER LE NN 279581 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1616 MASTER LE NN 279583 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1617 MASTER LE NN 279553 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1618 MASTER LE NN 279551 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1619 MASTER LE NN 279557 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1620 MASTER LE NN 279559 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1621 MASTER LE NN 279555 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1622 MASTER LE NN 279563 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1623 MASTER LE NN 279561 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1624 MASTER LE NN 279549 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1625 MASTER LE NN 279579 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1626 MASTER LE NN 279577 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[3] (M31_1P5V6T_SFFSBQX1)
 Chain[5] 1627 MASTER LE NN 279571 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1628 MASTER LE NN 279569 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[7] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1629 MASTER LE NN 279564 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1630 MASTER LE NN 279547 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1631 MASTER LE NN 279565 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1632 MASTER LE NN 279566 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1633 MASTER LE NN 279546 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1634 MASTER LE NN 279545 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1635 MASTER LE NN 279518 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1636 MASTER LE NN 279574 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1637 MASTER LE NN 279381 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1638 MASTER LE NN 279380 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1639 MASTER LE NN 279379 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_
en_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1640 MASTER LE NN 279388 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_re
g (M31_1P5V6T_SFFRBQX1)
Chain[5] 1641 MASTER LE NN 279372 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1642 MASTER LE NN 279377 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1643 MASTER LE NN 279369 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1644 MASTER LE NN 279364 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1645 MASTER LE NN 279363 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1646 MASTER LE NN 279375 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1647 MASTER LE NN 279376 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1648 MASTER LE NN 279402 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_in
t_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1649 MASTER LE NN 279382 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_
vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1650 MASTER LE NN 279383 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1651 MASTER LE NN 279384 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1652 MASTER LE NN 279522 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1653 MASTER LE NN 279572 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1654 MASTER LE NN 279573 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_
reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1655 MASTER LE NN 279531 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1656 MASTER LE NN 279529 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1657 MASTER LE NN 279530 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1658 MASTER LE NN 279534 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 1659 MASTER LE NN 279532 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1660 MASTER LE NN 279536 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1661 MASTER LE NN 279568 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1662 MASTER LE NN 279562 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1663 MASTER LE NN 279365 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1664 MASTER LE NN 279362 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1665 MASTER LE NN 279368 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1666 MASTER LE NN 279367 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1667 MASTER LE NN 279361 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1668 MASTER LE NN 279490 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1669 MASTER LE NN 279491 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1670 MASTER LE NN 279457 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1671 MASTER LE NN 279458 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1672 MASTER LE NN 279447 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1673 MASTER LE NN 279461 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1674 MASTER LE NN 279540 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[5] 1675 MASTER LE NN 279542 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1676 MASTER LE NN 279449 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1677 MASTER LE NN 279312 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1678 MASTER LE NN 279543 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1679 MASTER LE NN 279539 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1680 MASTER LE NN 279541 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1681 MASTER LE NN 279296 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1682 MASTER LE NN 279300 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1683 MASTER LE NN 279297 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1684 MASTER LE NN 279299 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1685 MASTER LE NN 279298 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1686 MASTER LE NN 279317 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1687 MASTER LE NN 279316 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1688 MASTER LE NN 279314 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1689 MASTER LE NN 279271 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1690 MASTER LE NN 279272 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1691 MASTER LE NN 279273 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1692 MASTER LE NN 279274 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 1693 MASTER LE NN 279500 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1694 MASTER LE NN 279504 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1695 MASTER LE NN 279468 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1696 MASTER LE NN 279488 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1697 MASTER LE NN 279482 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1698 MASTER LE NN 279462 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1699 MASTER LE NN 279484 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1700 MASTER LE NN 279506 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1701 MASTER LE NN 279481 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/d
out_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1702 MASTER LE NN 279523 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1703 MASTER LE NN 279452 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1704 MASTER LE NN 279480 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1705 MASTER LE NN 279525 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1706 MASTER LE NN 279510 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1707 MASTER LE NN 279451 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1708 MASTER LE NN 279527 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1709 MASTER LE NN 279346 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1710 MASTER LE NN 279538 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1711 MASTER LE NN 279311 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1712 MASTER LE NN 279310 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1713 MASTER LE NN 279448 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1714 MASTER LE NN 279459 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1715 MASTER LE NN 279460 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1716 MASTER LE NN 279450 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1717 MASTER LE NN 279537 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 1718 MASTER LE NN 279528 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1719 MASTER LE NN 279309 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1720 MASTER LE NN 279360 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1721 MASTER LE NN 279305 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1722 MASTER LE NN 279313 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1723 MASTER LE NN 279423 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1724 MASTER LE NN 279422 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1725 MASTER LE NN 279307 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1726 MASTER LE NN 279306 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1727 MASTER LE NN 279308 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1728 MASTER LE NN 279526 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1729 MASTER LE NN 279470 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1730 MASTER LE NN 279513 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1731 MASTER LE NN 279304 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1732 MASTER LE NN 279511 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1733 MASTER LE NN 279315 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1734 MASTER LE NN 279492 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1735 MASTER LE NN 279514 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1736 MASTER LE NN 279456 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1737 MASTER LE NN 279455 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1738 MASTER LE NN 279493 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1739 MASTER LE NN 279509 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1740 MASTER LE NN 279494 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1741 MASTER LE NN 279496 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1742 MASTER LE NN 279495 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1743 MASTER LE NN 279524 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1744 MASTER LE NN 279453 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1745 MASTER LE NN 279483 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1746 MASTER LE NN 279454 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1747 MASTER LE NN 279466 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1748 MASTER LE NN 279478 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1749 MASTER LE NN 279465 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1750 MASTER LE NN 279508 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1751 MASTER LE NN 279512 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1752 MASTER LE NN 279479 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1753 MASTER LE NN 279463 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX2J)
Chain[5] 1754 MASTER LE NN 279303 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1755 MASTER LE NN 279486 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dou
t_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1756 MASTER LE NN 279471 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1757 MASTER LE NN 279485 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1758 MASTER LE NN 279502 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1759 MASTER LE NN 279464 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1760 MASTER LE NN 279497 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[5] 1761 MASTER LE NN 279276 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1762 MASTER LE NN 279278 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1763 MASTER LE NN 279275 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1764 MASTER LE NN 279277 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1765 MASTER LE NN 279291 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1766 MASTER LE NN 279287 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1767 MASTER LE NN 279289 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1768 MASTER LE NN 279290 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1769 MASTER LE NN 279286 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1770 MASTER LE NN 279284 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1771 MASTER LE NN 279285 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1772 MASTER LE NN 279340 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1773 MASTER LE NN 279341 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1774 MASTER LE NN 279342 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1775 MASTER LE NN 279339 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1776 MASTER LE NN 279338 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1777 MASTER LE NN 279344 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1778 MASTER LE NN 279282 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1779 MASTER LE NN 279358 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1780 MASTER LE NN 279359 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1781 MASTER LE NN 279288 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1782 MASTER LE NN 279501 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1783 MASTER LE NN 279503 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1784 MASTER LE NN 279301 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1785 MASTER LE NN 279302 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1786 MASTER LE NN 279498 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1787 MASTER LE NN 279467 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1788 MASTER LE NN 279469 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1789 MASTER LE NN 279487 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1790 MASTER LE NN 279489 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1791 MASTER LE NN 279499 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1792 MASTER LE NN 279507 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1793 MASTER LE NN 279505 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1794 MASTER LE NN 279322 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1795 MASTER LE NN 279407 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1796 MASTER LE NN 279406 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1797 MASTER LE NN 279283 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1798 MASTER LE NN 279345 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1799 MASTER LE NN 279356 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1800 MASTER LE NN 279347 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1801 MASTER LE NN 279348 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1802 MASTER LE NN 279420 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1803 MASTER LE NN 279280 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1804 MASTER LE NN 279419 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1805 MASTER LE NN 279318 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1806 MASTER LE NN 279281 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1807 MASTER LE NN 279279 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1808 MASTER LE NN 279327 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1809 MASTER LE NN 279357 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1810 MASTER LE NN 279351 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1811 MASTER LE NN 279412 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1812 MASTER LE NN 279413 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1813 MASTER LE NN 279472 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1814 MASTER LE NN 279428 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1815 MASTER LE NN 279410 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1816 MASTER LE NN 279328 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1817 MASTER LE NN 279352 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1818 MASTER LE NN 279331 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1819 MASTER LE NN 279332 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1820 MASTER LE NN 279325 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1821 MASTER LE NN 279335 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1822 MASTER LE NN 279326 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1823 MASTER LE NN 279321 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1824 MASTER LE NN 279324 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1825 MASTER LE NN 279350 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1826 MASTER LE NN 279323 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1827 MASTER LE NN 279411 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1828 MASTER LE NN 279429 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1829 MASTER LE NN 279473 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1830 MASTER LE NN 279443 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1831 MASTER LE NN 279474 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1832 MASTER LE NN 279476 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1833 MASTER LE NN 279430 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1834 MASTER LE NN 279417 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1835 MASTER LE NN 279477 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1836 MASTER LE NN 279475 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
csr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1837 MASTER LE NN 279334 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1838 MASTER LE NN 279408 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1839 MASTER LE NN 279355 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1840 MASTER LE NN 279431 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1841 MASTER LE NN 279409 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1842 MASTER LE NN 279353 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1843 MASTER LE NN 279294 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1844 MASTER LE NN 279343 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1845 MASTER LE NN 279433 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1846 MASTER LE NN 279354 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1847 MASTER LE NN 279415 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1848 MASTER LE NN 279414 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1849 MASTER LE NN 279432 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1850 MASTER LE NN 279293 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1851 MASTER LE NN 279295 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1852 MASTER LE NN 279268 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1853 MASTER LE NN 279261 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1854 MASTER LE NN 279257 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1855 MASTER LE NN 279262 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1856 MASTER LE NN 279266 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1857 MASTER LE NN 279270 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
 Chain[5] 1858 MASTER LE NN 279260 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1859 MASTER LE NN 279269 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1860 MASTER LE NN 279265 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1861 MASTER LE NN 279258 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1862 MASTER LE NN 279263 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1863 MASTER LE NN 279267 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1864 MASTER LE NN 279259 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1865 MASTER LE NN 279264 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_m
od_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1866 MASTER LE NN 279292 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1867 MASTER LE NN 279416 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1868 MASTER LE NN 279329 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1869 MASTER LE NN 279330 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1870 MASTER LE NN 279320 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1871 MASTER LE NN 279319 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1872 MASTER LE NN 279418 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1873 MASTER LE NN 279333 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1874 MASTER LE NN 279336 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1875 MASTER LE NN 279337 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1876 MASTER LE NN 279421 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 1877 MASTER LE NN 279349 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1878 MASTER LE NN 279584 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[10]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_
core/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1879 MASTER LE NN 279051 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 257022 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX3)
Chain[5] 1880 MASTER LE NN 279052 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1881 MASTER LE NN 279049 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1882 MASTER LE NN 279053 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1883 MASTER LE NN 279256 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1884 MASTER LE NN 278893 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1885 MASTER LE NN 278892 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1886 MASTER LE NN 278933 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1887 MASTER LE NN 279042 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1888 MASTER LE NN 279044 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1889 MASTER LE NN 279040 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1890 MASTER LE NN 279046 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1891 MASTER LE NN 279041 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1892 MASTER LE NN 279083 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 1893 MASTER LE NN 279023 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1894 MASTER LE NN 279022 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1895 MASTER LE NN 279021 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1896 MASTER LE NN 279028 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1897 MASTER LE NN 279031 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1898 MASTER LE NN 279043 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1899 MASTER LE NN 279032 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1900 MASTER LE NN 279012 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1901 MASTER LE NN 278912 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1902 MASTER LE NN 278913 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1903 MASTER LE NN 278914 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1904 MASTER LE NN 279016 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1905 MASTER LE NN 279013 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1906 MASTER LE NN 279033 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1907 MASTER LE NN 279029 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1908 MASTER LE NN 279014 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1909 MASTER LE NN 279030 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1910 MASTER LE NN 279026 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1911 MASTER LE NN 279027 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1912 MASTER LE NN 279036 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1913 MASTER LE NN 279015 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1914 MASTER LE NN 279047 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1915 MASTER LE NN 279045 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1916 MASTER LE NN 279255 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 1917 MASTER LE NN 279038 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1918 MASTER LE NN 279048 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1919 MASTER LE NN 279085 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1920 MASTER LE NN 279084 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1921 MASTER LE NN 279039 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1922 MASTER LE NN 279035 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1923 MASTER LE NN 279020 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1924 MASTER LE NN 279034 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1925 MASTER LE NN 279018 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1926 MASTER LE NN 279050 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
 Chain[5] 1927 MASTER LE NN 279037 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1928 MASTER LE NN 279149 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1929 MASTER LE NN 278901 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1930 MASTER LE NN 279151 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1931 MASTER LE NN 278902 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1932 MASTER LE NN 279025 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1933 MASTER LE NN 278903 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1934 MASTER LE NN 279017 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1935 MASTER LE NN 279024 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1936 MASTER LE NN 279011 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1937 MASTER LE NN 279010 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1938 MASTER LE NN 278915 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1939 MASTER LE NN 278911 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1940 MASTER LE NN 279155 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1941 MASTER LE NN 279153 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1942 MASTER LE NN 278898 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1943 MASTER LE NN 278899 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1944 MASTER LE NN 278987 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1945 MASTER LE NN 278988 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1946 MASTER LE NN 278908 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1947 MASTER LE NN 278907 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1948 MASTER LE NN 279019 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1949 MASTER LE NN 278906 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1950 MASTER LE NN 278905 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1951 MASTER LE NN 278904 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1952 MASTER LE NN 279008 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1953 MASTER LE NN 279007 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1954 MASTER LE NN 278924 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1955 MASTER LE NN 278990 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1956 MASTER LE NN 279005 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1957 MASTER LE NN 278964 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 1958 MASTER LE NN 279055 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1959 MASTER LE NN 279061 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1960 MASTER LE NN 278977 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1961 MASTER LE NN 278970 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1962 MASTER LE NN 278969 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1963 MASTER LE NN 279054 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1964 MASTER LE NN 278897 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1965 MASTER LE NN 279006 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1966 MASTER LE NN 278973 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1967 MASTER LE NN 278991 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1968 MASTER LE NN 279080 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 1969 MASTER LE NN 278979 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1970 MASTER LE NN 278974 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1971 MASTER LE NN 278978 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1972 MASTER LE NN 278985 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1973 MASTER LE NN 278992 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1974 MASTER LE NN 279078 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1975 MASTER LE NN 278926 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1976 MASTER LE NN 278984 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1977 MASTER LE NN 278925 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1978 MASTER LE NN 278980 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 1979 MASTER LE NN 278983 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1980 MASTER LE NN 278982 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1981 MASTER LE NN 278981 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1982 MASTER LE NN 279079 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[5] 1983 MASTER LE NN 279063 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1984 MASTER LE NN 278975 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1985 MASTER LE NN 279062 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1986 MASTER LE NN 279077 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 1987 MASTER LE NN 278971 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1988 MASTER LE NN 278968 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1989 MASTER LE NN 278972 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1990 MASTER LE NN 278910 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1991 MASTER LE NN 278928 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1992 MASTER LE NN 278967 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1993 MASTER LE NN 278895 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1994 MASTER LE NN 278896 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1995 MASTER LE NN 278994 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1996 MASTER LE NN 279147 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1997 MASTER LE NN 279146 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 1998 MASTER LE NN 278923 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 1999 MASTER LE NN 278922 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2000 MASTER LE NN 278887 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2001 MASTER LE NN 278891 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2002 MASTER LE NN 278888 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2003 MASTER LE NN 278934 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2004 MASTER LE NN 279254 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2005 MASTER LE NN 278948 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2006 MASTER LE NN 278950 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2007 MASTER LE NN 278947 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2008 MASTER LE NN 278949 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2009 MASTER LE NN 279069 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2010 MASTER LE NN 278962 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2011 MASTER LE NN 278952 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2012 MASTER LE NN 279071 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2013 MASTER LE NN 278951 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2014 MASTER LE NN 278937 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2015 MASTER LE NN 278935 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2016 MASTER LE NN 278955 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2017 MASTER LE NN 279000 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2018 MASTER LE NN 278996 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2019 MASTER LE NN 278931 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2020 MASTER LE NN 278930 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2021 MASTER LE NN 278999 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2022 MASTER LE NN 278998 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2023 MASTER LE NN 278916 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2024 MASTER LE NN 278889 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2025 MASTER LE NN 278917 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2026 MASTER LE NN 278890 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 2027 MASTER LE NN 279009 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2028 MASTER LE NN 279145 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[5] 2029 MASTER LE NN 279160 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2030 MASTER LE NN 279159 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2031 MASTER LE NN 278886 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2032 MASTER LE NN 278918 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2033 MASTER LE NN 279108 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2034 MASTER LE NN 279105 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2035 MASTER LE NN 279094 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2036 MASTER LE NN 279141 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2037 MASTER LE NN 279104 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2038 MASTER LE NN 279196 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2039 MASTER LE NN 279187 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2040 MASTER LE NN 279093 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2041 MASTER LE NN 279138 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2042 MASTER LE NN 278941 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2043 MASTER LE NN 278944 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2044 MASTER LE NN 279107 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2045 MASTER LE NN 279242 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX3)
Chain[5] 2046 MASTER LE NN 279243 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX2)
Chain[5] 2047 MASTER LE NN 279152 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2048 MASTER LE NN 279175 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2049 MASTER LE NN 278940 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2050 MASTER LE NN 279095 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2051 MASTER LE NN 278939 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2052 MASTER LE NN 279157 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2053 MASTER LE NN 279106 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2054 MASTER LE NN 279137 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2055 MASTER LE NN 278942 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2056 MASTER LE NN 279198 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2057 MASTER LE NN 278989 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2058 MASTER LE NN 279173 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2059 MASTER LE NN 279197 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2060 MASTER LE NN 279202 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2061 MASTER LE NN 279140 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2062 MASTER LE NN 279125 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2063 MASTER LE NN 279179 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 2064 MASTER LE NN 279181 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 2065 MASTER LE NN 279184 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2066 MASTER LE NN 279144 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2067 MASTER LE NN 279176 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 2068 MASTER LE NN 279177 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 2069 MASTER LE NN 278879 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2070 MASTER LE NN 278882 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2071 MASTER LE NN 278883 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2072 MASTER LE NN 278876 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2073 MASTER LE NN 278877 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2074 MASTER LE NN 278881 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
 Chain[5] 2075 MASTER LE NN 278894 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2076 MASTER LE NN 279178 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 2077 MASTER LE NN 279180 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 2078 MASTER LE NN 279128 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2079 MASTER LE NN 279201 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2080 MASTER LE NN 279200 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2081 MASTER LE NN 279174 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2082 MASTER LE NN 279150 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2083 MASTER LE NN 279158 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2084 MASTER LE NN 279156 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2085 MASTER LE NN 279182 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2086 MASTER LE NN 278919 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2087 MASTER LE NN 279060 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2088 MASTER LE NN 279089 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2089 MASTER LE NN 279086 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2090 MASTER LE NN 279058 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2091 MASTER LE NN 279059 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2092 MASTER LE NN 279087 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2093 MASTER LE NN 279056 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2094 MASTER LE NN 279057 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2095 MASTER LE NN 278966 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2096 MASTER LE NN 278993 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2097 MASTER LE NN 278965 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2098 MASTER LE NN 278900 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2099 MASTER LE NN 279126 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2100 MASTER LE NN 279127 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2101 MASTER LE NN 279161 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2102 MASTER LE NN 279199 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2103 MASTER LE NN 279148 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2104 MASTER LE NN 278995 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2105 MASTER LE NN 279154 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2106 MASTER LE NN 279162 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2107 MASTER LE NN 278921 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
 Chain[5] 2108 MASTER LE NN 278920 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2109 MASTER LE NN 278997 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2110 MASTER LE NN 278929 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2111 MASTER LE NN 278932 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2112 MASTER LE NN 279001 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2113 MASTER LE NN 278961 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2114 MASTER LE NN 278954 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2115 MASTER LE NN 278936 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2116 MASTER LE NN 278959 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2117 MASTER LE NN 279073 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2118 MASTER LE NN 278960 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2119 MASTER LE NN 279070 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2120 MASTER LE NN 279072 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2121 MASTER LE NN 278963 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2122 MASTER LE NN 278953 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2123 MASTER LE NN 279076 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2124 MASTER LE NN 278938 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2125 MASTER LE NN 278946 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2126 MASTER LE NN 279186 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2127 MASTER LE NN 279111 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2128 MASTER LE NN 279129 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2129 MASTER LE NN 279109 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2130 MASTER LE NN 279116 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2131 MASTER LE NN 279134 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2132 MASTER LE NN 279130 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2133 MASTER LE NN 278943 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2134 MASTER LE NN 278945 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2135 MASTER LE NN 279103 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2136 MASTER LE NN 279117 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2137 MASTER LE NN 279102 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2138 MASTER LE NN 279132 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
 Chain[5] 2139 MASTER LE NN 279133 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2140 MASTER LE NN 279113 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2141 MASTER LE NN 279096 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2142 MASTER LE NN 279098 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2143 MASTER LE NN 279124 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2144 MASTER LE NN 279142 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2145 MASTER LE NN 279081 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2146 MASTER LE NN 279115 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2147 MASTER LE NN 279082 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2148 MASTER LE NN 279139 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2149 MASTER LE NN 279172 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2150 MASTER LE NN 279171 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2151 MASTER LE NN 279183 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2152 MASTER LE NN 279114 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2153 MASTER LE NN 279185 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2154 MASTER LE NN 279101 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2155 MASTER LE NN 279100 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2156 MASTER LE NN 279121 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2157 MASTER LE NN 279097 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2158 MASTER LE NN 279122 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2159 MASTER LE NN 279120 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2160 MASTER LE NN 279118 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2161 MASTER LE NN 279123 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2162 MASTER LE NN 278986 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2163 MASTER LE NN 279067 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2164 MASTER LE NN 279004 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2165 MASTER LE NN 279064 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2166 MASTER LE NN 278909 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX2J)
Chain[5] 2167 MASTER LE NN 278927 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2168 MASTER LE NN 279066 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2169 MASTER LE NN 278976 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2170 MASTER LE NN 279002 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2171 MASTER LE NN 278885 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2172 MASTER LE NN 278880 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2173 MASTER LE NN 278873 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2174 MASTER LE NN 278878 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2175 MASTER LE NN 278872 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2176 MASTER LE NN 278874 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2177 MASTER LE NN 278884 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2178 MASTER LE NN 278875 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2179 MASTER LE NN 279068 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2180 MASTER LE NN 279003 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2181 MASTER LE NN 279065 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2182 MASTER LE NN 279119 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2183 MASTER LE NN 279099 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2184 MASTER LE NN 279143 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2185 MASTER LE NN 279110 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2186 MASTER LE NN 279136 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2187 MASTER LE NN 279135 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2188 MASTER LE NN 279131 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2189 MASTER LE NN 279112 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2190 MASTER LE NN 279168 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2191 MASTER LE NN 279231 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2192 MASTER LE NN 279195 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2193 MASTER LE NN 279219 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2194 MASTER LE NN 279163 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2195 MASTER LE NN 279244 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFRBQX2)
Chain[5] 2196 MASTER LE NN 279239 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2197 MASTER LE NN 279218 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2198 MASTER LE NN 279222 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2199 MASTER LE NN 279208 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2200 MASTER LE NN 278957 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2201 MASTER LE NN 278958 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2202 MASTER LE NN 278956 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2203 MASTER LE NN 279075 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2204 MASTER LE NN 279074 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2205 MASTER LE NN 279216 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2206 MASTER LE NN 279203 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2207 MASTER LE NN 279211 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2208 MASTER LE NN 279207 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2209 MASTER LE NN 279205 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2210 MASTER LE NN 279206 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2211 MASTER LE NN 279204 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2212 MASTER LE NN 279220 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2213 MASTER LE NN 279237 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2214 MASTER LE NN 279233 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2215 MASTER LE NN 279235 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2216 MASTER LE NN 279226 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[5] 2217 MASTER LE NN 279223 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2218 MASTER LE NN 279225 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2219 MASTER LE NN 279188 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2220 MASTER LE NN 279224 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2221 MASTER LE NN 279190 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2222 MASTER LE NN 279189 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2223 MASTER LE NN 279191 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2224 MASTER LE NN 279192 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2225 MASTER LE NN 279194 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2226 MASTER LE NN 279217 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2227 MASTER LE NN 279221 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2228 MASTER LE NN 279165 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2229 MASTER LE NN 279193 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2230 MASTER LE NN 279229 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2231 MASTER LE NN 279169 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2232 MASTER LE NN 279232 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2233 MASTER LE NN 279215 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2234 MASTER LE NN 279236 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2235 MASTER LE NN 279240 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2236 MASTER LE NN 279228 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2237 MASTER LE NN 279230 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2238 MASTER LE NN 279241 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2239 MASTER LE NN 279213 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2240 MASTER LE NN 279209 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2241 MASTER LE NN 279214 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2242 MASTER LE NN 279212 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2243 MASTER LE NN 279210 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2244 MASTER LE NN 279170 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2245 MASTER LE NN 279227 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2246 MASTER LE NN 279167 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2247 MASTER LE NN 279166 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2248 MASTER LE NN 279164 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2249 MASTER LE NN 279234 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2250 MASTER LE NN 279238 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[9]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2251 MASTER LE NN 278690 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256993 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX2)
Chain[5] 2252 MASTER LE NN 278687 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2253 MASTER LE NN 278691 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2254 MASTER LE NN 278714 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2255 MASTER LE NN 278682 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2256 MASTER LE NN 278684 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2257 MASTER LE NN 278678 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2258 MASTER LE NN 278656 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2259 MASTER LE NN 278686 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2260 MASTER LE NN 278673 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2261 MASTER LE NN 278677 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 2262 MASTER LE NN 278713 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2263 MASTER LE NN 278672 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2264 MASTER LE NN 278676 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2265 MASTER LE NN 278674 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2266 MASTER LE NN 278675 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2267 MASTER LE NN 278660 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2268 MASTER LE NN 278663 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2269 MASTER LE NN 278662 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2270 MASTER LE NN 278576 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2271 MASTER LE NN 278577 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2272 MASTER LE NN 278584 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2273 MASTER LE NN 278650 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2274 MASTER LE NN 278665 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2275 MASTER LE NN 278664 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2276 MASTER LE NN 278661 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2277 MASTER LE NN 278658 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2278 MASTER LE NN 278657 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2279 MASTER LE NN 278679 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2280 MASTER LE NN 278712 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 2281 MASTER LE NN 278653 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2282 MASTER LE NN 278683 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2283 MASTER LE NN 278685 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2284 MASTER LE NN 278692 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2285 MASTER LE NN 278688 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2286 MASTER LE NN 278837 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2287 MASTER LE NN 278870 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2288 MASTER LE NN 278839 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2289 MASTER LE NN 278865 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2290 MASTER LE NN 278869 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2291 MASTER LE NN 278867 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2292 MASTER LE NN 278843 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2293 MASTER LE NN 278847 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2294 MASTER LE NN 278849 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
 Chain[5] 2295 MASTER LE NN 278852 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2296 MASTER LE NN 278832 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2297 MASTER LE NN 278853 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2298 MASTER LE NN 278833 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2299 MASTER LE NN 278831 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2300 MASTER LE NN 278834 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2301 MASTER LE NN 278851 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2302 MASTER LE NN 278850 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2303 MASTER LE NN 278855 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2304 MASTER LE NN 278848 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2305 MASTER LE NN 278854 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2306 MASTER LE NN 278824 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2307 MASTER LE NN 278856 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2308 MASTER LE NN 278857 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2309 MASTER LE NN 278846 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2310 MASTER LE NN 278861 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2311 MASTER LE NN 278859 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2312 MASTER LE NN 278844 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2313 MASTER LE NN 278858 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2314 MASTER LE NN 278807 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2315 MASTER LE NN 278804 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2316 MASTER LE NN 278822 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2317 MASTER LE NN 278803 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2318 MASTER LE NN 278818 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2319 MASTER LE NN 278817 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2320 MASTER LE NN 278816 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2321 MASTER LE NN 278802 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2322 MASTER LE NN 278820 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2323 MASTER LE NN 278806 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2324 MASTER LE NN 278805 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2325 MASTER LE NN 278809 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2326 MASTER LE NN 278823 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2327 MASTER LE NN 278819 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2328 MASTER LE NN 278808 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2329 MASTER LE NN 278821 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2330 MASTER LE NN 278860 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2331 MASTER LE NN 278842 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2332 MASTER LE NN 278863 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2333 MASTER LE NN 278862 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2334 MASTER LE NN 278868 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2335 MASTER LE NN 278836 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2336 MASTER LE NN 278866 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2337 MASTER LE NN 278864 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2338 MASTER LE NN 278838 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2339 MASTER LE NN 278835 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2340 MASTER LE NN 278840 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2341 MASTER LE NN 278845 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2342 MASTER LE NN 278841 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2343 MASTER LE NN 278689 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2344 MASTER LE NN 278711 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 2345 MASTER LE NN 278681 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2346 MASTER LE NN 278680 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2347 MASTER LE NN 278666 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2348 MASTER LE NN 278669 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2349 MASTER LE NN 278668 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2350 MASTER LE NN 278667 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2351 MASTER LE NN 278671 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2352 MASTER LE NN 278670 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2353 MASTER LE NN 278648 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2354 MASTER LE NN 278649 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2355 MASTER LE NN 278587 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2356 MASTER LE NN 278563 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2357 MASTER LE NN 278652 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2358 MASTER LE NN 278586 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2359 MASTER LE NN 278585 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2360 MASTER LE NN 278651 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2361 MASTER LE NN 278655 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2362 MASTER LE NN 278654 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2363 MASTER LE NN 278659 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2364 MASTER LE NN 278571 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2365 MASTER LE NN 278578 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2366 MASTER LE NN 278574 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2367 MASTER LE NN 278575 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2368 MASTER LE NN 278788 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2369 MASTER LE NN 278646 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2370 MASTER LE NN 278570 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2371 MASTER LE NN 278792 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2372 MASTER LE NN 278794 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2373 MASTER LE NN 278631 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2374 MASTER LE NN 278559 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2375 MASTER LE NN 278565 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2376 MASTER LE NN 278564 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2377 MASTER LE NN 278561 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2378 MASTER LE NN 278562 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2379 MASTER LE NN 278603 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2380 MASTER LE NN 278604 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2381 MASTER LE NN 278583 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2382 MASTER LE NN 278602 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2383 MASTER LE NN 278591 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2384 MASTER LE NN 278784 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[5] 2385 MASTER LE NN 278785 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2386 MASTER LE NN 278786 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2387 MASTER LE NN 278638 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2388 MASTER LE NN 278609 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2389 MASTER LE NN 278730 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2390 MASTER LE NN 278774 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2391 MASTER LE NN 278756 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2392 MASTER LE NN 278753 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2393 MASTER LE NN 278740 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2394 MASTER LE NN 278782 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2395 MASTER LE NN 278800 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2396 MASTER LE NN 278739 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2397 MASTER LE NN 278791 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2398 MASTER LE NN 278709 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2399 MASTER LE NN 278633 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2400 MASTER LE NN 278798 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2401 MASTER LE NN 278710 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2402 MASTER LE NN 278801 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2403 MASTER LE NN 278594 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2404 MASTER LE NN 278596 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2405 MASTER LE NN 278592 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2406 MASTER LE NN 278600 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2407 MASTER LE NN 278778 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2408 MASTER LE NN 278815 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2409 MASTER LE NN 278744 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2410 MASTER LE NN 278745 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2411 MASTER LE NN 278734 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2412 MASTER LE NN 278737 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2413 MASTER LE NN 278597 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2414 MASTER LE NN 278599 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2415 MASTER LE NN 278779 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2416 MASTER LE NN 278827 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2417 MASTER LE NN 278826 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2418 MASTER LE NN 278593 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2419 MASTER LE NN 278749 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2420 MASTER LE NN 278757 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2421 MASTER LE NN 278796 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2422 MASTER LE NN 278595 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2423 MASTER LE NN 278775 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2424 MASTER LE NN 278797 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2425 MASTER LE NN 278795 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2426 MASTER LE NN 278738 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2427 MASTER LE NN 278770 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2428 MASTER LE NN 278787 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2429 MASTER LE NN 278799 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2430 MASTER LE NN 278751 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2431 MASTER LE NN 278789 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2432 MASTER LE NN 278755 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2433 MASTER LE NN 278772 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2434 MASTER LE NN 278793 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2435 MASTER LE NN 278741 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2436 MASTER LE NN 278760 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2437 MASTER LE NN 278743 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2438 MASTER LE NN 278781 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2439 MASTER LE NN 278742 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2440 MASTER LE NN 278783 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2441 MASTER LE NN 278766 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2442 MASTER LE NN 278769 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2443 MASTER LE NN 278750 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2444 MASTER LE NN 278752 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2445 MASTER LE NN 278759 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2446 MASTER LE NN 278771 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2447 MASTER LE NN 278754 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2448 MASTER LE NN 278773 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2449 MASTER LE NN 278761 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2450 MASTER LE NN 278776 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2451 MASTER LE NN 278765 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2452 MASTER LE NN 278810 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2453 MASTER LE NN 278812 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
 Chain[5] 2454 MASTER LE NN 278811 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2455 MASTER LE NN 278813 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2456 MASTER LE NN 278814 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2457 MASTER LE NN 278767 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2458 MASTER LE NN 278830 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2459 MASTER LE NN 278828 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2460 MASTER LE NN 278829 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2461 MASTER LE NN 278768 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2462 MASTER LE NN 278825 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2463 MASTER LE NN 278747 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2464 MASTER LE NN 278746 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2465 MASTER LE NN 278748 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2466 MASTER LE NN 278736 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2467 MASTER LE NN 278735 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2468 MASTER LE NN 278598 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 2469 MASTER LE NN 278780 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2470 MASTER LE NN 278777 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2471 MASTER LE NN 278647 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2472 MASTER LE NN 278601 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2473 MASTER LE NN 278558 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2474 MASTER LE NN 278589 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2475 MASTER LE NN 278590 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2476 MASTER LE NN 278588 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2477 MASTER LE NN 278790 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2478 MASTER LE NN 278560 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2479 MASTER LE NN 278645 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2480 MASTER LE NN 278632 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2481 MASTER LE NN 278569 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2482 MASTER LE NN 278572 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2483 MASTER LE NN 278573 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2484 MASTER LE NN 278545 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX2J)
Chain[5] 2485 MASTER LE NN 278552 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2486 MASTER LE NN 278555 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2487 MASTER LE NN 278550 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2488 MASTER LE NN 278553 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2489 MASTER LE NN 278628 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2490 MASTER LE NN 278627 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2491 MASTER LE NN 278625 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2492 MASTER LE NN 278624 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2493 MASTER LE NN 278705 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2494 MASTER LE NN 278620 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2495 MASTER LE NN 278636 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2496 MASTER LE NN 278623 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2497 MASTER LE NN 278635 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2498 MASTER LE NN 278634 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2499 MASTER LE NN 278607 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2500 MASTER LE NN 278606 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2501 MASTER LE NN 278605 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2502 MASTER LE NN 278582 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2503 MASTER LE NN 278643 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 2504 MASTER LE NN 278644 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2505 MASTER LE NN 278695 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2506 MASTER LE NN 278702 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2507 MASTER LE NN 278715 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2508 MASTER LE NN 278694 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2509 MASTER LE NN 278693 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2510 MASTER LE NN 278716 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2511 MASTER LE NN 278699 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2512 MASTER LE NN 278697 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2513 MASTER LE NN 278581 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2514 MASTER LE NN 278696 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2515 MASTER LE NN 278701 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2516 MASTER LE NN 278703 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2517 MASTER LE NN 278567 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2518 MASTER LE NN 278639 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2519 MASTER LE NN 278618 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2520 MASTER LE NN 278637 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2521 MASTER LE NN 278608 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 2522 MASTER LE NN 278622 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2523 MASTER LE NN 278617 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2524 MASTER LE NN 278615 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2525 MASTER LE NN 278619 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2526 MASTER LE NN 278718 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2527 MASTER LE NN 278579 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2528 MASTER LE NN 278630 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2529 MASTER LE NN 278580 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2530 MASTER LE NN 278640 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2531 MASTER LE NN 278698 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2532 MASTER LE NN 278700 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2533 MASTER LE NN 278758 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2534 MASTER LE NN 278763 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2535 MASTER LE NN 278621 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2536 MASTER LE NN 278762 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2537 MASTER LE NN 278704 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2538 MASTER LE NN 278764 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2539 MASTER LE NN 278717 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2540 MASTER LE NN 278641 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2541 MASTER LE NN 278719 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2542 MASTER LE NN 278720 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2543 MASTER LE NN 278642 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2544 MASTER LE NN 278566 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2545 MASTER LE NN 278614 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2546 MASTER LE NN 278568 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2547 MASTER LE NN 278612 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2548 MASTER LE NN 278613 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2549 MASTER LE NN 278611 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2550 MASTER LE NN 278616 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2551 MASTER LE NN 278610 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2552 MASTER LE NN 278871 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2553 MASTER LE NN 278626 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2554 MASTER LE NN 278708 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 2555 MASTER LE NN 278707 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2556 MASTER LE NN 278629 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2557 MASTER LE NN 278706 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2558 MASTER LE NN 278549 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2559 MASTER LE NN 278551 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2560 MASTER LE NN 278547 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2561 MASTER LE NN 278546 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2562 MASTER LE NN 278557 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2563 MASTER LE NN 278556 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2564 MASTER LE NN 278544 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2565 MASTER LE NN 278548 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2566 MASTER LE NN 278554 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[8]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2567 MASTER LE NN 278462 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256970 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX2)
Chain[5] 2568 MASTER LE NN 278488 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2569 MASTER LE NN 278465 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2570 MASTER LE NN 278491 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2571 MASTER LE NN 278495 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2572 MASTER LE NN 278469 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2573 MASTER LE NN 278494 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2574 MASTER LE NN 278468 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2575 MASTER LE NN 278417 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2576 MASTER LE NN 278429 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2577 MASTER LE NN 278415 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2578 MASTER LE NN 278433 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2579 MASTER LE NN 278408 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2580 MASTER LE NN 278428 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2581 MASTER LE NN 278414 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2582 MASTER LE NN 278434 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2583 MASTER LE NN 278413 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2584 MASTER LE NN 278435 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2585 MASTER LE NN 278432 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2586 MASTER LE NN 278431 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2587 MASTER LE NN 278412 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2588 MASTER LE NN 278421 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2589 MASTER LE NN 278357 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2590 MASTER LE NN 278291 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2591 MASTER LE NN 278159 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2592 MASTER LE NN 278160 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2593 MASTER LE NN 278161 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2594 MASTER LE NN 278171 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2595 MASTER LE NN 278172 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2596 MASTER LE NN 278167 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2597 MASTER LE NN 278162 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2598 MASTER LE NN 278420 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2599 MASTER LE NN 278214 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2600 MASTER LE NN 278353 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2601 MASTER LE NN 278355 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2602 MASTER LE NN 278354 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2603 MASTER LE NN 278356 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2604 MASTER LE NN 278165 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2605 MASTER LE NN 278164 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2606 MASTER LE NN 278181 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2607 MASTER LE NN 278169 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2608 MASTER LE NN 278170 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2609 MASTER LE NN 278196 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2610 MASTER LE NN 278274 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2611 MASTER LE NN 278292 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2612 MASTER LE NN 278264 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2613 MASTER LE NN 278290 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2614 MASTER LE NN 278422 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2615 MASTER LE NN 278423 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2616 MASTER LE NN 278397 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2617 MASTER LE NN 278395 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2618 MASTER LE NN 278409 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2619 MASTER LE NN 278480 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 2620 MASTER LE NN 278425 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2621 MASTER LE NN 278398 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2622 MASTER LE NN 278479 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 2623 MASTER LE NN 278483 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2624 MASTER LE NN 278485 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2625 MASTER LE NN 278484 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2626 MASTER LE NN 278481 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 2627 MASTER LE NN 278461 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2628 MASTER LE NN 278426 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2629 MASTER LE NN 278370 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2630 MASTER LE NN 278472 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2631 MASTER LE NN 278411 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2632 MASTER LE NN 278486 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2633 MASTER LE NN 278441 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2634 MASTER LE NN 278476 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 2635 MASTER LE NN 278396 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2636 MASTER LE NN 278410 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2637 MASTER LE NN 278419 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2638 MASTER LE NN 278430 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2639 MASTER LE NN 278399 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2640 MASTER LE NN 278400 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2641 MASTER LE NN 278418 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2642 MASTER LE NN 278402 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2643 MASTER LE NN 278460 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2644 MASTER LE NN 278205 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2645 MASTER LE NN 278416 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2646 MASTER LE NN 278438 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2647 MASTER LE NN 278439 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2648 MASTER LE NN 278401 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2649 MASTER LE NN 278437 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2650 MASTER LE NN 278228 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 2651 MASTER LE NN 278225 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2652 MASTER LE NN 278277 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2653 MASTER LE NN 278443 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2654 MASTER LE NN 278471 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2655 MASTER LE NN 278499 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2656 MASTER LE NN 278229 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2657 MASTER LE NN 278482 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2658 MASTER LE NN 278427 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2659 MASTER LE NN 278502 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2660 MASTER LE NN 278371 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2661 MASTER LE NN 278498 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2662 MASTER LE NN 278501 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2663 MASTER LE NN 278500 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2664 MASTER LE NN 278497 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2665 MASTER LE NN 278406 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2666 MASTER LE NN 278407 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2667 MASTER LE NN 278393 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2668 MASTER LE NN 278440 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2669 MASTER LE NN 278405 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2670 MASTER LE NN 278394 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2671 MASTER LE NN 278404 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2672 MASTER LE NN 278403 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2673 MASTER LE NN 278496 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2674 MASTER LE NN 278392 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2675 MASTER LE NN 278527 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2676 MASTER LE NN 278540 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2677 MASTER LE NN 278521 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2678 MASTER LE NN 278508 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2679 MASTER LE NN 278510 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2680 MASTER LE NN 278514 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2681 MASTER LE NN 278516 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2682 MASTER LE NN 278543 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2683 MASTER LE NN 278518 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2684 MASTER LE NN 278538 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2685 MASTER LE NN 278533 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2686 MASTER LE NN 278506 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2687 MASTER LE NN 278522 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2688 MASTER LE NN 278520 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2689 MASTER LE NN 278492 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2690 MASTER LE NN 278466 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2691 MASTER LE NN 278493 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2692 MASTER LE NN 278467 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2693 MASTER LE NN 278436 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2694 MASTER LE NN 278490 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2695 MASTER LE NN 278463 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2696 MASTER LE NN 278489 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2697 MASTER LE NN 278464 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2698 MASTER LE NN 278513 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2699 MASTER LE NN 278517 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2700 MASTER LE NN 278515 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2701 MASTER LE NN 278530 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2702 MASTER LE NN 278531 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2703 MASTER LE NN 278509 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2704 MASTER LE NN 278528 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2705 MASTER LE NN 278537 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2706 MASTER LE NN 278539 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2707 MASTER LE NN 278507 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2708 MASTER LE NN 278535 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2709 MASTER LE NN 278511 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2710 MASTER LE NN 278519 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
 Chain[5] 2711 MASTER LE NN 278526 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2712 MASTER LE NN 278487 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2713 MASTER LE NN 278478 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 2714 MASTER LE NN 278231 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2715 MASTER LE NN 278233 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2716 MASTER LE NN 278442 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2717 MASTER LE NN 278424 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2718 MASTER LE NN 278474 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2719 MASTER LE NN 278477 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 2720 MASTER LE NN 278470 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2721 MASTER LE NN 278163 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2722 MASTER LE NN 278168 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2723 MASTER LE NN 278166 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2724 MASTER LE NN 278504 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2725 MASTER LE NN 278524 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2726 MASTER LE NN 278523 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
 Chain[5] 2727 MASTER LE NN 278505 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2728 MASTER LE NN 278503 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2729 MASTER LE NN 278525 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2730 MASTER LE NN 278542 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2731 MASTER LE NN 278456 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2732 MASTER LE NN 278473 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2733 MASTER LE NN 278297 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2734 MASTER LE NN 278475 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2735 MASTER LE NN 278447 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2736 MASTER LE NN 278187 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2737 MASTER LE NN 278253 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2738 MASTER LE NN 278254 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2739 MASTER LE NN 278197 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2740 MASTER LE NN 278347 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2741 MASTER LE NN 278215 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2742 MASTER LE NN 278281 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2743 MASTER LE NN 278257 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2744 MASTER LE NN 278265 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2745 MASTER LE NN 278346 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2746 MASTER LE NN 278345 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2747 MASTER LE NN 278255 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2748 MASTER LE NN 278266 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2749 MASTER LE NN 278256 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2750 MASTER LE NN 278184 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2751 MASTER LE NN 278263 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2752 MASTER LE NN 278454 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2753 MASTER LE NN 278294 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2754 MASTER LE NN 278343 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2755 MASTER LE NN 278183 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2756 MASTER LE NN 278182 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2757 MASTER LE NN 278258 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2758 MASTER LE NN 278444 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
 Chain[5] 2759 MASTER LE NN 278388 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2760 MASTER LE NN 278350 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2761 MASTER LE NN 278349 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2762 MASTER LE NN 278348 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2763 MASTER LE NN 278376 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2764 MASTER LE NN 278377 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2765 MASTER LE NN 278206 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2766 MASTER LE NN 278283 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2767 MASTER LE NN 278449 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2768 MASTER LE NN 278455 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2769 MASTER LE NN 278230 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2770 MASTER LE NN 278457 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2771 MASTER LE NN 278232 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2772 MASTER LE NN 278249 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2773 MASTER LE NN 278219 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2774 MASTER LE NN 278289 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2775 MASTER LE NN 278208 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2776 MASTER LE NN 278227 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2777 MASTER LE NN 278451 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2778 MASTER LE NN 278226 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2779 MASTER LE NN 278453 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2780 MASTER LE NN 278282 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2781 MASTER LE NN 278445 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2782 MASTER LE NN 278446 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2783 MASTER LE NN 278207 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2784 MASTER LE NN 278252 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2785 MASTER LE NN 278173 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2786 MASTER LE NN 278209 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2787 MASTER LE NN 278202 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2788 MASTER LE NN 278299 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2789 MASTER LE NN 278312 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2790 MASTER LE NN 278298 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2791 MASTER LE NN 278221 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2792 MASTER LE NN 278217 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2793 MASTER LE NN 278216 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2794 MASTER LE NN 278224 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2795 MASTER LE NN 278288 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2796 MASTER LE NN 278284 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2797 MASTER LE NN 278359 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2798 MASTER LE NN 278239 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2799 MASTER LE NN 278237 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2800 MASTER LE NN 278358 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2801 MASTER LE NN 278360 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2802 MASTER LE NN 278362 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2803 MASTER LE NN 278248 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2804 MASTER LE NN 278250 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2805 MASTER LE NN 278247 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2806 MASTER LE NN 278365 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2807 MASTER LE NN 278534 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2808 MASTER LE NN 278529 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2809 MASTER LE NN 278536 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2810 MASTER LE NN 278532 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2811 MASTER LE NN 278541 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2812 MASTER LE NN 278512 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 2813 MASTER LE NN 278245 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2814 MASTER LE NN 278363 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2815 MASTER LE NN 278364 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2816 MASTER LE NN 278251 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2817 MASTER LE NN 278244 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2818 MASTER LE NN 278246 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2819 MASTER LE NN 278361 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2820 MASTER LE NN 278241 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2821 MASTER LE NN 278242 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2822 MASTER LE NN 278236 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2823 MASTER LE NN 278235 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2824 MASTER LE NN 278234 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2825 MASTER LE NN 278238 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2826 MASTER LE NN 278223 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2827 MASTER LE NN 278240 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2828 MASTER LE NN 278222 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2829 MASTER LE NN 278243 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2830 MASTER LE NN 278320 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2831 MASTER LE NN 278287 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2832 MASTER LE NN 278218 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2833 MASTER LE NN 278286 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2834 MASTER LE NN 278285 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2835 MASTER LE NN 278220 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2836 MASTER LE NN 278210 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2837 MASTER LE NN 278198 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2838 MASTER LE NN 278344 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 2839 MASTER LE NN 278262 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2840 MASTER LE NN 278293 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2841 MASTER LE NN 278261 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2842 MASTER LE NN 278273 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2843 MASTER LE NN 278366 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2844 MASTER LE NN 278185 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2845 MASTER LE NN 278189 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2846 MASTER LE NN 278276 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2847 MASTER LE NN 278275 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2848 MASTER LE NN 278270 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2849 MASTER LE NN 278268 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2850 MASTER LE NN 278271 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2851 MASTER LE NN 278272 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2852 MASTER LE NN 278267 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2853 MASTER LE NN 278369 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 2854 MASTER LE NN 278213 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2855 MASTER LE NN 278368 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
 Chain[5] 2856 MASTER LE NN 278351 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2857 MASTER LE NN 278260 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2858 MASTER LE NN 278259 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2859 MASTER LE NN 278280 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2860 MASTER LE NN 278279 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2861 MASTER LE NN 278278 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2862 MASTER LE NN 278352 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2863 MASTER LE NN 278367 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2864 MASTER LE NN 278269 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2865 MASTER LE NN 278295 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2866 MASTER LE NN 278211 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2867 MASTER LE NN 278212 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2868 MASTER LE NN 278177 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2869 MASTER LE NN 278296 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2870 MASTER LE NN 278192 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2871 MASTER LE NN 278195 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2872 MASTER LE NN 278194 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2873 MASTER LE NN 278193 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 2874 MASTER LE NN 278180 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2875 MASTER LE NN 278174 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2876 MASTER LE NN 278204 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2877 MASTER LE NN 278203 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2878 MASTER LE NN 278452 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2879 MASTER LE NN 278459 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2880 MASTER LE NN 278450 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2881 MASTER LE NN 278458 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2882 MASTER LE NN 278448 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2883 MASTER LE NN 278201 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2884 MASTER LE NN 278200 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2885 MASTER LE NN 278199 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2886 MASTER LE NN 278304 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2887 MASTER LE NN 278302 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2888 MASTER LE NN 278306 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2889 MASTER LE NN 278307 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2890 MASTER LE NN 278329 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
 Chain[5] 2891 MASTER LE NN 278309 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2892 MASTER LE NN 278175 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2893 MASTER LE NN 278310 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2894 MASTER LE NN 278179 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2895 MASTER LE NN 278332 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2896 MASTER LE NN 278334 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2897 MASTER LE NN 278328 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2898 MASTER LE NN 278336 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2899 MASTER LE NN 278341 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2900 MASTER LE NN 278337 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2901 MASTER LE NN 278342 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2902 MASTER LE NN 278335 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2903 MASTER LE NN 278373 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 2904 MASTER LE NN 278333 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2905 MASTER LE NN 278303 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2906 MASTER LE NN 278308 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2907 MASTER LE NN 278324 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2908 MASTER LE NN 278314 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2909 MASTER LE NN 278305 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2910 MASTER LE NN 278301 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2911 MASTER LE NN 278300 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2912 MASTER LE NN 278313 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2913 MASTER LE NN 278319 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2914 MASTER LE NN 278330 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2915 MASTER LE NN 278339 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2916 MASTER LE NN 278321 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2917 MASTER LE NN 278331 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2918 MASTER LE NN 278318 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2919 MASTER LE NN 278317 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2920 MASTER LE NN 278316 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2921 MASTER LE NN 278325 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2922 MASTER LE NN 278315 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2923 MASTER LE NN 278372 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 2924 MASTER LE NN 278322 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2925 MASTER LE NN 278338 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2926 MASTER LE NN 278340 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2927 MASTER LE NN 278323 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2928 MASTER LE NN 278327 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2929 MASTER LE NN 278374 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2930 MASTER LE NN 278326 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2931 MASTER LE NN 278375 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2932 MASTER LE NN 278311 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2933 MASTER LE NN 278178 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2934 MASTER LE NN 278176 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2935 MASTER LE NN 278191 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2936 MASTER LE NN 278186 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2937 MASTER LE NN 278188 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2938 MASTER LE NN 278190 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[7]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2939 MASTER LE NN 277885 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256940 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX1)
Chain[5] 2940 MASTER LE NN 277883 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2941 MASTER LE NN 277886 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2942 MASTER LE NN 277884 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2943 MASTER LE NN 277888 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2944 MASTER LE NN 277895 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2945 MASTER LE NN 277877 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2946 MASTER LE NN 277876 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2947 MASTER LE NN 277878 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2948 MASTER LE NN 277799 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2949 MASTER LE NN 277805 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2950 MASTER LE NN 277797 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2951 MASTER LE NN 277804 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2952 MASTER LE NN 277803 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2953 MASTER LE NN 277809 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2954 MASTER LE NN 277808 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2955 MASTER LE NN 277793 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2956 MASTER LE NN 277806 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2957 MASTER LE NN 277810 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2958 MASTER LE NN 277800 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2959 MASTER LE NN 277798 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2960 MASTER LE NN 277894 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2961 MASTER LE NN 277873 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2962 MASTER LE NN 277881 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2963 MASTER LE NN 277887 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2964 MASTER LE NN 277981 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2965 MASTER LE NN 277983 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2966 MASTER LE NN 277984 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 2967 MASTER LE NN 277871 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2968 MASTER LE NN 277870 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2969 MASTER LE NN 277882 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2970 MASTER LE NN 277982 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2971 MASTER LE NN 277826 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2972 MASTER LE NN 277827 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2973 MASTER LE NN 277874 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2974 MASTER LE NN 277828 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2975 MASTER LE NN 277868 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2976 MASTER LE NN 277869 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2977 MASTER LE NN 277961 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2978 MASTER LE NN 277960 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2979 MASTER LE NN 277966 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2980 MASTER LE NN 277875 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2981 MASTER LE NN 277812 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2982 MASTER LE NN 277830 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2983 MASTER LE NN 277880 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2984 MASTER LE NN 277908 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2985 MASTER LE NN 277872 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2986 MASTER LE NN 277801 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2987 MASTER LE NN 277893 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2988 MASTER LE NN 277891 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2989 MASTER LE NN 277890 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2990 MASTER LE NN 277909 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2991 MASTER LE NN 277967 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2992 MASTER LE NN 277958 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 2993 MASTER LE NN 277992 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 2994 MASTER LE NN 277991 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
 Chain[5] 2995 MASTER LE NN 278060 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 2996 MASTER LE NN 278059 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[5] 2997 MASTER LE NN 278076 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 2998 MASTER LE NN 277821 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 2999 MASTER LE NN 278062 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3000 MASTER LE NN 278071 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3001 MASTER LE NN 278072 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3002 MASTER LE NN 277822 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3003 MASTER LE NN 277788 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3004 MASTER LE NN 277823 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3005 MASTER LE NN 278065 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3006 MASTER LE NN 277819 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3007 MASTER LE NN 278074 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3008 MASTER LE NN 278063 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3009 MASTER LE NN 278073 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3010 MASTER LE NN 278069 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3011 MASTER LE NN 277959 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3012 MASTER LE NN 277910 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3013 MASTER LE NN 277911 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3014 MASTER LE NN 278067 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3015 MASTER LE NN 277867 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3016 MASTER LE NN 277807 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3017 MASTER LE NN 277792 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3018 MASTER LE NN 277791 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3019 MASTER LE NN 277794 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3020 MASTER LE NN 277795 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3021 MASTER LE NN 277790 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3022 MASTER LE NN 277919 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3023 MASTER LE NN 277789 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3024 MASTER LE NN 277825 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3025 MASTER LE NN 277816 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3026 MASTER LE NN 277815 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3027 MASTER LE NN 277817 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3028 MASTER LE NN 277814 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3029 MASTER LE NN 277931 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3030 MASTER LE NN 277932 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3031 MASTER LE NN 277945 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3032 MASTER LE NN 277933 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3033 MASTER LE NN 277916 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3034 MASTER LE NN 277915 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3035 MASTER LE NN 277944 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3036 MASTER LE NN 277940 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3037 MASTER LE NN 277917 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3038 MASTER LE NN 277924 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3039 MASTER LE NN 277925 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3040 MASTER LE NN 277926 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3041 MASTER LE NN 277920 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3042 MASTER LE NN 277939 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3043 MASTER LE NN 277942 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3044 MASTER LE NN 277938 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3045 MASTER LE NN 277937 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3046 MASTER LE NN 277941 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3047 MASTER LE NN 277921 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3048 MASTER LE NN 277922 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3049 MASTER LE NN 277947 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3050 MASTER LE NN 277989 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3051 MASTER LE NN 277923 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3052 MASTER LE NN 277948 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3053 MASTER LE NN 277990 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3054 MASTER LE NN 277950 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3055 MASTER LE NN 277949 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3056 MASTER LE NN 277943 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3057 MASTER LE NN 277946 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3058 MASTER LE NN 277957 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3059 MASTER LE NN 277928 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3060 MASTER LE NN 277987 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 3061 MASTER LE NN 277988 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 3062 MASTER LE NN 277953 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3063 MASTER LE NN 277955 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3064 MASTER LE NN 277952 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3065 MASTER LE NN 277956 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3066 MASTER LE NN 277951 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3067 MASTER LE NN 277918 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3068 MASTER LE NN 277930 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3069 MASTER LE NN 277929 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3070 MASTER LE NN 277914 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3071 MASTER LE NN 277913 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3072 MASTER LE NN 277824 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3073 MASTER LE NN 277813 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3074 MASTER LE NN 277818 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3075 MASTER LE NN 278061 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3076 MASTER LE NN 277897 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3077 MASTER LE NN 277965 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3078 MASTER LE NN 277964 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3079 MASTER LE NN 277963 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3080 MASTER LE NN 277962 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3081 MASTER LE NN 277802 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
 Chain[5] 3082 MASTER LE NN 277896 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3083 MASTER LE NN 277907 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3084 MASTER LE NN 277968 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3085 MASTER LE NN 277905 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3086 MASTER LE NN 277906 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3087 MASTER LE NN 277796 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3088 MASTER LE NN 277972 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3089 MASTER LE NN 277879 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3090 MASTER LE NN 277820 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3091 MASTER LE NN 277829 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3092 MASTER LE NN 277969 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3093 MASTER LE NN 277970 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3094 MASTER LE NN 277971 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3095 MASTER LE NN 277811 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3096 MASTER LE NN 278037 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3097 MASTER LE NN 278038 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3098 MASTER LE NN 277889 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 3099 MASTER LE NN 278036 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3100 MASTER LE NN 278057 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3101 MASTER LE NN 278031 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3102 MASTER LE NN 278094 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 3103 MASTER LE NN 278095 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 3104 MASTER LE NN 278011 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3105 MASTER LE NN 278010 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3106 MASTER LE NN 277841 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3107 MASTER LE NN 277842 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3108 MASTER LE NN 278093 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 3109 MASTER LE NN 278033 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3110 MASTER LE NN 278013 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3111 MASTER LE NN 277847 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3112 MASTER LE NN 278029 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3113 MASTER LE NN 277844 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3114 MASTER LE NN 277892 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
 Chain[5] 3115 MASTER LE NN 277912 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3116 MASTER LE NN 278039 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3117 MASTER LE NN 278058 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3118 MASTER LE NN 278101 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3119 MASTER LE NN 278026 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3120 MASTER LE NN 278028 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3121 MASTER LE NN 278086 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3122 MASTER LE NN 277986 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3123 MASTER LE NN 278085 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3124 MASTER LE NN 278068 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3125 MASTER LE NN 278041 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3126 MASTER LE NN 278091 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 3127 MASTER LE NN 278070 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3128 MASTER LE NN 278003 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3129 MASTER LE NN 278066 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3130 MASTER LE NN 278064 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3131 MASTER LE NN 278099 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3132 MASTER LE NN 278113 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3133 MASTER LE NN 278116 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3134 MASTER LE NN 278098 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3135 MASTER LE NN 278097 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3136 MASTER LE NN 278075 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3137 MASTER LE NN 278088 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3138 MASTER LE NN 278087 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3139 MASTER LE NN 278112 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3140 MASTER LE NN 278054 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3141 MASTER LE NN 278117 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3142 MASTER LE NN 278102 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3143 MASTER LE NN 278020 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3144 MASTER LE NN 278022 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3145 MASTER LE NN 278111 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3146 MASTER LE NN 277898 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3147 MASTER LE NN 277934 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3148 MASTER LE NN 277936 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3149 MASTER LE NN 277935 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3150 MASTER LE NN 277927 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3151 MASTER LE NN 277954 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3152 MASTER LE NN 277902 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3153 MASTER LE NN 277901 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3154 MASTER LE NN 277832 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3155 MASTER LE NN 277831 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3156 MASTER LE NN 277836 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3157 MASTER LE NN 277835 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3158 MASTER LE NN 277864 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3159 MASTER LE NN 277858 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3160 MASTER LE NN 277837 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3161 MASTER LE NN 277853 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3162 MASTER LE NN 277854 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3163 MASTER LE NN 277863 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3164 MASTER LE NN 277838 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3165 MASTER LE NN 277862 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3166 MASTER LE NN 277974 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3167 MASTER LE NN 277977 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3168 MASTER LE NN 277851 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3169 MASTER LE NN 277855 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3170 MASTER LE NN 277973 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3171 MASTER LE NN 277852 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3172 MASTER LE NN 277849 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3173 MASTER LE NN 277850 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3174 MASTER LE NN 277903 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3175 MASTER LE NN 277899 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3176 MASTER LE NN 277833 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3177 MASTER LE NN 277900 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3178 MASTER LE NN 277904 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3179 MASTER LE NN 277834 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3180 MASTER LE NN 277839 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3181 MASTER LE NN 278052 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3182 MASTER LE NN 278051 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3183 MASTER LE NN 278157 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3184 MASTER LE NN 278114 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3185 MASTER LE NN 278053 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3186 MASTER LE NN 278115 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3187 MASTER LE NN 278090 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3188 MASTER LE NN 278089 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3189 MASTER LE NN 278100 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3190 MASTER LE NN 278096 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 3191 MASTER LE NN 278092 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 3192 MASTER LE NN 278042 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3193 MASTER LE NN 277985 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3194 MASTER LE NN 278040 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3195 MASTER LE NN 278034 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3196 MASTER LE NN 278032 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3197 MASTER LE NN 277783 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3198 MASTER LE NN 277778 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3199 MASTER LE NN 277780 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3200 MASTER LE NN 277779 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3201 MASTER LE NN 277781 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3202 MASTER LE NN 277776 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3203 MASTER LE NN 277775 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3204 MASTER LE NN 277784 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3205 MASTER LE NN 277785 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3206 MASTER LE NN 278049 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3207 MASTER LE NN 278035 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3208 MASTER LE NN 278030 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3209 MASTER LE NN 278047 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3210 MASTER LE NN 278027 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3211 MASTER LE NN 278043 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3212 MASTER LE NN 278023 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3213 MASTER LE NN 278050 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3214 MASTER LE NN 278044 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3215 MASTER LE NN 278056 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3216 MASTER LE NN 277840 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3217 MASTER LE NN 277843 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3218 MASTER LE NN 277848 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3219 MASTER LE NN 278015 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3220 MASTER LE NN 277845 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3221 MASTER LE NN 278024 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3222 MASTER LE NN 278025 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3223 MASTER LE NN 278017 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3224 MASTER LE NN 278103 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3225 MASTER LE NN 278104 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3226 MASTER LE NN 278106 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3227 MASTER LE NN 278081 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3228 MASTER LE NN 278108 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3229 MASTER LE NN 278105 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3230 MASTER LE NN 278107 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3231 MASTER LE NN 278009 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3232 MASTER LE NN 278007 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3233 MASTER LE NN 278138 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3234 MASTER LE NN 278136 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3235 MASTER LE NN 278110 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3236 MASTER LE NN 278084 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3237 MASTER LE NN 278077 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 3238 MASTER LE NN 278080 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3239 MASTER LE NN 278078 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3240 MASTER LE NN 278079 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3241 MASTER LE NN 278109 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3242 MASTER LE NN 278083 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3243 MASTER LE NN 278082 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3244 MASTER LE NN 278134 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3245 MASTER LE NN 278144 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3246 MASTER LE NN 278155 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3247 MASTER LE NN 278122 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3248 MASTER LE NN 278119 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3249 MASTER LE NN 278143 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3250 MASTER LE NN 278141 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3251 MASTER LE NN 278140 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3252 MASTER LE NN 278121 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3253 MASTER LE NN 278149 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3254 MASTER LE NN 278120 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3255 MASTER LE NN 278128 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3256 MASTER LE NN 278132 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3257 MASTER LE NN 278146 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3258 MASTER LE NN 278147 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3259 MASTER LE NN 278130 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3260 MASTER LE NN 278151 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3261 MASTER LE NN 278126 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3262 MASTER LE NN 278124 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3263 MASTER LE NN 278153 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3264 MASTER LE NN 278145 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3265 MASTER LE NN 278154 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3266 MASTER LE NN 278156 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3267 MASTER LE NN 278133 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3268 MASTER LE NN 278129 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3269 MASTER LE NN 278137 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3270 MASTER LE NN 277980 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3271 MASTER LE NN 277978 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3272 MASTER LE NN 277857 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3273 MASTER LE NN 277979 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3274 MASTER LE NN 277976 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3275 MASTER LE NN 277865 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3276 MASTER LE NN 277975 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3277 MASTER LE NN 277856 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3278 MASTER LE NN 277866 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3279 MASTER LE NN 277861 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3280 MASTER LE NN 277859 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3281 MASTER LE NN 277860 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3282 MASTER LE NN 278131 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3283 MASTER LE NN 278127 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3284 MASTER LE NN 278125 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3285 MASTER LE NN 278123 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3286 MASTER LE NN 278135 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3287 MASTER LE NN 278152 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3288 MASTER LE NN 278148 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3289 MASTER LE NN 278158 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3290 MASTER LE NN 278150 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3291 MASTER LE NN 278139 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3292 MASTER LE NN 278118 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3293 MASTER LE NN 278142 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3294 MASTER LE NN 278018 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3295 MASTER LE NN 278055 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3296 MASTER LE NN 278019 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3297 MASTER LE NN 278021 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3298 MASTER LE NN 278008 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3299 MASTER LE NN 278016 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3300 MASTER LE NN 277846 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3301 MASTER LE NN 278014 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3302 MASTER LE NN 278045 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3303 MASTER LE NN 278046 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3304 MASTER LE NN 278012 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3305 MASTER LE NN 278048 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3306 MASTER LE NN 277777 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3307 MASTER LE NN 277782 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3308 MASTER LE NN 277787 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3309 MASTER LE NN 277786 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3310 MASTER LE NN 277774 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[6]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3311 MASTER LE NN 277563 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
DSLAVE LS NN 256911 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX1)
Chain[5] 3312 MASTER LE NN 277423 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 3313 MASTER LE NN 277535 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3314 MASTER LE NN 277536 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3315 MASTER LE NN 277604 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3316 MASTER LE NN 277570 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3317 MASTER LE NN 277569 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3318 MASTER LE NN 277565 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3319 MASTER LE NN 277537 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3320 MASTER LE NN 277561 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3321 MASTER LE NN 277421 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3322 MASTER LE NN 277425 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3323 MASTER LE NN 277424 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3324 MASTER LE NN 277584 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX3)
Chain[5] 3325 MASTER LE NN 277426 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3326 MASTER LE NN 277494 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3327 MASTER LE NN 277519 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3328 MASTER LE NN 277484 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3329 MASTER LE NN 277483 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3330 MASTER LE NN 277580 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 3331 MASTER LE NN 277595 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3332 MASTER LE NN 277496 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3333 MASTER LE NN 277581 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3334 MASTER LE NN 277533 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3335 MASTER LE NN 277500 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3336 MASTER LE NN 277442 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3337 MASTER LE NN 277441 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3338 MASTER LE NN 277524 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3339 MASTER LE NN 277505 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3340 MASTER LE NN 277506 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3341 MASTER LE NN 277416 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3342 MASTER LE NN 277418 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3343 MASTER LE NN 277670 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3344 MASTER LE NN 277525 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3345 MASTER LE NN 277419 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3346 MASTER LE NN 277415 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3347 MASTER LE NN 277668 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 3348 MASTER LE NN 277420 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3349 MASTER LE NN 277566 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3350 MASTER LE NN 277557 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3351 MASTER LE NN 277558 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vset_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3352 MASTER LE NN 277422 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3353 MASTER LE NN 277603 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3354 MASTER LE NN 277555 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_en_
reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3355 MASTER LE NN 277552 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3356 MASTER LE NN 277551 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_cnt_cle
ar_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3357 MASTER LE NN 277553 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3358 MASTER LE NN 277544 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3359 MASTER LE NN 277543 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3360 MASTER LE NN 277531 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3361 MASTER LE NN 277545 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_e
n_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3362 MASTER LE NN 277548 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_clear_v
set_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3363 MASTER LE NN 277501 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3364 MASTER LE NN 277499 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3365 MASTER LE NN 277498 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3366 MASTER LE NN 277443 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3367 MASTER LE NN 277596 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3368 MASTER LE NN 277502 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3369 MASTER LE NN 277534 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync7/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3370 MASTER LE NN 277546 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3371 MASTER LE NN 277554 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_ack_fsm/d_vreg_ack_int_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3372 MASTER LE NN 277556 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3373 MASTER LE NN 277564 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3374 MASTER LE NN 277571 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3375 MASTER LE NN 277567 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3376 MASTER LE NN 277562 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3377 MASTER LE NN 277602 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 3378 MASTER LE NN 277540 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_no_latch_sync_del_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3379 MASTER LE NN 277532 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3380 MASTER LE NN 277539 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3381 MASTER LE NN 277538 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync9/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3382 MASTER LE NN 277601 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vset_valid_sync_first_reg (M31_1P5V6T_SFFSBQX1)
 Chain[5] 3383 MASTER LE NN 277568 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_int
_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3384 MASTER LE NN 277542 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3385 MASTER LE NN 277547 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync2/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3386 MASTER LE NN 277541 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync10/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3387 MASTER LE NN 277550 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3388 MASTER LE NN 277549 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync5/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3389 MASTER LE NN 277597 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3390 MASTER LE NN 277560 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3391 MASTER LE NN 277559 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync6/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3392 MASTER LE NN 277598 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 3393 MASTER LE NN 277508 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3394 MASTER LE NN 277497 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3395 MASTER LE NN 277503 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3396 MASTER LE NN 277510 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3397 MASTER LE NN 277489 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3398 MASTER LE NN 277485 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3399 MASTER LE NN 277411 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3400 MASTER LE NN 277417 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3401 MASTER LE NN 277582 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3402 MASTER LE NN 277583 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3403 MASTER LE NN 277586 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3404 MASTER LE NN 277520 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3405 MASTER LE NN 277390 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3406 MASTER LE NN 277585 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3407 MASTER LE NN 277521 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3408 MASTER LE NN 277504 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3409 MASTER LE NN 277444 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3410 MASTER LE NN 277640 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST1_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3411 MASTER LE NN 277511 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3412 MASTER LE NN 277574 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3413 MASTER LE NN 277575 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3414 MASTER LE NN 277445 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3415 MASTER LE NN 277427 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3416 MASTER LE NN 277495 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3417 MASTER LE NN 277522 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[5] 3418 MASTER LE NN 277486 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3419 MASTER LE NN 277493 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3420 MASTER LE NN 277491 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3421 MASTER LE NN 277509 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3422 MASTER LE NN 277530 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3423 MASTER LE NN 277492 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3424 MASTER LE NN 277414 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3425 MASTER LE NN 277412 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3426 MASTER LE NN 277490 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3427 MASTER LE NN 277413 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3428 MASTER LE NN 277488 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3429 MASTER LE NN 277487 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3430 MASTER LE NN 277523 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3431 MASTER LE NN 277529 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync3/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3432 MASTER LE NN 277528 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3433 MASTER LE NN 277527 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[5] 3434 MASTER LE NN 277429 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3435 MASTER LE NN 277430 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3436 MASTER LE NN 277431 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3437 MASTER LE NN 277432 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3438 MASTER LE NN 277608 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3439 MASTER LE NN 277642 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3440 MASTER LE NN 277643 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3441 MASTER LE NN 277396 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3442 MASTER LE NN 277389 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3443 MASTER LE NN 277391 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3444 MASTER LE NN 277577 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3445 MASTER LE NN 277395 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3446 MASTER LE NN 277576 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3447 MASTER LE NN 277398 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3448 MASTER LE NN 277401 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3449 MASTER LE NN 277394 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3450 MASTER LE NN 277605 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3451 MASTER LE NN 277641 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3452 MASTER LE NN 277512 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3453 MASTER LE NN 277579 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3454 MASTER LE NN 277578 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3455 MASTER LE NN 277606 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3456 MASTER LE NN 277573 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3457 MASTER LE NN 277572 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3458 MASTER LE NN 277482 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3459 MASTER LE NN 277526 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_error_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3460 MASTER LE NN 277436 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_STATUS1__SOFT_START_DONE_rifi_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3461 MASTER LE NN 277638 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST3_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3462 MASTER LE NN 277637 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST4_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3463 MASTER LE NN 277672 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3464 MASTER LE NN 277402 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor9_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3465 MASTER LE NN 277393 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3466 MASTER LE NN 277674 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3467 MASTER LE NN 277392 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor10_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3468 MASTER LE NN 277400 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3469 MASTER LE NN 277399 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3470 MASTER LE NN 277397 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3471 MASTER LE NN 277669 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3472 MASTER LE NN 277633 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3473 MASTER LE NN 277634 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3474 MASTER LE NN 277667 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3475 MASTER LE NN 277654 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__STRONG_CLAMP_EN_reg/dout_r
eg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3476 MASTER LE NN 277635 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3477 MASTER LE NN 277673 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3478 MASTER LE NN 277664 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[5] 3479 MASTER LE NN 277665 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3480 MASTER LE NN 277666 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3481 MASTER LE NN 277639 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__DTEST2_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3482 MASTER LE NN 277645 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3483 MASTER LE NN 277616 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3484 MASTER LE NN 277599 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3485 MASTER LE NN 277647 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_FOLLOW_PULSE_EN_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3486 MASTER LE NN 277657 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__LEGACY_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3487 MASTER LE NN 277680 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_SELF_SHUTDOWN_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3488 MASTER LE NN 277644 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__LPM_STABILITY_BOOST_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3489 MASTER LE NN 277600 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_mode_state_reg_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3490 MASTER LE NN 277646 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__FORCE_PULSE_EN_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3491 MASTER LE NN 277615 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3492 MASTER LE NN 277618 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3493 MASTER LE NN 277620 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3494 MASTER LE NN 277619 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3495 MASTER LE NN 277617 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TRIM_CTRL1__VOUT_TRIM_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3496 MASTER LE NN 277671 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3497 MASTER LE NN 277661 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__LEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3498 MASTER LE NN 277655 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AHC_TESTMODE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3499 MASTER LE NN 277652 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3500 MASTER LE NN 277649 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3501 MASTER LE NN 277651 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3502 MASTER LE NN 277650 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_TRIM_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3503 MASTER LE NN 277698 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 3504 MASTER LE NN 277696 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX2J)
Chain[5] 3505 MASTER LE NN 277630 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3506 MASTER LE NN 277629 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3507 MASTER LE NN 277636 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST2__I_TST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3508 MASTER LE NN 277459 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3509 MASTER LE NN 277695 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__VDSAT_DET_TH_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 3510 MASTER LE NN 277675 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_TESTMODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3511 MASTER LE NN 277662 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__WEAK_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3512 MASTER LE NN 277704 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3513 MASTER LE NN 277702 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3514 MASTER LE NN 277703 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__ANA_AUTOBYPASS_THR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3515 MASTER LE NN 277717 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3516 MASTER LE NN 277621 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3517 MASTER LE NN 277701 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_BYPASS_CTL1__SMART_BYPASS_ENTRY_EN_reg/dout_reg[0
] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3518 MASTER LE NN 277435 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3519 MASTER LE NN 277437 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_status_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3520 MASTER LE NN 277403 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3521 MASTER LE NN 277438 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_vreg_fault_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3522 MASTER LE NN 277622 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TRIM_CTRL2_0_array_u_TRIM_CTRL2_0__LLC_TRIM_reg/dou
t_reg[0] (M31_1P5V6T_SFFSBQX3)
Chain[5] 3523 MASTER LE NN 277656 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3524 MASTER LE NN 277659 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_FAULT_INT_TEST_VAL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3525 MASTER LE NN 277721 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3526 MASTER LE NN 277719 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3527 MASTER LE NN 277677 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_GLOBAL_BROADCAST_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3528 MASTER LE NN 277676 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_STATUS_CLR_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3529 MASTER LE NN 277623 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3530 MASTER LE NN 277624 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3531 MASTER LE NN 277660 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3532 MASTER LE NN 277627 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3533 MASTER LE NN 277710 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_PMIC_AWAKE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3534 MASTER LE NN 277685 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3535 MASTER LE NN 277707 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3536 MASTER LE NN 277678 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3537 MASTER LE NN 277679 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3538 MASTER LE NN 277433 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3539 MASTER LE NN 277428 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3540 MASTER LE NN 277439 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3541 MASTER LE NN 277440 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3542 MASTER LE NN 277434 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3543 MASTER LE NN 277404 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3544 MASTER LE NN 277409 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3545 MASTER LE NN 277410 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3546 MASTER LE NN 277408 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3547 MASTER LE NN 277407 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3548 MASTER LE NN 277406 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3549 MASTER LE NN 277405 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3550 MASTER LE NN 277681 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3551 MASTER LE NN 277658 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_INT_TEST_VAL__VREG_ACK_INT_TEST_VAL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3552 MASTER LE NN 277720 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL2__MODE_SECONDARY_reg/dout_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3553 MASTER LE NN 277718 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3554 MASTER LE NN 277716 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MODE_CTL1__MODE_PRIMARY_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3555 MASTER LE NN 277691 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3556 MASTER LE NN 277690 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_CONFIG_reg/dout_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3557 MASTER LE NN 277693 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_SEL_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3558 MASTER LE NN 277507 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/d_vreg_ready_flag_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3559 MASTER LE NN 277663 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PD_CTL__STRONG_PD_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3560 MASTER LE NN 277460 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3561 MASTER LE NN 277461 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3562 MASTER LE NN 277632 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3563 MASTER LE NN 277653 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__AUTOBYP_CLAMP_CTL_reg/dout
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3564 MASTER LE NN 277648 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST5_0_array_u_TEST5_0__HLH_CLAMP_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3565 MASTER LE NN 277628 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3566 MASTER LE NN 277463 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3567 MASTER LE NN 277456 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3568 MASTER LE NN 277457 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3569 MASTER LE NN 277455 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3570 MASTER LE NN 277697 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__OS_SHIFT_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 3571 MASTER LE NN 277631 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_TEST1__ATEST2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3572 MASTER LE NN 277462 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_ub_rifi_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3573 MASTER LE NN 277699 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__PWR_RATING_reg/dout_
reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 3574 MASTER LE NN 277458 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/d_vset_valid_lb_rifi_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3575 MASTER LE NN 277692 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/FT_CTL1_0_array_u_FT_CTL1_0__FT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3576 MASTER LE NN 277771 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3577 MASTER LE NN 277706 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3578 MASTER LE NN 277705 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PBS_VOTE_CTL__PBS_MODE_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3579 MASTER LE NN 277626 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_re
g[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3580 MASTER LE NN 277625 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3581 MASTER LE NN 277772 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__DCR_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3582 MASTER LE NN 277770 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_npm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3583 MASTER LE NN 277700 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/AHC_CTL1_0_array_u_AHC_CTL1_0__AHC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFSRBQX1)
Chain[5] 3584 MASTER LE NN 277694 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/LLC_CTL1_0_array_u_LLC_CTL1_0__LLC_EN_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3585 MASTER LE NN 277451 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3586 MASTER LE NN 277450 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync_cg1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3587 MASTER LE NN 277514 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3588 MASTER LE NN 277518 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3589 MASTER LE NN 277449 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3590 MASTER LE NN 277446 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3591 MASTER LE NN 277454 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_adj_pulse_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3592 MASTER LE NN 277479 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3593 MASTER LE NN 277517 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3594 MASTER LE NN 277478 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3595 MASTER LE NN 277470 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3596 MASTER LE NN 277587 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3597 MASTER LE NN 277467 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3598 MASTER LE NN 277477 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3599 MASTER LE NN 277452 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3600 MASTER LE NN 277473 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/u_slib_sync1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3601 MASTER LE NN 277515 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3602 MASTER LE NN 277516 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3603 MASTER LE NN 277746 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[7] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3604 MASTER LE NN 277743 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3605 MASTER LE NN 277723 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3606 MASTER LE NN 277722 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3607 MASTER LE NN 277744 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3608 MASTER LE NN 277724 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3609 MASTER LE NN 277742 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[2]
(M31_1P5V6T_SFFSBQX1)
 Chain[5] 3610 MASTER LE NN 277748 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3611 MASTER LE NN 277761 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3612 MASTER LE NN 277752 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3613 MASTER LE NN 277725 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_UB__VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3614 MASTER LE NN 277735 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3615 MASTER LE NN 277733 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3616 MASTER LE NN 277749 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3617 MASTER LE NN 277739 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3618 MASTER LE NN 277741 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_UB__ULS_VSET_UB_reg/dout_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3619 MASTER LE NN 277745 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3620 MASTER LE NN 277715 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_EN_CTL__EN_LDO_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3621 MASTER LE NN 277612 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1_write_once_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3622 MASTER LE NN 277613 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3623 MASTER LE NN 277614 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3624 MASTER LE NN 277682 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3625 MASTER LE NN 277713 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3626 MASTER LE NN 277686 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_4_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3627 MASTER LE NN 277711 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN0_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3628 MASTER LE NN 277714 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_PMIC_AWAKE_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3629 MASTER LE NN 277689 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_7_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3630 MASTER LE NN 277709 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3631 MASTER LE NN 277688 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_6_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3632 MASTER LE NN 277708 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__EN_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3633 MASTER LE NN 277687 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_5_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3634 MASTER LE NN 277712 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_FOLLOW_HWEN__MODE_FOLLOW_HW_EN1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3635 MASTER LE NN 277683 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3636 MASTER LE NN 277684 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_MISC1__SCRATCH_2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3637 MASTER LE NN 277737 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3638 MASTER LE NN 277747 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3639 MASTER LE NN 277756 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3640 MASTER LE NN 277728 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3641 MASTER LE NN 277750 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3642 MASTER LE NN 277757 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3643 MASTER LE NN 277758 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3644 MASTER LE NN 277730 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3645 MASTER LE NN 277731 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3646 MASTER LE NN 277726 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3647 MASTER LE NN 277754 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3648 MASTER LE NN 277759 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3649 MASTER LE NN 277751 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3650 MASTER LE NN 277753 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3651 MASTER LE NN 277755 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_ULS_VSET_LB__ULS_VSET_LB_latched_write_reg/dout_r
eg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3652 MASTER LE NN 277736 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[5]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3653 MASTER LE NN 277732 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[3]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3654 MASTER LE NN 277729 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[1]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3655 MASTER LE NN 277760 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[2]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3656 MASTER LE NN 277472 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_clear_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3657 MASTER LE NN 277591 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3658 MASTER LE NN 277453 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_update_vset_sync_delay_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3659 MASTER LE NN 277592 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3660 MASTER LE NN 277480 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3661 MASTER LE NN 277464 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3662 MASTER LE NN 277466 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3663 MASTER LE NN 277471 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3664 MASTER LE NN 277590 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3665 MASTER LE NN 277475 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3666 MASTER LE NN 277740 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[7]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3667 MASTER LE NN 277738 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[6]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3668 MASTER LE NN 277727 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[0]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3669 MASTER LE NN 277734 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_VSET_LB__VSET_LB_latched_write_reg/dout_reg[4]
(M31_1P5V6T_SFFSRBQX1)
Chain[5] 3670 MASTER LE NN 277474 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3671 MASTER LE NN 277476 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3672 MASTER LE NN 277594 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[10]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3673 MASTER LE NN 277481 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3674 MASTER LE NN 277593 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_vset_sync_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3675 MASTER LE NN 277465 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3676 MASTER LE NN 277468 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3677 MASTER LE NN 277589 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[9]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3678 MASTER LE NN 277588 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3679 MASTER LE NN 277469 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_adj_vset_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3680 MASTER LE NN 277513 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3681 MASTER LE NN 277448 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sample1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3682 MASTER LE NN 277447 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[5]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/llc_inst_u_ldo_common_llc_logic_dig_mod/d_llc_sync2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3683 MASTER LE NN 277210 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[5] (M31_1P5V6T_SFFSBQX1)
DSLAVE LS NN 256886 - GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/LOCKUP1
(M31_1P5V6T_LOWLATCHX2)
Chain[5] 3684 MASTER LE NN 277388 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3685 MASTER LE NN 277171 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3686 MASTER LE NN 277181 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3687 MASTER LE NN 277183 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3688 MASTER LE NN 277184 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3689 MASTER LE NN 277180 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3690 MASTER LE NN 277020 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3691 MASTER LE NN 277025 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3692 MASTER LE NN 277023 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3693 MASTER LE NN 277217 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_cnt_state_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3694 MASTER LE NN 277179 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cnt
_clear_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3695 MASTER LE NN 277049 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3696 MASTER LE NN 277151 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3697 MASTER LE NN 277150 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync8/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3698 MASTER LE NN 277048 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3699 MASTER LE NN 277300 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3700 MASTER LE NN 277301 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_DEB_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3701 MASTER LE NN 277022 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3702 MASTER LE NN 277140 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3703 MASTER LE NN 277024 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3704 MASTER LE NN 277037 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3705 MASTER LE NN 277036 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3706 MASTER LE NN 277139 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3707 MASTER LE NN 277294 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3708 MASTER LE NN 277290 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3709 MASTER LE NN 277021 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3710 MASTER LE NN 277292 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_ERROR_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3711 MASTER LE NN 277019 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_vreg_fault_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3712 MASTER LE NN 277097 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_4p8mhz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3713 MASTER LE NN 277288 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3714 MASTER LE NN 277185 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3715 MASTER LE NN 277296 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL__VREG_READY_DEB_sync_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3716 MASTER LE NN 277060 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3717 MASTER LE NN 277121 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3718 MASTER LE NN 277120 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/slib_sync_u1/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3719 MASTER LE NN 277038 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3720 MASTER LE NN 277039 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3721 MASTER LE NN 277040 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_error_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3722 MASTER LE NN 277031 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_out_reg_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3723 MASTER LE NN 277035 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3724 MASTER LE NN 277034 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3725 MASTER LE NN 277033 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3726 MASTER LE NN 277123 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3727 MASTER LE NN 277028 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3728 MASTER LE NN 277106 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3729 MASTER LE NN 277027 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3730 MASTER LE NN 277029 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_from_pin_ctrl_delay_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3731 MASTER LE NN 277030 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_vreg_logic/u_vreg_ready_debouncer/d_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3732 MASTER LE NN 277058 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3733 MASTER LE NN 277057 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3734 MASTER LE NN 277137 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3735 MASTER LE NN 277056 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3736 MASTER LE NN 277194 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3737 MASTER LE NN 277187 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3738 MASTER LE NN 277138 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_clk_req_4p8mhz_req_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3739 MASTER LE NN 277104 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3740 MASTER LE NN 277105 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_softstart_done_delay_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3741 MASTER LE NN 277126 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_npm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3742 MASTER LE NN 277103 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3743 MASTER LE NN 277111 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3744 MASTER LE NN 277107 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_ldo_mode_changed_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3745 MASTER LE NN 277124 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_vreg_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3746 MASTER LE NN 277118 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3747 MASTER LE NN 277125 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3748 MASTER LE NN 277208 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3749 MASTER LE NN 277108 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/state_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3750 MASTER LE NN 277211 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_valid_reg (M31_1P5V6T_SFFSBQX1)
Chain[5] 3751 MASTER LE NN 277209 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3752 MASTER LE NN 277113 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3753 MASTER LE NN 277117 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3754 MASTER LE NN 277114 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3755 MASTER LE NN 277116 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3756 MASTER LE NN 277115 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_exit_bypass_20us_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3757 MASTER LE NN 277112 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_force_bypass_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3758 MASTER LE NN 277100 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3759 MASTER LE NN 277101 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_low_hr_detected_syncer/sync_d_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3760 MASTER LE NN 277098 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3761 MASTER LE NN 277099 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_bias_ready_syncer/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3762 MASTER LE NN 277102 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/d_smart_byp_entry_en_syncer/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3763 MASTER LE NN 277110 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_ldo_mode_lpm_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3764 MASTER LE NN 277188 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ssdone_lpm_pulse_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3765 MASTER LE NN 277193 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vreg_ok_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3766 MASTER LE NN 277042 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_counter_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3767 MASTER LE NN 277032 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_slowstart_ramp_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3768 MASTER LE NN 277218 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3769 MASTER LE NN 277191 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3770 MASTER LE NN 277186 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_4p8mhz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3771 MASTER LE NN 277286 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/dtmp_reg
(M31_1P5V6T_SFFRSBQX1)
Chain[5] 3772 MASTER LE NN 277119 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_bypass_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3773 MASTER LE NN 277199 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3774 MASTER LE NN 277109 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_lpm_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3775 MASTER LE NN 277134 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_monitor_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3776 MASTER LE NN 277197 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3777 MASTER LE NN 277135 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_amp_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3778 MASTER LE NN 277059 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/softstart_done_delay_sync/sync_d_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3779 MASTER LE NN 277198 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3780 MASTER LE NN 277006 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3781 MASTER LE NN 277009 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3782 MASTER LE NN 277004 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp2_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3783 MASTER LE NN 277014 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor7_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3784 MASTER LE NN 277192 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_test_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3785 MASTER LE NN 277219 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_vsense_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3786 MASTER LE NN 277190 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3787 MASTER LE NN 277189 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_ocp_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3788 MASTER LE NN 277136 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_mode_ctrl/u_ldo_p_dig_mode_ctrl_fsm/d_d2a_buff_en_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3789 MASTER LE NN 277026 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_startup_clk_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3790 MASTER LE NN 277012 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor5_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3791 MASTER LE NN 277041 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_softstart_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3792 MASTER LE NN 277013 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor6_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3793 MASTER LE NN 277011 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor4_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3794 MASTER LE NN 277230 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_lpm_clk_in_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3795 MASTER LE NN 277127 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/glib_cg_latch_98k_clk_gate/clk_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3796 MASTER LE NN 277287 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_STATUS_DEB_CTL_bus_sync_en/sync_u0/sync_d_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[5] 3797 MASTER LE NN 277043 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/clk_98khz_clkreq_gate/clk_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3798 MASTER LE NN 277055 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3799 MASTER LE NN 277054 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/u_clk_98khz_req_extend/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3800 MASTER LE NN 277046 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_reg_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3801 MASTER LE NN 277152 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_sync_del_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3802 MASTER LE NN 277176 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_error_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3803 MASTER LE NN 277175 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_error_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3804 MASTER LE NN 277016 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor8_reg (M31_1P5V6T_SFFRBQX1)
 Chain[5] 3805 MASTER LE NN 277008 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor1_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3806 MASTER LE NN 277010 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp_xor3_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3807 MASTER LE NN 277195 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3808 MASTER LE NN 277196 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_p_dig_glue/d_d2a_slowstart_ramp_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3809 MASTER LE NN 277005 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/u_ldo_p_dig_mo
d_dft_logic/tp0_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3810 MASTER LE NN 277267 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/TEST4_0_array_u_TEST4_0__START_UP_RAMP_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[5] 3811 MASTER LE NN 277303 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
sr/u_ldo_p_rif_wrap/u_ldo_p_rif/u_OCP_CTL1__OCP_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[5] 3812 MASTER LE NN 277047 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/d_en_rise_edge_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3813 MASTER LE NN 277044 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3814 MASTER LE NN 277045 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_ldo_ocp_logic/u_slib_sync_cg1/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3815 MASTER LE NN 277178 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_fault_req_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3816 MASTER LE NN 277147 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_slib_sync11/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3817 MASTER LE NN 277177 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/u_reg_int_logic_dig_vreg_fault_fsm/d_vreg_fault_cle
ar_vreg_fault_det_reg (M31_1P5V6T_SFFRBQX1)
Chain[5] 3818 MASTER LE NN 277170 + GPIO_07
I_DCORE/\ldo_p_rmod_gen[4]_u_ldo_p_rmod/u_ldo_p_rdig/u_ldo_p_dig_mod/\u_ldo_p_dig_c
ore/u_reg_int_logic_2p0_dig_mod/d_vreg_ack_cnt_state_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[5] 3819 MASTER TE NN 288706 - GPIO_07
I_DCORE/\SNPS_PipeHead_u_waimea_dcore_glue/u_dft_test_ctrl/scan_chain_in[5]_1
(M31_1P5V6T_SFFQX3)
Chain[6] 0 MASTER LE IN 288699 + GPIO_07
I_DCORE/\SNPS_PipeTail_u_waimea_dcore_glue/u_dft_test_ctrl/scan_chain_out[6]_1
(M31_1P5V6T_DFFQX1)
Chain[6] 1 MASTER LE IN 265254 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\xo_clk_count_reg[6] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS IN 256092 - GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/LOCKUP (M31_1P5V6T_LOWLATCHX2)
Chain[6] 2 MASTER LE IN 265181 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\xo_clk_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 3 MASTER LE IN 265179 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\xo_clk_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 4 MASTER LE IN 265249 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 5 MASTER LE IN 265250 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 6 MASTER LE IN 265247 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 7 MASTER LE IN 265251 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 8 MASTER LE IN 265229 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[22] (M31_1P5V6T_SFFRBQX1)
Chain[6] 9 MASTER LE IN 265231 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[20] (M31_1P5V6T_SFFRBQX1)
Chain[6] 10 MASTER LE IN 265230 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[21] (M31_1P5V6T_SFFRBQX1)
Chain[6] 11 MASTER LE IN 265248 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 12 MASTER LE IN 265242 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 13 MASTER LE IN 265241 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 14 MASTER LE IN 265239 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 15 MASTER LE IN 265236 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[6] 16 MASTER LE IN 265235 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[16] (M31_1P5V6T_SFFRBQX1)
Chain[6] 17 MASTER LE IN 265234 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[17] (M31_1P5V6T_SFFRBQX1)
Chain[6] 18 MASTER LE IN 265238 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 19 MASTER LE IN 265237 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 20 MASTER LE IN 265232 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[19] (M31_1P5V6T_SFFRBQX1)
Chain[6] 21 MASTER LE IN 265233 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[18] (M31_1P5V6T_SFFRBQX1)
Chain[6] 22 MASTER LE IN 265243 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 23 MASTER LE IN 265245 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 24 MASTER LE IN 265246 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 25 MASTER LE IN 265228 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\bin2ther_reg_reg[23] (M31_1P5V6T_SFFRBQX1)
Chain[6] 26 MASTER LE IN 265188 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\xo_adjust_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 27 MASTER LE IN 265183 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\xo_clk_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 28 MASTER LE IN 265182 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\xo_clk_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 29 MASTER LE IN 265184 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\xo_clk_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 30 MASTER LE IN 265180 + GPIO_07
I_DCORE/u_clksxo_rmod/u_clksxo_rdig_xrf_xlb_ldo/u_clksxo_xrf_xlb_ldo_dig_mod/u_clks
_dig_xo_stepper/\xo_clk_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 31 MASTER LE IN 264336 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[0] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS IN 256084 - GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/LOCKUP1 (M31_1P5V6T_LOWLATCHX3)
Chain[6] 32 MASTER LE IN 264217 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_r_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 33 MASTER LE IN 264216 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 34 MASTER LE IN 264333 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_sm_i_inst/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 35 MASTER LE IN 265125 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 36 MASTER LE IN 264214 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_i_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 37 MASTER LE IN 264210 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_i_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 38 MASTER LE IN 265112 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 39 MASTER LE IN 264263 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_sm_i_inst/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 40 MASTER LE IN 264280 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_sm_i_inst/allow_counting
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 41 MASTER LE IN 264282 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 42 MASTER LE IN 264283 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 43 MASTER LE IN 265143 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 44 MASTER LE IN 264212 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_i_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 45 MASTER LE IN 264209 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_i_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 46 MASTER LE IN 265113 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 47 MASTER LE IN 265137 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 48 MASTER LE IN 264264 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_sm_i_inst/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 49 MASTER LE IN 264285 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_sm_i_inst/enable_early_p
ulses_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 50 MASTER LE IN 264284 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 51 MASTER LE IN 264281 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 52 MASTER LE IN 264271 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_sm_i_inst/enable_early_p
ulses_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 53 MASTER LE IN 264270 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 54 MASTER LE IN 264266 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_sm_i_inst/allow_counting
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 55 MASTER LE IN 264393 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[14]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 56 MASTER LE IN 264267 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 57 MASTER LE IN 264269 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 58 MASTER LE IN 264401 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 59 MASTER LE IN 264400 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 60 MASTER LE IN 264396 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 61 MASTER LE IN 264399 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 62 MASTER LE IN 264268 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 63 MASTER LE IN 264398 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 64 MASTER LE IN 264397 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 65 MASTER LE IN 264395 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 66 MASTER LE IN 264323 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 67 MASTER LE IN 264324 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 68 MASTER LE IN 264368 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[25]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 69 MASTER LE IN 264367 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[24]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 70 MASTER LE IN 264331 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_i_inst/edge_0deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 71 MASTER LE IN 264363 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[24]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 72 MASTER LE IN 264475 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_sm_i_inst/reset_en_r_S19
_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 73 MASTER LE IN 264327 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_sm_i_inst/enable_early_p
ulses_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 74 MASTER LE IN 264320 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_sm_i_inst/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 75 MASTER LE IN 264474 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_sm_i_inst/set_en_r_S19_r
eg (M31_1P5V6T_SFFSBQX1)
Chain[6] 76 MASTER LE IN 264391 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[12]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 77 MASTER LE IN 264322 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_sm_i_inst/allow_counting
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 78 MASTER LE IN 264326 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 79 MASTER LE IN 264325 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 80 MASTER LE IN 264394 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 81 MASTER LE IN 264392 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[13]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 82 MASTER LE IN 264390 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[15]
(M31_1P5V6T_SFFRBQX1)
 Chain[6] 83 MASTER LE IN 264389 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[14]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 84 MASTER LE IN 264388 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[13]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 85 MASTER LE IN 264387 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[12]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 86 MASTER LE IN 264386 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[15]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 87 MASTER LE IN 264219 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_r_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 88 MASTER LE IN 264318 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_sm_i_inst/state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 89 MASTER LE IN 264275 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_i_inst/edge_0deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 90 MASTER LE IN 264234 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_sm_i_inst/state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 91 MASTER LE IN 264240 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 92 MASTER LE IN 264273 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_i_inst/reset_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 93 MASTER LE IN 264227 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_r_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 94 MASTER LE IN 264466 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_sm_i_inst/set_en_r_S19_r
eg (M31_1P5V6T_SFFSBQX1)
Chain[6] 95 MASTER LE IN 264467 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_sm_i_inst/reset_en_r_S19
_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 96 MASTER LE IN 264225 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_r_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 97 MASTER LE IN 264468 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_sm_i_inst/set_en_r_S19_r
eg (M31_1P5V6T_SFFSBQX1)
Chain[6] 98 MASTER LE IN 264286 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_i_inst/set_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 99 MASTER LE IN 264287 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_i_inst/reset_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 100 MASTER LE IN 264469 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_sm_i_inst/reset_en_r_S19
_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 101 MASTER LE IN 264272 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_i_inst/set_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 102 MASTER LE IN 265141 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 103 MASTER LE IN 264235 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_sm_i_inst/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 104 MASTER LE IN 265101 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 105 MASTER LE IN 264237 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_sm_i_inst/clk_sm_enabled
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 106 MASTER LE IN 265106 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 107 MASTER LE IN 265111 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 108 MASTER LE IN 264279 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_sm_i_inst/clk_sm_enabled
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 109 MASTER LE IN 265117 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 110 MASTER LE IN 265123 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 111 MASTER LE IN 264277 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_sm_i_inst/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 112 MASTER LE IN 264278 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_sm_i_inst/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 113 MASTER LE IN 264276 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_sm_i_inst/state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 114 MASTER LE IN 265136 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 115 MASTER LE IN 264262 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_sm_i_inst/state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 116 MASTER LE IN 264226 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 117 MASTER LE IN 264213 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_i_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 118 MASTER LE IN 265119 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 119 MASTER LE IN 265142 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 120 MASTER LE IN 265118 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 121 MASTER LE IN 264265 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[3]_buck_clk_en_sel_sm_i_inst/clk_sm_enabled
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 122 MASTER LE IN 264218 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 123 MASTER LE IN 265131 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 124 MASTER LE IN 264224 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 125 MASTER LE IN 265124 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 126 MASTER LE IN 264332 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_sm_i_inst/state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 127 MASTER LE IN 264067 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_sm_i_inst/clk_sm_enabled
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 128 MASTER LE IN 264222 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 129 MASTER LE IN 264211 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_i_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 130 MASTER LE IN 265130 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 131 MASTER LE IN 264321 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_sm_i_inst/clk_sm_enabled
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 132 MASTER LE IN 264215 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_i_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 133 MASTER LE IN 264251 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_sm_i_inst/clk_sm_enabled
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 134 MASTER LE IN 264228 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 135 MASTER LE IN 264307 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_sm_i_inst/clk_sm_enabled
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 136 MASTER LE IN 264471 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_sm_i_inst/reset_en_r_S19
_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 137 MASTER LE IN 264470 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_sm_i_inst/set_en_r_S19_r
eg (M31_1P5V6T_SFFSBQX1)
Chain[6] 138 MASTER LE IN 264292 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_sm_i_inst/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 139 MASTER LE IN 264355 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[28]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 140 MASTER LE IN 264354 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[31]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 141 MASTER LE IN 264476 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_sm_i_inst/set_en_r_S19_r
eg (M31_1P5V6T_SFFSBQX1)
 Chain[6] 142 MASTER LE IN 264339 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 143 MASTER LE IN 264340 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_sm_i_inst/enable_early_p
ulses_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 144 MASTER LE IN 264477 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_sm_i_inst/reset_en_r_S19
_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 145 MASTER LE IN 264334 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_sm_i_inst/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 146 MASTER LE IN 264335 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_sm_i_inst/allow_counting
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 147 MASTER LE IN 264338 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 148 MASTER LE IN 264337 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 149 MASTER LE IN 264357 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[30]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 150 MASTER LE IN 264359 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[28]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 151 MASTER LE IN 264360 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[29]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 152 MASTER LE IN 264294 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_sm_i_inst/allow_counting
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 153 MASTER LE IN 264299 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_sm_i_inst/enable_early_p
ulses_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 154 MASTER LE IN 264296 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 155 MASTER LE IN 264297 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 156 MASTER LE IN 264361 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[30]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 157 MASTER LE IN 264358 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[31]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 158 MASTER LE IN 264356 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[29]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 159 MASTER LE IN 264343 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_i_inst/reset_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 160 MASTER LE IN 264341 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_i_inst/set_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 161 MASTER LE IN 264342 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[8]_buck_clk_en_sel_i_inst/edge_0deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 162 MASTER LE IN 264290 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_sm_i_inst/state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 163 MASTER LE IN 264291 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_sm_i_inst/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 164 MASTER LE IN 264293 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_sm_i_inst/clk_sm_enabled
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 165 MASTER LE IN 265107 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 166 MASTER LE IN 265129 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 167 MASTER LE IN 265135 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 168 MASTER LE IN 264236 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_sm_i_inst/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 169 MASTER LE IN 264241 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 170 MASTER LE IN 264239 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 171 MASTER LE IN 264319 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_sm_i_inst/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 172 MASTER LE IN 264328 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_i_inst/set_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 173 MASTER LE IN 264329 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[7]_buck_clk_en_sel_i_inst/reset_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 174 MASTER LE IN 264362 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[27]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 175 MASTER LE IN 264366 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[27]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 176 MASTER LE IN 264365 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[26]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 177 MASTER LE IN 264364 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[25]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 178 MASTER LE IN 264369 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[26]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 179 MASTER LE IN 264948 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_bus_sync_toggle/togg
le_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 180 MASTER LE IN 264949 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 181 MASTER LE IN 264913 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_bus_sync_toggle/togg
le_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 182 MASTER LE IN 264912 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 183 MASTER LE IN 264947 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 184 MASTER LE IN 264946 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 185 MASTER LE IN 264915 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 186 MASTER LE IN 264944 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 187 MASTER LE IN 265050 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 188 MASTER LE IN 265057 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 189 MASTER LE IN 264981 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 190 MASTER LE IN 264916 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 191 MASTER LE IN 264917 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 192 MASTER LE IN 264952 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 193 MASTER LE IN 265053 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_bus_sync_toggle/togg
le_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 194 MASTER LE IN 264950 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 195 MASTER LE IN 264985 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 196 MASTER LE IN 264984 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 197 MASTER LE IN 265091 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 198 MASTER LE IN 264486 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d1_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 199 MASTER LE IN 265088 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_bus_sync_toggle/togg
le_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 200 MASTER LE IN 264987 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
 Chain[6] 201 MASTER LE IN 264484 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d1_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 202 MASTER LE IN 264095 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d2_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 203 MASTER LE IN 264099 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d2_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 204 MASTER LE IN 264419 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/FOLLOW_CLK_REQ_CH_S19_reg[7]
(M31_1P5V6T_SFFSBQX1)
Chain[6] 205 MASTER LE IN 264096 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d3_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 206 MASTER LE IN 264479 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d1_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 207 MASTER LE IN 264085 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d2_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 208 MASTER LE IN 264088 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d3_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 209 MASTER LE IN 264087 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d2_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 210 MASTER LE IN 264480 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d1_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 211 MASTER LE IN 264071 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[7]_slib_sync_buck_
clk_req_reg/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 212 MASTER LE IN 264075 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[5]_slib_sync_buck_
clk_req_reg/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 213 MASTER LE IN 264417 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 214 MASTER LE IN 264416 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 215 MASTER LE IN 264076 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[5]_slib_sync_buck_
clk_req_reg/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 216 MASTER LE IN 264072 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[7]_slib_sync_buck_
clk_req_reg/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 217 MASTER LE IN 264091 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d2_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 218 MASTER LE IN 264346 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/EN_CLK_INT_CH_S19_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 219 MASTER LE IN 265128 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 220 MASTER LE IN 264069 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[8]_slib_sync_buck_
clk_req_reg/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 221 MASTER LE IN 264421 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/FOLLOW_CLK_REQ_CH_S19_reg[5]
(M31_1P5V6T_SFFSBQX1)
Chain[6] 222 MASTER LE IN 265127 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 223 MASTER LE IN 264070 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[8]_slib_sync_buck_
clk_req_reg/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 224 MASTER LE IN 265146 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 225 MASTER LE IN 264244 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_i_inst/set_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 226 MASTER LE IN 264245 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_i_inst/reset_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 227 MASTER LE IN 264207 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/sync_clock_counter_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 228 MASTER LE IN 264463 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_sm_i_inst/reset_en_r_S19
_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 229 MASTER LE IN 265099 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 230 MASTER LE IN 264243 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_sm_i_inst/enable_early_p
ulses_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 231 MASTER LE IN 264242 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 232 MASTER LE IN 264238 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_sm_i_inst/allow_counting
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 233 MASTER LE IN 265100 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 234 MASTER LE IN 264201 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/sync_clock_counter_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 235 MASTER LE IN 264230 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_i_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 236 MASTER LE IN 264249 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_sm_i_inst/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 237 MASTER LE IN 264202 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/sync_clock_counter_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 238 MASTER LE IN 264208 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/sync_clock_counter_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 239 MASTER LE IN 264205 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/sync_clock_counter_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 240 MASTER LE IN 264258 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_i_inst/set_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 241 MASTER LE IN 264229 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_r_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 242 MASTER LE IN 264465 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_sm_i_inst/reset_en_r_S19
_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 243 MASTER LE IN 264305 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_sm_i_inst/state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 244 MASTER LE IN 264248 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_sm_i_inst/state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 245 MASTER LE IN 264250 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_sm_i_inst/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 246 MASTER LE IN 264300 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_i_inst/set_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 247 MASTER LE IN 264220 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 248 MASTER LE IN 264303 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_i_inst/edge_0deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 249 MASTER LE IN 264301 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_i_inst/reset_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 250 MASTER LE IN 264378 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[19]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 251 MASTER LE IN 264379 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[16]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 252 MASTER LE IN 264304 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_sm_i_inst/state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 253 MASTER LE IN 264306 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_sm_i_inst/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 254 MASTER LE IN 264472 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_sm_i_inst/set_en_r_S19_r
eg (M31_1P5V6T_SFFSBQX1)
Chain[6] 255 MASTER LE IN 264308 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_sm_i_inst/allow_counting
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 256 MASTER LE IN 264383 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[16]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 257 MASTER LE IN 264380 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[17]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 258 MASTER LE IN 264381 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[18]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 259 MASTER LE IN 264298 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 260 MASTER LE IN 264223 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_r_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 261 MASTER LE IN 264295 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[5]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 262 MASTER LE IN 264382 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[19]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 263 MASTER LE IN 264384 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[17]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 264 MASTER LE IN 264385 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[18]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 265 MASTER LE IN 264309 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 266 MASTER LE IN 264310 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 267 MASTER LE IN 264311 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 268 MASTER LE IN 264221 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_r_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 269 MASTER LE IN 264313 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_sm_i_inst/enable_early_p
ulses_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 270 MASTER LE IN 264473 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_sm_i_inst/reset_en_r_S19
_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 271 MASTER LE IN 264257 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_sm_i_inst/enable_early_p
ulses_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 272 MASTER LE IN 264252 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_sm_i_inst/allow_counting
_S19_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 273 MASTER LE IN 264464 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_sm_i_inst/set_en_r_S19_r
eg (M31_1P5V6T_SFFSBQX1)
Chain[6] 274 MASTER LE IN 264203 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/sync_clock_counter_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 275 MASTER LE IN 264204 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/sync_clock_counter_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 276 MASTER LE IN 264231 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 277 MASTER LE IN 264462 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_sm_i_inst/set_en_r_S19_r
eg (M31_1P5V6T_SFFSBQX1)
Chain[6] 278 MASTER LE IN 264410 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 279 MASTER LE IN 264232 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/on_the_fly_div_phase_ch_r_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 280 MASTER LE IN 264413 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 281 MASTER LE IN 264414 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 282 MASTER LE IN 264412 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 283 MASTER LE IN 264411 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 284 MASTER LE IN 264415 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 285 MASTER LE IN 264092 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d3_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 286 MASTER LE IN 264086 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d3_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 287 MASTER LE IN 264482 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d1_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 288 MASTER LE IN 264983 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_bus_sync_toggle/togg
le_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 289 MASTER LE IN 264986 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 290 MASTER LE IN 264951 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 291 MASTER LE IN 264945 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 292 MASTER LE IN 264980 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 293 MASTER LE IN 264979 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 294 MASTER LE IN 264982 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 295 MASTER LE IN 265056 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 296 MASTER LE IN 265055 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 297 MASTER LE IN 265054 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 298 MASTER LE IN 264914 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 299 MASTER LE IN 265052 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 300 MASTER LE IN 265051 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 301 MASTER LE IN 264911 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 302 MASTER LE IN 264905 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 303 MASTER LE IN 264906 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 304 MASTER LE IN 265046 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 305 MASTER LE IN 265047 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 306 MASTER LE IN 265044 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 307 MASTER LE IN 264904 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 308 MASTER LE IN 264942 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 309 MASTER LE IN 264940 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 310 MASTER LE IN 265080 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 311 MASTER LE IN 265081 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 312 MASTER LE IN 264941 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 313 MASTER LE IN 265086 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 314 MASTER LE IN 265087 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 315 MASTER LE IN 264910 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 316 MASTER LE IN 264842 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 317 MASTER LE IN 264841 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 318 MASTER LE IN 264876 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[2] (M31_1P5V6T_SFFSRBQX1)
 Chain[6] 319 MASTER LE IN 264877 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 320 MASTER LE IN 264875 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 321 MASTER LE IN 264840 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 322 MASTER LE IN 265090 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 323 MASTER LE IN 265085 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 324 MASTER LE IN 265092 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 325 MASTER LE IN 264847 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 326 MASTER LE IN 264845 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 327 MASTER LE IN 265021 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 328 MASTER LE IN 264881 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 329 MASTER LE IN 265089 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 330 MASTER LE IN 265022 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 331 MASTER LE IN 264882 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 332 MASTER LE IN 264483 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d1_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 333 MASTER LE IN 264093 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d2_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 334 MASTER LE IN 265102 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 335 MASTER LE IN 264846 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 336 MASTER LE IN 264843 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_bus_sync_toggle/togg
le_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 337 MASTER LE IN 264100 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d3_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 338 MASTER LE IN 265140 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 339 MASTER LE IN 265139 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 340 MASTER LE IN 265138 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 341 MASTER LE IN 265115 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 342 MASTER LE IN 265144 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 343 MASTER LE IN 264345 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/EN_CLK_INT_CH_S19_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 344 MASTER LE IN 264418 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/FOLLOW_CLK_REQ_CH_S19_reg[8]
(M31_1P5V6T_SFFSBQX1)
Chain[6] 345 MASTER LE IN 265116 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 346 MASTER LE IN 265145 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 347 MASTER LE IN 264348 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/EN_CLK_INT_CH_S19_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 348 MASTER LE IN 265126 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 349 MASTER LE IN 265114 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 350 MASTER LE IN 265103 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 351 MASTER LE IN 264090 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d3_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 352 MASTER LE IN 264425 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/FOLLOW_CLK_REQ_CH_S19_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[6] 353 MASTER LE IN 264352 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/EN_CLK_INT_CH_S19_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 354 MASTER LE IN 264350 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/EN_CLK_INT_CH_S19_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 355 MASTER LE IN 265121 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 356 MASTER LE IN 265122 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 357 MASTER LE IN 264422 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/FOLLOW_CLK_REQ_CH_S19_reg[4]
(M31_1P5V6T_SFFSBQX1)
Chain[6] 358 MASTER LE IN 264349 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/EN_CLK_INT_CH_S19_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 359 MASTER LE IN 264351 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/EN_CLK_INT_CH_S19_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 360 MASTER LE IN 264424 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/FOLLOW_CLK_REQ_CH_S19_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[6] 361 MASTER LE IN 264353 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/EN_MAIN_CLK_INT_S19_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 362 MASTER LE IN 264347 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/EN_CLK_INT_CH_S19_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 363 MASTER LE IN 264420 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/FOLLOW_CLK_REQ_CH_S19_reg[6]
(M31_1P5V6T_SFFSBQX1)
Chain[6] 364 MASTER LE IN 264074 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[6]_slib_sync_buck_
clk_req_reg/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 365 MASTER LE IN 264247 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[1]_buck_clk_en_sel_i_inst/edge_0deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 366 MASTER LE IN 264073 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[6]_slib_sync_buck_
clk_req_reg/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 367 MASTER LE IN 264233 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/dtest_sync_clock_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 368 MASTER LE IN 265105 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_pulse_sync_any/sync_
u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 369 MASTER LE IN 264206 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/sync_clock_counter_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 370 MASTER LE IN 264261 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_i_inst/edge_0deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 371 MASTER LE IN 264200 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/sync_clock_is_running_S19_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 372 MASTER LE IN 264198 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 373 MASTER LE IN 264068 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/clk_sm_enabled_d1_S19_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 374 MASTER LE IN 265098 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_BCLKGEN_ENABLE_pul
se_sync_any/sync_out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 375 MASTER LE IN 264403 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 376 MASTER LE IN 264405 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 377 MASTER LE IN 264404 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 378 MASTER LE IN 264402 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 379 MASTER LE IN 264259 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_i_inst/reset_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 380 MASTER LE IN 264255 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 381 MASTER LE IN 264256 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 382 MASTER LE IN 264253 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 383 MASTER LE IN 264314 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_i_inst/set_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 384 MASTER LE IN 264312 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 385 MASTER LE IN 264315 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_i_inst/reset_en_late_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 386 MASTER LE IN 264371 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[20]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 387 MASTER LE IN 264376 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[21]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 388 MASTER LE IN 264374 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[23]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 389 MASTER LE IN 264373 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[22]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 390 MASTER LE IN 264372 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[21]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 391 MASTER LE IN 264377 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[22]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 392 MASTER LE IN 264370 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[23]
(M31_1P5V6T_SFFRBQX1)
 Chain[6] 393 MASTER LE IN 264317 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[6]_buck_clk_en_sel_i_inst/edge_0deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 394 MASTER LE IN 264254 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[2]_buck_clk_en_sel_sm_i_inst/set_reset_coun
ter_S19_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 395 MASTER LE IN 264408 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 396 MASTER LE IN 264406 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_DIV_CH_S19_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 397 MASTER LE IN 264199 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 398 MASTER LE IN 264426 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/FOLLOW_MAIN_CLK_REQ_S19_reg
(M31_1P5V6T_SFFSBQX1)
Chain[6] 399 MASTER LE IN 265134 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 400 MASTER LE IN 264082 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[2]_slib_sync_buck_
clk_req_reg/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 401 MASTER LE IN 265133 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 402 MASTER LE IN 264289 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_sync[4]_buck_clk_en_sel_i_inst/edge_0deg_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 403 MASTER LE IN 265132 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 404 MASTER LE IN 264423 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/FOLLOW_CLK_REQ_CH_S19_reg[3]
(M31_1P5V6T_SFFSBQX1)
Chain[6] 405 MASTER LE IN 265104 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 406 MASTER LE IN 265120 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 407 MASTER LE IN 264089 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d2_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 408 MASTER LE IN 264481 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d1_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 409 MASTER LE IN 265018 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_bus_sync_toggle/togg
le_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 410 MASTER LE IN 264880 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 411 MASTER LE IN 265020 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 412 MASTER LE IN 264839 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 413 MASTER LE IN 265015 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 414 MASTER LE IN 265049 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 415 MASTER LE IN 265016 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 416 MASTER LE IN 265017 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 417 MASTER LE IN 265079 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 418 MASTER LE IN 265082 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 419 MASTER LE IN 264939 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 420 MASTER LE IN 264907 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 421 MASTER LE IN 265045 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 422 MASTER LE IN 264908 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 423 MASTER LE IN 265048 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 424 MASTER LE IN 265026 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 425 MASTER LE IN 264886 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 426 MASTER LE IN 265009 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 427 MASTER LE IN 265010 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 428 MASTER LE IN 265011 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 429 MASTER LE IN 264870 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 430 MASTER LE IN 264991 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 431 MASTER LE IN 264869 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 432 MASTER LE IN 264873 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 433 MASTER LE IN 264975 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 434 MASTER LE IN 264976 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 435 MASTER LE IN 264956 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 436 MASTER LE IN 264978 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 437 MASTER LE IN 264816 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 438 MASTER LE IN 264838 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 439 MASTER LE IN 264868 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 440 MASTER LE IN 264834 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 441 MASTER LE IN 264836 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 442 MASTER LE IN 264835 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 443 MASTER LE IN 264977 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 444 MASTER LE IN 264974 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 445 MASTER LE IN 264837 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 446 MASTER LE IN 264867 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 447 MASTER LE IN 265007 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 448 MASTER LE IN 264937 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 449 MASTER LE IN 264938 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 450 MASTER LE IN 265078 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 451 MASTER LE IN 265077 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
 Chain[6] 452 MASTER LE IN 265008 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 453 MASTER LE IN 264936 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL2__GANG_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 454 MASTER LE IN 264874 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 455 MASTER LE IN 265006 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL2__GANG_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 456 MASTER LE IN 265076 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL2__GANG_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 457 MASTER LE IN 265041 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL2__GANG_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 458 MASTER LE IN 264901 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL2__GANG_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 459 MASTER LE IN 264832 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 460 MASTER LE IN 264833 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 461 MASTER LE IN 264973 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 462 MASTER LE IN 264972 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 463 MASTER LE IN 264831 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL2__GANG_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 464 MASTER LE IN 265040 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 465 MASTER LE IN 264900 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 466 MASTER LE IN 265014 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 467 MASTER LE IN 264866 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL2__GANG_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 468 MASTER LE IN 265039 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 469 MASTER LE IN 264899 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 470 MASTER LE IN 264934 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 471 MASTER LE IN 265060 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__EN_CLK_INT_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 472 MASTER LE IN 265059 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__FOLLOW_CLK_SX_RE
Q_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 473 MASTER LE IN 264919 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__FOLLOW_CLK_SX_RE
Q_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 474 MASTER LE IN 265058 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_bus_sync_toggle/t
oggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 475 MASTER LE IN 264920 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__EN_CLK_INT_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 476 MASTER LE IN 264850 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__EN_CLK_INT_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 477 MASTER LE IN 265095 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__EN_CLK_INT_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 478 MASTER LE IN 264990 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__EN_CLK_INT_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 479 MASTER LE IN 264953 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_bus_sync_toggle/t
oggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 480 MASTER LE IN 264989 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__FOLLOW_CLK_SX_RE
Q_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 481 MASTER LE IN 264955 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__EN_CLK_INT_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 482 MASTER LE IN 264849 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__FOLLOW_CLK_SX_RE
Q_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 483 MASTER LE IN 265074 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 484 MASTER LE IN 264879 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 485 MASTER LE IN 264969 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 486 MASTER LE IN 264829 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 487 MASTER LE IN 265075 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 488 MASTER LE IN 264935 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 489 MASTER LE IN 265005 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 490 MASTER LE IN 264830 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 491 MASTER LE IN 264970 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 492 MASTER LE IN 264865 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 493 MASTER LE IN 265004 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 494 MASTER LE IN 264885 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__EN_CLK_INT_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 495 MASTER LE IN 264883 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_bus_sync_toggle/t
oggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 496 MASTER LE IN 264884 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__FOLLOW_CLK_SX_RE
Q_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 497 MASTER LE IN 264954 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__FOLLOW_CLK_SX_RE
Q_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 498 MASTER LE IN 265024 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__FOLLOW_CLK_SX_RE
Q_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 499 MASTER LE IN 265094 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__FOLLOW_CLK_SX_RE
Q_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 500 MASTER LE IN 265025 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE__EN_CLK_INT_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 501 MASTER LE IN 265023 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_bus_sync_toggle/t
oggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 502 MASTER LE IN 265093 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_bus_sync_toggle/t
oggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 503 MASTER LE IN 264878 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV_bus_sync_toggle/togg
le_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 504 MASTER LE IN 264098 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d3_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 505 MASTER LE IN 264094 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d3_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 506 MASTER LE IN 264083 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[1]_slib_sync_buck_
clk_req_reg/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 507 MASTER LE IN 264080 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[3]_slib_sync_buck_
clk_req_reg/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 508 MASTER LE IN 264078 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[4]_slib_sync_buck_
clk_req_reg/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 509 MASTER LE IN 265110 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_out_d_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 510 MASTER LE IN 264375 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[20]
(M31_1P5V6T_SFFRBQX1)
 Chain[6] 511 MASTER LE IN 264409 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 512 MASTER LE IN 264407 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/CLK_PHASE_CH_S19_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 513 MASTER LE IN 265097 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_BCLKGEN_ENABLE_pul
se_sync_any/sync_u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 514 MASTER LE IN 265109 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 515 MASTER LE IN 265096 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_BCLKGEN_ENABLE_pul
se_sync_any/sync_u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 516 MASTER LE IN 265108 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_pulse_sync_any/sy
nc_u0/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 517 MASTER LE IN 264081 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[2]_slib_sync_buck_
clk_req_reg/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 518 MASTER LE IN 264077 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[4]_slib_sync_buck_
clk_req_reg/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 519 MASTER LE IN 264084 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[1]_slib_sync_buck_
clk_req_reg/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 520 MASTER LE IN 264079 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/buck_clk_sync[3]_slib_sync_buck_
clk_req_reg/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 521 MASTER LE IN 264097 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d2_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 522 MASTER LE IN 264485 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_en_sel_inst/buck_clk_master_fsm_inst/ch_after_reset_d1_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 523 MASTER LE IN 264988 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_bus_sync_toggle/t
oggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 524 MASTER LE IN 264918 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_bus_sync_toggle/t
oggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 525 MASTER LE IN 264848 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_ENABLE_bus_sync_toggle/t
oggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 526 MASTER LE IN 264844 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 527 MASTER LE IN 265084 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 528 MASTER LE IN 264909 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_CLK_PHASE__CLK_PHASE_reg/dou
t_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 529 MASTER LE IN 264903 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 530 MASTER LE IN 265043 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 531 MASTER LE IN 264902 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 532 MASTER LE IN 265042 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 533 MASTER LE IN 265083 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 534 MASTER LE IN 264921 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 535 MASTER LE IN 265061 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 536 MASTER LE IN 264943 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 537 MASTER LE IN 265012 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 538 MASTER LE IN 264871 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 539 MASTER LE IN 265013 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 540 MASTER LE IN 264872 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[5] (M31_1P5V6T_SFFSRBQX1)
 Chain[6] 541 MASTER LE IN 264851 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL1__GANG_LEADER_PID_r
eg/dout_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 542 MASTER LE IN 264887 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1_write_once_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 543 MASTER LE IN 264922 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1_write_once_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 544 MASTER LE IN 265063 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 545 MASTER LE IN 264923 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 546 MASTER LE IN 264993 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 547 MASTER LE IN 264853 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 548 MASTER LE IN 265028 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 549 MASTER LE IN 264888 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 550 MASTER LE IN 264958 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 551 MASTER LE IN 264818 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 552 MASTER LE IN 264819 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 553 MASTER LE IN 264959 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 554 MASTER LE IN 264889 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 555 MASTER LE IN 265029 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 556 MASTER LE IN 264924 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 557 MASTER LE IN 264817 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1_write_once_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 558 MASTER LE IN 265027 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1_write_once_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 559 MASTER LE IN 264992 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1_write_once_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 560 MASTER LE IN 265062 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1_write_once_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 561 MASTER LE IN 264957 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1_write_once_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 562 MASTER LE IN 264994 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 563 MASTER LE IN 264854 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 564 MASTER LE IN 264927 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 565 MASTER LE IN 265033 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 566 MASTER LE IN 264893 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 567 MASTER LE IN 264895 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_OTS
T2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 568 MASTER LE IN 265035 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_OTS
T2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 569 MASTER LE IN 264894 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_WAR
M_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 570 MASTER LE IN 264892 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 571 MASTER LE IN 265032 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 572 MASTER LE IN 265031 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL4__LOCAL_SOFT
_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 573 MASTER LE IN 264891 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL4__LOCAL_SOFT
_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 574 MASTER LE IN 265030 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL2__FOLLOW_GLO
BAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 575 MASTER LE IN 264822 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 576 MASTER LE IN 264926 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL4__LOCAL_SOFT
_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 577 MASTER LE IN 265066 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL4__LOCAL_SOFT
_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 578 MASTER LE IN 265065 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL2__FOLLOW_GLO
BAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 579 MASTER LE IN 264925 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL2__FOLLOW_GLO
BAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 580 MASTER LE IN 264890 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL2__FOLLOW_GLO
BAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 581 MASTER LE IN 264960 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL2__FOLLOW_GLO
BAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 582 MASTER LE IN 264820 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL2__FOLLOW_GLO
BAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 583 MASTER LE IN 264821 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL4__LOCAL_SOFT
_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 584 MASTER LE IN 264855 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL2__FOLLOW_GLO
BAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 585 MASTER LE IN 264856 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL4__LOCAL_SOFT
_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 586 MASTER LE IN 264964 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_WAR
M_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 587 MASTER LE IN 264823 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 588 MASTER LE IN 264824 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_WAR
M_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 589 MASTER LE IN 265034 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_WAR
M_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 590 MASTER LE IN 265064 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1__LOCKBIT_D1_reg/d
out_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 591 MASTER LE IN 264852 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_LOCKBIT_D1_write_once_reg/do
ut_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 592 MASTER LE IN 264971 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_GANG_CTL2__GANG_EN_reg/dout_
reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 593 MASTER LE IN 265036 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_TEST1__EN_DTEST_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 594 MASTER LE IN 264896 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_TEST1__EN_DTEST_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 595 MASTER LE IN 264897 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 596 MASTER LE IN 265038 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 597 MASTER LE IN 264898 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[3]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 598 MASTER LE IN 264828 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 599 MASTER LE IN 264966 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_TEST1__EN_DTEST_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 600 MASTER LE IN 264826 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_TEST1__EN_DTEST_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 601 MASTER LE IN 264933 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 602 MASTER LE IN 265037 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[7]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 603 MASTER LE IN 265072 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 604 MASTER LE IN 265073 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 605 MASTER LE IN 264932 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 606 MASTER LE IN 265019 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_CLK_DIV__CLK_DIV_reg/dout_re
g[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 607 MASTER LE IN 264931 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_TEST1__EN_DTEST_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 608 MASTER LE IN 265071 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_TEST1__EN_DTEST_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 609 MASTER LE IN 264864 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_TEST1__SIG_SEL_reg/dout_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 610 MASTER LE IN 265002 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 611 MASTER LE IN 265003 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 612 MASTER LE IN 265001 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_TEST1__EN_DTEST_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 613 MASTER LE IN 264861 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_TEST1__EN_DTEST_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 614 MASTER LE IN 264862 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 615 MASTER LE IN 264863 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 616 MASTER LE IN 264968 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 617 MASTER LE IN 264967 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 618 MASTER LE IN 264827 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_TEST1__DTEST_SEL_reg/dout_re
g[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 619 MASTER LE IN 264930 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_OTS
T2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 620 MASTER LE IN 264929 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_WAR
M_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 621 MASTER LE IN 264928 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[4]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 622 MASTER LE IN 265068 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 623 MASTER LE IN 265067 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 624 MASTER LE IN 264857 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 625 MASTER LE IN 265069 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_WAR
M_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 626 MASTER LE IN 265070 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[8]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_OTS
T2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 627 MASTER LE IN 264859 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_WAR
M_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 628 MASTER LE IN 264858 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 629 MASTER LE IN 264785 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_BCLKGEN_ENABLE__FO
LLOW_CLK_REQ_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 630 MASTER LE IN 265000 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_OTS
T2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 631 MASTER LE IN 264999 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_WAR
M_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 632 MASTER LE IN 264997 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 633 MASTER LE IN 264963 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 634 MASTER LE IN 264825 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[1]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_OTS
T2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 635 MASTER LE IN 264965 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_OTS
T2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 636 MASTER LE IN 264996 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL4__LOCAL_SOFT
_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 637 MASTER LE IN 264739 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST10__DTEST1_SEL
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 638 MASTER LE IN 264748 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST11__DTEST4_SEL
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 639 MASTER LE IN 263855 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\smps_clk19m2_en_syn
c_reg[29] (M31_1P5V6T_SFFRBQX1)
Chain[6] 640 MASTER LE IN 263872 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/clk19m2_en_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 641 MASTER LE IN 264737 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST10__DTEST1_SEL
_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 642 MASTER LE IN 264741 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST10__DTEST2_SEL
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 643 MASTER LE IN 264998 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 644 MASTER LE IN 264860 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[2]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_OTS
T2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 645 MASTER LE IN 264786 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_BCLKGEN_ENABLE__EN
_BUCK_CMN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 646 MASTER LE IN 264784 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_BCLKGEN_ENABLE_bus
_sync_toggle/toggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 647 MASTER LE IN 264742 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST10__DTEST2_SEL
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 648 MASTER LE IN 264740 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST10__DTEST2_SEL
_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 649 MASTER LE IN 264743 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST11__DTEST3_SEL
_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 650 MASTER LE IN 264745 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST11__DTEST3_SEL
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 651 MASTER LE IN 264744 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST11__DTEST3_SEL
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 652 MASTER LE IN 264746 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST11__DTEST4_SEL
_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 653 MASTER LE IN 264747 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST11__DTEST4_SEL
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 654 MASTER LE IN 264962 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHU
TDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 655 MASTER LE IN 264995 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[6]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL2__FOLLOW_GLO
BAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 656 MASTER LE IN 264961 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_buck_cmn_u_buck_clk_dig_wra
pper/buck_clk_rif_wrap[5]_buck_cmn_idss_clk_rif_inst/u_PERPH_RESET_CTL4__LOCAL_SOFT
_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 657 MASTER LE IN 264677 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_LOCKB
IT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 658 MASTER LE IN 264600 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_LOCKBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 659 MASTER LE IN 264771 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE2__RFU_reg/do
ut_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 660 MASTER LE IN 264770 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE2__RFU_reg/do
ut_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 661 MASTER LE IN 264769 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE2__RFU_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 662 MASTER LE IN 264768 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE2__RFU_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 663 MASTER LE IN 264776 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE1__RFU_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 664 MASTER LE IN 264781 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE1__RFU_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 665 MASTER LE IN 264780 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE1__RFU_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 666 MASTER LE IN 264772 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE2__RFU_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 667 MASTER LE IN 265170 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC5__MIN_XO_COUNT_LMT_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX2)
Chain[6] 668 MASTER LE IN 264543 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE1__RTC_STORGE1_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 669 MASTER LE IN 264540 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE2__RTC_STORGE2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 670 MASTER LE IN 264544 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE1__RTC_STORGE1_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 671 MASTER LE IN 264554 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE0__RTC_STORGE0_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 672 MASTER LE IN 264783 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE1__RFU_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 673 MASTER LE IN 264546 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE1__RTC_STORGE1_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 674 MASTER LE IN 264552 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE0__RTC_STORGE0_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 675 MASTER LE IN 264777 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE1__RFU_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 676 MASTER LE IN 264779 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE1__RFU_reg/do
ut_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 677 MASTER LE IN 264763 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE3__RFU_reg/do
ut_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 678 MASTER LE IN 264761 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE3__RFU_reg/do
ut_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 679 MASTER LE IN 264545 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE1__RTC_STORGE1_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 680 MASTER LE IN 264778 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE1__RFU_reg/do
ut_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 681 MASTER LE IN 264553 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE0__RTC_STORGE0_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 682 MASTER LE IN 264762 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE3__RFU_reg/do
ut_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 683 MASTER LE IN 264529 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE3__RTC_STORGE3_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 684 MASTER LE IN 264537 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE2__RTC_STORGE2_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 685 MASTER LE IN 264538 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE2__RTC_STORGE2_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 686 MASTER LE IN 264530 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE3__RTC_STORGE3_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 687 MASTER LE IN 264528 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE3__RTC_STORGE3_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 688 MASTER LE IN 264670 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA1__TIMER_DATA1_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 689 MASTER LE IN 264640 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA0__RTC_ALARM_DATA0_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 690 MASTER LE IN 264642 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA0__RTC_ALARM_DATA0_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 691 MASTER LE IN 264643 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA0__RTC_ALARM_DATA0_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 692 MASTER LE IN 264676 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA1__TIMER_DATA1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 693 MASTER LE IN 264774 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE2__RFU_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 694 MASTER LE IN 264766 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE3__RFU_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 695 MASTER LE IN 264767 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE3__RFU_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 696 MASTER LE IN 264542 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE2__RTC_STORGE2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 697 MASTER LE IN 264550 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE1__RTC_STORGE1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 698 MASTER LE IN 264775 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE2__RFU_reg/do
ut_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 699 MASTER LE IN 264558 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE0__RTC_STORGE0_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 700 MASTER LE IN 264549 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE1__RTC_STORGE1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 701 MASTER LE IN 264541 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE2__RTC_STORGE2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 702 MASTER LE IN 264535 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE2__RTC_STORGE2_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 703 MASTER LE IN 264548 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE1__RTC_STORGE1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 704 MASTER LE IN 265150 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC5__MAX_XO_COUNT_LMT_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX2)
Chain[6] 705 MASTER LE IN 264648 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 706 MASTER LE IN 264649 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_LOC
KBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 707 MASTER LE IN 264782 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE1__RFU_reg/do
ut_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 708 MASTER LE IN 264539 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE2__RTC_STORGE2_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 709 MASTER LE IN 264547 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE1__RTC_STORGE1_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 710 MASTER LE IN 264654 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 711 MASTER LE IN 264655 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_PER
PH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 712 MASTER LE IN 264653 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_PER
PH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 713 MASTER LE IN 264652 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_PER
PH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 714 MASTER LE IN 264610 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_INT_TEST_VAL__RTC_ALARM_TEST_VAL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 715 MASTER LE IN 264656 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_INT
_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 716 MASTER LE IN 264609 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_INT_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 717 MASTER LE IN 264511 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_PE
RPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 718 MASTER LE IN 264650 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_PER
PH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 719 MASTER LE IN 264509 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_LO
CKBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 720 MASTER LE IN 264510 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_LO
CKBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 721 MASTER LE IN 264689 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_EN_CT
L__FOLLOW_PC_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 722 MASTER LE IN 264651 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_PER
PH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 723 MASTER LE IN 264688 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_PERPH
_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 724 MASTER LE IN 264512 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_PE
RPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 725 MASTER LE IN 264687 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_INT_T
EST_VAL__CLK_ACK_INT_TEST_VAL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 726 MASTER LE IN 264658 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_PER
PH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 727 MASTER LE IN 264659 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_EN_
CTL__TIMER_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 728 MASTER LE IN 264686 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_INT_T
EST1__INT_TEST_MODE_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 729 MASTER LE IN 264515 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_PE
RPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 730 MASTER LE IN 264611 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 731 MASTER LE IN 264697 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_PERPH_RESET_CTL2__
FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 732 MASTER LE IN 264603 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 733 MASTER LE IN 264604 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 734 MASTER LE IN 264606 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 735 MASTER LE IN 264605 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_PERPH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 736 MASTER LE IN 264607 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 737 MASTER LE IN 264602 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 738 MASTER LE IN 264601 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 739 MASTER LE IN 264647 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_LOC
KBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 740 MASTER LE IN 264508 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_LO
CKBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 741 MASTER LE IN 264678 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_LOCKB
IT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 742 MASTER LE IN 264679 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_LOCKB
IT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 743 MASTER LE IN 264608 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 744 MASTER LE IN 264682 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_PERPH
_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 745 MASTER LE IN 264680 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_PERPH
_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 746 MASTER LE IN 264683 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_PERPH
_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 747 MASTER LE IN 264738 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST10__DTEST1_SEL
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 748 MASTER LE IN 264754 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST13__DTEST1_SEL
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 749 MASTER LE IN 264755 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST13__DTEST1_SEL
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 750 MASTER LE IN 264756 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST13__DTEST2_SEL
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 751 MASTER LE IN 264685 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_PERPH
_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 752 MASTER LE IN 264681 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_PERPH
_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 753 MASTER LE IN 264757 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST13__DTEST2_SEL
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 754 MASTER LE IN 264698 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_PERPH_RESET_CTL4__
LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 755 MASTER LE IN 264684 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_PERPH
_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 756 MASTER LE IN 264691 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_DIV_C
TL1__DIV_FACTOR_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[6] 757 MASTER LE IN 264693 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_DIV_C
TL1__DIV_FACTOR_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 758 MASTER LE IN 264692 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_DIV_C
TL1__DIV_FACTOR_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[6] 759 MASTER LE IN 264690 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_divclk1_rif/u_EN_CT
L__DIVCLK_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 760 MASTER LE IN 264062 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_STATUS1__DIVCLK_OK_rifi_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 761 MASTER LE IN 264174 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 762 MASTER LE IN 264170 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 763 MASTER LE IN 264165 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_expired_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 764 MASTER LE IN 264660 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_MODE__CONTINUOUS_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 765 MASTER LE IN 264173 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 766 MASTER LE IN 264657 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_INT
_TEST_VAL__TIMER_EXPIRED_TEST_VAL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 767 MASTER LE IN 264167 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 768 MASTER LE IN 264169 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 769 MASTER LE IN 264166 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__tim
er_expired/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 770 MASTER LE IN 264168 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 771 MASTER LE IN 264164 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 772 MASTER LE IN 264181 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[6] 773 MASTER LE IN 264171 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 774 MASTER LE IN 264175 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 775 MASTER LE IN 264176 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 776 MASTER LE IN 264673 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA1__TIMER_DATA1_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 777 MASTER LE IN 264764 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE3__RFU_reg/do
ut_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 778 MASTER LE IN 264534 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE3__RTC_STORGE3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 779 MASTER LE IN 264536 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE2__RTC_STORGE2_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 780 MASTER LE IN 264773 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE2__RFU_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 781 MASTER LE IN 264765 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE3__RFU_reg/do
ut_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 782 MASTER LE IN 264101 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 783 MASTER LE IN 265167 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC2__DRIFT_LMT_RTC_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX2)
Chain[6] 784 MASTER LE IN 265172 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC2__DRIFT_LMT_RTC_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX2)
Chain[6] 785 MASTER LE IN 264496 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_PERPH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 786 MASTER LE IN 265166 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC2__DRIFT_LMT_RTC_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX2)
Chain[6] 787 MASTER LE IN 265155 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC4__CALRC_DTEST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX2)
Chain[6] 788 MASTER LE IN 264125 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[24] (M31_1P5V6T_SFFRBQX1)
Chain[6] 789 MASTER LE IN 265162 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_EDGE_CTL__OUT_EDGE_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX2)
Chain[6] 790 MASTER LE IN 265171 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_DRV_CTL1__OUT_DRV_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX2)
Chain[6] 791 MASTER LE IN 265151 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_EDGE_CTL__OUT_EDGE_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX3)
Chain[6] 792 MASTER LE IN 265147 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_DRV_CTL1__OUT_DRV_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX3)
Chain[6] 793 MASTER LE IN 264504 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC3__LFRC_DRIFT_DET_EN_BATT_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 794 MASTER LE IN 264497 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 795 MASTER LE IN 265152 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC2__DRIFT_LMT_RTC_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX2)
Chain[6] 796 MASTER LE IN 264498 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 797 MASTER LE IN 264499 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 798 MASTER LE IN 264505 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_SLPSRC_CTL1__EXT32K_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 799 MASTER LE IN 264493 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_PERPH_RESET_CTL6__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 800 MASTER LE IN 264492 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_PERPH_RESET_CTL5__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 801 MASTER LE IN 264495 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 802 MASTER LE IN 264500 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_PERPH_RESET_CTL1__ENABLE_PRESET_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 803 MASTER LE IN 264494 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 804 MASTER LE IN 264491 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 805 MASTER LE IN 264490 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_LOCKBIT_D1__LOCKBIT_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 806 MASTER LE IN 264489 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_LOCKBIT_D1_write_once_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 807 MASTER LE IN 264637 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA1__RTC_ALARM_DATA1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 808 MASTER LE IN 264557 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE0__RTC_STORGE0_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 809 MASTER LE IN 265168 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC5__MAX_XO_COUNT_LMT_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX2)
Chain[6] 810 MASTER LE IN 264671 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA1__TIMER_DATA1_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 811 MASTER LE IN 264527 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE3__RTC_STORGE3_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 812 MASTER LE IN 264672 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA1__TIMER_DATA1_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 813 MASTER LE IN 264641 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA0__RTC_ALARM_DATA0_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 814 MASTER LE IN 264532 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE3__RTC_STORGE3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 815 MASTER LE IN 264533 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE3__RTC_STORGE3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 816 MASTER LE IN 264675 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA1__TIMER_DATA1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 817 MASTER LE IN 264674 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA1__TIMER_DATA1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 818 MASTER LE IN 264629 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA2__RTC_ALARM_DATA2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 819 MASTER LE IN 264628 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA2__RTC_ALARM_DATA2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 820 MASTER LE IN 264644 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA0__RTC_ALARM_DATA0_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 821 MASTER LE IN 264627 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA2__RTC_ALARM_DATA2_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 822 MASTER LE IN 264669 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA1__TIMER_DATA1_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 823 MASTER LE IN 264631 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA1__RTC_ALARM_DATA1_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 824 MASTER LE IN 264619 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA3__RTC_ALARM_DATA3_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 825 MASTER LE IN 264666 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA2__TIMER_DATA2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 826 MASTER LE IN 264667 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA2__TIMER_DATA2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 827 MASTER LE IN 264620 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA3__RTC_ALARM_DATA3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 828 MASTER LE IN 264661 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA2__TIMER_DATA2_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 829 MASTER LE IN 264117 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[16] (M31_1P5V6T_SFFRBQX1)
Chain[6] 830 MASTER LE IN 264668 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA2__TIMER_DATA2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 831 MASTER LE IN 265149 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC5__MAX_XO_COUNT_LMT_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX2)
Chain[6] 832 MASTER LE IN 264662 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA2__TIMER_DATA2_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 833 MASTER LE IN 264664 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA2__TIMER_DATA2_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 834 MASTER LE IN 264624 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA2__RTC_ALARM_DATA2_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 835 MASTER LE IN 264663 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA2__TIMER_DATA2_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 836 MASTER LE IN 264626 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA2__RTC_ALARM_DATA2_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 837 MASTER LE IN 264625 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA2__RTC_ALARM_DATA2_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 838 MASTER LE IN 264516 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_PE
RPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 839 MASTER LE IN 264443 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[17] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 840 MASTER LE IN 264517 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_PE
RPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 841 MASTER LE IN 264514 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_PE
RPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
 Chain[6] 842 MASTER LE IN 264513 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_PE
RPH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 843 MASTER LE IN 264613 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_EN_CTL1__ABORT_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 844 MASTER LE IN 264478 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 845 MASTER LE IN 264519 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_IN
T_TEST_VAL__RTC_1HZ_TEST_VAL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 846 MASTER LE IN 264716 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_INT_TEST_VAL__CLK3
2K_HALT_DET_TEST_VAL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 847 MASTER LE IN 264758 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST6__DTEST_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 848 MASTER LE IN 264695 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_LOCKBIT_D1__LOCKBI
T_D1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 849 MASTER LE IN 264759 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST6__DTEST_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 850 MASTER LE IN 264736 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST9__FOLLOW_BCLK
GEN_ENA_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 851 MASTER LE IN 264712 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_PERPH_RESET_CTL3__
FOLLOW_SHUTDOWN1_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 852 MASTER LE IN 264709 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_LFRC_AON_TRIM__LFR
C_AON_TRIM_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[6] 853 MASTER LE IN 264735 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST9__FORCE_BCLKG
EN_ENA_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 854 MASTER LE IN 264727 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST4__HFRC_TEST_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 855 MASTER LE IN 264710 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_LFRC_AON_TRIM__LFR
C_AON_TRIM_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 856 MASTER LE IN 264184 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\rlib_status1__hfrc_ok/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 857 MASTER LE IN 264696 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_LOCKBIT_D1__LOCKBI
T_D1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 858 MASTER LE IN 264717 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_INT_TEST_VAL__XO_H
ALT_DET_TEST_VAL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 859 MASTER LE IN 264715 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_INT_TEST1__INT_TES
T_MODE_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 860 MASTER LE IN 264518 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_IN
T_TEST1__INT_TEST_MODE_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 861 MASTER LE IN 264178 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 862 MASTER LE IN 264177 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 863 MASTER LE IN 264172 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 864 MASTER LE IN 264180 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 865 MASTER LE IN 264179 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/timer_count_reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 866 MASTER LE IN 264487 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_timer_rstn_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 867 MASTER LE IN 264134 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_timer_rstn_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 868 MASTER LE IN 264194 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_clks_dig_div/u_divc
lk_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 869 MASTER LE IN 264193 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\divclk_gen[1]_u_clks_dig_div/u_divc
lk_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 870 MASTER LE IN 264060 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clkdiv_intr_gen/genblk2_divclk_di
sa_intr_dly_reg[1][0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 871 MASTER LE IN 264061 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clkdiv_intr_gen/genblk2_divclk_di
sa_intr_dly_reg[1][1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 872 MASTER LE IN 264064 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clkdiv_intr_gen/genblk1_divclk_en
a_intr_dly_reg[1][1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 873 MASTER LE IN 264063 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clkdiv_intr_gen/genblk1_divclk_en
a_intr_dly_reg[1][0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 874 MASTER LE IN 264135 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_rtc_en_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 875 MASTER LE IN 264488 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_rtc_en_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 876 MASTER LE IN 264694 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_LOCKBIT_D1_write_o
nce_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 877 MASTER LE IN 264559 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_EN
_CTL1__RTC_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 878 MASTER LE IN 264612 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_CTL__ALARM_CTL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 879 MASTER LE IN 264614 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_EN_CTL1__ALARM_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 880 MASTER LE IN 264623 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA2__RTC_ALARM_DATA2_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 881 MASTER LE IN 264621 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA3__RTC_ALARM_DATA3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 882 MASTER LE IN 264665 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_timer_rif/u_TIM
ER_DATA2__TIMER_DATA2_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 883 MASTER LE IN 264645 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA0__RTC_ALARM_DATA0_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 884 MASTER LE IN 264531 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE3__RTC_STORGE3_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 885 MASTER LE IN 264635 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA1__RTC_ALARM_DATA1_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 886 MASTER LE IN 264555 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE0__RTC_STORGE0_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 887 MASTER LE IN 264636 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA1__RTC_ALARM_DATA1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 888 MASTER LE IN 264556 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE0__RTC_STORGE0_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 889 MASTER LE IN 264760 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SPARE3__RFU_reg/do
ut_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 890 MASTER LE IN 264551 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ORGE0__RTC_STORGE0_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 891 MASTER LE IN 263962 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\clk_32k_en_sync_reg
[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 892 MASTER LE IN 264013 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 893 MASTER LE IN 264009 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 894 MASTER LE IN 264008 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 895 MASTER LE IN 264010 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 896 MASTER LE IN 264007 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 897 MASTER LE IN 264006 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 898 MASTER LE IN 264012 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 899 MASTER LE IN 264011 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 900 MASTER LE IN 264005 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[8]
(M31_1P5V6T_SFFRBQX1)
 Chain[6] 901 MASTER LE IN 264004 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 902 MASTER LE IN 264105 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 903 MASTER LE IN 264113 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 904 MASTER LE IN 265164 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC1__CAL_FREQ_RTC_DEFAULT_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[6] 905 MASTER LE IN 264502 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC4__COINCELL_GOOD_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 906 MASTER LE IN 264501 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC4__LFRC_DRIFT_DET_EN_COIN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 907 MASTER LE IN 264108 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 908 MASTER LE IN 264103 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 909 MASTER LE IN 264124 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[23] (M31_1P5V6T_SFFRBQX1)
Chain[6] 910 MASTER LE IN 264119 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[18] (M31_1P5V6T_SFFRBQX1)
Chain[6] 911 MASTER LE IN 264633 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA1__RTC_ALARM_DATA1_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 912 MASTER LE IN 264634 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA1__RTC_ALARM_DATA1_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 913 MASTER LE IN 264618 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA3__RTC_ALARM_DATA3_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 914 MASTER LE IN 264617 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA3__RTC_ALARM_DATA3_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 915 MASTER LE IN 264632 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA1__RTC_ALARM_DATA1_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 916 MASTER LE IN 264132 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[31] (M31_1P5V6T_SFFRBQX1)
Chain[6] 917 MASTER LE IN 264431 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[5] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 918 MASTER LE IN 264432 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[6] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 919 MASTER LE IN 264449 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[23] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 920 MASTER LE IN 264430 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[4] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 921 MASTER LE IN 264111 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 922 MASTER LE IN 264616 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA3__RTC_ALARM_DATA3_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 923 MASTER LE IN 264429 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[3] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 924 MASTER LE IN 265148 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC5__MIN_XO_COUNT_LMT_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX3)
Chain[6] 925 MASTER LE IN 265157 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC5__MIN_XO_COUNT_LMT_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX3)
Chain[6] 926 MASTER LE IN 265163 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC5__MIN_XO_COUNT_LMT_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX3)
Chain[6] 927 MASTER LE IN 264503 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC4__CALRC_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 928 MASTER LE IN 264507 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_EN_CTL__FORCE_SLPCLK_PAD_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 929 MASTER LE IN 264506 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_EN_CTL__FOLLOW_HW_SLPCLK_PAD_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 930 MASTER LE IN 264457 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[31] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 931 MASTER LE IN 264159 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_alarm_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 932 MASTER LE IN 264630 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA2__RTC_ALARM_DATA2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 933 MASTER LE IN 264163 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/alarm_d4_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 934 MASTER LE IN 264461 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\STATUS1__SLP_CLK_SOURCE_rifi_reg[0]
(M31_1P5V6T_SFFSBQX1)
Chain[6] 935 MASTER LE IN 264810 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL1__ADC_CLK_
SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 936 MASTER LE IN 264711 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_PERPH_RESET_CTL3__
FOLLOW_SHUTDOWN2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 937 MASTER LE IN 264806 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL3__SEL_ALT_
RTC_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 938 MASTER LE IN 264732 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST8__TS_ENABLE_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 939 MASTER LE IN 264599 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_ST
ATUS2__RTC_RST_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 940 MASTER LE IN 264161 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/alarm_d2_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 941 MASTER LE IN 264441 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[15] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 942 MASTER LE IN 264525 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TE
ST1__DTEST2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 943 MASTER LE IN 264524 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TE
ST1__DTEST2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 944 MASTER LE IN 264452 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[26] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 945 MASTER LE IN 264444 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[18] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 946 MASTER LE IN 264520 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TE
ST1__DTEST1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 947 MASTER LE IN 264523 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TE
ST1__BYPASSDIV2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 948 MASTER LE IN 264521 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TE
ST1__DIV20CLKSEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 949 MASTER LE IN 264522 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TE
ST1__DIVSEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 950 MASTER LE IN 264564 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TI
ME_ADJ__RTC_TIME_ADJ_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 951 MASTER LE IN 264566 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TI
ME_ADJ__RTC_TIME_ADJ_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 952 MASTER LE IN 264800 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_XO_HALT_CTL__FORCE
_XO_HALT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 953 MASTER LE IN 265161 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_HFRC_CTL__HFRC_OSC
_HW_CTL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 954 MASTER LE IN 264789 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SMPS_GP_STATUS_SEL
__STATUS_REQ_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 955 MASTER LE IN 264798 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_HFRC_CTL__FORCE_HF
RC_OSC_ON_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 956 MASTER LE IN 264801 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_XO_HALT_CTL__FOLLO
W_HW_XO_HALT_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 957 MASTER LE IN 264808 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL2__EN_ALT_S
C_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 958 MASTER LE IN 264718 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST1__DTEST_SEL_r
eg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 959 MASTER LE IN 264788 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SMPS_GP_STATUS_SEL
__STATUS_REQ_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 960 MASTER LE IN 264790 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SMPS_GP_STATUS_SEL
__STATUS_REQ_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 961 MASTER LE IN 264720 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST1__DTEST_SEL_r
eg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 962 MASTER LE IN 264807 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL2__SEL_ALT_
SC_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 963 MASTER LE IN 264791 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SMPS_GP_STATUS_SEL
__STATUS_REQ_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 964 MASTER LE IN 264065 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\clk_98k_en_sync_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 965 MASTER LE IN 264815 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL1__PBS_CLK_
SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 966 MASTER LE IN 264795 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK32K_HALT_CTL__H
OLD_CLK32K_HALT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 967 MASTER LE IN 264814 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL1__PBS_CLK_
SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 968 MASTER LE IN 264799 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_XO_HALT_CTL__HOLD_
XO_HALT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 969 MASTER LE IN 264794 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK98K_CTL__FORCE_
CLK98K_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 970 MASTER LE IN 264793 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK98K_CTL__FOLLOW
_HW_CLK98K_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 971 MASTER LE IN 264713 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_PERPH_RESET_CTL3__
FOLLOW_WARM_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 972 MASTER LE IN 264802 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL5__CLK_32K_
SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 973 MASTER LE IN 264797 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK32K_HALT_CTL__F
OLLOW_HW_CLK32K_HALT_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 974 MASTER LE IN 265156 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_PMIC_SLEEP_CTL__FO
RCE_AWAKE_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 975 MASTER LE IN 264722 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST2__TESTCLK_SEL
_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 976 MASTER LE IN 264749 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST12__TEST_CLK_E
N_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 977 MASTER LE IN 264796 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK32K_HALT_CTL__F
ORCE_CLK32K_HALT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 978 MASTER LE IN 264183 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\rlib_status1__smpsmx_sel/dout_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 979 MASTER LE IN 264721 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST1__DTEST_SEL_r
eg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 980 MASTER LE IN 264753 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST12__TEST_XO_re
g/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 981 MASTER LE IN 264719 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST1__DTEST_SEL_r
eg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 982 MASTER LE IN 264750 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST12__TEST_CLK_S
EL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 983 MASTER LE IN 264751 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST12__TEST_CLK_S
EL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 984 MASTER LE IN 264699 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_HFRC_TRIM__HFRC_TR
IM_reg/dout_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[6] 985 MASTER LE IN 264703 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_HFRC_TRIM__HFRC_TR
IM_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[6] 986 MASTER LE IN 264701 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_HFRC_TRIM__HFRC_TR
IM_reg/dout_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[6] 987 MASTER LE IN 264724 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST2__CLK_32KHZ_S
EL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 988 MASTER LE IN 264752 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST12__TEST_XO_WA
RM_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 989 MASTER LE IN 264725 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST2__CLK_1KHZ_SE
L_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 990 MASTER LE IN 264700 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_HFRC_TRIM__HFRC_TR
IM_reg/dout_reg[5] (M31_1P5V6T_SFFSBQX1)
Chain[6] 991 MASTER LE IN 264723 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST2__TESTCLK_SEL
_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 992 MASTER LE IN 264726 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST2__SMPS_CLK_SE
L_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 993 MASTER LE IN 264733 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST9__FORCE_PBSCL
K_ENA_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 994 MASTER LE IN 265165 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST9__FOLLOW_ADCC
LK_ENA_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 995 MASTER LE IN 264734 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST9__FOLLOW_PBSC
LK_ENA_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 996 MASTER LE IN 264708 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_LFRC_AON_TRIM__LFR
C_AON_TRIM_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX1)
Chain[6] 997 MASTER LE IN 264707 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_LFRC_AON_TRIM__LFR
C_AON_TRIM_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[6] 998 MASTER LE IN 264706 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_LFRC_AON_TRIM__LFR
C_AON_TRIM_reg/dout_reg[4] (M31_1P5V6T_SFFSBQX1)
Chain[6] 999 MASTER LE IN 265160 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST9__FORCE_ADCCL
K_ENA_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1000 MASTER LE IN 264792 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_PMIC_SLEEP_CTL__FO
LLOW_HW_EN_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1001 MASTER LE IN 264803 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL5__CLK_32K_
SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1002 MASTER LE IN 264714 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_PERPH_RESET_CTL3__
FOLLOW_OTST2_RB_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1003 MASTER LE IN 264805 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL4__EXT32K_D
IV_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1004 MASTER LE IN 264804 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL4__EXT32K_C
LK_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1005 MASTER LE IN 264526 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TE
ST1__DTEST2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1006 MASTER LE IN 264162 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/alarm_d3_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1007 MASTER LE IN 264160 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/alarm_d1_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1008 MASTER LE IN 264622 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA3__RTC_ALARM_DATA3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1009 MASTER LE IN 264615 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA3__RTC_ALARM_DATA3_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1010 MASTER LE IN 264638 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA1__RTC_ALARM_DATA1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1011 MASTER LE IN 264646 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA0__RTC_ALARM_DATA0_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1012 MASTER LE IN 264639 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_alarm_rif/u
_ALARM_DATA0__RTC_ALARM_DATA0_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1013 MASTER LE IN 264434 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[8] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1014 MASTER LE IN 264109 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1015 MASTER LE IN 264003 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1016 MASTER LE IN 264002 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1017 MASTER LE IN 264001 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[12]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1018 MASTER LE IN 264000 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[13]
(M31_1P5V6T_SFFRBQX1)
 Chain[6] 1019 MASTER LE IN 263999 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[14]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1020 MASTER LE IN 263998 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[15]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1021 MASTER LE IN 263997 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[16]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1022 MASTER LE IN 263891 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\hold_xo_mask_b_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1023 MASTER LE IN 263885 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\hold_xo_mask_b_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1024 MASTER LE IN 263883 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/rst_n_sync_pos_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1025 MASTER LE IN 263888 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/rst_n_sync_negpos_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1026 MASTER LE IN 263905 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/xo_halt_holder_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1027 MASTER LE IN 263890 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\xo_halt_holder_rst_n_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1028 MASTER LE IN 263884 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\xo_halt_holder_rst_n_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1029 MASTER LE IN 263942 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_halt/sel1_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1030 MASTER LE IN 263944 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
4] (M31_1P5V6T_SFFRBQX1J)
Chain[6] 1031 MASTER LE IN 264147 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1032 MASTER LE IN 264145 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1033 MASTER LE IN 264458 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[14] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1034 MASTER LE IN 264144 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1035 MASTER LE IN 264142 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1036 MASTER LE IN 264141 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1037 MASTER LE IN 264137 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/u_xo32k_halt_sync/sync_d_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1038 MASTER LE IN 264066 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\clk_98k_en_sync_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1039 MASTER LE IN 264584 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA1__RTC_WDATA1_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1040 MASTER LE IN 264587 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA1__RTC_WDATA1_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1041 MASTER LE IN 264589 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA1__RTC_WDATA1_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1042 MASTER LE IN 264585 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA1__RTC_WDATA1_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1043 MASTER LE IN 264586 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA1__RTC_WDATA1_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1044 MASTER LE IN 264590 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA1__RTC_WDATA1_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1045 MASTER LE IN 264591 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA0__RTC_WDATA0_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1046 MASTER LE IN 264428 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[2] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1047 MASTER LE IN 264427 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[1] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1048 MASTER LE IN 264439 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[13] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1049 MASTER LE IN 264127 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[26] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1050 MASTER LE IN 264436 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[10] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1051 MASTER LE IN 264129 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[28] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1052 MASTER LE IN 264122 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[21] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1053 MASTER LE IN 264121 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[20] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1054 MASTER LE IN 264130 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[29] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1055 MASTER LE IN 264123 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[22] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1056 MASTER LE IN 264131 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[30] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1057 MASTER LE IN 265153 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC1__CAL_FREQ_RTC_DEFAULT_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1058 MASTER LE IN 264120 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[19] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1059 MASTER LE IN 265154 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC1__CAL_FREQ_RTC_DEFAULT_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1060 MASTER LE IN 264118 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[17] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1061 MASTER LE IN 264114 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1062 MASTER LE IN 264106 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1063 MASTER LE IN 264104 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1064 MASTER LE IN 264435 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[9] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1065 MASTER LE IN 264112 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1066 MASTER LE IN 264437 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[11] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1067 MASTER LE IN 264128 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[27] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1068 MASTER LE IN 264440 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[14] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1069 MASTER LE IN 264451 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[25] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1070 MASTER LE IN 264442 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[16] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1071 MASTER LE IN 264448 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[22] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1072 MASTER LE IN 264446 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[20] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1073 MASTER LE IN 264450 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[24] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1074 MASTER LE IN 264445 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[19] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1075 MASTER LE IN 264447 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[21] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1076 MASTER LE IN 264456 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[30] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1077 MASTER LE IN 264453 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[27] (M31_1P5V6T_SFFSRBQX1)
 Chain[6] 1078 MASTER LE IN 264455 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[29] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1079 MASTER LE IN 264454 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[28] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1080 MASTER LE IN 264052 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Div2_reg (M31_1P5V6T_SFFRBQX1J)
Chain[6] 1081 MASTER LE IN 264560 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TI
ME_ADJ__RTC_TIME_ADJ_reg/dout_reg[6] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1082 MASTER LE IN 264728 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST7__FORCE_GP_EN
A_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1083 MASTER LE IN 264731 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST7__FOLLOW_SMPS
_ENA_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1084 MASTER LE IN 264187 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\STATUS2__SMPS_GP_REQ_rifi_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1085 MASTER LE IN 264460 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\STATUS1__SLP_CLK_SOURCE_rifi_reg[2]
(M31_1P5V6T_SFFSBQX1)
Chain[6] 1086 MASTER LE IN 264186 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\STATUS2__SMPS_GP_REQ_rifi_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1087 MASTER LE IN 264812 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL1__GPCLK_SE
L_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1088 MASTER LE IN 264185 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\STATUS2__SMPS_GP_REQ_rifi_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1089 MASTER LE IN 264182 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\rlib_status1__gpmx_sel/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1090 MASTER LE IN 264191 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\STATUS2__SMPS_GP_REQ_rifi_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1091 MASTER LE IN 264190 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\STATUS2__SMPS_GP_REQ_rifi_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1092 MASTER LE IN 265159 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL1__SMPS_CLK
_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1093 MASTER LE IN 264813 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL1__SMPS_CLK
_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1094 MASTER LE IN 264809 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL1__ADC_CLK_
SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1095 MASTER LE IN 264189 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\STATUS2__SMPS_GP_REQ_rifi_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1096 MASTER LE IN 264192 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\STATUS2__SMPS_GP_REQ_rifi_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1097 MASTER LE IN 264139 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1098 MASTER LE IN 264136 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/u_xo32k_halt_sync/sync_d_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1099 MASTER LE IN 264154 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count20_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1100 MASTER LE IN 264157 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count20_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1101 MASTER LE IN 264158 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count20_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1102 MASTER LE IN 264156 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count20_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1103 MASTER LE IN 264155 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count20_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1104 MASTER LE IN 264143 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1105 MASTER LE IN 264138 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/rTwo_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1106 MASTER LE IN 264153 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/rNineteen_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1107 MASTER LE IN 264047 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_mod_dft_logic/tp0_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1108 MASTER LE IN 264048 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_mod_dft_logic/tp_xor0_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1109 MASTER LE IN 264046 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_mod_dft_logic/tp1_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1110 MASTER LE IN 264702 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_HFRC_TRIM__HFRC_TR
IM_reg/dout_reg[3] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1111 MASTER LE IN 264704 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_HFRC_TRIM__HFRC_TR
IM_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1112 MASTER LE IN 264705 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_HFRC_TRIM__HFRC_TR
IM_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1113 MASTER LE IN 264459 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\STATUS1__SLP_CLK_SOURCE_rifi_reg[1]
(M31_1P5V6T_SFFSBQX1)
Chain[6] 1114 MASTER LE IN 264729 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST7__FOLLOW_GP_E
NA_reg/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1115 MASTER LE IN 264730 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_TEST7__FORCE_SMPS_
ENA_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1116 MASTER LE IN 264787 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_SMPS_GP_STATUS_SEL
__STATUS_REQ_SEL_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1117 MASTER LE IN 264188 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\STATUS2__SMPS_GP_REQ_rifi_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1118 MASTER LE IN 264811 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\u_clk_dist_rif/u_CLK_CTL1__GPCLK_SE
L_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1119 MASTER LE IN 264565 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TI
ME_ADJ__RTC_TIME_ADJ_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1120 MASTER LE IN 264563 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TI
ME_ADJ__RTC_TIME_ADJ_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1121 MASTER LE IN 264561 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TI
ME_ADJ__RTC_TIME_ADJ_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1122 MASTER LE IN 264562 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_TI
ME_ADJ__RTC_TIME_ADJ_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1123 MASTER LE IN 264438 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[12] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1124 MASTER LE IN 264126 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[25] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1125 MASTER LE IN 264433 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/rtc_count_reg[7] (M31_1P5V6T_SFFSRBQX1)
Chain[6] 1126 MASTER LE IN 264116 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1127 MASTER LE IN 264107 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1128 MASTER LE IN 264115 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1129 MASTER LE IN 264110 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1130 MASTER LE IN 264102 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_rlib_status1__ts_
rifi/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1131 MASTER LE IN 265158 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC1__CAL_FREQ_RTC_DEFAULT_reg/dout_reg[2] (M31_1P5V6T_SFFSBQX2)
Chain[6] 1132 MASTER LE IN 263981 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\cnt_1k_ena_sync_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1133 MASTER LE IN 263996 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[17]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1134 MASTER LE IN 263980 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\cnt_1k_ena_sync_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1135 MASTER LE IN 263995 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[18]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1136 MASTER LE IN 263994 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[19]
(M31_1P5V6T_SFFRBQX1)
 Chain[6] 1137 MASTER LE IN 263993 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[20]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1138 MASTER LE IN 263992 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[21]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1139 MASTER LE IN 263991 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[22]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1140 MASTER LE IN 263990 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[23]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1141 MASTER LE IN 263989 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[24]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1142 MASTER LE IN 263906 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_0_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1143 MASTER LE IN 263893 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_0_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1144 MASTER LE IN 263892 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_0_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1145 MASTER LE IN 263899 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_1_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1146 MASTER LE IN 263895 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_0_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1147 MASTER LE IN 263894 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_0_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1148 MASTER LE IN 263900 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_1_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1149 MASTER LE IN 263902 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_1_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1150 MASTER LE IN 263901 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_1_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1151 MASTER LE IN 263903 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1152 MASTER LE IN 263904 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1153 MASTER LE IN 263896 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_0_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1154 MASTER LE IN 263897 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_0_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1155 MASTER LE IN 263889 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/tcxo_clk_div2_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1156 MASTER LE IN 263898 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_1_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1157 MASTER LE IN 263886 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_0_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1158 MASTER LE IN 263887 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_clk_32k_h
alt_detector/\shift_1_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1159 MASTER LE IN 263941 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_halt/sel0_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1160 MASTER LE IN 263950 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1161 MASTER LE IN 263949 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1162 MASTER LE IN 263956 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1163 MASTER LE IN 263957 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1164 MASTER LE IN 263959 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1165 MASTER LE IN 263969 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1166 MASTER LE IN 263970 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1167 MASTER LE IN 263971 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1168 MASTER LE IN 263775 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_gp_clk/sel1_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1169 MASTER LE IN 264196 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/divclks_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1170 MASTER LE IN 264195 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/divclks_en_cg_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1171 MASTER LE IN 264197 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\rlib_status1__idss_tout/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1172 MASTER LE IN 264140 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1173 MASTER LE IN 264152 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1174 MASTER LE IN 264146 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1175 MASTER LE IN 264150 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1176 MASTER LE IN 264148 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1177 MASTER LE IN 264151 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1178 MASTER LE IN 264149 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_clks_dig_rtc_se
c/u_clks_dig_khzdivider/Count16384_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1179 MASTER LE IN 263974 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1180 MASTER LE IN 263976 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1181 MASTER LE IN 263977 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1182 MASTER LE IN 263966 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1183 MASTER LE IN 263978 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1184 MASTER LE IN 263967 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1185 MASTER LE IN 263973 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1186 MASTER LE IN 263943 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
14] (M31_1P5V6T_SFFRBQX1J)
Chain[6] 1187 MASTER LE IN 263960 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1188 MASTER LE IN 263945 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1189 MASTER LE IN 263946 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1190 MASTER LE IN 263948 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1191 MASTER LE IN 263947 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1192 MASTER LE IN 263958 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1193 MASTER LE IN 263954 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1194 MASTER LE IN 263953 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1195 MASTER LE IN 263952 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[7] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 1196 MASTER LE IN 263951 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1197 MASTER LE IN 263955 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\en_32k_haltoutp_dly
_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1198 MASTER LE IN 263930 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_extcalrcalt_32k/sel1_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1199 MASTER LE IN 263929 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_extcalrcalt_32k/sel0_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1200 MASTER LE IN 263968 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1201 MASTER LE IN 263972 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1202 MASTER LE IN 263979 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_32768div_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1203 MASTER LE IN 263774 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_gp_clk/sel0_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1204 MASTER LE IN 263873 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/clk1
9m2_en_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1205 MASTER LE IN 263860 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\hf_halt_detector_en
a_hfrcdom_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1206 MASTER LE IN 263877 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\gp_4m8_count_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1207 MASTER LE IN 263803 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/xo_halt_holder_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1208 MASTER LE IN 264578 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA2__RTC_WDATA2_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1209 MASTER LE IN 264570 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA3__RTC_WDATA3_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1210 MASTER LE IN 264598 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA0__RTC_WDATA0_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1211 MASTER LE IN 264597 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA0__RTC_WDATA0_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1212 MASTER LE IN 263850 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\gp_clk19m2_en_sync_
reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1213 MASTER LE IN 263851 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\gp_clk19m2_en_sync_
reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1214 MASTER LE IN 264588 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA1__RTC_WDATA1_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1215 MASTER LE IN 264583 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA1__RTC_WDATA1_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1216 MASTER LE IN 264595 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA0__RTC_WDATA0_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1217 MASTER LE IN 264596 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA0__RTC_WDATA0_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1218 MASTER LE IN 264567 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA3__RTC_WDATA3_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1219 MASTER LE IN 264593 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA0__RTC_WDATA0_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1220 MASTER LE IN 264592 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA0__RTC_WDATA0_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1221 MASTER LE IN 264568 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA3__RTC_WDATA3_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1222 MASTER LE IN 264594 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA0__RTC_WDATA0_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1223 MASTER LE IN 263876 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\smps_4m8_count_reg[
1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1224 MASTER LE IN 263859 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\smps_4m8_count_reg[
0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1225 MASTER LE IN 263918 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_ext_calrc_32k/sel1_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1226 MASTER LE IN 263800 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/\shift_1_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1227 MASTER LE IN 263791 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/\xo_halt_holder_rst_n_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1228 MASTER LE IN 263796 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/\xo_halt_holder_rst_n_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1229 MASTER LE IN 264573 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA3__RTC_WDATA3_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1230 MASTER LE IN 264571 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA3__RTC_WDATA3_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1231 MASTER LE IN 264572 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA3__RTC_WDATA3_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1232 MASTER LE IN 264576 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA2__RTC_WDATA2_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1233 MASTER LE IN 263868 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1234 MASTER LE IN 264575 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA2__RTC_WDATA2_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1235 MASTER LE IN 264580 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA2__RTC_WDATA2_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1236 MASTER LE IN 264579 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA2__RTC_WDATA2_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1237 MASTER LE IN 264582 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA2__RTC_WDATA2_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1238 MASTER LE IN 264577 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA2__RTC_WDATA2_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1239 MASTER LE IN 263799 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/\shift_0_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1240 MASTER LE IN 263802 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/\shift_1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1241 MASTER LE IN 263862 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1242 MASTER LE IN 263849 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1243 MASTER LE IN 263853 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\gp_4m8_count_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1244 MASTER LE IN 264051 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_lfrc_aon_98k_cl
k_div2_reg (M31_1P5V6T_SFFRBQX1J)
Chain[6] 1245 MASTER LE IN 264581 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA2__RTC_WDATA2_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1246 MASTER LE IN 264574 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA3__RTC_WDATA3_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1247 MASTER LE IN 264569 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_rtc_perph_u_rtc_rw_rif/u_WD
ATA3__RTC_WDATA3_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1248 MASTER LE IN 264133 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_clks_dig_sle
ep_clk/sleep_clk1_en_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1249 MASTER LE IN 265169 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/\include_slpclk_perph_u_slpclk_rif/u
_CAL_RC5__MAX_XO_COUNT_LMT_reg/dout_reg[1] (M31_1P5V6T_SFFSBQX2)
Chain[6] 1250 MASTER LE IN 263975 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/clk_1k_en_sync_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1251 MASTER LE IN 264059 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_calrc1p0_lfrc_e
n_sync_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1252 MASTER LE IN 263852 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\gp_clk19m2_en_sync_
reg[1] (M31_1P5V6T_SFFRBQX2J)
Chain[6] 1253 MASTER LE IN 263985 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[28]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1254 MASTER LE IN 263984 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[29]
(M31_1P5V6T_SFFRBQX1)
 Chain[6] 1255 MASTER LE IN 263986 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[27]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1256 MASTER LE IN 263988 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[25]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1257 MASTER LE IN 263987 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[26]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1258 MASTER LE IN 263878 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\smps_clk19m2_en_syn
c_reg[26] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1259 MASTER LE IN 263856 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\smps_clk19m2_en_syn
c_reg[28] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1260 MASTER LE IN 263857 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\smps_clk19m2_en_syn
c_reg[27] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1261 MASTER LE IN 263858 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\smps_clk19m2_en_syn
c_reg[25] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1262 MASTER LE IN 263794 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/rst_n_sync_negpos_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1263 MASTER LE IN 263790 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/rst_n_sync_pos_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1264 MASTER LE IN 263792 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/\shift_0_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1265 MASTER LE IN 263798 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/\shift_0_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1266 MASTER LE IN 263797 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/\shift_0_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1267 MASTER LE IN 263848 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1268 MASTER LE IN 263867 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1269 MASTER LE IN 263861 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\hf_halt_detector_en
a_hfrcdom_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1270 MASTER LE IN 263842 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1271 MASTER LE IN 263864 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1272 MASTER LE IN 263847 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1273 MASTER LE IN 263795 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/tcxo_clk_div2_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1274 MASTER LE IN 263846 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1275 MASTER LE IN 263845 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1276 MASTER LE IN 263841 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1277 MASTER LE IN 263843 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1278 MASTER LE IN 263874 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/clk1
9m2_en_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1279 MASTER LE IN 263844 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1280 MASTER LE IN 263786 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_smps_clk/sel0_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1281 MASTER LE IN 263875 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/clk1
9m2_en_sync_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1282 MASTER LE IN 263838 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/sel0_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1283 MASTER LE IN 263839 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_pbs_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/sel1_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1284 MASTER LE IN 263815 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/u_clks_dig_gfreemux2_xorc_clk/sel1_0_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1285 MASTER LE IN 263964 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\clk_32k_en_sync_reg
[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1286 MASTER LE IN 263963 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\clk_32k_en_sync_reg
[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1287 MASTER LE IN 263965 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\clk_32k_en_sync_reg
[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1288 MASTER LE IN 263827 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/sel1_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1289 MASTER LE IN 263826 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\u_adc_xorc_sel/u_cl
ks_dig_gfreemux2_xorc_clk/sel0_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1290 MASTER LE IN 263814 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\include_buck_cmn_xo
rc_sel_u_bclkgen_xorc_sel/u_clks_dig_gfreemux2_xorc_clk/sel0_0_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1291 MASTER LE IN 263787 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_gfreemux2
_smps_clk/sel1_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1292 MASTER LE IN 263854 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/xo_int_en_cg_sync_re
g (M31_1P5V6T_SFFRBQX1)
Chain[6] 1293 MASTER LE IN 263866 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1294 MASTER LE IN 263865 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1295 MASTER LE IN 263863 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/\idss_tout_hfrc_dly_
reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1296 MASTER LE IN 263801 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/\shift_1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1297 MASTER LE IN 263793 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_dvdd/u_clks_dig_xo_halt_d
etector/\shift_1_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1298 MASTER LE IN 263917 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/u_clks_dig_gfreemux2
_ext_calrc_32k/sel0_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1299 MASTER LE IN 263983 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[30]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1300 MASTER LE IN 263982 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\count_1k_reg[31]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1301 MASTER LE IN 264018 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[27]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1302 MASTER LE IN 264040 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1303 MASTER LE IN 264045 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1304 MASTER LE IN 264028 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[17]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1305 MASTER LE IN 264020 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[25]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1306 MASTER LE IN 264029 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[16]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1307 MASTER LE IN 264043 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1308 MASTER LE IN 264027 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[18]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1309 MASTER LE IN 264025 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[20]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1310 MASTER LE IN 264026 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[19]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1311 MASTER LE IN 264035 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1312 MASTER LE IN 264034 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1313 MASTER LE IN 264022 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[23]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1314 MASTER LE IN 264042 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1315 MASTER LE IN 264044 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1316 MASTER LE IN 264021 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[24]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1317 MASTER LE IN 264038 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1318 MASTER LE IN 264039 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1319 MASTER LE IN 264041 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1320 MASTER LE IN 264014 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[31]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1321 MASTER LE IN 264033 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[12]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1322 MASTER LE IN 264031 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[14]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1323 MASTER LE IN 264023 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[22]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1324 MASTER LE IN 264019 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[26]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1325 MASTER LE IN 264015 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[30]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1326 MASTER LE IN 264017 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[28]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1327 MASTER LE IN 264016 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[29]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1328 MASTER LE IN 264030 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[15]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1329 MASTER LE IN 264032 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[13]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1330 MASTER LE IN 264037 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1331 MASTER LE IN 264036 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1332 MASTER LE IN 264024 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/u_clks_dig_xvdd/\gc_tstamp_reg[21]
(M31_1P5V6T_SFFRBQX1)
 Chain[6] 1333 MASTER LE IN 263594 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xo19m2_en_fr_calrc_sync1_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1334 MASTER LE IN 263759 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\calrc_fsm_state_reg[2] (M31_1P5V6T_SFFRBQX3)
Chain[6] 1335 MASTER LE IN 263750 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\rc_cnt_reg[7] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1336 MASTER LE IN 263558 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\rc_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1337 MASTER LE IN 263557 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\rc_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1338 MASTER LE IN 263715 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[19] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1339 MASTER LE IN 263718 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[16] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1340 MASTER LE IN 263720 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1341 MASTER LE IN 263568 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1342 MASTER LE IN 263571 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1343 MASTER LE IN 263569 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1344 MASTER LE IN 263564 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1345 MASTER LE IN 263565 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1346 MASTER LE IN 263697 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1347 MASTER LE IN 263694 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1348 MASTER LE IN 263691 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1349 MASTER LE IN 263685 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1350 MASTER LE IN 263688 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1351 MASTER LE IN 263682 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1352 MASTER LE IN 263680 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[16] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1353 MASTER LE IN 263738 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[17] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1354 MASTER LE IN 263678 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[19] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1355 MASTER LE IN 263721 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1356 MASTER LE IN 263714 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_increasing_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1357 MASTER LE IN 263716 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[18] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1358 MASTER LE IN 263575 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/first_cal_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1359 MASTER LE IN 263739 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/zeroth_cal_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1360 MASTER LE IN 263576 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/rc_drifting_fast_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1361 MASTER LE IN 263735 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xo19m2_count_inrange_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 1362 MASTER LE IN 263556 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\rc_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1363 MASTER LE IN 263749 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\rc_cnt_reg[8] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1364 MASTER LE IN 263593 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xo19m2_en_fr_calrc_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1365 MASTER LE IN 263761 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\calrc_fsm_state_reg[1] (M31_1P5V6T_SFFRBQX3)
Chain[6] 1366 MASTER LE IN 263760 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\calrc_fsm_state_reg[0] (M31_1P5V6T_SFFRBQX3)
Chain[6] 1367 MASTER LE IN 263752 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\rc_cnt_reg[6] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1368 MASTER LE IN 263746 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\rc_cnt_reg[5] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1369 MASTER LE IN 263605 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_en_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1370 MASTER LE IN 263559 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\rc_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1371 MASTER LE IN 263751 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\rc_cnt_reg[2] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1372 MASTER LE IN 263600 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_reset_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1373 MASTER LE IN 263717 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[17] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1374 MASTER LE IN 263719 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1375 MASTER LE IN 263722 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1376 MASTER LE IN 263736 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[18] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1377 MASTER LE IN 263566 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1378 MASTER LE IN 263567 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1379 MASTER LE IN 263650 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1380 MASTER LE IN 263654 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1381 MASTER LE IN 263652 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1382 MASTER LE IN 263684 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1383 MASTER LE IN 263614 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1384 MASTER LE IN 263681 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1385 MASTER LE IN 263679 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[16] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1386 MASTER LE IN 263612 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[16] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1387 MASTER LE IN 263613 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1388 MASTER LE IN 263611 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[17] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1389 MASTER LE IN 263615 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1390 MASTER LE IN 263616 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1391 MASTER LE IN 263657 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[5] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 1392 MASTER LE IN 263661 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1393 MASTER LE IN 263663 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1394 MASTER LE IN 263659 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1395 MASTER LE IN 263665 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1396 MASTER LE IN 263667 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1397 MASTER LE IN 263610 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[18] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1398 MASTER LE IN 263572 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1399 MASTER LE IN 263763 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[18] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1400 MASTER LE IN 263662 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1401 MASTER LE IN 263737 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[17] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1402 MASTER LE IN 263602 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_reset_xodom_pe_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1403 MASTER LE IN 263601 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_reset_met_pe_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1404 MASTER LE IN 263660 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1405 MASTER LE IN 263607 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_en_xodom_pe_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1406 MASTER LE IN 263606 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_en_met_pe_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1407 MASTER LE IN 263658 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1408 MASTER LE IN 263656 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1409 MASTER LE IN 263570 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1410 MASTER LE IN 263563 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1411 MASTER LE IN 263705 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1412 MASTER LE IN 263703 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1413 MASTER LE IN 263710 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[22] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1414 MASTER LE IN 263702 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[23] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1415 MASTER LE IN 263698 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[25] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1416 MASTER LE IN 263706 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[24] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1417 MASTER LE IN 263695 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[26] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1418 MASTER LE IN 263521 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_freq_xodiv586_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1419 MASTER LE IN 263692 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[27] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1420 MASTER LE IN 263689 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[28] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1421 MASTER LE IN 263686 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[29] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1422 MASTER LE IN 263683 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[30] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1423 MASTER LE IN 263756 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[31] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1424 MASTER LE IN 263757 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[32] (M31_1P5V6T_SFFRBQX3)
Chain[6] 1425 MASTER LE IN 263700 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[21] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1426 MASTER LE IN 263701 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1427 MASTER LE IN 263699 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[17] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1428 MASTER LE IN 263561 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_capture_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1429 MASTER LE IN 263562 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/extrap_hold_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1430 MASTER LE IN 263581 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/restart_cal_rcdom_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1431 MASTER LE IN 263560 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\i_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1432 MASTER LE IN 263580 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/restart_cal_demet_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1433 MASTER LE IN 263579 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/restart_cal_met_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1434 MASTER LE IN 263582 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\i_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1435 MASTER LE IN 263585 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\i_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1436 MASTER LE IN 263708 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[20] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1437 MASTER LE IN 263586 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\i_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1438 MASTER LE IN 263588 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\i_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1439 MASTER LE IN 263587 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\i_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1440 MASTER LE IN 263578 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/slp_clk_xo_sel_demet_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1441 MASTER LE IN 263597 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/comp_out_reg_xodom_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1442 MASTER LE IN 263599 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/slp_clk_xo_sel_dly_xodom1_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1443 MASTER LE IN 263740 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/toggle_xo_init_cnt_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 1444 MASTER LE IN 263728 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xo_cnt_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1445 MASTER LE IN 263727 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xo_cnt_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1446 MASTER LE IN 263734 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xo_cnt_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1447 MASTER LE IN 263507 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xo_clkdiv586_reg (M31_1P5V6T_SFFRBQX1J)
Chain[6] 1448 MASTER LE IN 263596 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/comp_out_reg_demet_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1449 MASTER LE IN 263514 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\slp_clk_xo_sel_demet_dly_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1450 MASTER LE IN 263589 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\i_reg[8] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 1451 MASTER LE IN 263584 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\i_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1452 MASTER LE IN 263591 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\i_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1453 MASTER LE IN 263592 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\i_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1454 MASTER LE IN 263577 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/slp_clk_xo_sel_met_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1455 MASTER LE IN 263723 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/rc_clk_new_xodom_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1456 MASTER LE IN 263555 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/slp_gen_clk_demet_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1457 MASTER LE IN 263554 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/slp_gen_clk_met_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1458 MASTER LE IN 263509 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\slp_clk_xo_sel_demet_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1459 MASTER LE IN 263517 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\slp_clk_xo_sel_demet_dly_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1460 MASTER LE IN 263515 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\slp_clk_xo_sel_demet_dly_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1461 MASTER LE IN 263508 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\slp_clk_xo_sel_demet_dly_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1462 MASTER LE IN 263725 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xo_cnt_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1463 MASTER LE IN 263733 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xo_cnt_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1464 MASTER LE IN 263731 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xo_cnt_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1465 MASTER LE IN 263523 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/calrc_rstn_sync2_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1466 MASTER LE IN 263522 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/calrc_rstn_sync1_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1467 MASTER LE IN 263732 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xo_cnt_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1468 MASTER LE IN 263595 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/comp_out_reg_met_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1469 MASTER LE IN 263516 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\slp_clk_xo_sel_demet_dly_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1470 MASTER LE IN 263513 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\slp_clk_xo_sel_demet_dly_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1471 MASTER LE IN 263511 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\slp_clk_xo_sel_demet_dly_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1472 MASTER LE IN 263512 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\slp_clk_xo_sel_demet_dly_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1473 MASTER LE IN 263762 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/rc_clk_inv_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1474 MASTER LE IN 263598 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/slp_gen_clk_xodom_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1475 MASTER LE IN 263510 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\slp_clk_xo_sel_demet_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1476 MASTER LE IN 263724 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/rc_clk_new_xodom_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1477 MASTER LE IN 263590 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\i_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1478 MASTER LE IN 263583 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\i_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1479 MASTER LE IN 263704 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[19] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1480 MASTER LE IN 263712 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[18] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1481 MASTER LE IN 263707 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[16] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1482 MASTER LE IN 263711 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1483 MASTER LE IN 263709 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1484 MASTER LE IN 263648 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/xocntrc_capture_pre_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1485 MASTER LE IN 263573 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1486 MASTER LE IN 263668 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1487 MASTER LE IN 263677 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[19] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1488 MASTER LE IN 263664 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1489 MASTER LE IN 263666 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k1_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1490 MASTER LE IN 263687 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1491 MASTER LE IN 263690 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1492 MASTER LE IN 263693 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1493 MASTER LE IN 263696 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1494 MASTER LE IN 263649 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1495 MASTER LE IN 263655 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1496 MASTER LE IN 263617 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1497 MASTER LE IN 263653 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1498 MASTER LE IN 263574 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\k_extrap_dec_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1499 MASTER LE IN 263651 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1500 MASTER LE IN 263618 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1501 MASTER LE IN 263619 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1502 MASTER LE IN 263474 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/u_clks_dig_gfreemux2_calrc_32k/sel1_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1503 MASTER LE IN 263473 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/u_clks_dig_gfreemux2_calrc_32k/sel0_0_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1504 MASTER LE IN 263534 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[22] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1505 MASTER LE IN 263535 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[21] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1506 MASTER LE IN 263536 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[20] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1507 MASTER LE IN 263538 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[18] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1508 MASTER LE IN 263539 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[17] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1509 MASTER LE IN 263543 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[13] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 1510 MASTER LE IN 263544 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1511 MASTER LE IN 263546 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1512 MASTER LE IN 263552 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1513 MASTER LE IN 263626 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1514 MASTER LE IN 263608 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1515 MASTER LE IN 263609 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1516 MASTER LE IN 263742 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[1] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1517 MASTER LE IN 263625 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1518 MASTER LE IN 263620 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1519 MASTER LE IN 263747 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[2] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1520 MASTER LE IN 263553 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1521 MASTER LE IN 263672 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1522 MASTER LE IN 263675 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1523 MASTER LE IN 263674 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1524 MASTER LE IN 263743 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[0] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1525 MASTER LE IN 263755 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1526 MASTER LE IN 263745 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[1] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1527 MASTER LE IN 263673 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1528 MASTER LE IN 263670 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1529 MASTER LE IN 263671 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1530 MASTER LE IN 263713 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1531 MASTER LE IN 263676 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1532 MASTER LE IN 263669 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_delta_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1533 MASTER LE IN 263748 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/slp_clk_xo_sel_dly_xodom_reg (M31_1P5V6T_SFFRBQX2)
Chain[6] 1534 MASTER LE IN 263520 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_freq_xodiv586_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1535 MASTER LE IN 263518 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_freq_xodiv586_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1536 MASTER LE IN 263519 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\cal_freq_xodiv586_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1537 MASTER LE IN 263729 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xo_cnt_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1538 MASTER LE IN 263726 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xo_cnt_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1539 MASTER LE IN 263528 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[28] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1540 MASTER LE IN 263730 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xo_cnt_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1541 MASTER LE IN 263527 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[29] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1542 MASTER LE IN 263524 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[32] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1543 MASTER LE NI 263744 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/comp_out_posedge_reg (M31_1P5V6T_SFFRBQBX4J)
Chain[6] 1544 MASTER LE IN 263758 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[33] (M31_1P5V6T_SFFRBQBX1)
Chain[6] 1545 MASTER LE IN 263525 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[31] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1546 MASTER LE IN 263526 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[30] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1547 MASTER LE IN 263529 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[27] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1548 MASTER LE IN 263530 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[26] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1549 MASTER LE IN 263532 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[24] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1550 MASTER LE IN 263531 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[25] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1551 MASTER LE IN 263533 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[23] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1552 MASTER LE IN 263537 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[19] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1553 MASTER LE IN 263540 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[16] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1554 MASTER LE IN 263541 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[15] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1555 MASTER LE IN 263542 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1556 MASTER LE IN 263545 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1557 MASTER LE IN 263547 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1558 MASTER LE IN 263548 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1559 MASTER LE IN 263549 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1560 MASTER LE IN 263550 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1561 MASTER LE IN 263551 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\jplusp_posedge_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1562 MASTER LE IN 263621 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1563 MASTER LE IN 263623 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1564 MASTER LE IN 263622 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1565 MASTER LE IN 263624 + GPIO_07
I_DCORE/u_clks_rmod/u_clks_rdig/u_clks_dig_mod/include_slpclk_perph_u_clks_dig_calr
c/\xocntrc_posedge_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1566 MASTER LE IN 266027 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/TEST6_FTS_REFDAC_VREF_0_array_u_TEST6_FTS_RE
FDAC_VREF_0__OPEN_LOOP_TEST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
DSLAVE LS IN 256141 - GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/LOCKUP
(M31_1P5V6T_LOWLATCHX2)
Chain[6] 1567 MASTER LE IN 266018 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/u_TEST1__DTEST4_SEL_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1568 MASTER LE IN 266020 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/u_TEST1__DTEST4_SEL_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1569 MASTER LE IN 266019 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/u_TEST1__DTEST4_SEL_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1570 MASTER LE IN 266013 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/u_PERPH_RESET_CTL4__LOCAL_SOFT_RESET_reg/dou
t_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1571 MASTER LE IN 266012 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/u_PERPH_RESET_CTL2__FOLLOW_GLOBAL_SOFT_RB_re
g/dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1572 MASTER LE IN 266031 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/FTS_SPARE_CTL_0_array_u_FTS_SPARE_CTL_0__FTS
_SPARE_REG_BITS_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1573 MASTER LE IN 266035 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/HFS_SPARE_CTL_0_array_u_HFS_SPARE_CTL_0__HFS
_SPARE_REG_BITS_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1574 MASTER LE IN 266000 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/rlib_reg_buf_trim_out/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1575 MASTER LE IN 266005 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/PROCESS_RC_TRIM_0_array_u_PROCESS_RC_TRIM_0_
_PROCESS_RC_TRIM_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1576 MASTER LE IN 266041 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/HFS_REFDAC_VREF_TRIM_0_array_u_HFS_REFDAC_VR
EF_TRIM_0__HFS_REFDAC_VREF_TRIM_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1577 MASTER LE IN 266011 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/FTS_REFDAC_VREF_TRIM_0_array_u_FTS_REFDAC_VR
EF_TRIM_0__FTS_REFDAC_VREF_TRIM_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1578 MASTER LE IN 266015 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_WARM_RB_reg/dout_
reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1579 MASTER LE IN 266016 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN1_RB_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1580 MASTER LE IN 266033 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/HFS_SPARE_CTL_0_array_u_HFS_SPARE_CTL_0__HFS
_SPARE_REG_BITS_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1581 MASTER LE IN 266014 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_OTST2_RB_reg/dout
_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1582 MASTER LE IN 266017 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/u_PERPH_RESET_CTL3__FOLLOW_SHUTDOWN2_RB_reg/
dout_reg[0] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1583 MASTER LE IN 266030 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/FTS_SPARE_CTL_0_array_u_FTS_SPARE_CTL_0__FTS
_SPARE_REG_BITS_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1584 MASTER LE IN 266028 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/FTS_SPARE_CTL_0_array_u_FTS_SPARE_CTL_0__FTS
_SPARE_REG_BITS_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1585 MASTER LE IN 266003 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/PROCESS_RC_TRIM_0_array_u_PROCESS_RC_TRIM_0_
_PROCESS_RC_TRIM_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1586 MASTER LE IN 266007 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/FTS_REFDAC_VREF_TRIM_0_array_u_FTS_REFDAC_VR
EF_TRIM_0__FTS_REFDAC_VREF_TRIM_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1587 MASTER LE IN 266004 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/PROCESS_RC_TRIM_0_array_u_PROCESS_RC_TRIM_0_
_PROCESS_RC_TRIM_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1588 MASTER LE IN 266008 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/FTS_REFDAC_VREF_TRIM_0_array_u_FTS_REFDAC_VR
EF_TRIM_0__FTS_REFDAC_VREF_TRIM_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1589 MASTER LE IN 266010 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/FTS_REFDAC_VREF_TRIM_0_array_u_FTS_REFDAC_VR
EF_TRIM_0__FTS_REFDAC_VREF_TRIM_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1590 MASTER LE IN 266029 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/FTS_SPARE_CTL_0_array_u_FTS_SPARE_CTL_0__FTS
_SPARE_REG_BITS_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1591 MASTER LE IN 266009 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/FTS_REFDAC_VREF_TRIM_0_array_u_FTS_REFDAC_VR
EF_TRIM_0__FTS_REFDAC_VREF_TRIM_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1592 MASTER LE IN 266006 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/FTS_REFDAC_VREF_TRIM_0_array_u_FTS_REFDAC_VR
EF_TRIM_0__FTS_REFDAC_VREF_TRIM_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1593 MASTER LE IN 266025 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/TEST3_FTS_ATEST_0_array_u_TEST3_FTS_ATEST_0_
_FTS_ATEST3_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1594 MASTER LE IN 266023 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/TEST3_FTS_ATEST_0_array_u_TEST3_FTS_ATEST_0_
_FTS_ATEST4_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1595 MASTER LE IN 266043 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/TEST2_HFS_ATEST_0_array_u_TEST2_HFS_ATEST_0_
_HFS_ATEST3_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1596 MASTER LE IN 266021 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/TEST2_HFS_ATEST_0_array_u_TEST2_HFS_ATEST_0_
_HFS_ATEST4_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1597 MASTER LE IN 266024 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/TEST3_FTS_ATEST_0_array_u_TEST3_FTS_ATEST_0_
_FTS_ATEST4_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1598 MASTER LE IN 266026 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/TEST3_FTS_ATEST_0_array_u_TEST3_FTS_ATEST_0_
_FTS_ATEST3_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1599 MASTER LE IN 266022 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/TEST2_HFS_ATEST_0_array_u_TEST2_HFS_ATEST_0_
_HFS_ATEST3_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1600 MASTER LE IN 266045 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/HFS_REFDAC_VREF_TRIM_0_array_u_HFS_REFDAC_VR
EF_TRIM_0__HFS_REFDAC_VREF_TRIM_reg/dout_reg[5] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1601 MASTER LE IN 266038 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/HFS_REFDAC_VREF_TRIM_0_array_u_HFS_REFDAC_VR
EF_TRIM_0__HFS_REFDAC_VREF_TRIM_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX3)
Chain[6] 1602 MASTER LE IN 266001 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/PROCESS_RC_TRIM_0_array_u_PROCESS_RC_TRIM_0_
_PROCESS_RC_TRIM_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1603 MASTER LE IN 266002 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/PROCESS_RC_TRIM_0_array_u_PROCESS_RC_TRIM_0_
_PROCESS_RC_TRIM_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1604 MASTER LE IN 266042 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/HFS_REFDAC_VREF_TRIM_0_array_u_HFS_REFDAC_VR
EF_TRIM_0__HFS_REFDAC_VREF_TRIM_reg/dout_reg[4] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1605 MASTER LE IN 266047 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/HFS_REFDAC_VREF_TRIM_0_array_u_HFS_REFDAC_VR
EF_TRIM_0__HFS_REFDAC_VREF_TRIM_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1606 MASTER LE IN 266039 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/TEST2_HFS_ATEST_0_array_u_TEST2_HFS_ATEST_0_
_HFS_ATEST4_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1607 MASTER LE IN 266040 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/HFS_REFDAC_VREF_TRIM_0_array_u_HFS_REFDAC_VR
EF_TRIM_0__HFS_REFDAC_VREF_TRIM_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1608 MASTER LE IN 266032 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/HFS_SPARE_CTL_0_array_u_HFS_SPARE_CTL_0__HFS
_SPARE_REG_BITS_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1609 MASTER LE IN 266034 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/HFS_SPARE_CTL_0_array_u_HFS_SPARE_CTL_0__HFS
_SPARE_REG_BITS_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1610 MASTER LE IN 266037 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/u_HFS_QM_MODE__HFS_QM_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1611 MASTER LE IN 266044 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/TEST5_HFS_REFDAC_VREF_0_array_u_TEST5_HFS_RE
FDAC_VREF_0__OPEN_LOOP_TEST_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX2)
 Chain[6] 1612 MASTER LE IN 266046 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/TEST8_PROCESS_RC_OSC_0_array_u_TEST8_PROCESS
_RC_OSC_0__PROCESS_RC_OSC_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1613 MASTER LE IN 266036 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/\u_wrap_buck_cmn_di
g_mod_glue/buck_cmn_idss_main_rif_inst/u_HFS_QM_MODE__FOLLOW_QM_EXT_EN_reg/dout_reg
[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1614 MASTER LE IN 265999 + GPIO_07
I_DCORE/u_buck_cmn_rmod/u_wrap_buck_cmn_rdig/u_buck_cmn_dig_mod/u_buck_cmn_iobyp_lo
gic/\tp_dft_reg[12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1615 MASTER LE IN 266555 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[9]
(M31_1P5V6T_SFFRBQX1)
DSLAVE LS IN 256242 - GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/LOCKUP1 (M31_1P5V6T_LOWLATCHX3)
Chain[6] 1616 MASTER LE IN 266549 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1617 MASTER LE IN 266550 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1618 MASTER LE IN 266547 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1619 MASTER LE IN 266607 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1620 MASTER LE IN 266608 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1621 MASTER LE IN 266611 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1622 MASTER LE IN 268229 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[12]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1623 MASTER LE IN 266614 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1624 MASTER LE IN 266613 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1625 MASTER LE IN 266612 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1626 MASTER LE IN 266606 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1627 MASTER LE IN 266610 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1628 MASTER LE IN 266604 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1629 MASTER LE IN 266615 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1630 MASTER LE IN 266538 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_en_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1631 MASTER LE IN 266616 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[13]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1632 MASTER LE IN 268175 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_btm_pbs_trigger_reg (M31_1P5V6T_SFFRBQX2)
Chain[6] 1633 MASTER LE IN 268145 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1634 MASTER LE IN 268146 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1635 MASTER LE IN 266537 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_en_19p2m_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1636 MASTER LE IN 266501 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_en_19p2m_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1637 MASTER LE IN 266599 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1638 MASTER LE IN 266601 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1639 MASTER LE IN 266594 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_rst_19p2m_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1640 MASTER LE IN 266569 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_en_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1641 MASTER LE IN 266486 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_timer_active_r
eg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1642 MASTER LE IN 266600 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_timer_active_r
eg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1643 MASTER LE IN 266482 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_rst_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1644 MASTER LE IN 266477 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_rst_19p2m_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1645 MASTER LE IN 266525 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_rst_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1646 MASTER LE IN 266484 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_en_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1647 MASTER LE IN 266609 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1648 MASTER LE IN 266605 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1649 MASTER LE IN 266546 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1650 MASTER LE IN 266548 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1651 MASTER LE IN 266485 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_en_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1652 MASTER LE IN 266539 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_en_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1653 MASTER LE IN 266542 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_timer_active_r
eg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1654 MASTER LE IN 266595 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_rst_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1655 MASTER LE IN 266526 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_rst_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1656 MASTER LE IN 266596 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_rst_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1657 MASTER LE IN 266483 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_rst_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1658 MASTER LE IN 266598 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1659 MASTER LE IN 266499 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1660 MASTER LE IN 266528 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1661 MASTER LE IN 266487 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1662 MASTER LE IN 266496 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_cnt_done_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1663 MASTER LE IN 266636 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[17]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1664 MASTER LE IN 266544 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_cnt_done_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1665 MASTER LE IN 266552 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1666 MASTER LE IN 266551 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1667 MASTER LE IN 266554 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1668 MASTER LE IN 266556 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1669 MASTER LE IN 266564 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[18]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1670 MASTER LE IN 266553 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[7]
(M31_1P5V6T_SFFRBQX1)
 Chain[6] 1671 MASTER LE IN 266563 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[17]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1672 MASTER LE IN 266557 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1673 MASTER LE IN 266558 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[12]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1674 MASTER LE IN 266560 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[14]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1675 MASTER LE IN 266559 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[13]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1676 MASTER LE IN 266562 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[16]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1677 MASTER LE IN 266561 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[15]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1678 MASTER LE IN 266445 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[17]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1679 MASTER LE IN 266439 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1680 MASTER LE IN 266440 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[12]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1681 MASTER LE IN 266623 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1682 MASTER LE IN 266621 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1683 MASTER LE IN 266632 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[13]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1684 MASTER LE IN 266443 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[15]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1685 MASTER LE IN 266442 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[14]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1686 MASTER LE IN 266441 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[13]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1687 MASTER LE IN 266438 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1688 MASTER LE IN 266429 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1689 MASTER LE IN 266428 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1690 MASTER LE IN 266446 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[18]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1691 MASTER LE IN 266376 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1692 MASTER LE IN 266377 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1693 MASTER LE IN 266430 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[2]
(M31_1P5V6T_SFFRBQX2J)
Chain[6] 1694 MASTER LE IN 266375 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1695 MASTER LE IN 266367 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1696 MASTER LE IN 266384 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[17]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1697 MASTER LE IN 266385 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[18]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1698 MASTER LE IN 266361 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_en_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1699 MASTER LE IN 266346 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_rst_19p2m_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1700 MASTER LE IN 266369 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1701 MASTER LE IN 266347 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_rst_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1702 MASTER LE IN 266306 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_en_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1703 MASTER LE IN 266388 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_en_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1704 MASTER LE IN 266308 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_timer_active_r
eg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1705 MASTER LE IN 266408 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_timer_active_r
eg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1706 MASTER LE IN 266403 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_rst_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1707 MASTER LE IN 266348 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_rst_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1708 MASTER LE IN 266415 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1709 MASTER LE IN 266416 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1710 MASTER LE IN 266389 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_en_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1711 MASTER LE IN 266307 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_en_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1712 MASTER LE IN 266368 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1713 MASTER LE IN 266370 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1714 MASTER LE IN 266371 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1715 MASTER LE IN 266372 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1716 MASTER LE IN 266373 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1717 MASTER LE IN 266374 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1718 MASTER LE IN 266381 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[14]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1719 MASTER LE IN 266380 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[13]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1720 MASTER LE IN 266379 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[12]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1721 MASTER LE IN 266431 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1722 MASTER LE IN 266432 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[4]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1723 MASTER LE IN 266437 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1724 MASTER LE IN 266444 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[16]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1725 MASTER LE IN 266631 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[12]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1726 MASTER LE IN 266633 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[14]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1727 MASTER LE IN 266622 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1728 MASTER LE IN 266620 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1729 MASTER LE IN 266619 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
 Chain[6] 1730 MASTER LE IN 266637 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[18]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1731 MASTER LE IN 266527 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1732 MASTER LE IN 266498 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1733 MASTER LE IN 266543 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1734 MASTER LE IN 266597 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1735 MASTER LE IN 266570 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_en_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1736 MASTER LE IN 266524 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_rst_19p2m_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1737 MASTER LE IN 266568 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_en_19p2m_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1738 MASTER LE IN 268147 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1739 MASTER LE IN 268148 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1740 MASTER LE IN 266617 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[14]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1741 MASTER LE IN 266618 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[15]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1742 MASTER LE IN 266602 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_cnt_done_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1743 MASTER LE IN 267480 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/first_arb_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 1744 MASTER LE IN 266500 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 1745 MASTER LE IN 268223 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1746 MASTER LE IN 266520 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1747 MASTER LE IN 266517 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1748 MASTER LE IN 266534 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1749 MASTER LE IN 266531 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1750 MASTER LE IN 266533 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1751 MASTER LE IN 266518 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/holdoff_rst_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1752 MASTER LE IN 266541 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1753 MASTER LE IN 266540 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1754 MASTER LE IN 266571 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1755 MASTER LE IN 266489 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_clk_req/inc_async_clk_req_async_clk_en_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1756 MASTER LE IN 266490 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_clk_req/clk_en_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1757 MASTER LE IN 266508 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_low_thr_wip_dly_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1758 MASTER LE IN 266488 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_clk_req/inc_async_clk_req_async_clk_en_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1759 MASTER LE IN 266514 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_csr_itfc/csr_adc_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1760 MASTER LE IN 266516 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/csr_re
q_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1761 MASTER LE IN 266479 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_clk_32k_req/inc_async_clk_req_async_clk_en_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1762 MASTER LE IN 266478 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_clk_32k_req/inc_async_clk_req_async_clk_en_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 1763 MASTER LE IN 266529 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1764 MASTER LE IN 266635 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[16]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1765 MASTER LE IN 266497 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_cnt_done_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1766 MASTER LE IN 266480 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_clk_32k_req/clk_en_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1767 MASTER LE IN 268144 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1768 MASTER LE IN 268143 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1769 MASTER LE IN 268142 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME3_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1770 MASTER LE IN 266515 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_csr_itfc/csr_req_toggle_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1771 MASTER LE IN 268141 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME3_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1772 MASTER LE IN 266110 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_csr_itfc/csr_req_toggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1773 MASTER LE IN 266494 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_clk_req/clk_en_dly_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1774 MASTER LE IN 266492 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_clk_req/clk_en_dly_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1775 MASTER LE IN 266493 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_clk_req/clk_en_dly_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1776 MASTER LE IN 266506 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_low_thr_wip_dly_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1777 MASTER LE IN 266626 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1778 MASTER LE IN 266301 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_clk_32k_req/inc_async_clk_req_async_clk_en_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1779 MASTER LE IN 266627 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1780 MASTER LE IN 266624 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1781 MASTER LE IN 266433 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1782 MASTER LE IN 266630 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1783 MASTER LE IN 266629 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1784 MASTER LE IN 266625 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1785 MASTER LE IN 266435 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1786 MASTER LE IN 266434 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1787 MASTER LE IN 267892 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME3_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1788 MASTER LE IN 267893 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME3_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1789 MASTER LE IN 266302 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_clk_32k_req/clk_en_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1790 MASTER LE IN 266297 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/holdoff_rst_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1791 MASTER LE IN 266333 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_csr_itfc/csr_req_toggle_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1792 MASTER LE IN 266102 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_csr_itfc/csr_req_toggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1793 MASTER LE IN 267476 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/first_arb_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 1794 MASTER LE IN 266325 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1795 MASTER LE IN 266326 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1796 MASTER LE IN 266324 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1797 MASTER LE IN 266344 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1798 MASTER LE IN 266355 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1799 MASTER LE IN 266352 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/holdoff_rst_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1800 MASTER LE IN 266356 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1801 MASTER LE IN 266339 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1802 MASTER LE IN 266353 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1803 MASTER LE IN 266359 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_en_19p2m_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1804 MASTER LE IN 267478 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/first_arb_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 1805 MASTER LE IN 266323 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_en_19p2m_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1806 MASTER LE IN 266299 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_rst_19p2m_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1807 MASTER LE IN 266364 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1808 MASTER LE IN 266387 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_en_19p2m_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1809 MASTER LE IN 266318 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_cnt_done_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1810 MASTER LE IN 266309 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1811 MASTER LE IN 266319 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_cnt_done_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1812 MASTER LE IN 266322 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1813 MASTER LE IN 266332 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_csr_itfc/csr_adc_en_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1814 MASTER LE IN 266334 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/csr_re
q_latch_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1815 MASTER LE IN 266321 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1816 MASTER LE IN 266409 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_done_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1817 MASTER LE IN 266320 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1818 MASTER LE IN 266365 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_cnt_done_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1819 MASTER LE IN 266406 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1820 MASTER LE IN 266407 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1821 MASTER LE IN 266366 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_cnt_done_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1822 MASTER LE IN 266349 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1823 MASTER LE IN 266350 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1824 MASTER LE IN 266411 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_cnt_done_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1825 MASTER LE IN 266420 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1826 MASTER LE IN 266414 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1827 MASTER LE IN 266410 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_cnt_done_
reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1828 MASTER LE IN 266412 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1829 MASTER LE IN 266413 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1830 MASTER LE IN 266417 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[5]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1831 MASTER LE IN 266418 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[6]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1832 MASTER LE IN 266404 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_rst_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1833 MASTER LE IN 266402 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_rst_19p2m_reg
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1834 MASTER LE IN 266405 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1835 MASTER LE IN 266305 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_rst_reg[0
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1836 MASTER LE IN 266304 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_rst_reg[1
] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1837 MASTER LE IN 266363 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_timer_active_r
eg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1838 MASTER LE IN 266360 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_en_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1839 MASTER LE IN 266383 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[16]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1840 MASTER LE IN 266382 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[15]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1841 MASTER LE IN 266378 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1842 MASTER LE IN 267890 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME3_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1843 MASTER LE IN 267891 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME3_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX3)
Chain[6] 1844 MASTER LE IN 266436 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[8]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1845 MASTER LE IN 266303 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_clk_32k_req/clk_en_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1846 MASTER LE IN 266300 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_clk_32k_req/inc_async_clk_req_async_clk_en_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1847 MASTER LE IN 266628 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1848 MASTER LE NI 268222 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL__MEAS_INTERVAL_TIME1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQBX1)
Chain[6] 1849 MASTER LE NI 266634 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[15]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1850 MASTER LE NI 266481 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_clk_32k_req/clk_en_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1851 MASTER LE NI 266545 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_cnt_done_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1852 MASTER LE NI 266603 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_holdoff_cnt_done_
reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1853 MASTER LE NI 267481 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/first_arb_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 1854 MASTER LE NI 266530 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/holdoff_rst_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1855 MASTER LE NI 266519 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1856 MASTER LE NI 266522 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1857 MASTER LE NI 266475 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/holdoff_rst_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1858 MASTER LE NI 267479 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/first_arb_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 1859 MASTER LE NI 266502 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1860 MASTER LE NI 266503 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1861 MASTER LE NI 266504 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1862 MASTER LE NI 266476 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1863 MASTER LE NI 266521 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/btm_ac
tive_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1864 MASTER LE NI 266495 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1865 MASTER LE NI 267954 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/BTM2P_MEAS_INTERVAL_CTL_1_array_u_BTM2P_MEAS_INTERVAL_CTL_1__MEAS_INTERVAL_
TIME_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1866 MASTER LE NI 267953 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/BTM2P_MEAS_INTERVAL_CTL_1_array_u_BTM2P_MEAS_INTERVAL_CTL_1__MEAS_INTERVAL_
TIME_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1867 MASTER LE NI 267936 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/BTM2P_EN_1_array_u_BTM2P_EN_1__MEAS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1868 MASTER LE NI 267938 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/BTM2P_EN_0_array_u_BTM2P_EN_0__MEAS_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1869 MASTER LE NI 266578 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/btm_data_valid_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1870 MASTER LE NI 268048 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_BTM_MEAS_INTERVAL_CTL_1__MEAS_INTERVAL_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1871 MASTER LE NI 268047 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_BTM_MEAS_INTERVAL_CTL_1__MEAS_INTERVAL_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1872 MASTER LE NI 266586 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_low_thr_sts_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1873 MASTER LE NI 266507 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_high_thr_wip_dly_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1874 MASTER LE NI 268039 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_BTM_EN_1__MEAS_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1875 MASTER LE NI 268166 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/BTM2P_EN_0_array_u_BTM2P_EN_0__HIGH_THR_INT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX2)
Chain[6] 1876 MASTER LE NI 268038 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_BTM_EN_1__HIGH_THR_INT_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1877 MASTER LE NI 267935 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/BTM2P_EN_1_array_u_BTM2P_EN_1__LOW_THR_INT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1878 MASTER LE NI 268167 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/BTM2P_EN_1_array_u_BTM2P_EN_1__HIGH_THR_INT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX2)
Chain[6] 1879 MASTER LE NI 268037 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_BTM_EN_1__LOW_THR_INT_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1880 MASTER LE NI 267937 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/BTM2P_EN_0_array_u_BTM2P_EN_0__LOW_THR_INT_EN_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1881 MASTER LE NI 266593 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_btm_thr_irq_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1882 MASTER LE NI 266114 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_low_thr_wip_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1883 MASTER LE NI 266113 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_low_thr_wip_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1884 MASTER LE NI 268099 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_BTM_MEAS_INTERVAL_CTL_0__MEAS_INTERVAL_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1885 MASTER LE NI 266581 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_low_thr_sts_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1886 MASTER LE NI 266582 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_low_thr_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1887 MASTER LE NI 266115 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_low_thr_wip_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1888 MASTER LE NI 268100 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_BTM_MEAS_INTERVAL_CTL_0__MEAS_INTERVAL_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1889 MASTER LE NI 266112 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_low_thr_wip_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1890 MASTER LE NI 266509 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_high_thr_wip_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1891 MASTER LE NI 266574 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_high_thr_sts_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 1892 MASTER LE NI 266580 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_high_thr_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1893 MASTER LE NI 266585 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_high_thr_dly_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1894 MASTER LE NI 267372 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_low_hold_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1895 MASTER LE NI 267371 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_high_hold_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1896 MASTER LE NI 266584 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_high_thr_sts_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1897 MASTER LE NI 268090 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_BTM_EN_0__HIGH_THR_INT_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1898 MASTER LE NI 266505 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_high_thr_wip_dly_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1899 MASTER LE NI 266579 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_high_thr_sts_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1900 MASTER LE NI 268089 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_BTM_EN_0__LOW_THR_INT_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1901 MASTER LE NI 266589 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_high_thr_sts_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1902 MASTER LE NI 267368 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_low_hold_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1903 MASTER LE NI 267367 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_high_hold_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1904 MASTER LE NI 268169 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_high_thr_wip_reg[0] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1905 MASTER LE NI 268172 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_high_thr_wip_reg[1] (M31_1P5V6T_SFFRBQX2)
Chain[6] 1906 MASTER LE NI 267373 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_high_hold_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1907 MASTER LE NI 266590 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_high_thr_dly_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1908 MASTER LE NI 267374 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_low_hold_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1909 MASTER LE NI 268091 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_BTM_EN_0__MEAS_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1910 MASTER LE NI 266575 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_high_thr_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1911 MASTER LE NI 266511 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_high_thr_wip_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1912 MASTER LE NI 266101 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_hold_toggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1913 MASTER LE NI 267796 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_MEAS_INTERVAL_CTL_1__MEAS_INTERVAL_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1914 MASTER LE NI 266331 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_hold_toggle_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1915 MASTER LE NI 266109 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_hold_toggle_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1916 MASTER LE NI 266513 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_hold_toggle_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1917 MASTER LE NI 266336 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/holdoff_rst_done_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1918 MASTER LE NI 266338 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1919 MASTER LE NI 266337 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1920 MASTER LE NI 266335 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_req_ctrl_fsm/req_fsm_state_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1921 MASTER LE NI 266351 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/sync_19p2m_holdoff_rst
_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1922 MASTER LE NI 266421 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[9]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1923 MASTER LE NI 266422 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[10]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1924 MASTER LE NI 266310 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_clk_req/inc_async_clk_req_async_clk_en_sync_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1925 MASTER LE NI 267477 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/first_arb_reg (M31_1P5V6T_SFFSBQX1)
Chain[6] 1926 MASTER LE NI 266340 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/btm_ac
tive_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1927 MASTER LE NI 266342 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/adc_co
nv_req_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1928 MASTER LE NI 267395 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1929 MASTER LE NI 267467 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1930 MASTER LE NI 267419 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1931 MASTER LE NI 267073 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1932 MASTER LE NI 267897 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME2_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1933 MASTER LE NI 266316 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_clk_req/clk_en_dly_reg[4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1934 MASTER LE NI 267896 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME2_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1935 MASTER LE NI 267894 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME2_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1936 MASTER LE NI 266311 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_clk_req/inc_async_clk_req_async_clk_en_sync_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1937 MASTER LE NI 266426 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[14]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1938 MASTER LE NI 266419 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[7]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1939 MASTER LE NI 266425 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[13]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1940 MASTER LE NI 266423 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[11]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1941 MASTER LE NI 266424 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[12]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1942 MASTER LE NI 266427 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/u_adc_dig_holdoff_timer/holdoff_cnt_reg[15]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1943 MASTER LE NI 266358 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/btm_ar
b_not_empty_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1944 MASTER LE NI 267240 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1945 MASTER LE NI 267114 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][5] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 1946 MASTER LE NI 267449 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1947 MASTER LE NI 267461 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1948 MASTER LE NI 267414 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1949 MASTER LE NI 267413 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1950 MASTER LE NI 267402 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1951 MASTER LE NI 267401 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1952 MASTER LE NI 267407 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1953 MASTER LE NI 267455 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1954 MASTER LE NI 267408 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1955 MASTER LE NI 267420 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1956 MASTER LE NI 267443 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1957 MASTER LE NI 267396 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1958 MASTER LE NI 267781 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_TEST1__SEL_FSM_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1959 MASTER LE NI 267784 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_TEST1__DTEST_SEL_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1960 MASTER LE NI 267797 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_MEAS_INTERVAL_CTL_1__MEAS_INTERVAL_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 1961 MASTER LE NI 267783 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_TEST1__DTEST_SEL_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1962 MASTER LE NI 268205 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/cur_rd
_ptr_reg[1] (M31_1P5V6T_SFFSBQX3)
Chain[6] 1963 MASTER LE NI 266341 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/cur_rd
_ptr_reg[0] (M31_1P5V6T_SFFRBQX2J)
Chain[6] 1964 MASTER LE NI 266390 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1965 MASTER LE NI 266298 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1966 MASTER LE NI 266317 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1967 MASTER LE NI 266362 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/req_fs
m_btm_loop[0]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1968 MASTER LE NI 266512 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_low_thr_wip_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1969 MASTER LE NI 266577 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_low_thr_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1970 MASTER LE NI 266576 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_low_thr_sts_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1971 MASTER LE NI 266592 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_low_thr_dly_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1972 MASTER LE NI 266591 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_low_thr_sts_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1973 MASTER LE NI 266510 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_low_thr_wip_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1974 MASTER LE NI 266491 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_clk_req/clk_en_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1975 MASTER LE NI 266587 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/adc_low_thr_dly_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1976 MASTER LE NI 266536 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/btm_ar
b_not_empty_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1977 MASTER LE NI 266572 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[1]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1978 MASTER LE NI 268206 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/req_fs
m_btm_loop[2]_u_adc_dig_btm_req_ctrl/cur_rd_ptr_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1979 MASTER LE NI 268204 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/cur_rd
_ptr_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1980 MASTER LE NI 268203 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/cur_rd
_ptr_reg[1] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1981 MASTER LE NI 266565 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/adc_co
nv_req_dly_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 1982 MASTER LE NI 267454 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1983 MASTER LE NI 267406 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1984 MASTER LE NI 267442 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][10] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 1985 MASTER LE NI 267394 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1986 MASTER LE NI 267388 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1987 MASTER LE NI 267466 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1988 MASTER LE NI 266588 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/btm_data_valid_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1989 MASTER LE NI 267382 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1990 MASTER LE NI 267430 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1991 MASTER LE NI 267418 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1992 MASTER LE NI 267238 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[2][11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1993 MASTER LE NI 266583 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/btm_data_valid_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1994 MASTER LE NI 267469 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][15] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1995 MASTER LE NI 267417 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1996 MASTER LE NI 267471 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][15] (M31_1P5V6T_SFFSBQX1)
Chain[6] 1997 MASTER LE NI 267464 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1998 MASTER LE NI 267440 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 1999 MASTER LE NI 267470 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][15] (M31_1P5V6T_SFFSBQX1)
Chain[6] 2000 MASTER LE NI 267400 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2001 MASTER LE NI 267459 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2002 MASTER LE NI 267457 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2003 MASTER LE NI 267458 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2004 MASTER LE NI 267423 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2005 MASTER LE NI 267393 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2006 MASTER LE NI 267381 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2007 MASTER LE NI 267453 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2008 MASTER LE NI 267428 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2009 MASTER LE NI 267451 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2010 MASTER LE NI 267387 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2011 MASTER LE NI 267434 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2012 MASTER LE NI 267435 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2013 MASTER LE NI 267433 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2014 MASTER LE NI 267391 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2015 MASTER LE NI 267415 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2016 MASTER LE NI 267392 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2017 MASTER LE NI 267386 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2018 MASTER LE NI 267399 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2019 MASTER LE NI 267397 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2020 MASTER LE NI 267404 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2021 MASTER LE NI 267403 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2022 MASTER LE NI 267416 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2023 MASTER LE NI 267465 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2024 MASTER LE NI 267370 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_low_hold_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2025 MASTER LE NI 267369 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_high_hold_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2026 MASTER LE NI 267379 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2027 MASTER LE NI 267398 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2028 MASTER LE NI 267445 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2029 MASTER LE NI 267409 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2030 MASTER LE NI 267410 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2031 MASTER LE NI 267236 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2032 MASTER LE NI 267899 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL__MEAS_INTERVAL_TIME1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 2033 MASTER LE NI 267785 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_TEST1__DTEST_SEL_reg/dout_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2034 MASTER LE NI 267848 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_MEAS_INTERVAL_CTL_0__MEAS_INTERVAL_TIME_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 2035 MASTER LE NI 267782 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_TEST1__DTEST_SEL_reg/dout_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2036 MASTER LE NI 267849 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_MEAS_INTERVAL_CTL_0__MEAS_INTERVAL_TIME_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 2037 MASTER LE NI 267840 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_EN_0__MEAS_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2038 MASTER LE NI 267383 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2039 MASTER LE NI 267432 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2040 MASTER LE NI 267900 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL__MEAS_INTERVAL_TIME1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 2041 MASTER LE NI 267178 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2042 MASTER LE NI 267136 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2043 MASTER LE NI 267157 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2044 MASTER LE NI 267156 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2045 MASTER LE NI 267093 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2046 MASTER LE NI 267304 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2047 MASTER LE NI 267303 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2048 MASTER LE NI 267115 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2049 MASTER LE NI 267072 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2050 MASTER LE NI 267282 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2051 MASTER LE NI 266314 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_clk_req/clk_en_dly_reg[2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2052 MASTER LE NI 267895 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL2__MEAS_INTERVAL_TIME2_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 2053 MASTER LE NI 266315 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_clk_req/clk_en_dly_reg[3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2054 MASTER LE NI 266312 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_clk_req/clk_en_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2055 MASTER LE NI 266397 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/adc_high_thr_sts_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2056 MASTER LE NI 266392 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/adc_high_thr_sts_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2057 MASTER LE NI 266398 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/adc_high_thr_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2058 MASTER LE NI 266400 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/adc_low_thr_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2059 MASTER LE NI 266393 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/adc_high_thr_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2060 MASTER LE NI 266395 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/adc_low_thr_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2061 MASTER LE NI 266313 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_clk_req/clk_en_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 2062 MASTER LE NI 267364 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_high_hold_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2063 MASTER LE NI 267362 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_high_hold_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2064 MASTER LE NI 267363 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_low_hold_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2065 MASTER LE NI 267365 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_low_hold_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2066 MASTER LE NI 267473 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][15] (M31_1P5V6T_SFFSBQX1)
Chain[6] 2067 MASTER LE NI 267425 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2068 MASTER LE NI 267426 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2069 MASTER LE NI 267437 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2070 MASTER LE NI 267438 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2071 MASTER LE NI 267219 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2072 MASTER LE NI 267390 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2073 MASTER LE NI 267431 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2074 MASTER LE NI 267384 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2075 MASTER LE NI 267898 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL__MEAS_INTERVAL_TIME1_reg/dout_reg[3]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 2076 MASTER LE NI 267901 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL__MEAS_INTERVAL_TIME1_reg/dout_reg[0]
(M31_1P5V6T_SFFRBQX1)
Chain[6] 2077 MASTER LE NI 267299 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2078 MASTER LE NI 267194 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2079 MASTER LE NI 267441 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2080 MASTER LE NI 266573 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/btm_data_valid_reg[0] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 2081 MASTER LE NI 267463 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2082 MASTER LE NI 267439 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2083 MASTER LE NI 267429 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2084 MASTER LE NI 267427 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2085 MASTER LE IN 268232 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL__MEAS_INTERVAL_TIME1_reg/dout_reg[1]
(M31_1P5V6T_SFFRBQBX3)
Chain[6] 2086 MASTER LE IN 267380 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2087 MASTER LE IN 267385 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2088 MASTER LE IN 267421 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2089 MASTER LE IN 267422 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2090 MASTER LE IN 267195 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2091 MASTER LE IN 267405 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][4] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2092 MASTER LE IN 267452 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2093 MASTER LE IN 267447 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2094 MASTER LE IN 267301 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[2][14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2095 MASTER LE IN 267196 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[2][9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2096 MASTER LE IN 267424 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2097 MASTER LE IN 267472 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][15] (M31_1P5V6T_SFFSBQX1)
Chain[6] 2098 MASTER LE IN 267436 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2099 MASTER LE IN 267412 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2100 MASTER LE IN 267460 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2101 MASTER LE IN 267197 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[3][9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2102 MASTER LE IN 268213 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2103 MASTER LE IN 267389 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2104 MASTER LE IN 267011 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2105 MASTER LE IN 267839 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_EN_0__HIGH_THR_INT_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2106 MASTER LE IN 267788 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_EN_1__MEAS_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2107 MASTER LE IN 267177 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2108 MASTER LE IN 267135 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2109 MASTER LE IN 267283 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2110 MASTER LE IN 267444 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2111 MASTER LE IN 267450 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2112 MASTER LE IN 267474 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][15] (M31_1P5V6T_SFFSBQX1)
Chain[6] 2113 MASTER LE IN 267500 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][15] (M31_1P5V6T_SFFSBQX1)
Chain[6] 2114 MASTER LE IN 267261 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2115 MASTER LE IN 266396 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/btm_data_valid_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2116 MASTER LE IN 267241 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2117 MASTER LE IN 266107 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_high_thr_wip_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2118 MASTER LE IN 266105 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_high_thr_wip_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2119 MASTER LE IN 267815 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_LOW_THR1_1__LOW_THR_15_8_reg/dout_reg[6] (M31_1P5V6T_SFFRBQX1)
 Chain[6] 2120 MASTER LE IN 266391 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/btm_data_valid_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2121 MASTER LE IN 266394 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/adc_low_thr_sts_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2122 MASTER LE IN 266401 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/adc_btm_thr_irq_reg (M31_1P5V6T_SFFRBQX1)
Chain[6] 2123 MASTER LE IN 266399 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/adc_low_thr_sts_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2124 MASTER LE IN 266327 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_high_thr_wip_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2125 MASTER LE IN 266328 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_low_thr_wip_dly_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2126 MASTER LE IN 266330 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_low_thr_wip_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2127 MASTER LE IN 266329 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_high_thr_wip_dly_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2128 MASTER LE IN 266106 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_low_thr_wip_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2129 MASTER LE IN 267814 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_LOW_THR1_1__LOW_THR_15_8_reg/dout_reg[7] (M31_1P5V6T_SFFSBQX1)
Chain[6] 2130 MASTER LE IN 267866 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_LOW_THR1_0__LOW_THR_15_8_reg/dout_reg[7] (M31_1P5V6T_SFFSBQX1)
Chain[6] 2131 MASTER LE IN 267850 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_HIGH_THR1_0__HIGH_THR_15_8_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2132 MASTER LE IN 267499 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][15] (M31_1P5V6T_SFFSBQX1)
Chain[6] 2133 MASTER LE IN 267262 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2134 MASTER LE IN 267456 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[0][12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2135 MASTER LE IN 267199 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2136 MASTER LE IN 267198 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][9] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2137 MASTER LE IN 267220 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][10] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2138 MASTER LE IN 267838 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_EN_0__LOW_THR_INT_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2139 MASTER LE IN 267786 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_EN_1__LOW_THR_INT_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2140 MASTER LE IN 267787 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm1_perph_u_adc_btm1_perph/u_adc_
btm_rif/u_BTM_EN_1__HIGH_THR_INT_EN_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2141 MASTER LE IN 268117 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_BTM_LOW_THR1_0__LOW_THR_15_8_reg/dout_reg[7] (M31_1P5V6T_SFFSBQX1)
Chain[6] 2142 MASTER LE IN 268101 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_BTM_HIGH_THR1_0__HIGH_THR_15_8_reg/dout_reg[7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2143 MASTER LE IN 267131 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][6] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2144 MASTER LE IN 267068 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[0][3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2145 MASTER LE NI 268221 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/u_MEAS_INTERVAL_CTL__MEAS_INTERVAL_TIME1_reg/dout_reg[2]
(M31_1P5V6T_SFFRBQBX1)
Chain[6] 2146 MASTER LE NI 267049 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][2] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2147 MASTER LE NI 267008 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2148 MASTER LE NI 267300 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][14] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2149 MASTER LE NI 267258 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2150 MASTER LE NI 267279 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2151 MASTER LE NI 267112 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[2][5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2152 MASTER LE NI 267070 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[2][3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2153 MASTER LE NI 267071 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[3][3] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2154 MASTER LE NI 267155 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[3][7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2155 MASTER LE NI 267239 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[3][11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2156 MASTER LE NI 267113 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[3][5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2157 MASTER LE NI 267281 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[3][13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2158 MASTER LE NI 267498 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[3][15] (M31_1P5V6T_SFFSBQX1)
 Chain[6] 2159 MASTER LE NI 267259 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[2][12] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2160 MASTER LE NI 267411 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[2][5] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2161 MASTER LE NI 267955 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/BTM2P_MEAS_INTERVAL_CTL_0_array_u_BTM2P_MEAS_INTERVAL_CTL_0__MEAS_INTERVAL_
TIME_reg/dout_reg[1] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2162 MASTER LE NI 267956 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
btm_rif/BTM2P_MEAS_INTERVAL_CTL_0_array_u_BTM2P_MEAS_INTERVAL_CTL_0__MEAS_INTERVAL_
TIME_reg/dout_reg[0] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2163 MASTER LE NI 267280 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[2][13] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2164 MASTER LE NI 267154 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[2][7] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2165 MASTER LE NI 267175 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[2][8] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2166 MASTER LE NI 267497 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[2][15] (M31_1P5V6T_SFFSBQX1)
Chain[6] 2167 MASTER LE NI 267496 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_reg[1][15] (M31_1P5V6T_SFFSBQX1)
Chain[6] 2168 MASTER LE NI 267448 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[3][11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2169 MASTER LE NI 267446 + GPIO_07
I_DCORE/u_adc_rmod/u_adc_rdig/u_adc_dig_mod/\adc_btm2_perph_u_adc_btm2_perph/u_adc_
dig_btm_csr_itfc/csr_mx_data_hold_reg[1][11] (M31_1P5V6T_SFFRBQX1)
Chain[6] 2170 MASTER LE NI 267237 + GPIO_07
I_DCORE/u