A B C D E

1 1

Compal confidential 2

Schematics Document
Mobile Merom uFCPGA with Intel
3
Crestline_PM+ICH8-M core logic 3

IBT00 LA-3261P UMA

2007-03-28 REV:1A (MV2)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 28, 2007 Sheet 1 of 55
A B C D E
 A B C D E

Compal confidential
File Name : LA-3261P
Chimay UMA
Thermal Sensor Mobile Merom
1 1
ADM1032ARMZ
uFCPGA-478 CPU
P4

P4, 5, 6 CK505 TSSOP-64

Fan conn Clock Generator

CRT & TV OUT P4 H_A#(3..35)
FSB
P16
ICS 9LPRS355
H_D#(0..63) 667/800MHz 1.05V

DDR2 667MHz 1.8V DDR2-SO-DIMM X2 P15

BANK 0, 1, 2, 3 P13, 14

LVDS Panel Interface Intel Crestline MCH

P17 Dual Channel
SDVO FCBGA 1299
USB conn x2 P33
P7, 8, 9, 10, 11, 12 (Docking)
2 2

DVI (Docking) CH7307C FingerPrinter 2501B

P33 P16 DMI X4 C-Link USBx1 P30 daughter board

USB conn x3
USB2.0
PCI-E BUS P28

Intel ICH8-M Azalia

BT Conn P28
CardBus Controller & PCMCIA conn PCI mBGA-676 SATA Master
10/100/1000 LAN Mini-Card PATA Slave
Mini-Card WWAN
Intel 82566MM P25
Ricoh R5C853 & R5C851 P18, 19, 20, 21
P25
P23 P25 MDC
P32
SPI Audio CKT
AD1981HD P26 AMP & Audio Jack
Slot 0/Smart Card MAX9710
RJ45/11 CONN P27
3 P24 3

SPI ROM & Debug port SATA HDD Connector

1394 port 6in1 Slot P22 P33
P28 16Mb*2 or 32Mb*1 Docking CONN.
LED P30
P30 *RJ-45(LED*2)
Multi-bay II Connector *RJ-11(Pass Through)
daughter board P22 *CRT
LPC BUS *COMPOSITE Video Out
RTC CKT. *TVOUT
P19 *DVI
*LINE IN
*LINE OUT
TPM1.2 SMSC KBC 1070 SMSC Super I/O *PCI-E x2
Power OK CKT. SMSC KBC 1021-NU *Serial Port
P35
SLB9635TT LPC47N217 P29 *Parallel Port
P30 P31 *PS/2 x2
*USB x2
4 Int.KBD C OM1 LPT *DC JACK 4
Power On/Off CKT. Touch Pad CONN. ( Docking
P33
) ( Docking
P33
)
P32 P32 P32

TrackPoint CONN. Security Classification Compal Secret Data Compal Electronics, Inc.
P32 2006/02/13 2006/03/10 Title
DC/DC Interface CKT. Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P34 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 2 of 55
A B C D E
 A

O MEANS ON X MEANS OFF

Voltage Rails IRQ Device

+5VS 0 System Timer

+3VS
power 1 Keyboard
plane +2.5VS
+1.8VS 2 N/A
+B
+1.5VS
LDO3 +5VALW +1.8V +3VM Serial port (COM2),LAN/Modem
+1.25VS CLOCK 3
LDO5 +3VALW +5V +1.05VM
+VGA_CORE 4 Serial port (COM1)
+0.9V
+CPU_CORE +1.25VM
State 5 Audio/VGA
+VCCP
6 Floppy

7 Parallel port
S0 O O O O O O
8 System CMOS/Real-time clock

S3/M1 Microsoft ACPI

O O O X O O 9

10 N/A,Momem,LAN
S3
O O O X O O
11 Mass strorage control/ PCI simple communication control
S5 S4/AC
O O X X O O 12 synactic PS2 port GlidePAD

S5 S4/ Battery only Numeric Data Process

O X X X X X 13

14 Primary IDE interface,HDD

S5 S4/AC & Battery
don't exist X X X X X X Secondary IDE innterface,CD-ROM
15

16 Mobile Intel Crestline Express Chipset Family

Microsoft UAA Bus Driver for High Definition Audio
Intel 82801H (ICH8 Family) PCI Express Root Port -27D0
PCI Devices
1
Broadcom NetXtreme Gigabit Ethernet 1

EXTERNAL IDSEL# REQ/G NT# PI RQ

17 Intel 82801H (ICH8 Family)PCI Express Root Port - 27D2
CARD BUS & 1394 AD22 2 C,D,E,G Broadcom 802.11b/g WLAN
Intel 82801H (ICH8 Family)USB Universal Host Controll
Intel 82801H (ICH8 Family)USB Universal Host Controll
DMA Channel Device 18
Ricoh R5C853 Cardbus Control
DMA0 MODEM / LAN Ricoh R5C853 Integrates FlashMedia Control
DMA1 ECP Ricoh R5C853 Gemcore based SmartCard Control
DMA2 FLOPPY DISK 19 Intel 82801H (ICH8 Family)PCI Express Root Port - 27D6
DMA3 AUDIO Intel 82801H (ICH8 Family)USB Universal Host Controll
DMA4 (Cascade)
DMA5 Unused 20 Intel 82801H (ICH8 Family)USB Universal Host Controll

DMA6 Unused Intel 82801H (ICH8 Family)USB2 Enhanced Host Controll

DMA7 Unused 21 Intel 82801H (ICH8 Family)USB Universal Host Controll

22
SDA Standard Compliant SD Host Controller
USB PORT# Destination
23 HP Mobile Data Protection Sensor
0 Walk-up0 (Right side)

1 Fingerprint

2 Reserve

3 WWAN

4 Walk-up1 (Left Side)

5 Walk-up2 (Left Side)

6 Bluetooth

7 Reserve Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

8 Docking THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-3261P U MA 0.4
9 Docking MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 3 of 55
A
 5 4 3 2 1

layout note: Change R237 to 649 ohm if using XTP to ITP adapter
XDP Connector +3VS

R243
XDP_DBRESET#_R 1 2 @ 1K_0402_5%

04/10 no stuff +VCCP

JP51 XDP_TDI R143 1 2 54.9_0402_1%

1 2
XDP_BPM#5 GND0 GND1 XDP_TMS R236 1 54.9_0402_1%
3 OBSFN_A0 OBSFN_C0 4 2
XDP_BPM#4 5 6
OBSFN_A1 OBSFN_C1 XDP_TDO R1670 1 54.9_0402_1%
7 GND2 GND3 8 2
D XDP_BPM#3 D
9 OBSDATA_A0 OBSDATA_C0 10
XDP_BPM#2 11 12 XDP_BPM#5 R241 1 2 54.9_0402_1%
OBSDATA_A1 OBSDATA_C1
13 GND4 GND5 14
XDP_BPM#1 15 16 XDP_HOOK1 R1430 1 2 @ 54.9_0402_1%
XDP_BPM#0 OBSDATA_A2 OBSDATA_C2
17 18
OBSDATA_A3 OBSDATA_C3
19 GND6 GND7 20
21 22 XDP_TRST# R237 1 2 51_0402_1%
OBSFN_B0 OBSFN_D0
7 H_A#[3..16] 23 OBSFN_B1 OBSFN_D1 24
JP12A 25 26 XDP_TCK R239 1 2 54.9_0402_1%
H_A#3 H_ADS# GND8 GND9
J4 H1 H_ADS# 7 27 28
A[3]# ADS# OBSDATA_B0 OBSDATA_D0

ADDR GROUP 0
H_A#4 L5 E2 H_BNR# 29 30
H_A#5 A[4]# BNR# H_BPRI# H_BNR# 7 OBSDATA_B1 OBSDATA_D1
L4 G5 H_BPRI# 7 31 32
H_A#6 A[5]# BPRI# GND10 GND11
K5 A[6]# 33 OBSDATA_B2 OBSDATA_D2 34
H_A#7 M3 H5 H_DEFER# 35 36
H_A#8 A[7]# DEFER# H_DRD Y# H_DEFER# 7 OBSDATA_B3 OBSDATA_D3
N2 F21 H_DRDY# 7 37 38
H_A#9 A[8]# DRDY# H_DBSY# H_PWRGOOD_R GND12 GND13 CLK_CPU_XDP
J1 E1 H_DBSY# 7 5 H_PWRGOOD_R 39 40 CLK_CPU_XDP 15
H_A#10 A[9]# DBSY# XDP_HOOK1 PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_CPU_XDP#
N3 A[10]# 41 HOOK1 ITPCLK#/HOOK5 42 CLK_CPU_XDP# 15
H_A#11 P5 F1 H_BR0# R172 43 44 1K_0402_1%
A[11]# BR0# H_BR0# 7 +VCCP VCC_OBS_AB VCC_OBS_CD +VCCP
H_A#12 P2 56_0402_5% 45 46 H_RESET#_R 1 R1431 2 H_RESET#
A[12]# HOOK2 RESET#/HOOK6

CONTROL
H_A#13 L2 D20 H_IERR# 2 1 1 47 48 XDP_DBRESET#_R 2 1 XDP_DBRESET#
H_A#14 A[13]# IERR# H_INIT# +VCCP HOOK3 DBR#/HOOK7 200_0402_1%
P4 B3 H_INIT# 19 49 50
H_A#15 A[14]# INIT# C1099 GND14 GND15 XDP_TDO R1432
P1 51 52
H_A#16 A[15]# H_LOCK# SDA TD0 XDP_TRST#
R1 A[16]# LOCK# H4 H_LOCK# 7 53 SCL TRST# 54
H_ADSTB#0 2 XDP_TDI
7 H_ADSTB#0 M1 ADSTB[0]# 55 TCK1 TDI 56
C1 H_RESET# XDP_TCK 57 58 XDP_TMS
RESET# H_RESET# 7 TCK0 TMS
H_REQ#0 K3 F3 H_RS#0 59 60 XDP_PRE 1 R1433 2 0_0402_5%
7 H_REQ#0 H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_RS#0 7 GND16 GND17
H2 F4 0.1U_0402_16V4Z
7 H_REQ#1 H_REQ#2 REQ[1]# RS[1]# H_RS#2 H_RS#1 7
K2 G3 conn@ SAMTE_BSH-030-01-L-D-A
7 H_REQ#2 REQ[2]# RS[2]# H_RS#2 7
H_REQ#3 J3 G2 H_TRDY# Place R1431 within 200ps (~1") to CPU
7 H_REQ#3 REQ[3]# TRDY# H_TRDY# 7
H_REQ#4 L1
7 H_REQ#4 REQ[4]# H_HIT#
7 H_A#[17..35] G6 H_HIT# 7
H_A#17 HIT# H_HITM#
Y2 E4 H_HITM# 7
C H_A#18 A[17]# HITM# C
U5 A[18]#
H_A#19 R3 AD4 XDP_BPM#0
A[19]# BPM[0]#
ADDR GROUP 1

H_A#20 W6 AD3 XDP_BPM#1

H_A#21 A[20]# BPM[1]# XDP_BPM#2
U4 AD1
XDP/ITP SIGNALS

H_A#22 A[21]# BPM[2]# XDP_BPM#3

Y5 A[22]# BPM[3]# AC4
H_A#23 U1 AC2 XDP_BPM#4
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
H_A#26 A[25]# TCK XDP_TDI
T3 AA6
H_A#27
H_A#28
W2
W5
A[26]#
A[27]#
TDI
TDO
AB3
AB5
XDP_TDO
XDP_TMS
Thermal Sensor ADM1032ARMZ
H_A#29 A[28]# TMS XDP_TRST# +3VS
Y4 AB6
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 A[30]# DBR# C20 XDP_DBRESET# 20
H_A#31 V4
H_A#32 A[31]# H_PROCHOT# 43
W3 R410 2
H_A#33 A[32]# H_PROCHOT# C273
AA4
A[33]# THERMAL 2 1
+VCCP

2
H_A#34 AB2 68_0402_5%
H_A#35 A[34]# 0.1U_0402_16V4Z R227
AA3 D21
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA_R1 R1798 H_THERMDA 1
7 H_ADSTB#1 V1 A24 2 0_0402_5% 10K_0402_5%
ADSTB[1]# THERMDA H_THERMDC_R1 R1799 H_THERMDC
THERMDC B25 2 0_0402_5% U16
H_A20M# A6 1 8 ICH_SM_CLK
19 H_A20M#

1
A20M# VDD SCLK
ICH

H_FERR# A5 C7 H_THERMTRIP#
19 H_FERR# H_IGNNE# FERR# THERMTRIP# H_THERMTRIP# 7,19 H_THERMDA ICH_SM_DA
19 H_IGNNE# C4 2 7
IGNNE# C264 D+ SDATA
H_STPCLK# D5 1 2 H_THERMDC 3 6 THERM_SCI#
19 H_STPCLK# H_INTR STPCLK# D- ALERT# THERM_SCI# 20
19 H_INTR C6
LINT0 H CLK
H_NMI B4 A22 CLK_CPU_BCLK 2200P_0402_50V7K THERM# 4 5
19 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 15 THERM# GND
H_SMI# A3 A21 CLK_CPU_BCLK#
19 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 15
R228
M4 +3VS 1 2 ADM1032ARMZ-2REEL_MSOP8
RSVD[01]
N5
RSVD[02] H_THERMDA, H_THERMDC routing together,
T2 10K_0402_5% Address:100_1100
B
V3
RSVD[03] Trace width / Spacing = 10 / 10 mil B
RSVD[04]
B2
RESERVED

RSVD[05]
C3
RSVD[06] ICH_SM_CLK
D2 RSVD[07] 1113 Add resistors in series with the diode signals going to ADM1032. 20,25 ICH_SM_CLK
D22 ICH_SM_DA
RSVD[08] 20,25 ICH_SM_DA
D3
RSVD[09]
F6
RSVD[10] For Merom, R1798 and R1799 are 0ohm
For Penryn, R1798 and R1799 are 100ohm.
Merom Ball-out Rev 1a
conn@
PWM Fan Control circuit
+VCCP
1

0308 change design

R1255 +3VS

@ 56_0402_5%
conn@
2 2

5
U24 JP8
B

1 1

P
31 FAN_PWM INB +5VS 1
4 2 4
O 2 G1
E

H_PROCHOT# 3 1 OCP# THERM# 2 3 5

OCP# 20,44 INA 3 G2

G
C

@ Q85
MMBT3904_SOT23 TC7SH00FU_SSOP5 ACES_85204-03001

3
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(1/3)-AGTL+/XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 4 of 55
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE
7 H_D#[0..15] H_D#[32..47] 7
JP12B JP12C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
G22 D[3]# D[35]# V26 A12 VCC[004] VCC[071] AC9

DATA GRP 0
D H_D#4 H_D#36 D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 Y25 A20 AC18

DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
G24 D[9]# D[41]# W22 B7 VCC[010] VCC[077] AD7
H_D#10 J24 Y23 H_D#42 B9 AD9
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
J23 D[11]# D[43]# W24 B10 VCC[012] VCC[079] AD10
H_D#12 H22 W25 H_D#44 B12 AD12
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
F26 AA23 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 D[14]# D[46]# AA24 B15 VCC[015] VCC[082] AD15
H_D#15 H23 AB25 H_D#47 B17 AD17
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
7 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 7 B18 VCC[017] VCC[084] AD18
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
7 H_DSTBP#0 H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2 H_DSTBP#2 7 VCC[018] VCC[085]
7 H_DINV#0 H25 U22 H_DINV#2 7 C9 AE10
DINV[0]# DINV[2]# VCC[019] VCC[086]
7 H_D#[16..31] H_D#[48..63] 7 C10 AE12
VCC[020] VCC[087]
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 AB22 C18 AE20
H_D#20 D[19]# D[51]# H_D#52 VCC[025] VCC[092]
L23 AB21 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 AE21 D18 AF18

DATA GRP 3
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099] +VCCP
T24 D[27]# D[59]# AD21 E7 VCC[033] VCC[100] AF20
H_D#28 R24 AC22 H_D#60 E9 R1434 0_0402_5%
H_D#29 D[28]# D[60]# H_D#61 VCC[034] 0228 change value
L25 AD23 E10 G21 2 1
H_D#30 D[29]# D[61]# H_D#62 VCC[035] VCCP[01]
T25 AF22 E12 V6 2 1
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP[02] R1435 0_0402_5% C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
7 H_DSTBN#1 H_DSTBP#1 DSTBN[1]# DSTBN[3]# H_DSTBP#3 H_DSTBN#3 7 VCC[038] VCCP[04]
7 H_DSTBP#1 M26 AF24 H_DSTBP#3 7 E17 M6
H_DINV#1 DSTBP[1]# DSTBP[3]# H_DINV#3 VCC[039] VCCP[05] C1100 +
7 H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 7 E18 VCC[040] VCCP[06] J21
E20 VCC[041] VCCP[07] K21
V_CPU_GTLREF AD26 R26 COMP0 F7 M21 330U_D2E_2.5VM_R7
R1264 1 TEST1 GTLREF COMP[0] COMP1 VCC[042] VCCP[08] 2
2 @ 1K_0402_5% C23 TEST1 MISC COMP[1] U26 F9 VCC[043] VCCP[09] N21
R1265 1 2 @ 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T1 C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
C1101 1 2 @ 0.1U_0402_16V4Z TEST4 AF26 F14 R6
TEST5 TEST4 H_DPRSTP# VCC[046] VCCP[12]
T2 AF1 TEST5 DPRSTP# E5 H_DPRSTP# 7,19,43 F15 VCC[047] VCCP[13] T21

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T3 TEST6 DPSLP# H_DPSLP# 19 VCC[048] VCCP[14]

1
D24 H_DPWR# F18 V21
CPU_BSEL0 DPWR# H_PWRGOOD H_DPWR# 7 VCC[049] VCCP[15]
15 CPU_BSEL0 B22 D6 H_PWRGOOD 19 F20 W21
BSEL[0] PWRGOOD VCC[050] VCCP[16]

R1220

R355

R245

R244
CPU_BSEL1 B23 D7 H_CPUSLP# AA7
15 CPU_BSEL1 CPU_BSEL2 BSEL[1] SLP# H_PSI# H_CPUSLP# 7 VCC[051]
15 CPU_BSEL2 C21 AE6 H_PSI# 43 AA9 B26
BSEL[2] PSI# VCC[052] VCCA[01] +1.5VS

0.01U_0402_16V7K
AA10 C26

2
VCC[053] VCCA[02]

10U_0805_6.3V6M
Merom Ball-out Rev 1a R1436 AA12
VCC[054]
conn@ 2 1 H_PWRGOOD_R H_PWRGOOD_R 4 AA13 AD6 CPU_VID0 43
1K_0402_5% VCC[055] VID[0]
AA15 VCC[056] VID[1] AF5 CPU_VID1 43 1 1
AA17 AE5 CPU_VID2 43
VCC[057] VID[2]

C520

C531
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs Resistor placed within AA18
VCC[058] VID[3]
AF4 CPU_VID3 43
AA20 AE3
0.5" of CPU pin.Trace AB9
VCC[059] VID[4]
AF3
CPU_VID4 43 2 2
VCC[060] VID[5] CPU_VID5 43
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 should be at least 25 AC10
VCC[061] VID[6]
AE2 CPU_VID6 43
AB10
mils away from any other AB12
VCC[062]
VCC[063]
toggling signal. AB14
VCC[064] VCCSENSE
AF7 VCCSENSE
VCCSENSE 43
166 0 1 1 COMP[0,2] trace width is AB15
VCC[065] Near pin B26
AB17
18 mils. COMP[1,3] trace VCC[066] VSSSENSE
AB18 AE7 VSSSENSE 43
VCC[067] VSSSENSE
B width is 4 mils. B
200 0 1 0 Merom Ball-out Rev 1a
conn@ .
Length match within 25 mils.
The trace width/space/other is
20/7/25.
+VCCP
1

R1268
1K_0402_1%
+VCC_CORE
2

V_CPU_GTLREF R1269
100_0402_1%
1 2 VCCSENSE
1

R1270
R1271 100_0402_1%
2K_0402_1% 1 2 VSSSENSE
2

Close to CPU pin AD26

within 500mils. Close to CPU pin
within 500mils.
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(2/3)-AGTL+/PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 5 of 55
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE

1 1 1 1 1 1 1 1
C899 C900 C901 C902 C903 C904 C905 C906
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
D 2 2 2 2 2 2 2 2 D

JP12D
A4 P6
VSS[001] VSS[082] +VCC_CORE
A8 P21
VSS[002] VSS[083]
A11 VSS[003] VSS[084] P24
A14 R2
VSS[004] VSS[085]
A16 VSS[005] VSS[086] R5 1 1 1 1 1 1 1 1
A19 R22 C907 C908 C909 C910 C911 C912 C913 C914
VSS[006] VSS[087] Place these capacitors on L8
A23 R25
VSS[007] VSS[088] (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AF2 VSS[008] VSS[089] T1
B6 T4 2 2 2 2 2 2 2 2
VSS[009] VSS[090]
B8 VSS[010] VSS[091] T23
B11 T26
VSS[011] VSS[092]
B13 U3
VSS[012] VSS[093] +VCC_CORE
B16 U6
VSS[013] VSS[094]
B19 VSS[014] VSS[095] U21
B21 U24
VSS[015] VSS[096]
B24 VSS[016] VSS[097] V2 1 1 1 1 1 1 1 1
C5 V5 C915 C916 C917 C918 C919 C920 C921 C922
VSS[017] VSS[098] Place these capacitors on L8
C8 V22
VSS[018] VSS[099] (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
C11 V25
VSS[019] VSS[100] 2 2 2 2 2 2 2 2
C14 VSS[020] VSS[101] W1
C16 VSS[021] VSS[102] W4
C19 W23
VSS[022] VSS[103]
C2 VSS[023] VSS[104] W26
C22 Y3 +VCC_CORE
VSS[024] VSS[105]
C25 Y6
VSS[025] VSS[106]
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24 1 1 1 1 1 1 1 1
D8 AA2 C923 C924 C925 C926 C927 C928 C929 C930
VSS[028] VSS[109] Place these capacitors on L8
D11 AA5
C VSS[029] VSS[110] (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M C
D13 VSS[030] VSS[111] AA8
D16 AA11 2 2 2 2 2 2 2 2
VSS[031] VSS[112]
D19
D23
VSS[032] VSS[113]
AA14
AA16
Mid Frequence Decoupling
VSS[033] VSS[114]
D26 VSS[034] VSS[115] AA19
E3 AA22
VSS[035] VSS[116]
E6 VSS[036] VSS[117] AA25
E8 AB1
VSS[037] VSS[118]
E11 VSS[038] VSS[119] AB4
E14 AB8
VSS[039] VSS[120]
E16 VSS[040] VSS[121] AB11
E19 AB13
VSS[041] VSS[122]
E21 VSS[042] VSS[123] AB16
E24 AB19
VSS[043] VSS[124]
F5 AB23
VSS[044] VSS[125]
F8 AB26
VSS[045] VSS[126]
F11 AC3
VSS[046] VSS[127]
F13 AC6
VSS[047] VSS[128]
F16 AC8
F19
F2
VSS[048]
VSS[049]
VSS[129]
VSS[130] AC11
AC14
ESR <= 1.5m ohm
VSS[050] VSS[131] Near CPU CORE regulator
F22
F25
VSS[051]
VSS[052]
VSS[132]
VSS[133]
AC16
AC19
Capacitor > 1980uF
G4 AC21
VSS[053] VSS[134]
G1 AC24
VSS[054] VSS[135]
G23 AD2
VSS[055] VSS[136]
G26 VSS[056] VSS[137] AD5
H3 AD8 +VCC_CORE
VSS[057] VSS[138]
H6 AD11
VSS[058] VSS[139] 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7
H21 AD13
VSS[059] VSS[140]
H24 AD16
VSS[060] VSS[141] 0314 change to mount
J2 AD19
B VSS[061] VSS[142] B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25 1 1 1 1 1 1 1
J25 AE1
VSS[064] VSS[145] C931 + C932 + C933 + C935 + C936 + C937 + C934 + @
K1 VSS[065] VSS[146] AE4
K4 AE8 820U_E9_2_5V_M_R7
VSS[066] VSS[147] 330U_D2E_2.5VM_R7
K23 AE11
VSS[067] VSS[148] 2 2 2 2 2 2 2
K26 AE14
VSS[068] VSS[149]
L3 AE16
VSS[069] VSS[150]
L6 AE19
VSS[070] VSS[151] 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
M2 A2
VSS[073] VSS[154]
M5 VSS[074] VSS[155] AF6
M22 AF8
VSS[075] VSS[156]
M25 AF11 Place these inside
VSS[076] VSS[157]
N1 AF13 socket cavity on L8
VSS[077] VSS[158]
N4 AF16 (North side
VSS[078] VSS[159]
N23 AF19
VSS[079] VSS[160] Secondary)
N26 AF21
VSS[080] VSS[161]
P3 A25
VSS[081] VSS[162] +VCCP
AF25
VSS[163]
Merom Ball-out Rev 1a
conn@ . 1 1 1 1 1 1
C940 C941 C942 C943 C944 C945

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(3/3)-GND&Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 6 of 55
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] 4 U15B For Crestline: 20ohm

5 H_D#[0..63] U15A For Calero: 80.6ohm
J13 H_A#3 P36
H_D#0 H_A#_3 H_A#4 RSVD1 M_CLK_DDR0
E2 H_D#_0 H_A#_4 B11 P37 RSVD2 SM_CK_0 AV29 M_CLK_DDR0 13
H_D#1 G2 C11 H_A#5 R35 BB23 M_CLK_DDR1 M_CLK_DDR1 13
H_D#2 H_D#_1 H_A#_5 H_A#6 RSVD3 SM_CK_1 M_CLK_DDR2
G7 H_D#_2 H_A#_6 M11 N35 RSVD4 SM_CK_3 BA25 M_CLK_DDR2 14
H_D#3 M6 C15 H_A#7 AR12 AV23 M_CLK_DDR3

2.2U_0603_6.3V4Z
H_D#_3 H_A#_7 RSVD5 SM_CK_4 M_CLK_DDR3 14

0.01U_0402_25V7K
H_D#4 H7 F16 H_A#8 +1.8V AR13
H_D#5 H_D#_4 H_A#_8 H_A#9 RSVD6 M_CLK_DDR#0
H3 H_D#_5 H_A#_9 L13 AM12 RSVD7 SM_CK#_0 AW30 M_CLK_DDR#0 13
H_D#6 G4 G17 H_A#10 2 2 AN13 BA23 M_CLK_DDR#1
H_D#_6 H_A#_10 RSVD8 SM_CK#_1 M_CLK_DDR#1 13

1
H_D#7 F3 C14 H_A#11 J12 AW25 M_CLK_DDR#2
H_D#_7 H_A#_11 RSVD9 SM_CK#_3 M_CLK_DDR#2 14

RSVD
H_D#8 N8 K16 H_A#12 R1437 AR37 AW23 M_CLK_DDR#3
H_D#_8 H_A#_12 RSVD10 SM_CK#_4 M_CLK_DDR#3 14

C1102

C1103
H_D#9 H2 B13 H_A#13 AM36
H_D#10 H_D#_9 H_A#_13 H_A#14 1 1 1K_0402_1% RSVD11 DDR_CKE0_DIMMA
M10 L16 AL36 BE29 DDR_CKE0_DIMMA 13
H_D#11 H_D#_10 H_A#_14 H_A#15 RSVD12 SM_CKE_0 DDR_CKE1_DIMMA
N12 J17 AM37 AY32 DDR_CKE1_DIMMA 13

2
D H_D#12 H_D#_11 H_A#_15 H_A#16 SMRCOMP_VOH RSVD13 SM_CKE_1 DDR_CKE2_DIMMB D
N9 H_D#_12 H_A#_16 B14 D20 RSVD14 SM_CKE_3 BD39 DDR_CKE2_DIMMB 14
H_D#13 H5 K19 H_A#17 BG37 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SM_CKE_4 DDR_CKE3_DIMMB 14

1
H_D#14 P13 P15 H_A#18
H_D#15 H_D#_14 H_A#_18 H_A#19 R31 DDR_CS0_DIMMA#
K9 R17 BG20 DDR_CS0_DIMMA# 13
H_D#16 H_D#_15 H_A#_19 H_A#20 3.01K_0402_1% SM_CS#_0 DDR_CS1_DIMMA#
M2 B16 BK16 DDR_CS1_DIMMA# 13
H_D#17 H_D#_16 H_A#_20 H_A#21 NA lead free SM_CS#_1 DDR_CS2_DIMMB#
W10 H_D#_17 H_A#_21 H20 SM_CS#_2 BG16 DDR_CS2_DIMMB# 14
H_D#18 Y8 L19 H_A#22 H10 BE13 DDR_CS3_DIMMB#
DDR_CS3_DIMMB# 14

2
H_D#_18 H_A#_22 RSVD20 SM_CS#_3

MUXING
H_D#19 V4 D17 H_A#23 SMRCOMP_VOL B51
H_D#20 H_D#_19 H_A#_23 H_A#24 RSVD21 M_ODT0
M3 H_D#_20 H_A#_24 M17 BJ20 RSVD22 SM_ODT_0 BH18 M_ODT0 13

1
2.2U_0603_6.3V4Z

0.01U_0402_25V7K
H_D#21 J1 N16 H_A#25 BK22 BJ15 M_ODT1 M_ODT1 13
H_D#22 H_D#_21 H_A#_25 H_A#26 R1438 RSVD23 SM_ODT_1 M_ODT2 +1.8V
N5 H_D#_22 H_A#_26 J19 1 1 BF19 RSVD24 SM_ODT_2 BJ14 M_ODT2 14
H_D#23 N3 B18 H_A#27 BH20 BE16 M_ODT3
H_D#_23 H_A#_27 RSVD25 SM_ODT_3 M_ODT3 14
H_D#24 W6 E19 H_A#28 1K_0402_1% BK18 20_0402_1%
H_D#_24 H_A#_28 RSVD26

C1104

C1105
H_D#25 W9 B17 H_A#29 BJ18 BL15 SMRCOMP R1194 2 1

2
H_D#26 H_D#_25 H_A#_29 H_A#30 2 2 RSVD27 SM_RCOMP SMRCOMP#
N2 B15 BF23 BK14 2 1
H_D#27 H_D#_26 H_A#_30 H_A#31 RSVD28 SM_RCOMP#
Y7
H_D#_27 H_A#_31
E17 0612 add BG23
RSVD29
R1195 20_0402_1%
H_D#28 Y9 C18 H_A#32 BC23 BK31 SMRCOMP_VOH
H_D#29 H_D#_28 H_A#_32 H_A#33 RSVD30 SM_RCOMP_VOH SMRCOMP_VOL
P4 A19 BD24 BL31

DDR
H_D#30 H_D#_29 H_A#_33 H_A#34 RSVD31 SM_RCOMP_VOL
W3 H_D#_30 H_A#_34 B19 13 DDR_A_MA14 BJ29 RSVD32
H_D#31 N1 N19 H_A#35 BE24 AR49
H_D#_31 H_A#_35 14 DDR_B_MA14 RSVD33 SM_VREF_0
H_D#32 AD12 BH39 AW4 V_DDR_MCH_REF
H_D#33 H_D#_32 H_ADS# RSVD34 SM_VREF_1
AE3 G12 H_ADS# 4 AW20
H_D#34 H_D#_33 H_ADS# H_ADSTB#0 +3VS RSVD35
AD9 H17 BK20
H_D#35 H_D#_34
HOST H_ADSTB#_0 H_ADSTB#1 H_ADSTB#0 4
R1439 RSVD36
AC9 H_D#_35 H_ADSTB#_1 G20 H_ADSTB#1 4 C48 RSVD37
H_D#36 AC7 C8 H_BNR# PM_EXTTS#0 2 1 D47 B42 CLK_MCH_DREFCLK
H_D#_36 H_BNR# H_BNR# 4 RSVD38 DPLL_REF_CLK CLK_MCH_DREFCLK 15
H_D#37 AC14 E8 H_BPRI# B44 C42 CLK_MCH_DREFCLK#
H_D#38 H_D#_37 H_BPRI# H_BR0# H_BPRI# 4 RSVD39 DPLL_REF_CLK# MCH_SSCDREFCLK CLK_MCH_DREFCLK# 15
AD11 F12 10K_0402_5% C44 H48
H_D#39 H_D#_38 H_BREQ# H_DEFER# H_BR0# 4 RSVD40 DPLL_REF_SSCLK MCH_SSCDREFCLK# MCH_SSCDREFCLK 15
AC11 D6 H_DEFER# 4 A35 H47 MCH_SSCDREFCLK# 15
H_D#40 H_D#_39 H_DEFER# H_DBSY# R1440 RSVD41 DPLL_REF_SSCLK#
AB2 H_D#_40 H_DBSY# C10 H_DBSY# 4 B37 RSVD42
H_D#41 AD7 AM5 CLK_MCH_BCLK PM_EXTTS#1 2 1 B36 K44 CLK_MCH_3GPLL

CLK
H_D#42 H_D#_41 HPLL_CLK CLK_MCH_BCLK# CLK_MCH_BCLK 15 RSVD43 PEG_CLK CLK_MCH_3GPLL# CLK_MCH_3GPLL 15
AB1 AM7 CLK_MCH_BCLK# 15 B34 K45 CLK_MCH_3GPLL# 15
H_D#43 H_D#_42 HPLL_CLK# H_DPWR# 10K_0402_5% RSVD44 PEG_CLK#
Y3 H8 H_DPWR# 5 C34
C H_D#44 H_D#_43 H_DPWR# H_DRD Y# RSVD45 C
AC6 H_D#_44 H_DRDY# K7 H_DRDY# 4
H_D#45 AE2 E4 H_HIT# R1441
H_D#46 H_D#_45 H_HIT# H_HITM# H_HIT# 4 CLKREQ#_B DMI_TXN0
AC5 C6 H_HITM# 4 2 1 AN47 DMI_TXN0 20
H_D#47 H_D#_46 H_HITM# H_LOCK# <> DMI_RXN_0 DMI_TXN1
AG3 H_D#_47 H_LOCK# G10 H_LOCK# 4 DMI_RXN_1 AJ38 DMI_TXN1 20
H_D#48 AJ9 B7 H_TRDY# 10K_0402_5% AN42 DMI_TXN2
H_D#49 H_D#_48 H_TRDY# H_TRDY# 4 DMI_RXN_2 DMI_TXN3 DMI_TXN2 20
AH8 AN46 DMI_TXN3 20
H_D#50 H_D#_49 DMI_RXN_3
AJ14 H_D#_50
H_D#51 AE9 AM47 DMI_TXP0
H_D#52 H_D#_51 MCH_CLKSEL0 DMI_RXP_0 DMI_TXP1 DMI_TXP0 20
AE11 H_D#_52 15 MCH_CLKSEL0 P27 CFG_0 DMI_RXP_1 AJ39 DMI_TXP1 20
+VCCP H_D#53 AH12 K5 H_DINV#0 MCH_CLKSEL1 N27 AN41 DMI_TXP2
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 H_DINV#0 5 15 MCH_CLKSEL1 MCH_CLKSEL2 CFG_1 DMI_RXP_2 DMI_TXP3 DMI_TXP2 20
AJ5 H_D#_54 H_DINV#_1 L2 H_DINV#1 5 15 MCH_CLKSEL2 N24 CFG_2 DMI_RXP_3 AN45 DMI_TXP3 20
H_D#55 AH5 AD13 H_DINV#2 C21
H_D#_55 H_DINV#_2 H_DINV#2 5 CFG_3
H_D#56 AJ6 AE13 H_DINV#3 C23 AJ46 DMI_RXN0
H_D#_56 H_DINV#_3 H_DINV#3 5 CFG_4 DMI_TXN_0 DMI_RXN0 20
54.9_0402_1%

54.9_0402_1%

H_D#57 AE7 C FG5 F23 AJ41 DMI_RXN1

H_D#_57 9 CFG5 CFG_5 DMI_TXN_1 DMI_RXN1 20
1

H_D#58 AJ7 M7 H_DSTBN#0 C FG6 N23 AM40 DMI_RXN2

H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1 H_DSTBN#0 5 CFG6 C FG7 CFG_6 DMI_TXN_2 DMI_RXN3 DMI_RXN2 20
AJ2 K3 H_DSTBN#1 5 9 CFG7 G23 AM44 DMI_RXN3 20
H_D#_59 H_DSTBN#_1 CFG_7 DMI_TXN_3
R1196

R1197

H_D#60 AE5 AD2 H_DSTBN#2 J20

DMI
H_D#_60 H_DSTBN#_2 H_DSTBN#2 5 9 CFG8 CFG_8

CFG
H_D#61 AJ3 AH11 H_DSTBN#3 C FG9 C20 AJ47 DMI_RXP0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 5 9 CFG9 CFG_9 DMI_TXP_0 DMI_RXP0 20
H_D#62 AH2 CFG10 R24 AJ42 DMI_RXP1
CFG10 DMI_RXP1 20
2

H_D#63 H_D#_62 H_DSTBP#0 CFG11 CFG_10 DMI_TXP_1 DMI_RXP2

AH13 H_D#_63 H_DSTBP#_0 L7 H_DSTBP#0 5 CFG11 L23 CFG_11 DMI_TXP_2 AM39 DMI_RXP2 20
K2 H_DSTBP#1 CFG12 J23 AM43 DMI_RXP3
H_DSTBP#_1 H_DSTBP#1 5 9 CFG12 CFG_12 DMI_TXP_3 DMI_RXP3 20
AC2 H_DSTBP#2 CFG13 E23
H_SWNG H_DSTBP#_2 H_DSTBP#3 H_DSTBP#2 5 9 CFG13 CFG_13
B3 AJ10 H_DSTBP#3 5 E20
H_RCOMP H_SWING H_DSTBP#_3 CFG_14
C2 K23
H_RCOMP H_REQ#0 CFG16 CFG_15
M14 H_REQ#0 4 9 CFG16 M20
H_SCOMP H_REQ#_0 H_REQ#1 CFG_16

GRAPHICS VID
W1 E13 H_REQ#1 4 M24
H_SCOMP# H_SCOMP H_REQ#_1 H_REQ#2 CFG18 CFG_17
W2 H_SCOMP# H_REQ#_2 A11 H_REQ#2 4 CFG18 L32 CFG_18
H13 H_REQ#3 CFG19 N33
H_RESET# H_REQ#_3 H_REQ#4 H_REQ#3 4 9 CFG19 CFG20 CFG_19
4 H_RESET# B6 B12 H_REQ#4 4 9 CFG20 L35
H_CPUSLP# H_CPURST# H_REQ#_4 CFG_20
5 H_CPUSLP# E5
H_CPUSLP# H_RS#0
E12 H_RS#0 4
H_RS#_0 H_RS#1 DFGT_VID_0
D7 H_RS#1 4 E35 DFGT_VID_0 45
B H_RS#_1 H_RS#2 PM_BMBUSY# GFX_VID_0 DFGT_VID_1 B
H_RS#_2 D8 H_RS#2 4 20 PM_BMBUSY# G41 PM_BM_BUSY# GFX_VID_1 A39 DFGT_VID_1 45
B9 H_DPRSTP# L39 C38 DFGT_VID_2
H_VREF H_AVREF 5,19,43 H_DPRSTP# PM_EXTTS#0 PM_DPRSTP# GFX_VID_2 DFGT_VID_3 DFGT_VID_2 45
A9 13 PM_EXTTS#0 L36 B39 DFGT_VID_3 45
H_DVREF PM_EXT_TS#_0 GFX_VID_3

PM
PM_EXTTS#1 J36 E36 DFGT_VR_EN
14 PM_EXTTS#1 PM_EXT_TS#_1 GFX_VR_EN DFGT_VR_EN 45
CRESTLINE_1p0 PM_POK_R AW49
PLT_RST#_R PWROK +1.25VM_AXD
layout note: R1739 0_0402_5% AV20
RSTIN#
2 1 THERMTRIP# N20
4,19 H_THERMTRIP# THERMTRIP#
20,43 DPRSLPVR DPRSLPVR G36
DPRSLPVR

1
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
AM49 CL_CLK0 R1442
CL_CLK CL_DATA0 CL_CLK0 20
@ R1483 0_0402_5% 0612 add CL_DATA AK50 CL_DATA0 20

0.1U_0402_16V4Z
2 1 PM_POK_R 1128 Install R1739 BJ51 AT43 M_PWROK 1K_0402_1%
20,31,45 PM_PWROK NC_1 CL_PWROK CL_RST# M_PWROK 20,35
Layout Note:

ME
20,31 VGATE 2 1 BK51 AN49 CL_RST# 20

2
0309 add NC_2 CL_RST# CL_VREF CL_VREF
H_RCOMP / H_VREF / H_SWNG
R1484 0_0402_5% 1226 Add C 1 BK50
NC_3 CL_VREF
AM50
BL50 NC_4

1
C1370
trace width and spacing is 10/20 BL49
NC_5
0.1U_0402_16V4Z 1
Layout Note: BL3
NC_6
0621 add CLK and DAT for DVI R1443
2 BL2 C1106 392_0402_1%
V_DDR_MCH_REF +1.8V NC_7

NC
BK1
trace width and NC_8 SDVO_SCLK SDVO_SCLK 16 2
BJ1 H35

2
+VCCP NC_9 SDVO_CTRL_CLK SDVO_SDAT SDVO_SDAT 16

MISC
spacing is 20/20. E1
NC_10 SDVO_CTRL_DATA
K36
1

+VCCP A5 G39 CLKREQ#_B CLKREQ#_B 15

R1201 NC_11 CLK_REQ# M CH_ICH_SYNC#
C51 G40 MCH_ICH_SYNC# 20
NC_12 ICH_SYNC#
1K_0402_1%

221_0603_1%

@ 1K_0402_1% B50 NC_13

04/10 change size
1

A50
NC_14
R1206

A49 A37 DFGT_VID_0

2

NC_15 TEST_1
R1208

V_DDR_MCH_REF BK2 R32 DFGT_VID_1 +3VS

13,14,42 V_DDR_MCH_REF NC_16 TEST_2
0.1U_0402_16V4Z

DFGT_VID_3
1

1
0.1U_0402_16V4Z CRESTLINE_1p0
2

22K_0402_5%

22K_0402_5%

22K_0402_5%

22K_0402_5%
H_VREF H_RCOMP H_SWNG 1 R1204 R1444 R1445

1
0.1U_0402_16V4Z
24.9_0402_1%

C895

@ 1K_0402_1% 20K_0402_5% 0_0402_5%

1

1
2K_0402_1%

100_0402_1%

A A
1 1
2

2
2

R1786

R1787

R1788

R1789
R1446
R1212

C60

R1199

R1210

C896

PLT_RST#_R 2 1 PLT_RST#
PLT_RST# 16,18,22,30

2
DFGT_VID_2
2 2 100_0402_5%
2

0830 Add pull-up and pull-down resistor.

Security Classification Compal Secret Data Compal Electronics, Inc.

within 100 mils from NB Near B3 pin Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(1/6)-AGTL+/DMI/DDR2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 7 of 55
5 4 3 2 1
 5 4 3 2 1

D D

13 DDR_A_D[0..63] 14 DDR_B_D[0..63]
U15D U15E
DDR_A_D0 AR43 BB19 DDR_A_BS0 DDR_B_D0 AP49 AY17 DDR_B_BS0
DDR_A_D1 SA_DQ_0 SA_BS_0 DDR_A_BS1 DDR_A_BS0 13 DDR_B_D1 SB_DQ_0 SB_BS_0 DDR_B_BS1 DDR_B_BS0 14
AW44 BK19 DDR_A_BS1 13 AR51 BG18 DDR_B_BS1 14
DDR_A_D2 SA_DQ_1 SA_BS_1 DDR_A_BS2 DDR_B_D2 SB_DQ_1 SB_BS_1 DDR_B_BS2
BA45 SA_DQ_2 SA_BS_2 BF29 DDR_A_BS2 13 AW50 SB_DQ_2 SB_BS_2 BG36 DDR_B_BS2 14
DDR_A_D3 AY46 DDR_B_D3 AW51
DDR_A_D4 SA_DQ_3 DDR_A_CAS# DDR_B_D4 SB_DQ_3 DDR_B_CAS#
AR41 SA_DQ_4 SA_CAS# BL17 DDR_A_CAS# 13 AN51 SB_DQ_4 SB_CAS# BE17 DDR_B_CAS# 14
DDR_A_D5 AR45 DDR_B_D5 AN50
SA_DQ_5 DDR_A_DM[0..7] 13 SB_DQ_5 DDR_B_DM[0..7] 14
DDR_A_D6 AT42 AT45 DDR_A_DM0 DDR_B_D6 AV50 AR50 DDR_B_DM0
DDR_A_D7 SA_DQ_6 SA_DM_0 DDR_A_DM1 DDR_B_D7 SB_DQ_6 SB_DM_0 DDR_B_DM1
AW47 SA_DQ_7 SA_DM_1 BD44 AV49 SB_DQ_7 SB_DM_1 BD49
DDR_A_D8 BB45 BD42 DDR_A_DM2 DDR_B_D8 BA50 BK45 DDR_B_DM2
DDR_A_D9 SA_DQ_8 SA_DM_2 DDR_A_DM3 DDR_B_D9 SB_DQ_8 SB_DM_2 DDR_B_DM3
BF48 SA_DQ_9 SA_DM_3 AW38 BB50 SB_DQ_9 SB_DM_3 BL39
DDR_A_D10 BG47 AW13 DDR_A_DM4 DDR_B_D10 BA49 BH12 DDR_B_DM4
DDR_A_D11 SA_DQ_10 SA_DM_4 DDR_A_DM5 DDR_B_D11 SB_DQ_10 SB_DM_4 DDR_B_DM5
BJ45 BG8 BE50 BJ7
DDR_A_D12 SA_DQ_11 SA_DM_5 DDR_A_DM6 DDR_B_D12 SB_DQ_11 SB_DM_5 DDR_B_DM6
BB47 AY5 BA51 BF3
DDR_A_D13 SA_DQ_12 SA_DM_6 DDR_A_DM7 DDR_B_D13 SB_DQ_12 SB_DM_6 DDR_B_DM7
BG50 SA_DQ_13 SA_DM_7 AN6 AY49 SB_DQ_13 SB_DM_7 AW2
DDR_A_D14 BH49 DDR_B_D14 BF50
SA_DQ_14 DDR_A_DQS[0..7] 13 SB_DQ_14 DDR_B_DQS[0..7] 14
DDR_A_D15 BE45 AT46 DDR_A_DQS0 DDR_B_D15 BF49 AT50 DDR_B_DQS0

A
DDR_A_D16 SA_DQ_15 SA_DQS_0 DDR_A_DQS1 DDR_B_D16 SB_DQ_15 SB_DQS_0 DDR_B_DQS1
AW43 BE48 BJ50 BD50

B
DDR_A_D17 SA_DQ_16 SA_DQS_1 DDR_A_DQS2 DDR_B_D17 SB_DQ_16 SB_DQS_1 DDR_B_DQS2
BE44 BB43 BJ44 BK46
DDR_A_D18 SA_DQ_17 SA_DQS_2 DDR_A_DQS3 DDR_B_D18 SB_DQ_17 SB_DQS_2 DDR_B_DQS3
BG42 BC37 BJ43 BK39
DDR_A_D19 SA_DQ_18 SA_DQS_3 DDR_A_DQS4 DDR_B_D19 SB_DQ_18 SB_DQS_3 DDR_B_DQS4
BE40 SA_DQ_19 SA_DQS_4 BB16 BL43 SB_DQ_19 SB_DQS_4 BJ12
DDR_A_D20 DDR_A_DQS5 DDR_B_D20 DDR_B_DQS5

MEMORY
BF44 SA_DQ_20 SA_DQS_5 BH6 BK47 SB_DQ_20 SB_DQS_5 BL7
DDR_A_D21 DDR_A_DQS6 DDR_B_D21 DDR_B_DQS6

MEMORY
BH45 BB2 BK49 BE2
DDR_A_D22 SA_DQ_21 SA_DQS_6 DDR_A_DQS7 DDR_B_D22 SB_DQ_21 SB_DQS_6 DDR_B_DQS7
BG40 SA_DQ_22 SA_DQS_7 AP3 DDR_A_DQS#[0..7] 13 BK43 SB_DQ_22 SB_DQS_7 AV2 DDR_B_DQS#[0..7] 14
DDR_A_D23 BF40 AT47 DDR_A_DQS#0 DDR_B_D23 BK42 AU50 DDR_B_DQS#0
DDR_A_D24 SA_DQ_23 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D24 SB_DQ_23 SB_DQS#_0 DDR_B_DQS#1
AR40 BD47 BJ41 BC50
DDR_A_D25 SA_DQ_24 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D25 SB_DQ_24 SB_DQS#_1 DDR_B_DQS#2
AW40 SA_DQ_25 SA_DQS#_2 BC41 BL41 SB_DQ_25 SB_DQS#_2 BL45
DDR_A_D26 AT39 BA37 DDR_A_DQS#3 DDR_B_D26 BJ37 BK38 DDR_B_DQS#3
DDR_A_D27 SA_DQ_26 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D27 SB_DQ_26 SB_DQS#_3 DDR_B_DQS#4
AW36 BA16 BJ36 BK12
DDR_A_D28 SA_DQ_27 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D28 SB_DQ_27 SB_DQS#_4 DDR_B_DQS#5
AW41 BH7 BK41 BK7
C DDR_A_D29 SA_DQ_28 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D29 SB_DQ_28 SB_DQS#_5 DDR_B_DQS#6 C
AY41 SA_DQ_29 SA_DQS#_6 BC1 BJ40 SB_DQ_29 SB_DQS#_6 BF2
DDR_A_D30 AV38 AP2 DDR_A_DQS#7 DDR_B_D30 BL35 AV3 DDR_B_DQS#7
DDR_A_D31 SA_DQ_30 SA_DQS#_7 DDR_A_MA[0..13] 13 DDR_B_D31 SB_DQ_30 SB_DQS#_7
AT38 BK37 DDR_B_MA[0..13] 14
DDR_A_D32 SA_DQ_31 DDR_A_MA0 DDR_B_D32 SB_DQ_31 DDR_B_MA0
AV13 SA_DQ_32 SA_MA_0 BJ19 BK13 SB_DQ_32 SB_MA_0 BC18
SYSTEM

DDR_A_D33 AT13 BD20 DDR_A_MA1 DDR_B_D33 BE11 BG28 DDR_B_MA1

DDR_A_D34 SA_DQ_33 SA_MA_1 DDR_A_MA2 DDR_B_D34 SB_DQ_33 SB_MA_1

SYSTEM
AW11 BK27 BK11 BG25 DDR_B_MA2
DDR_A_D35 SA_DQ_34 SA_MA_2 DDR_A_MA3 DDR_B_D35 SB_DQ_34 SB_MA_2 DDR_B_MA3
AV11 SA_DQ_35 SA_MA_3 BH28 BC11 SB_DQ_35 SB_MA_3 AW17
DDR_A_D36 AU15 BL24 DDR_A_MA4 DDR_B_D36 BC13 BF25 DDR_B_MA4
DDR_A_D37 SA_DQ_36 SA_MA_4 DDR_A_MA5 DDR_B_D37 SB_DQ_36 SB_MA_4 DDR_B_MA5
AT11 SA_DQ_37 SA_MA_5 BK28 BE12 SB_DQ_37 SB_MA_5 BE25
DDR_A_D38 BA13 BJ27 DDR_A_MA6 DDR_B_D38 BC12 BA29 DDR_B_MA6
DDR_A_D39 SA_DQ_38 SA_MA_6 DDR_A_MA7 DDR_B_D39 SB_DQ_38 SB_MA_6 DDR_B_MA7
BA11 SA_DQ_39 SA_MA_7 BJ25 BG12 SB_DQ_39 SB_MA_7 BC28
DDR_A_D40 BE10 BL28 DDR_A_MA8 DDR_B_D40 BJ10 AY28 DDR_B_MA8
DDR_A_D41 SA_DQ_40 SA_MA_8 DDR_A_MA9 DDR_B_D41 SB_DQ_40 SB_MA_8 DDR_B_MA9
BD10 SA_DQ_41 SA_MA_9 BA28 BL9 SB_DQ_41 SB_MA_9 BD37
DDR_A_D42 BD8 BC19 DDR_A_MA10 DDR_B_D42 BK5 BG17 DDR_B_MA10
DDR_A_D43 SA_DQ_42 SA_MA_10 DDR_A_MA11 DDR_B_D43 SB_DQ_42 SB_MA_10 DDR_B_MA11
AY9 BE28 BL5 BE37
DDR_A_D44 SA_DQ_43 SA_MA_11 DDR_A_MA12 DDR_B_D44 SB_DQ_43 SB_MA_11 DDR_B_MA12
BG10 BG30 BK9 BA39
DDR_A_D45 SA_DQ_44 SA_MA_12 DDR_A_MA13 DDR_B_D45 SB_DQ_44 SB_MA_12 DDR_B_MA13
AW9 BJ16 BK10 BG13
SA_DQ_45 SA_MA_13 SB_DQ_45 SB_MA_13
DDR

DDR_A_D46 BD7 DDR_B_D46 BJ8

SA_DQ_46 SB_DQ_46

DDR
DDR_A_D47 BB9 DDR_B_D47 BJ6 AV16 DDR_B_RAS#
DDR_A_D48 SA_DQ_47 DDR_A_RAS# DDR_B_D48 SB_DQ_47 SB_RAS# SB_RCVEN# DDR_B_RAS# 14
BB5 SA_DQ_48 SA_RAS# BE18 DDR_A_RAS# 13 BF4 SB_DQ_48 SB_RCVEN# AY18
DDR_A_D49 AY7 AY20 SA_RCVEN# DDR_B_D49 BH5 T4
DDR_A_D50 SA_DQ_49 SA_RCVEN# T5 DDR_B_D50 SB_DQ_49 DDR_B_WE#
AT5 BG1 BC17 DDR_B_WE# 14
DDR_A_D51 SA_DQ_50 DDR_A_WE# DDR_B_D51 SB_DQ_50 SB_WE#
AT7 BA19 DDR_A_WE# 13 BC2
DDR_A_D52 SA_DQ_51 SA_WE# DDR_B_D52 SB_DQ_51
AY6 BK3
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52
BB7 BE4
DDR_A_D54 SA_DQ_53 DDR_B_D54 SB_DQ_53
AR5 BD3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AR8 SA_DQ_55 BJ2 SB_DQ_55
DDR_A_D56 AR9 DDR_B_D56 BA3
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AN3 BB3
DDR_A_D58 SA_DQ_57 DDR_B_D58 SB_DQ_57
AM8 AR1
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AN10 AT3
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59
AT9 AY2
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AN9 SA_DQ_61 AY3 SB_DQ_61
DDR_A_D62 AM9 DDR_B_D62 AU2
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AN11 AT2
SA_DQ_63 SB_DQ_63
CRESTLINE_1p0 CRESTLINE_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 8 of 55
5 4 3 2 1
 5 4 3 2 1

For Crestline:2.4kohm
For Calero: 1.5Kohm
0314 add
PEGCOMP trace width
U15C
R1176
+VCCP
and spacing is 20/25 mils. Strap Pin Table
17 BLON_PWM BLON_PWM J40 24.9_0402_1%
ENABLT L_BKLT_CTRL PEGCOMP
17 ENABLT H39 L_BKLT_EN PEG_COMPI N43 1 2
+3VS R95 1 2 10K_0402_5% E39 M43 010 = FSB 800MHz
R160 1 L_CTRL_CLK PEG_COMPO
2 10K_0402_5% E40 L_CTRL_DATA
DDC2_CLK C37 CFG[2:0] FSB Freq select 011 = FSB 667MHz
17 DDC2_CLK L_DDC_CLK
DDC2_DATA D35 J51
17 DDC2_DATA ENAVDD L_DDC_DATA PEG_RX#_0 PEG_RXN1
17 ENAVDD K40
L_VDD_EN PEG_RX#_1
L51 PEG_RXN1 16 Others = Reserved
2.4K_0402_1% N47
PEG_RX#_2
2 1 L41 T45
R1447 LVDS_IBG PEG_RX#_3
D
L43 LVDS_VBG PEG_RX#_4 T50 0 = DMI x 2 D
N41 LVDS_VREFH PEG_RX#_5 U40 CFG5 (DMI select)
N40 Y44 1 = DMI x 4
17
17
TXCLK_L-
TXCLK_L+
TXCLK_L-
TXCLK_L+
D46
C45
LVDS_VREFL
LVDSA_CLK#
PEG_RX#_6
PEG_RX#_7 Y40
AB51
*
TXCLK_U- LVDSA_CLK PEG_RX#_8
17 TXCLK_U- D44
LVDSB_CLK# PEG_RX#_9
W49 CFG6 Reserved
17 TXCLK_U+ TXCLK_U+ E42 AD44
LVDSB_CLK PEG_RX#_10

LVDS
AD40
TXOUT_L0- PEG_RX#_11
17 TXOUT_L0- G51 LVDSA_DATA#_0 PEG_RX#_12 AG46 CFG7 (CPU Strap) 0 = Reserved
TXOUT_L1- E51 AH49
17 TXOUT_L1- LVDSA_DATA#_1 PEG_RX#_13
TXOUT_L2- F49 AG45 1 = Mobile CPU
17 TXOUT_L2- LVDSA_DATA#_2 PEG_RX#_14
PEG_RX#_15 AG41 *

GRAPHICS
TXOUT_L0+ G50 J50 0 = Normal mode
17 TXOUT_L0+ LVDSA_DATA_0 PEG_RX_0
TXOUT_L1+ E50 L50 PEG_RXP1 CFG8 (Low power PCIE)
17 TXOUT_L1+ LVDSA_DATA_1 PEG_RX_1 PEG_RXP1 16
TXOUT_L2+ F48 M47 1 = Low Power mode
17 TXOUT_L2+ LVDSA_DATA_2 PEG_RX_2
PEG_RX_3
U44
T49
*
TXOUT_U0- PEG_RX_4
17 TXOUT_U0- G44
LVDSB_DATA#_0 PEG_RX_5
T41 CFG9 0 = Reverse Lane
17 TXOUT_U1- TXOUT_U1- B47 W45
TXOUT_U2- LVDSB_DATA#_1 PEG_RX_6
B45 W41 (PCIE Graphics Lane Reversal) 1 = Normal Operation
17 TXOUT_U2- LVDSB_DATA#_2 PEG_RX_7
PEG_RX_8
AB50
Y48
*
TXOUT_U0+ PEG_RX_9
17 TXOUT_U0+ E44 LVDSB_DATA_0 PEG_RX_10 AC45
TXOUT_U1+ A47 AC41 CFG[11:10] Reserved
17 TXOUT_U1+ LVDSB_DATA_1 PEG_RX_11
TXOUT_U2+ A45 AH47
17 TXOUT_U2+ LVDSB_DATA_2 PEG_RX_12
AG49

PCI-EXPRESS
M_COMP PEG_RX_13
AH45
00 = Reserved
M_COMP PEG_RX_14 01 = XOR Mode Enabled
M_LUMA AG42 CFG[13:12] (XOR/ALLZ)
M_LUMA PEG_RX_15
M_CRMA M_CRMA 10 = All Z Mode Enabled
E27 N45 PEG_TXN0 C1058 1 2 0.1U_0402_16V4Z 11 = Normal Operation (Default)
TVA_DAC PEG_TX#_0 SDVOB_R- 16
*
1

1
75_0402_1%

75_0402_1%

75_0402_1%

0622 change value R177 G27 U39 PEG_TXN1 C1059 1 2 0.1U_0402_16V4Z SDVOB_G- 16
TVB_DAC PEG_TX#_1
R175 K27 U47 PEG_TXN2 C1060 1 2 0.1U_0402_16V4Z SDVOB_B- 16
TVC_DAC PEG_TX#_2

TV
C C
R176
PEG_TX#_3 N51 PEG_TXN3 C1061 1 2 0.1U_0402_16V4Z SDVOB_CLK- 16 CFG[15:14] Reserved
F27 R50
TVA_RTN PEG_TX#_4
J27 T42
2

TVB_RTN PEG_TX#_5
L27 TVC_RTN PEG_TX#_6 Y43 CFG16 (FSB Dynamic ODT) 0 = Disabled
PEG_TX#_7 W46
2.2K_0402_5% M35 W38 1 = Enabled
+3VS R94 1 2
0314 add
P33
TV_DCONSEL_0
TV_DCONSEL_1
PEG_TX#_8
PEG_TX#_9 AD39
AC46
*
PEG_TX#_10
PEG_TX#_11 AC49 CFG[18:17] Reserved
M_BLUE AC42
M_BLUE M_GREEN PEG_TX#_12
M_GREEN PEG_TX#_13 AH39
M_RED AE49 0 = No SDVO Device Present
M_RED PEG_TX#_14
PEG_TX#_15 AH44 SDVO_CTRLDATA *
1

1
75_0402_1%

75_0402_1%

1 = SDVO Device Present

75_0402_1%

0314 change design R180 R182 H32 M45 PEG_TXP0 C1062 1 2 0.1U_0402_16V4Z SDVOB_R+ 16
CRT_BLUE PEG_TX_0
G32 T38 PEG_TXP1 C1063 1 2 0.1U_0402_16V4Z SDVOB_G+ 16
CRT_BLUE# PEG_TX_1
R181 K29 T46 PEG_TXP2 C1066 1 2 0.1U_0402_16V4Z 0 = Normal Operation
0821 J29
CRT_GREEN PEG_TX_2
N50 PEG_TXP3 C1067 1 2 0.1U_0402_16V4Z
SDVOB_B+ 16
SDVOB_CLK+ 16 CFG19 (DMI Lane Reversal) (Lane number in Order) *
2

CRT_GREEN# PEG_TX_3
F29 R51
CRT_RED PEG_TX_4
VGA

1013 change value E29 CRT_RED# PEG_TX_5 U43 1 = Reverse Lane

W42
PEG_TX_6
Y47
DDC1_CLK PEG_TX_7
K33 Y39 0 = Only PCIE or SDVO is operational.
16 DDC1_CLK
16 DDC1_DATA
DDC1_DATA
M _HSYNC R165 1 2 H S YNC
G35
F33
CRT_DDC_CLK
CRT_DDC_DATA
PEG_TX_8
PEG_TX_9
AC38
AD47
CFG20 (PCIE/SDVO concurrent)
1 = PCIE/SDVO are operating simu.
*
16 M_HSYNC CRT_HSYNC PEG_TX_10
30.1_0402_1% C32 AC50
M_VSYNC R166 1 VSYNC CRT_TVO_IREF PEG_TX_11
16 M_VSYNC 2 E33 CRT_VSYNC PEG_TX_12 AD43
30.1_0402_1% AG39
PEG_TX_13
1

AE50 R1151 1 2 @ 4.02K_0402_1%

PEG_TX_14 7 CFG5
1.15K_0402_1%

0821 PEG_TX_15
AH43 0809 Add MAX9511
R1449
B
1013 change value 1013 Remove MAX9511 7 CFG7
R1152 1 2 @ 4.02K_0402_1%
B
CRESTLINE_1p0
2

2.2K_0402_5% R1451 1 2 @ 4.02K_0402_1%

DDC2_CLK 7 CFG8
+3VS R92 1 2
R158 1 2 DDC2_DATA
2.2K_0402_5% R1153 1 2 @ 4.02K_0402_1%
7 CFG9
For Crestline:1.3kohm
For Calero: 255ohm
R1155 1 2 @ 4.02K_0402_1%
7 CFG12

R1156 1 2 @ 4.02K_0402_1%
7 CFG13

TV-Out Termination/EMI Filter Place clo se to U15 CRT Termination/EMI Filter Place C losed to U15
7 CFG16
R1157 1 2 @ 4.02K_0402_1%
L28 L31
M_COMP L38 1 2 COMP 16,33 1 2 C_RED_L 1 2 R ED
M_COMP M_RED RED 33
CHB1608U301_0603 HLC0603CSCC39NJT_0603 HLC0603CSCCR11JT_0603
L35 L34 CFG[17:3] have internal pull up
M_LUMA L37 1 2 1 2 C_GRN_L 1 2 GREEN
M_LUMA LUMA 16,33 M_GREEN GREEN 33 +3VS
CHB1608U301_0603 HLC0603CSCC39NJT_0603 HLC0603CSCCR11JT_0603 CFG[19:18] have internal pull down
L27 L26
M_CRMA L17 1 2 1 2 C_BLU_L 1 2 BLUE
M_CRMA CRMA 16,33 M_BLUE BLUE 33
CHB1608U301_0603 HLC0603CSCC39NJT_0603 HLC0603CSCCR11JT_0603 R1159 1 2 @ 4.02K_0402_1%
7 CFG19
10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
5.6P_0402_50V8D

5.6P_0402_50V8D

1 1 1
5.6P_0402_50V8D

5.6P_0402_50V8D

1 1 1 1 1 1 1 1 1
C253 1 1 1 R1160 1 2 @ 4.02K_0402_1%
7 CFG20
C251 @ C194 C237 C232 @ C195
2 2 2
@ C233 C193
J37
2 2 2 C243 2 2 2 22P_0402_50V8J 22P_0402_50V8J 2 2 2
C238 2 2 2 C FG5 2 1
C8 10P_0402_50V8J
A C7 5.6P_0402_50V8D 0314 change design 10P_0402_50V8J 22P_0402_50V8J @ C244 @ C245 A
5.6P_0402_50V8D @ C240 PAD-NO SHORT 2x2m

0314 change design

Note: CRT / TV-out should route to JP30 first then to the JP1 & JP2 on system side.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((3/6)-VGA/LVDS/TV
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 9 of 55
5 4 3 2 1
 5 4 3 2 1

+3VS VCC SYNC

+3VS_DAC_BG +3VS R1452
MBK1608102YZF 0603 2 1
2 1 0_0603_5%
0.022U_0402_16V7K

22U_0805_6.3V

0.1U_0402_16V4Z
R1453 1
+1.25VS_DPLLB +1.25VS

0.1U_0402_16V4Z
+V1.25VS_AXF
+VCCP R1454
1 1 1 C1107

C1375
1 2 +1.25VS 1 2
2
C1108

C1109

0.1U_0402_16V4Z

10U_0805_10V4Z

1U_0603_10V4Z
U 15H

22U_0805_6.3VAM
10U_FLC-453232-100K_0.25A_10% R1455
2 2 2 330U_D2E_2.5VM_R7 0_0603_5%
J32 U13 1 1 1 1
VCCSYNC VTT_1

4.7U_0805_10V4Z

C1110

C1111

C1112
0621 Change R to BLM18PG1SN1D VTT_2
U12

C1231
A33 U11 1 1
VCCA_CRT_DAC_1 VTT_3
+3VS_DAC_CRT B33 U9
VCCA_CRT_DAC_2 VTT_4 + 2 2 2 2

C838
U8 C830
VTT_5

CRT
U7 0619 change
VTT_6 2
D
+3VS_DAC_CRT +3VS_DAC_BG A30 VCCA_DAC_BG VTT_7 U5 D
+3VS 2
VTT_8 U3
BLM18PG181SN1D_0603 B32 U2 0316 add
VSSA_DAC_BG VTT_9
2 1 VTT_10 U1
0.022U_0402_16V7K

R1456 T13
VTT_11 +1.25VS_DMI +1.8V_SM_CK
0.1U_0402_16V4Z

VTT
B49 T11 +1.25VS 0619 change value +1.8V
+1.25VS_DPLLA VCCA_DPLLA VTT_12

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
1 1 T10 R1458
VTT_13
+1.25VS_DPLLB H49 VCCA_DPLLB VTT_14 T9 1 1 1 1 2 1 2
C1113

C1114

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z
T7 0_0805_5%
VTT_15

0.1U_0402_16V4Z
PLL

C849

C836

C837
+1.25VM_HPLL AL2 T6 R1457 1 1
2 2 VCCA_HPLL VTT_16 0_0603_5%
T5 1
VTT_17 2 2 2

C1230

C1115

C1116
+1.25VM_MPLL AM2 VCCA_MPLL VTT_18 T3 1

C1117
VTT_19 T2
R3 2 2
VTT_20 2

A LVDS
+1.8V_TXLVDS 1000P_0402_50V7K A41 R2
VCCA_LVDS VTT_21 2
1 R1
C1118 VTT_22 +1.25VM_AXD
B41
VSSA_LVDS R1671
+3VS_PEG_BG
AT23 1 2 +1.25VM
R1459 2 VCC_AXD_1 0_0805_5%
AU28
VCC_AXD_2

1U_0603_10V4Z

10U_0805_10V4Z
+3VS 2 1 K50 AU24 1 1
VCCA_PEG_BG VCC_AXD_3 +1.25VS_PEGPLL

AXD

C1119

C1120
0_0603_5% AT29 +1.25VS
VCC_AXD_4 L77 +1.5VS_TVDAC +1.5VS
1 K49 AT25
VSSA_PEG_BG VCC_AXD_5

A PEG
0.1U_0402_16V4Z AT30 BLM18PG121SN1D_0603 R1460
VCC_AXD_6 2 2
2 1 1 2

0.022U_0402_16V7K

0.1U_0402_16V4Z
C1121 +1.25VS_PEGPLL 20 mils U51 VCCA_PEG_PLL VCC_AXD_NCTF AR29 0_0805_5%
2

0.1U_0402_16V4Z

10U_0805_10V4Z
1 1 1 1

C1122

C1123
AW18 B23 +V1.25VS_AXF
VCCA_SM_1 VCC_AXF_1

C1124

C1125
AV19 B21
VCCA_SM_2
POWER VCC_AXF_2

AXF
AU19 A21
VCCA_SM_3 VCC_AXF_3 2 2 2 2
+1.25VM_A_SM AU18 VCCA_SM_4
AU17 VCCA_SM_5 VCC_DMI AJ50 +1.25VS_DMI
R1461 0317 change value

A SM
+1.25VM 1 2 AT22
C
0_0805_5% VCCA_SM_7 C
1 AT21 BK24 +1.8V_SM_CK
VCCA_SM_8 VCC_SM_CK_1

SM CK
1 1 1 AT19 VCCA_SM_9 VCC_SM_CK_2 BK23
C1126 + C1127 C1128 C1129 AT18 BJ24
VCCA_SM_10 VCC_SM_CK_3
AT17 VCCA_SM_11 VCC_SM_CK_4 BJ23
150U_D_6.3VM 22U_0805_6.3VAM 4.7U_0805_10V4Z AR17 +1.25VM_HPLL
2 2 2 2 VCCA_SM_NCTF_1 +1.25VS_DPLLA R1464 +1.25VM
AR16 R1463
1U_0603_10V4Z VCCA_SM_NCTF_2
R1462 +1.25VM_A_SM_CK
A43 +1.8V_TXLVDS 1 2 +1.25VS 2 1
VCC_TX_LVDS

10U_0805_10V4Z
A CK
2 1 BC29 MBK2012121YZF_0805
VCCA_SM_CK_1 +3VS_HV
1U_0402_6.3V4Z

22U_0805_6.3VAM

1U_0603_10V4Z

0.1U_0402_16V4Z

0_0603_5% BB29 1 10U_FLC-453232-100K_0.25A_10%

VCCA_SM_CK_2

220U_D2_4VM
C40 1 1 1 1
VCC_HV_1

C1227

C1133

C1276
C25 B40 + C1134 C1135
1 1 1 1 +3VS_TVDACA VCCA_TVA_DAC_1 VCC_HV_2
C1226

C1130

C1131

C1132

HV
B25
VCCA_TVA_DAC_2

0.1U_0402_16V4Z
+3VS_TVDACB C27 0.1U_0402_16V4Z 10U_0805_10V4Z
VCCA_TVB_DAC_1 2 2 2 2 2
B27 AD51 +VCC_PEG 1
2 2 2 2 VCCA_TVB_DAC_2 VCC_PEG_1

C1136
TV

0316 add B28 W50

+3VS_TVDACC VCCA_TVC_DAC_1 VCC_PEG_2

PEG
A28 W51 0316 add
VCCA_TVC_DAC_2 VCC_PEG_3 0.1U_0402_16V4Z
V49
0317 change value VCC_PEG_4 2
V50
VCC_PEG_5
D TV/CRT

M32
VCCD_CRT
+1.5VS_TVDAC L29
VCCD_TVDAC
AH50 +VCCP
VCC_RXR_DMI_1 +1.25VM_MPLL
DMI

+1.5VS_QDAC N28
VCCD_QDAC VCC_RXR_DMI_2
AH51 04/10 stuff
20mils +VCC_PEG R1466 +1.25VM
+1.25VM_HPLL AN2 R1465
VCCD_HPLL
A7 2 1 2 1
VTTLF1
VTTLF

+1.25VS_PEGPLL U48 F2 0_0805_5% MBK2012121YZF_0805

VCCD_PEG_PLL VTTLF2

10U_0805_10V4Z
AH1 1
VTTLF3

220U_D2_4VM
J41 1 +1.25VS 1 1
VCCD_LVDS_1 0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

C1137

C1138
LVDS

1116 Change to BLM18PG181SN1D_0603 H42 + C1139 C1140

+1.8V_LVDS VCCD_LVDS_2
1 1 1 @ R1467
C1141

C1142

C1143
2 1 0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 0_0805_5% 2 2
+3VS_TVDACC +3VS CRESTLINE_1p0
B BLM18PG181SN1D_0603 2 2 2 04/10 no stuff B
2 1
0.022U_0402_16V7K

R1468
0.1U_0402_16V4Z

1 1
C1144

C1145

+VCCP_D
2 2

D12 R1469 R1470

1107 Change to 100 ohm +VCCP 2 1 2 1 2 1 +3VS_HV
10_0402_5% 0_0402_5%
CH751H-40PT_SOD323-2
+3VS
+1.5VS_QDAC +1.5VS
+3VS_TVDACA +3VS R1471
BLM18PG181SN1D_0603 2 1
0.022U_0402_16V7K

2 1 100_0603_1%
0.022U_0402_16V7K

0.1U_0402_16V4Z

R1472 1
+1.8V_TXLVDS
0.1U_0402_16V4Z

220U_D2_4VM

1 1 40 mils
C1374

+
1 1 R1476
C1146

C1147
C1148

C1149

1000P_0402_50V7K 2 1 +1.8V
2 2 2 0_0603_5%
2 2
1
1 220U_D2_4VM_R15
C1269 +
0119 Add C1374 C1285
20070301 Install C1374 2 2

+1.8V_LVDS
A +3VS_TVDACB +3VS A

BLM18PG181SN1D_0603 R1474
2 1 2 1 +1.8V
0.022U_0402_16V7K

10U_0805_10V4Z

R1473 0_0603_5%
0.1U_0402_16V4Z

1U_0603_10V4Z

1 1
C1150

C1151

1 1
C1152

C1153

2 2
2 2 Security Classification
2006/02/13
Compal Secret Data
2006/03/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(4/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C ustom LA-32 61P UMA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: Tuesday, March 27, 2007 Sheet 10 of 55
5 4 3 2 1
 5 4 3 2 1

+VCCP
U15G VCCGFX

AT35 VCC_1
AT34 VCC_2 VCC_AXG_NCTF_1 T17
AH28 T18
VCC_3 VCC_AXG_NCTF_2 0.1U_0402_16V4Z 4.7U_0603_6.3V6M
AC32 VCC_5 VCC_AXG_NCTF_3 T19
AC31 T21
VCC_4 VCC_AXG_NCTF_4
AK32 VCC_6 VCC_AXG_NCTF_5 T22 1 C1287 1 1

C1288
AJ31 T23 C1176
+VCCP VCC_7 VCC_AXG_NCTF_6
AJ28 VCC_8 VCC_AXG_NCTF_7 T25
D U15F D
AH32 VCC_9 VCC_AXG_NCTF_8 U15
2 2 2

VCC CORE
AH31 VCC_10 VCC_AXG_NCTF_9 U16
AB33 VCC_NCTF_1 AH29 VCC_11 VCC_AXG_NCTF_10 U17
AB36 AF32 U19 0.22U_0402_10V4Z
VCC_NCTF_2 VCC_12 VCC_AXG_NCTF_11
AB37 U20
VCC_NCTF_3 VCC_AXG_NCTF_12
AC33 VCC_NCTF_4 VSS_NCTF_1 T27 VCC_AXG_NCTF_13 U21
AC35 T37 R1475 U23 0316 add
VCC_NCTF_5 VSS_NCTF_2 VCC_AXG_NCTF_14
AC36 VCC_NCTF_6 VSS_NCTF_3 U24 1 2 R30 VCC_13 VCC_AXG_NCTF_15 U26
AD35 U28 0_0603_5% V16
VCC_NCTF_7 VSS_NCTF_4 VCC_AXG_NCTF_16
AD36 V31 V17
VCC_NCTF_8 VSS_NCTF_5 VCC_AXG_NCTF_17
AF33 VCC_NCTF_9 VSS_NCTF_6 V35 VCC_AXG_NCTF_18 V19
AF36 AA19 V20
VCC_NCTF_10 VSS_NCTF_7 VCC_AXG_NCTF_19
220U_D2_4VM_R15

22U_0805_6.3VAM

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z

AH33 VCC_NCTF_11 VSS_NCTF_8 AB17 VCC_AXG_NCTF_20 V21

VSS NCTF
1 AH35 AB35 V23
VCC_NCTF_12 VSS_NCTF_9 VCC_AXG_NCTF_21
1 1 1 1 AH36 AD19 V24
VCC_NCTF_13 VSS_NCTF_10 VCC_AXG_NCTF_22
C806

C803

C796

C798

C797

+ AH37 AD37 Y15

2 2 2 2 2
AJ33
AJ35
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
AF17
AF35
POWER VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
Y16
Y17
AK33 VCC_NCTF_17 VSS_NCTF_14 AK17 AU32 VCC_SM_1 VCC_AXG_NCTF_26 Y19
AK35 AM17 330U_D2E_2.5VM_R9 AU33 Y20
VCC_NCTF_18 VSS_NCTF_15 VCC_SM_2 VCC_AXG_NCTF_27
AK36 AM24 +1.8V AU35 Y21
VCC_NCTF_19 VSS_NCTF_16 VCC_SM_3 VCC_AXG_NCTF_28
AK37 AP26 AV33 Y23
VCC_NCTF_20 VSS_NCTF_17 VCC_SM_4 VCC_AXG_NCTF_29

0.01U_0402_16V7K
AD33 VCC_NCTF_21 VSS_NCTF_18 AP28 AW33 VCC_SM_5 VCC_AXG_NCTF_30 Y24

22U_0805_6.3VAM

22U_0805_6.3VAM
0317 change value AJ36 AR15 1 AW35 Y26
VCC_NCTF_22 VSS_NCTF_19 VCC_SM_6 VCC_AXG_NCTF_31

VCC NCTF
AM35 AR19 1 1 2 AY35 Y28
VCC_NCTF_23 VSS_NCTF_20 VCC_SM_7 VCC_AXG_NCTF_32

C809

C810

C794
AL33 AR28 C808 + BA32 Y29
VCC_NCTF_24 VSS_NCTF_21 VCC_SM_8 VCC_AXG_NCTF_33
AL35 BA33 AA16
VCC_NCTF_25 VCC_SM_9 VCC_AXG_NCTF_34
AA33 BA35 AA17
VCC_NCTF_26 2 2 2 1 VCC_SM_10 VCC_AXG_NCTF_35
AA35 VCC_NCTF_27 BB33 VCC_SM_11 VCC_AXG_NCTF_36 AB16
AA36 VCC_NCTF_28 BC32 VCC_SM_12 VCC_AXG_NCTF_37 AB19
AP35 BC33 AC16
VCC_NCTF_29 VCC_SM_13 VCC_AXG_NCTF_38
AP36 BC35 AC17
VCC_NCTF_30 VCC_SM_14 VCC_AXG_NCTF_39

VCC SM
C 0_0402_5% 0317 change value C
AR35 VCC_NCTF_31 BD32 VCC_SM_15 VCC_AXG_NCTF_40 AC19
AR36 0_0402_5% BD35 AD15
VCC_NCTF_32 0_0402_5% VCC_SM_16 VCC_AXG_NCTF_41
Y32 BE32 AD16
VCC_NCTF_33 0_0402_5% VCC_SM_17 VCC_AXG_NCTF_42
Y33 BE33 AD17
VCC_NCTF_34
POWER VCC_SM_18 VCC_AXG_NCTF_43

VCC GFX NCTF

Y35 0_0402_5% BE35 AF16
VCC_NCTF_35 0_0402_5% VCC_SM_19 VCC_AXG_NCTF_44
Y36 BF33 AF19
VCC_NCTF_36 MCHGND1 R112 VCC_SM_20 VCC_AXG_NCTF_45
Y37 VCC_NCTF_37 VSS_SCB1 A3 1 2 BF34 VCC_SM_21 VCC_AXG_NCTF_46 AH15
T30 B2 MCHGND2 R132 1 2 BG32 AH16
VCC_NCTF_38 VSS_SCB2 VCC_SM_22 VCC_AXG_NCTF_47
VSS SCB
T34 C1 MCHGND3 R133 1 2 BG33 AH17
VCC_NCTF_39 VSS_SCB3 MCHGND4 R122 VCC_SM_23 VCC_AXG_NCTF_48
T35 BL1 1 2 BG35 AH19
VCC_NCTF_40 VSS_SCB4 MCHGND5 R113 VCC_SM_24 VCC_AXG_NCTF_49
U29 VCC_NCTF_41 VSS_SCB5 BL51 1 2 BH32 VCC_SM_25 VCC_AXG_NCTF_50 AJ16
U31 A51 MCHGND6 R111 1 2 BH34 AJ17
VCC_NCTF_42 VSS_SCB6 VCC_SM_26 VCC_AXG_NCTF_51
U32 VCC_NCTF_43 BH35 VCC_SM_27 VCC_AXG_NCTF_52 AJ19
U33 BJ32 AK16
VCC_NCTF_44 VCC_SM_28 VCC_AXG_NCTF_53
U35 BJ33 AK19
VCC_NCTF_45 0314 add VCC_SM_29 VCC_AXG_NCTF_54
U36 BJ34 AL16
VCC_NCTF_46 VCC_SM_30 VCC_AXG_NCTF_55
V32
VCC_NCTF_47
1013 install R111,R113,R122,R132 BK32
VCC_SM_31 VCC_AXG_NCTF_56
AL17
V33
VCC_NCTF_48
1213 No-install R111,R113,R122,R132 BK33
VCC_SM_32 VCC_AXG_NCTF_57
AL19
V36
VCC_NCTF_49
0129 No-install R111,R113,R122,R132 BK34
VCC_SM_33 VCC_AXG_NCTF_58
AL20
V37 VCC_NCTF_50
20070227 Install R111,R113,R122,R132 BK35 VCC_SM_34 VCC_AXG_NCTF_59 AL21
BL33 AL23
+1.05VM VCC_SM_35 VCC_AXG_NCTF_60
AT33 +1.05VM AU30 AM15
VCC_AXM_1 VCC_SM_36 VCC_AXG_NCTF_61
AT31 AM16
VCC_AXM_2 VCC_AXG_NCTF_62
VCC AXM

AK29 AM19
VCC_AXM_3 VCC_AXG_NCTF_63
AK24 AM20
VCC_AXM_4 VCC_AXG_NCTF_64
10U_0805_10V4Z

10U_0805_10V4Z

AK23 AM21
VCC_AXM_5 VCC_AXG_NCTF_65
1 1 AL24 VCC_AXM_NCTF_1 VCC_AXM_6 AJ26 R20 VCC_AXG_1 VCC_AXG_NCTF_66 AM23
C1154

C1155

AL26 AJ23 T14 AP15

VCC_AXM_NCTF_2 VCC_AXM_7 VCC_AXG_2 VCC_AXG_NCTF_67
AL28 W13 AP16
VCC_AXM_NCTF_3 VCCGFX VCC_AXG_3 VCC_AXG_NCTF_68
04/10 monitor NB crack AM26
VCC_AXM_NCTF_4
W14
VCC_AXG_4 VCC_AXG_NCTF_69
AP17
2 2
VCC AXM NCTF

AM28 Y12 AP19

VCC_AXM_NCTF_5 10U_0805_10V4Z 0.1U_0402_16V4Z VCC_AXG_5 VCC_AXG_NCTF_70
AM29 AA20 AP20
B VCC_AXM_NCTF_6 VCC_AXG_6 VCC_AXG_NCTF_71 B
AM31 VCC_AXM_NCTF_7 AA23 VCC_AXG_7 VCC_AXG_NCTF_72 AP21
AM32 VCC_AXM_NCTF_8 1 AA26 VCC_AXG_8 VCC_AXG_NCTF_73 AP23
AM33 1 1 1 1 AA28 AP24
VCC_AXM_NCTF_9 C1175 C1286 + C812 VCC_AXG_9 VCC_AXG_NCTF_74
AP29 VCC_AXM_NCTF_10 AB21 VCC_AXG_10 VCC_AXG_NCTF_75 AR20
AP31 C811 C1156 AB24 AR21
VCC_AXM_NCTF_11 1U_0603_10V4Z VCC_AXG_11 VCC_AXG_NCTF_76
AP32 AB29 AR23
VCC_AXM_NCTF_12 2 2 2 2 2 VCC_AXG_12 VCC_AXG_NCTF_77
AP33 AC20 AR24
VCC_AXM_NCTF_13 VCC_AXG_13 VCC_AXG_NCTF_78

VCC GFX
AL29 AC21 AR26
VCC_AXM_NCTF_14 330U_D2E_2.5VM_R9 10U_0805_10V4Z VCC_AXG_14 VCC_AXG_NCTF_79
AL31 AC23 V26
VCC_AXM_NCTF_15 VCC_AXG_15 VCC_AXG_NCTF_80
AL32 VCC_AXM_NCTF_16 AC24 VCC_AXG_16 VCC_AXG_NCTF_81 V28
AR31 VCC_AXM_NCTF_17 AC26 VCC_AXG_17 VCC_AXG_NCTF_82 V29
AR32 AC28 Y31
VCC_AXM_NCTF_18 VCC_AXG_18 VCC_AXG_NCTF_83
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

AR33 VCC_AXM_NCTF_19 AC29 VCC_AXG_19

1 1 1 1 1 0316 change value AD20
VCC_AXG_20
C1157

C1158

C1159

C1160

C1161

AD23 VCC_AXG_21
AD24 AW45VCCSM_LF1
VCC_AXG_22 VCC_SM_LF1
AD28 BC39 VCCSM_LF2
2 2 2 2 2 VCC_AXG_23 VCC_SM_LF2

VCC SM LF
CRESTLINE_1p0 AF21 BE39 VCCSM_LF3
VCC_AXG_24 VCC_SM_LF3
AF26 BD17 VCCSM_LF4
VCC_AXG_25 VCC_SM_LF4
AA31 BD4 VCCSM_LF5
VCC_AXG_26 VCC_SM_LF5
AH20 AW8 VCCSM_LF6
VCC_AXG_27 VCC_SM_LF6
AH21 VCC_AXG_28 VCC_SM_LF7 AT6 VCCSM_LF7

C1162 0.1U_0402_16V4Z

C1163 0.1U_0402_16V4Z

C1318 0.22U_0603_10V7K

C795 0.22U_0603_10V7K

C1164 0.47U_0402_6.3V6K

C814 1U_0603_10V4Z

C813 1U_0603_10V4Z
04/10 monitor NB crack AH23
VCC_AXG_29 1 1 1 1 1 1 1
1013 no install AH24 VCC_AXG_30
1213 install AH26
VCC_AXG_31
0129 install AD31
VCC_AXG_32
20070227 No install 20070228 Change to +3VL 2 2 2 2 2 2 2
AJ20 VCC_AXG_33
AN14
VCC_AXG_34

+3VS +3VS +3VL

+3VS +3VS
A A
2
100K_0402_5%

100K_0402_5%
2
100K_0402_5%

100K_0402_5%

@ R1709 CRESTLINE_1p0
2

100K_0402_5% R1702
R1701 CRACK_GPIO28
@ CRACK_GPIO28 @ R1711 CRACK_GPIO28 @ R1703 CRACK_GPIO28
1 1
1

D CRACK_GPIO28 21,31
1
1

D D MCHGND2 D
2 Security Classification Compal Secret Data Compal Electronics, Inc.
1

MCHGND6 2 MCHGND4 2 G MCHGND5 2

G G @ Q121 S G Issued Date 2006/02/13 2006/03/10 Title
Deciphered Date
3

@ Q118 S @ Q123 S RHU002N06_SOT323 @ Q119 S

CRESTLINE((5/6)-PWR/GND
3

RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 11 of 55
5 4 3 2 1
 5 4 3 2 1

U15I

A13 VSS_1 VSS_100 AW24

A15 VSS_2 VSS_101 AW29
A17 AW32
VSS_3 VSS_102
A24 VSS_4 VSS_103 AW5
AA21 AW7
VSS_5 VSS_104
AA24 VSS_6 VSS_105 AY10
AA29 AY24
VSS_7 VSS_106 U15J
AB20 VSS_8 VSS_107 AY37
D D
AB23 VSS_9 VSS_108 AY42 C46 VSS_199 VSS_287 W11
AB26 VSS_10 VSS_109 AY43 C50 VSS_200 VSS_288 W39
AB28 VSS_11 VSS_110 AY45 C7 VSS_201 VSS_289 W43
AB31 AY47 D13 W47
VSS_12 VSS_111 VSS_202 VSS_290
AC10 AY50 D24 W5
VSS_13 VSS_112 VSS_203 VSS_291
AC13 VSS_14 VSS_113 B10 D3 VSS_204 VSS_292 W7
AC3 B20 D32 Y13
VSS_15 VSS_114 VSS_205 VSS_293
AC39 VSS_16 VSS_115 B24 D39 VSS_206 VSS_294 Y2
AC43 VSS_17 VSS_116 B29 D45 VSS_207 VSS_295 Y41
AC47 B30 D49 Y45
VSS_18 VSS_117 VSS_208 VSS_296
AD1 VSS_19 VSS_118 B35 E10 VSS_209 VSS_297 Y49
AD21 B38 E16 Y5
VSS_20 VSS_119 VSS_210 VSS_298
AD26 VSS_21 VSS_120 B43 E24 VSS_211 VSS_299 Y50
AD29 B46 E28 Y11
VSS_22 VSS_121 VSS_212 VSS_300
AD3 B5 E32 P29
VSS_23 VSS_122 VSS_213 VSS_301
AD41 B8 E47 T29
VSS_24 VSS_123 VSS_214 VSS_302
AD45 VSS_25 VSS_124 BA1 F19 VSS_215 VSS_303 T31
AD49 BA17 F36 T33
VSS_26 VSS_125 VSS_216 VSS_304
AD5 VSS_27 VSS_126 BA18 F4 VSS_217 VSS_305 R28
AD50 BA2 F40
VSS_28 VSS_127 VSS_218
AD8 BA24 F50
VSS_29 VSS_128 VSS_219
AE10 BB12 G1
VSS_30 VSS_129 VSS_220
AE14 VSS_31 VSS_130 BB25 G13 VSS_221 VSS_306 AA32
AE6 VSS_32 VSS_131 BB40 G16 VSS_222 VSS_307 AB32
AF20 BB44 G19 AD32
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
G24
G28
VSS_223
VSS_224
VSS_225
VSS_308
VSS_309
VSS_310
AF28
AF29
AF31 BC16 G29 AT27
VSS_36 VSS_135 VSS_226 VSS_311
AG2 VSS_37 VSS_136 BC24 G33 VSS_227 VSS_312 AV25
AG38 VSS_38 VSS_137 BC25 G42 VSS_228 VSS_313 H50
AG43 BC36 G45
VSS_39 VSS_138 VSS_229
AG47 BC40 G48
C VSS_40 VSS_139 VSS_230 C
AG50 VSS_41 VSS_140 BC51 G8 VSS_231
AH3 BD13 H24
VSS_42 VSS_141 VSS_232
AH40 BD2 H28
VSS_43 VSS_142 VSS_233
AH41 VSS_44 VSS_143 BD28 H4 VSS_234
AH7 VSS_45 VSS_144 BD45 H45 VSS_235
AH9 BD48 J11
VSS_46 VSS_145 VSS_236
AJ11 VSS_47 VSS_146 BD5 J16 VSS_237
AJ13 BE1 J2
VSS_48 VSS_147 VSS_238
AJ21 VSS_49 VSS_148 BE19 J24 VSS_239
AJ24 BE23 J28
VSS_50 VSS_149 VSS_240
AJ29 BE30 J33
AJ32
AJ43
VSS_51
VSS_52
VSS_53
VSS_150
VSS_151
VSS_152
BE42
BE51
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AJ45 BE8
VSS_54 VSS_153
AJ49 BF12 K12
VSS_55 VSS_154 VSS_245
AK20 BF16 K47
VSS_56 VSS_155 VSS_246
AK21 BF36 K8
VSS_57 VSS_156 VSS_247
AK26 BG19 L1
VSS_58 VSS_157 VSS_248
AK28 BG2 L17
VSS_59 VSS_158 VSS_249
AK31 VSS_60 VSS_159 BG24 L20 VSS_250
AK51 BG29 L24
VSS_61 VSS_160 VSS_251
AL1 BG39 L28
VSS_62 VSS_161 VSS_252
AM11 BG48 L3
VSS_63 VSS_162 VSS_253
AM13 BG5 L33
VSS_64 VSS_163 VSS_254
AM3 BG51 L49
VSS_65 VSS_164 VSS_255
AM4 BH17 M28
VSS_66 VSS_165 VSS_256
AM41 VSS_67 VSS_166 BH30 M42 VSS_257
AM45 BH44 M46
VSS_68 VSS_167 VSS_258
AN1 BH46 M49
VSS_69 VSS_168 VSS_259
AN38 BH8 M5
VSS_70 VSS_169 VSS_260
AN39 BJ11 M50
VSS_71 VSS_170 VSS_261
AN43 BJ13 M9
B VSS_72 VSS_171 VSS_262 B
AN5 VSS_73 VSS_172 BJ38 N11 VSS_263
AN7 VSS_74 VSS_173 BJ4 N14 VSS_264
AP4 BJ42 N17
VSS_75 VSS_174 VSS_265
AP48 VSS_76 VSS_175 BJ46 N29 VSS_266
AP50 BK15 N32
VSS_77 VSS_176 VSS_267
AR11 BK17 N36
VSS_78 VSS_177 VSS_268
AR2 BK25 N39
VSS_79 VSS_178 VSS_269
AR39 BK29 N44
VSS_80 VSS_179 VSS_270
AR44 BK36 N49
VSS_81 VSS_180 VSS_271
AR47 VSS_82 VSS_181 BK40 N7 VSS_272
AR7 VSS_83 VSS_182 BK44 P19 VSS_273
AT10 BK6 P2
VSS_84 VSS_183 VSS_274
AT14 VSS_85 VSS_184 BK8 P23 VSS_275
AT41 BL11 P3
VSS_86 VSS_185 VSS_276
AT49 VSS_87 VSS_186 BL13 P50 VSS_277
AU1 BL19 R49
VSS_88 VSS_187 VSS_278
AU23 BL22 T39
VSS_89 VSS_188 VSS_279
AU29 BL37 T43
VSS_90 VSS_189 VSS_280
AU3 BL47 T47
VSS_91 VSS_190 VSS_281
AU36 C12 U41
VSS_92 VSS_191 VSS_282
AU49 C16 U45
VSS_93 VSS_192 VSS_283
AU51 VSS_94 VSS_193 C19 U50 VSS_284
AV39 C28 V2
VSS_95 VSS_194 VSS_285
AV48 VSS_96 VSS_195 C29 V3 VSS_286
AW1 C33
VSS_97 VSS_196
AW12 C36
VSS_98 VSS_197 CRESTLINE_1p0
AW16 VSS_99 VSS_198 C41

CRESTLINE_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 12 of 55
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

V_DDR_MCH_REF
8 DDR_A_DQS#[0..7] V_DDR_MCH_REF 7,14,42

8 DDR_A_D[0..63] JP34

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D6 1 1
8 DDR_A_DM[0..7] VSS DQ4

C363

C362
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
8 DDR_A_DQS[0..7] 7 8
DQ1 VSS DDR_A_DM0
9 VSS DM0 10
DDR_A_DQS#0 11 12 2 2
7,8 DDR_A_MA[0..14] DQS0# VSS
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D7
15 16
DDR_A_D2 VSS DQ7
17 DQ2 VSS 18
D DDR_A_D3 DDR_A_D13 D
19 DQ3 DQ12 20
21 22 DDR_A_D12
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
DQ9 DM1
27 28
Place near JP34 DDR_A_DQS#1 29
VSS VSS
30 M_CLK_DDR0
M_CLK_DDR0 7
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 32 M_CLK_DDR#0 7
DQS1 CK0#
33 VSS VSS 34
DDR_A_D9 35 36 DDR_A_D11
DDR_A_D15 DQ10 DQ14 DDR_A_D10
37 38
DQ11 DQ15
39 VSS VSS 40
+1.8V
41 42
DDR_A_D16 VSS VSS DDR_A_D20
43 44
0317 add DDR_A_D17 DQ16 DQ20 DDR_A_D21
45 46
DQ17 DQ21
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 47 VSS VSS 48
1 1 1 1 1 1 1 1 1 DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 7
C458

C498

C473

C491

C465

C255

C242

C280

C235
+ C246 DDR_A_DQS2 51 52 DDR_A_DM2
330U_D2_2.5VM_R15 DQS2 DM2
53 54
DDR_A_D18 VSS VSS DDR_A_D23
55 56
2 2 2 2 2 2 2 2 2 2 DDR_A_D19 DQ18 DQ22 DDR_A_D22
57 58
DQ19 DQ23
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 64
DQ25 DQ29
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 70
NC DQS3
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 76
DQ27 DQ31
77 78
C DDR_CKE0_DIMMA VSS VSS DDR_CKE1_DIMMA C
7 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 7
81 82
VDD VDD
83 84
DDR_A_BS#2 NC NC/A15 DDR_A_MA14
8 DDR_A_BS2 85 BA2 NC/A14 86 0612 add
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 90
Place one cap close to every 2 pullup DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 DDR_A_MA6
resistors terminated to +0.9VS 93
A8 A6
94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
DDR_A_BS#0 A10/AP BA1 DDR_A_RAS# DDR_A_BS1 8
8 DDR_A_BS0 107 108 DDR_A_RAS# 8
DDR_A_WE# BA0 RAS# DDR_CS0_DIMMA#
109 110 DDR_CS0_DIMMA# 7
+0.9V 8 DDR_A_WE# WE# S0#
111 112
DDR_A_CAS# VDD VDD M_ODT0
8 DDR_A_CAS# 113 114 M_ODT0 7
DDR_CS1_DIMMA# CAS# ODT0 DDR_A_MA13
115 116
7 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

M_ODT1 119 120

7 M_ODT1 NC/ODT1 NC
121 122
DDR_A_D37 VSS VSS DDR_A_D39
1 1 1 1 1 1 1 1 1 1 1 1 1 123 124
DDR_A_D36 DQ32 DQ36 DDR_A_D38
125 126
DQ33 DQ37
127 128
DDR_A_DQS#4 VSS VSS DDR_A_DM4
129 130
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C229

C239

C250

C257

C272

C279

C281

C274

C268

C252

C241

C234

C227

133 134 DDR_A_D34

DDR_A_D35 VSS DQ38 DDR_A_D33
135 136
DDR_A_D32 DQ34 DQ39
137 138
DQ35 VSS DDR_A_D45
139 140
DDR_A_D40 VSS DQ44 DDR_A_D43
141 142
B DDR_A_D44 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 148
DM5 DQS5
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42
153 154
DQ43 DQ47
155 156
DDR_A_D49 VSS VSS DDR_A_D52
157 158
DDR_A_D48 DQ48 DQ52 DDR_A_D53
159 160
DQ49 DQ53
161 VSS VSS 162
163 164 M_CLK_DDR1
+0.9V NC,TEST CK1 M_CLK_DDR1 7
Layout Note: 165 166 M_CLK_DDR#1
DDR_A_DQS#6 VSS CK1# M_CLK_DDR#1 7
Place t hes e resistor 167 DQS6# VSS 168
RP27 RP22 56_0404_4P2R_5% DDR_A_DQS6 169 170 DDR_A_DM6
DDR_A_MA5 1 4 4 1 DDR_A_BS#2 closely JP34,all 171
DQS6 DM6
172
DDR_A_MA8 trace length Max=1.5" VSS VSS
2 3 3 2 DDR_CKE0_DIMMA DDR_A_D54 173 174 DDR_A_D51
DDR_A_D50 DQ50 DQ54 DDR_A_D55
175 176
RP29 56_0404_4P2R_5% RP26 56_0404_4P2R_5% DQ51 DQ55
177 178
DDR_A_MA1 VSS VSS
1 4 4 1 DDR_A_MA7 DDR_A_D61 179 180 DDR_A_D57
DDR_A_MA3 DQ56 DQ60
2 3 3 2 DDR_A_MA6 DDR_A_D60 181 182 DDR_A_D56
DQ57 DQ61
183 184
RP32 56_0404_4P2R_5% RP25 56_0404_4P2R_5% DDR_A_DM7 VSS VSS DDR_A_DQS#7
185 DM7 DQS7# 186
DDR_A_RAS# 1 4 4 1 DDR_A_MA9 187 188 DDR_A_DQS7
DDR_CS0_DIMMA# 2 VSS DQS7
3 3 2 DDR_A_MA12 DDR_A_D59 189 DQ58 VSS 190
DDR_A_D58 191 192 DDR_A_D62
RP31 56_0404_4P2R_5% RP28 56_0404_4P2R_5% DQ59 DQ62 DDR_A_D63
193 194
DDR_A_BS#0 VSS DQ63
1 4 4 1 DDR_A_MA4 14,15,20 ICH_SMBDATA
ICH_SMBDATA 195 SDA VSS 196
DDR_A_MA10 2 3 3 2 DDR_A_MA2 ICH_SMBCLK 197 198
14,15,20 ICH_SMBCLK SCL SAO
+3VM 199 200
RP33 56_0404_4P2R_5% RP30 56_0404_4P2R_5% VDDSPD SA1
203 204
GND GND

1
10K_0402_5%

10K_0402_5%
2.2U_0603_6.3V4Z

DDR_A_CAS# 1 4 4 1 DDR_A_MA0 1 1
0.1U_0402_16V4Z

DDR_A_WE# 2 3 3 2 DDR_A_BS#1 C308 conn@ FOX_ASOA426-M4R-TR

A

R455

R453
C311 A
RP35 56_0404_4P2R_5% RP34 56_0404_4P2R_5%
DDR_CS1_DIMMA# 2 3 4 1 M_ODT0
2 2
SO-DIMM A
REVERSE

2
M_ODT1 1 4 3 2 DDR_A_MA13

56_0404_4P2R_5% RP24 56_0404_4P2R_5%

4 1 DDR_CKE1_DIMMA Top side
DDR_A_MA11 1 2 3 2 DDR_A_MA14

R1742 56_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

0612 add THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 13 of 55
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V
8 DDR_B_DQS#[0..7]

8 DDR_B_D[0..63]
V_DDR_MCH_REF
V_DDR_MCH_REF 7,13,42
8 DDR_B_DM[0..7] JP10

2.2U_0805_16V4Z

0.1U_0402_16V4Z
8 DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D5 1 1
DDR_B_D0 VSS DQ4 DDR_B_D4
7,8 DDR_B_MA[0..14] 5 6
DQ0 DQ5

C89

C90
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 10
DDR_B_DQS#0 VSS DM0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
D DDR_B_D2 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP10 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 26
DQ9 DM1
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DDR_B_DQS1 DQS1# CK0 M_CLK_DDR#3 M_CLK_DDR3 7
31 DQS1 CK0# 32 M_CLK_DDR#3 7
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 42
VSS VSS
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C236

C265

C247

C159

C164

C166

C219

C188

C161
47 48
DDR_B_DQS#2 VSS VSS
49 DQS2# NC 50 PM_EXTTS#1 7
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 54
DDR_B_D18 VSS VSS DDR_B_D22
55 56
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 66
DDR_B_DM3 VSS VSS DDR_B_DQS#3
67 68
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 76
C DQ27 DQ31 C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
7 DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB 7
81 82
VDD VDD
Layout Note: DDR_B_BS#2
83 NC NC/A15 84
DDR_B_MA14
8 DDR_B_BS2 85 BA2 NC/A14 86
Place one cap close to every 2 pullup 87 88 0612 add
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9VS DDR_B_MA9
89 A12 A11 90
DDR_B_MA7
91 92
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 96
DDR_B_MA5 VDD VDD DDR_B_MA4
97 A5 A4 98
DDR_B_MA3 99 100 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
101 A1 A0 102
103 104
DDR_B_MA10 VDD VDD DDR_B_BS#1
105 106 DDR_B_BS1 8
+0.9V DDR_B_BS#0 A10/AP BA1 DDR_B_RAS#
8 DDR_B_BS0 107 108 DDR_B_RAS# 8
DDR_B_WE# BA0 RAS# DDR_CS2_DIMMB#
8 DDR_B_WE# 109 110 DDR_CS2_DIMMB# 7
WE# S0#
111 112
DDR_B_CAS# VDD VDD M_ODT2
8 DDR_B_CAS# 113 114 M_ODT2 7
CAS# ODT0
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13

7 DDR_CS3_DIMMB# NC/S1# NC/A13
117 118
M_ODT3 VDD VDD
1 1 1 1 1 1 1 1 1 1 1 1 1 7 M_ODT3 119 120
NC/ODT1 NC
121 122
DDR_B_D32 VSS VSS DDR_B_D36
123 124
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 126
2 2 2 2 2 2 2 2 2 2 2 2 2 DQ33 DQ37
127 128
VSS VSS
C176

C179

C186

C197

C213

C220

C183

C210

C199

C173

C218

C163

C177

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 132
DQS4 VSS DDR_B_D39
133 134
DDR_B_D34 VSS DQ38 DDR_B_D38
135 136
DDR_B_D35 DQ34 DQ39
137 138
DQ35 VSS DDR_B_D44
139 140
B DDR_B_D40 VSS DQ44 DDR_B_D45 B
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 146
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
147 DM5 DQS5 148
149 150
DDR_B_D42 VSS VSS DDR_B_D46
151 152
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 154
DQ43 DQ47
155 156
DDR_B_D48 VSS VSS DDR_B_D52
157 158
DDR_B_D49 DQ48 DQ52 DDR_B_D53
Layout Note: 159 DQ49 DQ53 160
Place t hes e resistor 161 VSS VSS 162
+0.9V 163 164 M_CLK_DDR2
closely JP10,all NC,TEST CK1 M_CLK_DDR#2 M_CLK_DDR2 7
165 VSS CK1# 166
RP14 RP10 56_0404_4P2R_5% trace length Max=1.5" DDR_B_DQS#6 M_CLK_DDR#2 7
167 168
DDR_B_MA1 DDR_B_MA9 DDR_B_DQS6 DQS6# VSS DDR_B_DM6
1 4 4 1 169 DQS6 DM6 170
DDR_B_MA3 2 3 3 2 DDR_B_MA12 171 172
DDR_B_D51 VSS VSS DDR_B_D54
173 174
RP17 56_0404_4P2R_5% RP11 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 176
DDR_B_BS#0 DDR_B_MA14 DQ51 DQ55
1 4 4 1 177 178
DDR_B_MA10 DDR_B_MA11 DDR_B_D56 VSS VSS DDR_B_D60
2 3 3 2 179 180
DDR_B_D61 DQ56 DQ60 DDR_B_D57
181 182
RP16 56_0404_4P2R_5% RP12 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_MA0 1 4 4 1 DDR_B_MA5 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_BS#1 DDR_B_MA8 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D59 189 190
RP18 56_0404_4P2R_5% RP13 56_0404_4P2R_5% DDR_B_D58 DQ58 VSS DDR_B_D62
191 192
DDR_B_RAS# DDR_B_MA7 DQ59 DQ62 DDR_B_D63
1 4 4 1 193 VSS DQ63 194
DDR_CS2_DIMMB# 2 3 3 2 DDR_B_MA6 ICH_SMBDATA 195 196
13,15,20 ICH_SMBDATA ICH_SMBCLK SDA VSS
197 198 R257
13,15,20 ICH_SMBCLK SCL SAO
RP19 56_0404_4P2R_5% RP15 56_0404_4P2R_5% 199 200 1 2 +3VM
+3VM VDDSPD SA1
DDR_B_CAS# 1 4 4 1 DDR_B_MA4 203 204
GND GND

1
10K_0402_5%
2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

DDR_B_WE# 2 3 3 2 DDR_B_MA2 1 1 10K_0402_5%

R254
A RP23 0310 add C301 FOX_ASOA426-M4R-TR A
56_0404_4P2R_5% RP21 56_0404_4P2R_5% C312 conn@
DDR_CS3_DIMMB# 2
M_ODT3 1
3
4
4
3
1
2
M_ODT2
DDR_B_MA13 2 2
SO-DIMM B
STANDARD

2
56_0404_4P2R_5% RP9
4 1 DDR_B_BS#2 Bottom side
DDR_CKE3_DIMMB 1 2 3 2 DDR_CKE2_DIMMB
R1743
56_0402_5% 56_0404_4P2R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

0612 add THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P UMA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 14 of 55
5 4 3 2 1
 5 4 3 2 1

+3VM_CK505
FSLC FSLB FSLA CPU SRC PCI C353 2 1 CLK_48M_ICH
+3VM
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz 1
R1066
2
0_1206_5% 1 C357
5P_0402_50V8C
CLK_14M_ICH
1 1 1 1 1 1 2 1
C1165 C1166 C1167 C1168 C1169 C1170 C1171 4.7P_0402_50V8C
0 1 0 200 100 33.3 03/02 change C372 2 1 CLK_PCI_ICH
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7P_0402_50V8C
2 2 2 2 2 2 2 C373 CLK_14M_KBC
2 1
0 1 1 166 100 33.3 4.7P_0402_50V8C
C374 2 1 CLK_14M_SIO
4.7P_0402_50V8C
C375 CLK_PCI_EC
FSB Frequency Selet: +1.25VM
2 1
4.7P_0402_50V8C
Place close to U7 CLK_PCI_TCG
C376 2 1
D +1.25VM_CK505 D
CPU Driven Stuff R1107 R1135 R1083 4.7P_0402_50V8C
R1068 0_1206_5% C378 2 1 CLK_PCI_PCM
1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 4.7P_0402_50V8C
CLK_PCI_SIO
*(Default) No Stuff R1074 R1086 R1098 R1113 R1128 R1139 1 1 1 1
C1353
1 1
C1355
C379 2 1
4.7P_0402_50V8C
C1173 C1174 C1354 C380 2 1 CLK_DEBUG_PORT
Stuff R1086 R1139 R1135 R1074 R1139 R1135 C1172
2 2 2 2 2 2
5P_0402_50V8C

667MHz 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

No Stuff R1083 R1107 R1128
03/02 change 20070301 Add CAP for WWAN issue
R1113 R1098
Stuff
R1135 R1139
+3VM_CK505 U7
800MHz
No Stuff R1083 R1086 R1098 R1128 2
VDD_PCI NC
48
9 VDD48
R1074 R1107 R1113 16
VDDPLL3
61
VDDREF
R1074 64
@ SCLK ICH_SMBCLK 13,14,20
39 VDDSRC SDATA 63
1 2 55 ICH_SMBDATA 13,14,20
+VCCP VDDCPU
38
56_0402_5% PCI_STOP# H_STP_PCI# 20
CPU_STOP# 37
12 H_STP_CPU# 20
+1.25VM_CK505 VDD96_IO
R1078 20
2.2K_0402_5% VDDPLL3_IO R1070
26 VDDSRC_IO
FSA 2 1 1 2 54 R_CPU_BCLK 1 2 0_0402_5%
MCH_CLKSEL0 7 CPU0 R_CPU_BCLK# CLK_CPU_BCLK 4
36 53 1 2 0_0402_5%
VDDSRC_IO CPU0# CLK_CPU_BCLK# 4
1 2 R1079 49 R1072
C 5 CPU_BSEL0 VDDCPU_IO C
1K_0402_5%
0_0402_5% 1111 Add CLRP4,CLRP5 for 667/800 FSB select R1075
1

R1083 51 R_MCH_BCLK 1 2 0_0402_5%

R1086 SHORT CLRP5, NO SHORT CLRP4 -- FSB 800 CPU1_F
50 R_MCH_BCLK# 1 2 0_0402_5%
CLK_MCH_BCLK 7
CPU1#_F CLK_MCH_BCLK# 7
SHORT CLRP4, NO SHORT CLRP5 -- FSB 667 R1081
@ 1K_0402_5%
0216 Delete CLRP4,CLRP5 47 R_CPU_XDP R1033 1 2 0_0402_5%
CLK_CPU_XDP 4
2

SRC8/ITP R_CPU_XDP# 0_0402_5%

46 1 2 CLK_CPU_XDP# 4
SRC8#/ITP# R1143
475_0402_1%1 2 R1692 1
+VCCP 20 CLKSATAREQ# PCI0/CR#_A R1111
1 2 PCI_CLK1 3 35 R_PCIE_3GPLL# 1 2 0_0402_5%
7 CLKREQ#_B PCI1/CR#_B SRC10# CLK_PCIE_DOCK# 33
R1693 475_0402_1% 34 R_PCIE_3GPLL 1 2 0_0402_5%
SRC10 CLK_PCIE_DOCK 33
2

22_0402_5% 2 1 R1097 PCI2_TME 4 R1115

R1098 25,30 CLK_DEBUG_PORT 12_0402_5% 2 PCI2/TME
29 CLK_PCI_SIO 1 R1114 1 2 +3VS
12_0402_5% 1 2 R1140 PCI_CLK3 5 R1695 R149 10K_0402_5%
30 CLK_PCI_TCG PCI3
@ 1K_0402_5% 12_0402_5% 1 2 R1110 33 CLKREQ#_H 2 1 475_0402_1%
31 CLK_PCI_EC SRC11/CR#_H CPPE# 33
12_0402_5% 1 2 R1141 27_SEL 6 32 R_CLKREQ#_G 2 1 475_0402_1%
CLKREQ#_G 25
1

FSB 25 CLK_PCI_PCM PCI4/27_Select SRC11#/CR#_G R1694 R150 10K_0402_5%

1 2 MCH_CLKSEL1 7
22_0402_5% 1 2 R1117 ITP_EN 7 1 2
18 CLK_PCI_ICH PCIF5/ITP_EN +3VS
1 2 R1105 R1093
5 CPU_BSEL1
R1107 1K_0402_5% 30 R_CLK_PCIE_MCard 1 2 0_0402_5%
SRC9 R_CLK_PCIE_MCard# 1 CLK_PCIE_MCARD 25
0_0402_5% 31 2 0_0402_5%
SRC9# CLK_PCIE_MCARD# 25
1

CLK_XTAL_IN 60 R1095
@ R1113 X1
CLK_XTAL_OUT 59
0_0402_5% X2 R14 10K_0402_5%
SRC7/CR#_F 44
43 1 2 +3VS
2

SRC7#/CR#_E
1 2 CLKREQ#_E 25
R17 475_0402_1% 0612 add for Robson
B +VCCP R1077 33_0402_1% 41 R_CLK_Rob R5 1 2 0_0402_5% 0612 add for Robson B
SRC6 CLK_PCIE_Rob 25
1 2 FSA 10 40 R_CLK_Rob# R13 1 2 0_0402_5%
20 CLK_48M_ICH USB_48MHZ/FSLA SRC6# CLK_PCIE_Rob# 25
2

R1128 FSB 57 R1144

FSLB/TEST MODE R_MCH_3GPLL 0_0402_5%
27 1 2 CLK_MCH_3GPLL 7
R1130 @ 1K_0402_5% SRC4 R_MCH_3GPLL# 0_0402_5%
28 1 2 CLK_MCH_3GPLL# 7
10K_0402_5% 33_0402_1% 1 R1087 FSC SRC4# R1145
2 62
1

FSC 20 CLK_14M_ICH 33_0402_1% 1 R1088 REF0/FSLC/TEST_SEL

2 1 1 2 MCH_CLKSEL2 7 2
29 CLK_14M_SIO 33_0402_1% 1 2 R1089 R1684
1 2 R1131 31 CLK_14M_KBC 24 R _PCIE_ICH 1 2 0_0402_5%
5 CPU_BSEL2 SRC3/CR#_C CLK_PCIE_ICH 20
R1135 1K_0402_5% 45 25 R_PCIE_ICH# 1 2 0_0402_5%
+1.25VM_CK505 VDDSRC_IO SRC3#/CR#_D CLK_PCIE_ICH# 20
0_0402_5% R1685
1

@ R1139 For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# R1257

21 R_PCIE_SATA 1 2 0_0402_5%
SRC2/SATA CLK_PCIE_SATA 19
0_0402_5% For 27_SEL, 0 = Enable DOT96 & SRC1, 42 22 R_PCIE_SATA# 1 2 0_0402_5%
GNDSRC SRC2#/SATA# CLK_PCIE_SATA# 19
R1259
2

1= Enable SRC0 & 27MHz 8

GNDPCI
For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed 11 17 SSCDREFCLK
R1686 1 2 0_0402_5%
GND48 SRC1/SE1/27MHz_NonSS MCH_SSCDREFCLK 7
18 SSCDREFCLK#
R1687 1 2 0_0402_5%
SRC1#/SE2/27MHz_SS MCH_SSCDREFCLK# 7
0529 change power plane 1 = Overclocking of CPU and SRC NOT allowed 15
GND
19 R1688
CLK_XTAL_OUT GND R_MCH_DREFCLK 0_0402_5%
13 1 2 CLK_MCH_DREFCLK 7
+3VS +3VS +3VS SRC0/DOT96 R_MCH_DREFCLK# 0_0402_5%
52 GNDCPU SRC0/DOT96# 14 1 2 CLK_MCH_DREFCLK# 7
CLK_XTAL_IN R1689
23
GNDSRC
2

14.31818MHZ_16P R1245 R1690 R1108 29

GNDSRC
10K_0402_5% 10K_0402_5% 10K_0402_5% CK_PWRGD/PD# 56
A
58 CK_PWRGD 20 A
Y6 @ GNDREF
1

2 1 ICS9LPRS355_TSSOP64
ITP_EN 27_SEL PCI2_TME
* Internal Pull-Up Resistor
2 2 ** Internal Pull-Down Resistor
2

C509 C505 R1247 R1691 R1246

18P_0402_50V8J
1 1
18P_0402_50V8J 10K_0402_5% 10K_0402_5% 10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
@ @ Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
Clock generator
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Routing the trace at least 10mil AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P UMA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 15 of 55
5 4 3 2 1
 A B C D E

+5VS +RCRT_VCC +CRTVDD

CRT Connector F1 D18

W=40mils
33 L_BLUE 1 2 2 1
1013 Add CRT circuit BLUE_R
1.1A_6VDC_FUSE CH491D_SC59 GREEN_R
33 L_GREEN
1 RED_R

DAN217_SC59

DAN217_SC59

@ DAN217_SC59
33 L_RED C315

D19

D20
0.1U_0402_16V4Z

1
2

150_0402_1%

D4
Place close to JP2

150_0402_1%
JP2
@ 6
R171 R174 R542 11
1 RED_R @ @ 1
1 2 1

2
0315 add BK1608LL560-T 0603 7 +CRTVDD

3
12P_0402_50V8C
@ R543 12
1 2 GREEN_R 2

12P_0402_50V8C
C313
BK1608LL560-T 0603 8
150_0402_1% R544 13

C314
@ R173 1 2 BLUE_R 3
BK1608LL560-T 0603 9 +3VS

18P_0402_50V8J

18P_0402_50V8J

18P_0402_50V8J
12P_0402_50V8C
+5VS +5VS 14 16
C359 C370
1 1 1 @ 1 1 1 4 17

C310

C317

C316

C318
1 2 1 2 10
15
0.1U_0402_16V4Z 0.1U_0402_16V4Z @ 5

2
2 2 2 2 2 2

2.2K_0402_5%

2.2K_0402_5%
SUYIN_070912FR015S207CR
5
1

R2

R4
U33 @ conn@
SN74AHCT1G125GW_SOT353-5 R545 0315 add +CRTVDD +CRTVDD
OE#
P

2 4 H SYNC_G_A 1 2 D_HSYNC
9 M_HSYNC

1
A Y 0_0603_5%
G

5
1

1
D_HSYNC 33
R546 R162 R183
OE#
P
3

2 4 VSYNC_G_A1 2 D_VSYNC Place close to docking connector

9 M_VSYNC A Y 0_0603_5% 2.2K_0402_5% 2.2K_0402_5%
G

U54
D_VSYNC 33

2
R53 51K_0402_5%

R54 51K_0402_5%

SN74AHCT1G125GW_SOT353-5 Q46

G
1 1
3

C351 C352
2

D_DDCDATA 1 3
33 D_DDCDATA DDC1_DATA 9
@ 5P_0402_50V8C @ 5P_0402_50V8C

S
2 2

2
RHU002N06_SOT323

G
1

D_DDCCLK 1 3
2 33 D_DDCCLK DDC1_CLK 9 2

S
Q52
Place close to docking connector RHU002N06_SOT323

layout note: D_HSYNC & D_VSYNC should be routed to docking connector then to VGA connector

Place close to JP1 02/28 change -->solve DVI issue

TV-Out Connector R1369
CHB1608U301_0603 R1367
KC FBM-L11-201209-221LMA30T_0805
R1368
DAN217_SC59 DAN217_SC59 DAN217_SC59 +3VS +2.5VS 2 1 DVI_DVDD_2.5V DVI_AVDD_2.5V 1 2 +2.5VS
DVI_AVDD_3V 1 2 +3VS
@ D3 @ D5 @ D1 KC FBM-L11-201209-221LMA30T_0805
1 1
C178 C143 C150 C174 C141 C371 C358 C368
1

C140 C369
+2.5VS 22U_0805_6.3VAM 10U_0805_10V4Z
2 2

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z
0_0603_5% R497 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
9,33 LUMA
2

R547 1 2 10K_0402_5% 0.1U_0402_16V4Z

9,33 CRMA 0_0603_5%
R548 1 2 W=20 mils

2
0_0603_5% JP1 AS
9,33 COMP
R549 1 2
1
2
5.6P_0402_50V8D

5.6P_0402_50V8D

DVI_AVDD_3V DVI_AVDD_2.5V
3
1

3 @ R187 TV_LUMA 3
@ R184 4 DVI_DVDD_2.5V
1 1 1 5
150_0402_1%

TV_CRMA
6
150_0402_1%

@ @ @

12
28

15
21
36
42
48
7

1
TV_COMP U11
2

2 2 2 0.1U_0402_16V4Z

AVDD_PLL
DVDD
DVDD

TVDD
TVDD
AVDD
AVDD
AVDD
C333 C355 conn@
@ R185 C1043 SDVOB_INT+ 32 13 R_DVI_CLK- R1673 1 2 0_0603_5%
9 PEG_RXP1 SDVOB_INT+ TLC# DVI_CLK- 33
0315 add 150_0402_1% 5.6P_0402_50V8D SUYIN_33007SR-07T1-C C1042 SDVOB_INT- 33 14 R_DVI_CLK+ R1674 1 2 0_0603_5%
9 PEG_RXN1 SDVOB_INT- TLC DVI_CLK+ 33
C354 0.1U_0402_16V4Z 16 R_DVI_TX0- R1675 1 2 0_0603_5% DVI_TX0- 33
TDC0# R_DVI_TX0+ R1676 0_0603_5%
37 SDVOB_R+ TDC0 17 1 2 DVI_TX0+ 33
9 SDVOB_R+ R_DVI_TX1- R1677 0_0603_5%
38 19 1 2
Cl ose to JP1 9 SDVOB_R- SDVOB_R- TDC1#
20 R_DVI_TX1+ R1678 1 2 0_0603_5%
DVI_TX1- 33
TDC1 DVI_TX1+ 33
40 22 R_DVI_TX2- R1679 1 2 0_0603_5%
9 SDVOB_G+ SDVOB_G+ TDC2# DVI_TX2- 33
41 23 R_DVI_TX2+ R1680 1 2 0_0603_5%
9 SDVOB_G- SDVOB_G- TDC2 DVI_TX2+ 33
43
la yo u t n ote: TV-out signals should be routed to JP30 then to JP1 9 SDVOB_B+
44
SDVOB_B+
29 DVI_DETECT
9 SDVOB_B- SDVOB_B- HPDET DVI_DETECT 33
46 11 DVI_CLK 33
9 SDVOB_CLK+ SDVOB_CLK+ SC_DDC
47 10 DVI_DAT 33
9 SDVOB_CLK- SDVOB_CLK- SD_DDC

@
10K_0402_5%1 R17202
AS 3 9 10K_0402_5%1 2
AS SC_PROM +5VS

@
PLT_RST# 2 8 R1721
7,18,22,30 PLT_RST# DVI_VSWING 25 RESET# SD_PROM
VSWING 0620 change

AGND_PLL
5 SDVO_SDAT SDVO_SDAT 7
SPD SDVO_SCLK
27 ATPG SPC 4 SDVO_SCLK 7

DGND
DGND
AGND
AGND
AGND
TGND
TGND
26

PAD
SCEN
1

C1371

NC
NC
2

R103 56P_0402_50V +2.5VS

R114 R498 CH7307C_LQFP48 1226 Add C for DVI I2C

49

7
30
31
39
45
18
24
6

34
35
1.3K_0402_1%
4 10K_0402_5% 4
2

SDVO_SDAT R144 1 2 5.6K_0402_5%

1

SDVO_SCLK R142 1 2 5.6K_0402_5%

DVI Transnitter 10K_0402_5% 0830 Change to 3.9K ohm 1113 Change to 5.6K ohm

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 16 of 55
A B C D E
 5 4 3 2 1

LVDS CONN B+_LCD 20070209 Add 10uF for wavy issue

C586 10U_1206_25V6M
LCD POWER CIRCUIT LCDVDD +3VALW
1 2 Q8
LCDVDD AO3413_SOT23
1 2
C587 68P_0402_50V8J 1 3

S
1
JP35 1 2
10U_1206_25V6M R19
C1376 R12

G
2
41
41 40
40 0628 change size 100_0402_1% 1 2
42 39

1 2
D 42 39 1M_0402_5% D
43 43 38 38 2 1 B+ D
44 37 L62 KC FBM-L11-201209-221LMA30T_1210 R474 C28
44 37 Q5
45 45 36 36 2 1 2 1 2
46 35 +3VS G
46 35 RHU002N06_SOT323 47K_0402_5% 0.1U_0402_16V7K
34 S 1 1 1

3
34 C29 C31 C20
33 33
32 LCDVDD
32

1
31 4.7U_0805_10V4Z @ 4.7U_0805_10V4Z
31 Q6 2 2 2
30 30
29 +5VS_INV DTC124EK_SC59
29
28 28
27 BKLT_PWM ALS_EN 20 2 0.1U_0402_16V4Z
27 9 ENAVDD
26 26
25 DDC2_CLK 9 0216 Change C28 to 0.1uF
25

2
24 DDC2_DATA 9
24 R502
23 TXCLK_U+ 9

3
23 100K_0402_1%
22 22 TXCLK_U- 9
21
21
20 TXOUT_U2+ 9

1
20
19 TXOUT_U2- 9
19 0314 add
18
18
17 TXOUT_U1+ 9
17
16 16 TXOUT_U1- 9
15 15
14 TXOUT_U0+ 9
14 Q53
13 13 TXOUT_U0- 9
12 DTA114YKA_SC59
12
11 TXOUT_L0- 9
11 +3V_U43
10 10 TXOUT_L0+ 9
9 9 +5VS 3 1 +5VS_INV
8 0_0402_5%

47K
8 TXOUT_L1- 9
7 R1728 1 2

10K
C 7 TXOUT_L1+ 9 +3VALW C
6 6
5 @ 0_0402_5%
5 TXOUT_L2- 9
4 +3VS R1729 1 2
TXOUT_L2+ 9

2
4 U43A
3 3
2 SN74LVC08APW_TSSOP14

14
2 TXCLK_L- 9
1 TXCLK_L+ 9
1

1
LID_SW# D
1

P
20,32 LID_SW# A
3 2 Q36
O G BSS138_SOT23
9 ENABLT 2 B

2
ACES_88316-4000 S

3
2
R360

7
conn@ 100K_0402_5%

1
R501

1
0314 change 100K_0402_1%

B R102 0_0402_5% BKLT_PWM B

9 BLON_PWM 1 2

Support 3V inverter

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 17 of 55
5 4 3 2 1
 5 4 3 2 1

+3VS

1 2 PCI_DEVSEL#
R1514 8.2K_0402_5%
1 2 PCI_STOP#
R1515 8.2K_0402_5% 25 PCI_AD[0..31]
1 2 PC I_TRDY# U26B
R1516 8.2K_0402_5% PCI_AD0 D20 A4 PCI_REQ0#
PCI_FRAME# PCI_AD1 AD0 REQ0# PCI_GNT0#
D
1
R1517
2
8.2K_0402_5% PCI_AD2
E19
D19
AD1 PCI GNT0# D7
E18 PCI_REQ1# D
PCI_PLOCK# PCI_AD3 AD2 REQ1#/GPIO50
1 2 A20 AD3 GNT1#/GPIO51 C18 MDC_DIS
R1518 8.2K_0402_5% PCI_AD4 D17 B19 PCI_REQ2#
AD4 REQ2#/GPIO52 PCI_REQ2# 25
1 2 PCI_IR DY# PCI_AD5 A21 F18 PCI_GNT2#
PCI_AD6 AD5 GNT2#/GPIO53 PCI_REQ3# PCI_GNT2# 25
R1519 8.2K_0402_5% A19 A11
PCI_SERR# PCI_AD7 AD6 REQ3#/GPIO54 PCI_GNT3#
1 2 C19 AD7 GNT3#/GPIO55 C10
R1520 8.2K_0402_5% PCI_AD8 A18
PCI_PERR# PCI_AD9 AD8 PCI_CBE#0
1 2 B16 AD9 C/BE0# C17 PCI_CBE#0 25
R1521 8.2K_0402_5% PCI_AD10 A12 E15 PCI_CBE#1
AD10 C/BE1# PCI_CBE#1 25
1 2 MBAY_DET# PCI_AD11 E16 F16 PCI_CBE#2
PCI_AD12 AD11 C/BE2# PCI_CBE#3 PCI_CBE#2 25
R1585 10K_0402_5% A14 E17
MDC_DIS PCI_AD13 AD12 C/BE3# PCI_CBE#3 25
1 2 G16
R1748 10K_0402_5% PCI_AD14 AD13 PCI_IR DY#
A15 AD14 IRDY# C8 PCI_IRDY# 25
PCI_AD15 B6 D9 PCI_PAR
PCI_AD16 AD15 PAR PCI_PCIRST# PCI_PAR 25
C11 G6
+3VS PCI_AD17 AD16 PCIRST# PCI_DEVSEL#
A9 D16 PCI_DEVSEL# 25
PCI_AD18 AD17 DEVSEL# PCI_PERR#
D11 AD18 PERR# A7 PCI_PERR# 25
PCI_AD19 B12 B7 PCI_PLOCK#
PCI_PIRQA# PCI_AD20 AD19 PLOCK# PCI_SERR#
1 2 C12 AD20 SERR# F10 PCI_SERR# 25,31
R1522 8.2K_0402_5% PCI_AD21 D10 C16 PCI_STOP#
AD21 STOP# PCI_STOP# 25
1 2 PCI_PIRQB# PCI_AD22 C7 C9 PC I_TRDY#
PCI_AD23 AD22 TRDY# PCI_FRAME# PCI_TRDY# 25
R1523 8.2K_0402_5% F13 A17
PCI_PIRQC# PCI_AD24 AD23 FRAME# PCI_FRAME# 25
1 2 E11 AD24
R1524 8.2K_0402_5% PCI_AD25 E13 AG24 PCI_PLTRST#
PCI_PIRQD# PCI_AD26 AD25 PLTRST# CLK_PCI_ICH PCI_PLTRST# 25
1 2 E12 B10 CLK_PCI_ICH 15
R1525 8.2K_0402_5% PCI_AD27 AD26 PCICLK PCI_PME#
D8 AD27 PME# G7 PCI_PME#
1 2 PCI_PIRQE# PCI_AD28 A6 R1527
R1526 8.2K_0402_5% PCI_AD29 AD28
E8 1 2 +3VALW
PCI_PIRQG# PCI_AD30 AD29 8.2K_0402_5%
1 2 D6 AD30
R10 8.2K_0402_5% PCI_AD31 A3
PIRQH# AD31
2 1
R189 8.2K_0402_5% Interrupt I/F
C PCI_REQ0# PCI_PIRQA# PCI_PIRQE# C
1 2 F9 PIRQA# PIRQE#/GPIO2 F8 PCI_PIRQE# 25
R1530 8.2K_0402_5% PCI_PIRQB# B5 G11 MBAY_DET#
PCI_REQ1# PCI_PIRQC# PIRQB# PIRQF#/GPIO3 MBAY_DET# 22
1 2 25 PCI_PIRQC# C5 F12 PCI_PIRQG# 25
R1531 8.2K_0402_5% PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PIRQH#
25 PCI_PIRQD# A10 PIRQD# PIRQH#/GPIO5 B3 2 1 ACCEL_INT 25
1 2 PCI_REQ2# 0_0402_5% 0601 change
R1532 8.2K_0402_5% ICH8M REV 1.0 R188 0301 change
1 2 PCI_REQ3#
R1533 8.2K_0402_5%

PCI_GNT3#
1

R1534
@
1K_0402_5%
Boot BIOS Strap
2

B B
+3VALW

PCI_GNT0# SPI_CS#1 Boot BIOS Location

5
U56
PCI_PCIRST# 1

P
B PCI_RST#
0 1 SPI * 2
A
Y
4 PCI_RST# 22,25

1
A16 swap override Strap @ TC7SH08FU_SSOP5 R192

3
R1051
Low= A16 swap override Enble 1 0 PCI 0_0402_5%
100K_0402_5%

PCI_GNT3# High= Default * 2 1

2
1 1 LPC +3VALW

5
U59
PCI_GNT0# SPI_CS1#_R PCI_PLTRST# 1

P
20 SPI_CS1#_R B
4 PLT_RST#
Y PLT_RST# 7,16,22,30
Place closely pin B10 2 A

G
1

1
R1536 @ TC7SH08FU_SSOP5 R191

3
CLK_PCI_ICH R1535 @ 100K_0402_5%
1K_0402_5% 1K_0402_5% R1057
2

0_0402_5%
2 2

2
R1537 2 1

@ 10_0402_5% J35
PAD-NO SHORT 2x2m
1

A A
1
C1177
1

@ 8.2P_0402_50V
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(1/4)-PCI/INT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P UMA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 18 of 55
5 4 3 2 1
 5 4 3 2 1

+3VS

R1538
GATEA20 2 1

10K_0402_5%

R1539
KB_RST# 2 1

10K_0402_5%
D +RTCVCC D

R1540 330K_0402_1%
1 2 LAN100_SLP +VCCP
R1541
R1542 1M_0402_5% H_FERR# 2 1
1 2 SM_INTRUDER# LPC_AD[0..3] 29,30,31
U26A 56_0402_5%
R1543 330K_0402_1% ICH_RTCX1 AG25 E5 LPC_AD0 R1544 @
RTCX1 FWH0/LAD0
1 2 ICH_INTVRMEN ICH_RTCX2 AF24 F5 LPC_AD1 H_DPRSTP# 2 1
R1545 RTCX2 FWH1/LAD1 LPC_AD2
FWH2/LAD2 G8
1 2 ICH_RTCRST# AF23 F6 LPC_AD3 56_0402_5%
+RTCVCC RTCRST# FWH3/LAD3 R1546 @
20K_0402_5% SM_INTRUDER# AD22 C4 LPC_FRAME# H_DPSLP# 2 1
SM_INTRUDER# INTRUDER# FWH4/LFRAME# LPC_FRAME# 29,30,31
2 CLRP1

RTC
LPC
C1178 SHORT PADS ICH_INTVRMEN AF25 G9 LPC_DRQ0# 56_0402_5%
LAN100_SLP INTVRMEN LDRQ0# LPC_DRQ#0 29
AD21 LAN100_SLP LDRQ1#/GPIO23 E6
1U_0603_10V4Z T39 PAD

1
1 GLAN_CLK GATEA20
23 GLAN_CLK B24 GLAN_CLK A20GATE AF13 GATEA20 31
AG26 H_A20M#
A20M# H_A20M# 4
LAN_RSTSYNC
0821 Change C528 and C516 to 15PF 23 LAN_RSTSYNC D22
LAN_RSTSYNC
AF26 H_DPRSTP_R# 2 1 H_DPRSTP#
ICH_RTCX1 LAN_RXD0 DPRSTP# H_DPRSTP# 5,7,43
23 LAN_RXD0 C21 AE26 R1548 0_0402_5%
R1733 LAN_RXD1 LAN_RXD0 DPSLP#
23 LAN_RXD1 B21 LAN_RXD1 H_DPSLP# 5
1 2 ICH_RTCX2 LAN_RXD2 C22 AD24 H_FERR#
23 LAN_RXD2 LAN_RXD2 FERR# H_FERR# 4

LAN / GLAN
10M_0402_5% LAN_TXD0 D21 AG29 H_PWRGOOD
23 LAN_TXD0 LAN_TXD1 LAN_TXD0 CPUPWRGD/GPIO49 H_PWRGOOD 5
1 1 23 LAN_TXD1 E20
C528 LAN_TXD2 LAN_TXD1 H_IGNNE#
23 LAN_TXD2 C20 LAN_TXD2 IGNNE# AF27 H_IGNNE# 4
15P_0402_50V8J C516 within 2" from R1557
15P_0402_50V8J AH21 AE24 H_INIT#
2 2 24 ENERGY_DET GLAN_DOCK#/GPIO13 INIT# H_INTR H_INIT# 4 +VCCP
AC20 H_INTR 4
INTR

CPU
C R1549 1 GLAN_COMP KB_RST# C
+1.5VS 2 24.9_0402_1% D25 GLAN_COMPI RCIN# AH14 KB_RST# 31
C25
GLAN_COMPO

1
R1551 33_0402_5% 1 2 HDA_BITCLK AD23 H_NMI
32 HDA_BITCLK_MDC NMI H_NMI 4
26 HDA_BITCLK_CODEC R1550 33_0402_5% 1 2 AJ16 AG28 H_SMI# R1552
HDA_BIT_CLK SMI# H_SMI# 4
R1553 33_0402_5% 1 2 AJ15
26 HDA_SYNC_CODEC HDA_SYNC HDA_SYNC H_STPCLK#
Y4 R1554 33_0402_5% 1 2 AA24 56_0402_5%
32 HDA_SYNC_MDC STPCLK# H_STPCLK# 4
1 4 R1555 33_0402_5% 1 2 HDARST# AE14
26 HDA_RST#_CODEC

2
R1556 33_0402_5% HDA_RST# THRMTRIP_ICH# R1557 24_0402_1%
26,32 HDA_RST#_MDC 1 2 AE27 1 2 H_THERMTRIP# 4,7
HDA_SDIN0 THRMTRIP#
2 3 26 HDA_SDIN0 AJ17 HDA_SDIN0
HDA_SDIN1 AH17 AA23
32 HDA_SDIN1 HDA_SDIN1 TP8 PD_D[0..15] 22
32.768KHZ_12.5P_MC-146 AH15 HDA_SDIN2

IHDA
+3VS R1560 AD13 V1 PD_D0 placed within 2" from ICH8M
10K_0402_5% R1558 33_0402_5% 1 HDA_SDOUT HDA_SDIN3 DD0 PD_D1
32 HDA_SDOUT_MDC 2 DD1 U2
2 1 IDE_LED# R1559 33_0402_5% 1 2 AE13 V3 PD_D2
26 HDA_SDOUT_CODEC HDA_SDOUT DD2 PD_D3
T1
DD3 PD_D4
2 1 1 2 AE10 V4
CLRP2 SHORT PADS HDA_DOCK_EN#/GPIO33 DD4 PD_D5
PAD T38 AG14 T5
R1801 1K_0402_5% HDA_DOCK_RST#/GPIO34 DD5 PD_D6
AB2
SATA_LED# DD6 PD_D7
AF10 T6
+3VS SATALED# DD7 PD_D8
DD8 T3
AF6 R2 PD_D9
22 SATA_RXN0_C SATA0RXN DD9
1

D 3900P_0402_50V7K PD_D10
22 SATA_RXP0_C AF5 T4
HDA_BITCLK SATA_TXN0 C1179 1 SATA_TXN0_C SATA0RXP DD10 PD_D11
2 22 SATA_TXN0 2 AH5 V6
G SATA_TXP0 C1180 1 SATA_TXP0_C SATA0TXN DD11 PD_D12
22 SATA_TXP0 2 AH6 V5
SATA0TXP DD12
2

Q141 S U1 PD_D13
3

R1561 RHU002N06_SOT323 3900P_0402_50V7K DD13 PD_D14 +3VS

AG3 V2
SATA1RXN DD14 PD_D15
10_0402_5% 25,31 GREEN_BATLED# AG4 SATA1RXP DD15 U6

IDE
@ AJ4
SATA1TXN PD_A0
AJ3 AA4 PD_A0 22
1

SATA1TXP DA0 PD_A1 PD_IORDY# R1562 1

0823 DA1
AA1 PD_A1 22 2 4.7K_0402_5%

SATA
AF2 AB3 PD_A2 PD_IRQ R1563 1 2 8.2K_0402_5%
SATA2RXN DA2 PD_A2 22
B
1 1220 Update GPIO33 circuit AF1
SATA2RXP B
AE4 Y6 PD_CS1#
SATA2TXN DCS1# PD_CS1# 22
C1181

AE3 Y5 PD_CS3#
SATA2TXP DCS3# PD_CS3# 22
2 CLK_PCIE_SATA# PD_IOR#
@ 10P_0402_25V8K 15 CLK_PCIE_SATA# AB7 SATA_CLKN DIOR# W4 PD_IOR# 22
CLK_PCIE_SATA AC6 W3 PD_IOW# BATT1
15 CLK_PCIE_SATA SATA_CLKP DIOW# PD_DACK# PD_IOW# 22
Y2 PD_DACK# 22
R1564 DDACK# PD_IRQ
AG1 Y3 PD_IRQ 22
SATARBIAS# IDEIRQ PD_IORDY#
1 2 AG2 Y1 PD_IORDY# 22
SATARBIAS IORDY PD_DREQ#
W5 PD_DREQ# 22
24.9_0402_1% DDREQ
+5VS +3VS ICH8M REV 1.0 CR2032 RTC BATTERY
Within 500 mils
1

R88
R90 +RTCVCC +3VL JP42
10K_0402_5%
10K_0402_5% ACES_85205-0200
BATT1.1
+
2

1
2
D14
R981 W=20mils 2
SATA_LED# 1 2 IDE_LED# 1 2 1 R976
D15 CH751H-40_SC76 IDE_LED# 25 W=20mils
0_0402_5%
3
W=20mils
1 2 W=20mils
-
MB2_LED#1 2 2 DAN202U_SC70 1K_0402_5%
22 MB2_LED#
D16 CH751H-40_SC76
C665 conn@
1U_0603_10V4Z
1

A A
XOR CHAIN ENTRANCE STRAP:RSVD

+3VS R1567
1K_0402_5%
2 1 HDA_SDOUT_CODEC
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(2/4)_LAN,HD,IDE,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 19 of 55
5 4 3 2 1
 5 4 3 2 1

+3VS 1 2 SIRQ R1569 10K_0402_5% Place closely pin G5 Place closely pin AG9
R1576 10K_0402_5% +3VALW 1 2
0316 change design PM_RSMRST#
+3VALW PM_RSMRST# 31
1 2 PM_CLKRUN# CLK_48M_ICH CLK_14M_ICH

1
R1578 8.2K_0402_5%

10K_0402_5%
R1570 R1571

1
1 2 GPIO39

2
R1579 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 1101 For auto boot issue R1574 R1575
U26C

2
@ 1 2 THERM_SCI# R1572 ICH_SMB_CLK AJ26 AJ12 +3VALW @ 10_0402_5% @ 10_0402_5%
SMBCLK SATA0GP/GPIO21 MB_PWR 22

10K_0402_5%
R1582 8.2K_0402_5% ICH_SMB_DATA AD19 AJ10 HDD_HALTLED

2
LINKALERT# SMBDATA SATA1GP/GPIO19
AG21 AF11

SATA
GPIO
1

1
25 CL_RST#1 LINKALERT# SATA2GP/GPIO36 NPCI_RST# 29,31

SMB
1 2 CLKSATAREQ# R1573 ME_EC_CLK1 AC17 SMLINK0 SATA3GP/GPIO37 AG11 GPIO37 1 1
R1600 10K_0402_5% ME_EC_DATA1 AE19 C1182 C1183
SMLINK1 CLK_14M_ICH
31 ME_EC_CLK1 CLK14 AG9 CLK_14M_ICH 15
D D
1 2 GPIO37 0320 add ICH _RI# AF17 G5 CLK_48M_ICH @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C

Clocks
31 ME_EC_DATA1 RI# CLK48 CLK_48M_ICH 15 2 2
R1595 8.2K_0402_5% +3VM
F4 D3 ICH_SUSCLK T14 PAD
30 LPC_PD# SUS_STAT#/LPCPD# SUSCLK
1 2 GPIO18 4 XDP_DBRESET#
XDP_DBRESET# AD15
SYS_RESET#

2
R1601 8.2K_0402_5% 10K_0402_5% 10K_0402_5% AG23 SLP_S3#
SLP_S3# SLP_S3# 23,26,27,31,33,34,41,42,43,44
@ R1580 @ R1581 PM_BMBUSY# AG12 AF21 SLP_S4#
7 PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4# SLP_S4# 34,42 HDD_HALTLED# 25
1 2 GPIO22 AD18 SLP_S5#
SLP_S5# 34,42
R1602 8.2K_0402_5% GPIO11 SLP_S5#
AG22 SMBALERT#/GPIO11
AH27 S4_STATE# 0105 For LED issue
S4_STATE# 28

1
S4_STATE#/GPIO26

1
D

GPIO
1 2 GPIO20 15 H_STP_PCI#
H_STP_PCI# AE20
STP_PCI#/GPIO15

SYS
R1617 8.2K_0402_5% 2 1 R_STP_CPU# AG18 AE23 PM_PWROK HDD_HALTLED2 Q114
15 H_STP_CPU# STP_CPU#/GPIO25 PWROK PM_PWROK 7,31,45
R179 0_0402_5% 1 2 R1583 G RHU002N06_SOT323
1 2 OCP# 0718 INSTALL R179 AH11 AJ14 DPRSLPVR 10K_0402_5% S
25,29,30,31 PM_CLKRUN# DPRSLPVR 7,43

3
CLKRUN#/GPIO32 DPRSLPVR/GPIO16

2
Power MGT
R1590 10K_0402_5%
ICH_PCIE_WAKE# AE17 AE21 ICH_LOW_BAT# 2 1 R15
25 ICH_PCIE_WAKE# WAKE# BATLOW# LOW_BAT# 31
+3VALW 1 2 LINKALERT# 25,29,30,31 SIRQ
SIRQ AF12 CH751H-40PT_SOD323-2 D22 100K_0402_5%
R1587 @ 10K_0402_5% THERM_SCI# SERIRQ ON/OFFBTN# 100K_0402_5%
4 THERM_SCI# AC13 THRM# PWRBTN# C2 ON/OFFBTN# 32
R1722 1 2 +3VL 03/01 change GPIO pin assignment

1
1 2 LID_SW# 1 2 VRMPWRGD AJ20 AH20 1 2 R1630 20070228 auto boot and leakage issue
7,31 VGATE VRMPWRGD LAN_RST# LAN_RST# 35
R1593 10K_0402_5% @ R145 0_0402_5% 0_0402_5%
0612 Change GPIO pin assignment SST_CTL AJ22 AG27 EC_RMRST# 1 2 R1586 PM_RSMRST# +3VALW
PAD T15 TP7 RSMRST#
2 1 ICH_LOW_BAT# 0825 Change GPIO pin assignment 100_0402_5%
R1594 8.2K_0402_5% AJ8 E1 CK_PWRGD_R 1 2 CK_PWRGD U83
4,44 OCP# TACH1/GPIO1 CK_PWRGD CK_PWRGD 15

5
RUNSCI_EC# AJ9 R148 0_0402_5% SN74AHC1G08DCKR_SC70
31 RUNSCI_EC# TACH2/GPIO6
1 2 ICH_PCIE_WAKE# ISO_PREP# AH9 E3 M_PWROK 1

P
33 ISO_PREP# TACH3/GPIO7 CLPWROK M_PWROK 7,35 23,26,27,31,33,34,41,42,43,44 SLP_S3# IN1
R1584 1K_0402_5% 17,32 LID_SW# AE16 4
LAN_PHYPC_R AC19 GPIO8 PM_SLP_M# O
23 LAN_PHYPC 1 2 AJ25 PM_SLP_M# 31,34,42,46 +3VM_LAN 2
GPIO12 SLP_M# IN2

G
1 2 ICH _RI# @ R349 ALS_EN# 0_0402_5%AG8
TACH0/GPIO17
R1597 10K_0402_5% 0821 1 2 SPI_CS1#
GPIO18 AH12 F23 CL_CLK0
CL_CLK0 7
R1588 3.24K_0402_1%

3
GPIO20 AE11 GPIO18 CL_CLK0
R1781 0901 0_0402_5%
GPIO20 CL_CLK1 AE18 CL_CLK1 25 1 2 +3VM

GPIO
Controller Link
1 2 LAN_PHYPC +3VS 1 2 GPIO22 AG10
SCLOCK/GPIO22

1
0.1U_0402_16V4Z
R1603 10K_0402_5% 0622 change value R1632 PAD T48 AH25 F22 CL_DATA0 1
C Cap_RST#_SB AD16 QRT_STATE0/GPIO27 CL_DATA0 CL_DATA0 7 C
8.2K_0402_5% AF19 C1184 R1592
32 Cap_RST#_SB QRT_STATE1/GPIO28 CL_DATA1 CL_DATA1 25
1 2 XDP_DBRESET# 15 CLKSATAREQ#
CLKSATAREQ# AG13 453_0402_1%
R1589 1K_0402_5% GPIO38 AF9 SATACLKREQ#/GPIO35 CL_VREF0_ICH +3VALW
33 DOCK_ID 2 1 D24
R1591 @ 0_0402_5% GPIO39 AJ11 SLOAD/GPIO38 CL_VREF0 CL_VREF1_ICH 2 NA lead free
AH23 2 1

2
SDATAOUT0/GPIO39 CL_VREF1

2
G
1 2 S4_STATE# 22 IDE_RESET#
IDE_RESET# AD10
SDATAOUT1/GPIO48
R1797 10K_0402_5%
R1631 10K_0402_5% AJ23
CL_RST# CL_RST# 7
SB_SPKR AD9 3 1 GPIO11
26 SB_SPKR SPKR 23,24,33 LED_LINK_LAN#
XMIT_OFF RHU002N06_SOT323

D
AJ27 XMIT_OFF 25
+3VS MEM_LED/GPIO24

MISC
M CH_ICH_SYNC# AJ13 AJ24 CB_IN# 0.1U_0402_16V4Z 1 2 Q140
7 MCH_ICH_SYNC# MCH_SYNC# ME_EC_ALERT/GPIO10 +3VALW
AF22 R1738 1 2 R1596 3.24K_0402_1%
EC_ME_ALERT/GPIO14 AMT ADP_PRES 31

1
ICH_RSVD AJ21 AG19 0_0402_5% 1
ICH_RSVD TP3 WOL_EN/GPIO9 LAN_WOL_EN 34
C1185 R1598
1

2.2K_0402_5% ICH8M REV 1.0 453_0402_1%

2.2K_0402_5% R207 R205 low-->default 0612 Change GPIO pin assignment 2
Q26 +3VS 1 2 SB_SPKR NA lead free

2
RHU002N06_SOT323 R1723 @ 10K_0402_5% High -->No boot
2

2
S

ICH_SM_DA 3 1 ICH_SMB_DATA U26D J36

4,25 ICH_SM_DA
P27 V27 DMI_RXN0 2 1
PERN1 DMI0RXN DMI_RXN0 7 CABLE_DETECT 24
S

ICH_SM_CLK 3 1 ICH_SMB_CLK P26 V26 DMI_RXP0

4,25 ICH_SM_CLK PERP1 DMI0RXP DMI_RXP0 7
N29 U29 DMI_TXN0 PAD-SHORT 2x2m
G

DMI_TXN0 7
2

PETN1 DMI0TXN DMI_TXP0 0320 add

N28 U28

Direct Media Interface

PETP1 DMI0TXP DMI_TXP0 7
Q29 WLAN
G
2

+5VS PCIE_RXN2 M27 Y27 DMI_RXN1 DMI_RXN1 7 0_0402_5%

25 PCIE_RXN2 PCIE_RXP2 M26 PERN2 DMI1RXN DMI_RXP1
25 PCIE_RXP2 Y26 DMI_RXP1 7 31 GPIO29
R161 1 2 CB_IN#
PERP2 DMI1RXP
RHU002N06_SOT323 25 PCIE_TXN2 0.1U_0402_16V4Z 2 1 C710 PCIE_C_TXN2 L29 W29 DMI_TXN1
DMI_TXN1 7
+3VM PETN2 DMI1TXN
25 PCIE_TXP2 0.1U_0402_16V4Z 2 1 C711 PCIE_C_TXP2 L28 PETP2 DMI1TXP W28 DMI_TXP1
DMI_TXP1 7
1 2 +3VALW

PCI-Express
0316 change design K27 AB26 DMI_RXN2 R1599 10K_0402_5%
PERN3 DMI2RXN DMI_RXN2 7
K26 AB25 DMI_RXP2
PERP3 DMI2RXP DMI_RXP2 7
1

2.2K_0402_5% J29 AA29 DMI_TXN2

PETN3 DMI2TXN DMI_TXN2 7 +3VS
2.2K_0402_5% R206 R204 J28 AA28 DMI_TXP2
B PETP3 DMI2TXP DMI_TXP2 7 B
Q24
0629 connect to +3VM RHU002N06_SOT323 Robson PCIE_RXN4 H27 AD27 DMI_RXN3
25 PCIE_RXN4 PERN4 DMI3RXN DMI_RXN3 7

2
PCIE_RXP4 H26 AD26 DMI_RXP3
25 PCIE_RXP4 DMI_RXP3 7
2

PERP4 DMI3RXP
S

13,14,15 ICH_SMBDATA 3 1 ICH_SMB_DATA 25 25 PCIE_TXN4 0.1U_0402_16V4Z 2 1 C708 PCIE_C_TXN4 G29 PETN4 DMI3TXN AC29 DMI_TXN3
DMI_TXN3 7 R433
25 PCIE_TXP4 0.1U_0402_16V4Z 2 1 C709 PCIE_C_TXP4 G28 AC28 DMI_TXP3 DMI_TXP3 7
PETP4 DMI3TXP
S

3 1 330_0402_5%
13,14,15 ICH_SMBCLK ICH_SMB_CLK 25
PCIE_RXN5 CLK_PCIE_ICH#
G

33 PCIE_RXN5 F27 T26 CLK_PCIE_ICH# 15

2

1
+3VM Q25 PCIE_RXP5 PERN5 DMI_CLKN CLK_PCIE_ICH ALS_EN
33 PCIE_RXP5 F26 T25 CLK_PCIE_ICH 15 ALS_EN 17
PERP5 DMI_CLKP
RHU002N06_SOT323 Dock 0.1U_0402_16V4Z 2 1C1361 PCIE_C_TXN5 E29
G

33 PCIE_TXN5
2

PETN5

1
D
1 2 33 PCIE_TXP5 0.1U_0402_16V4Z 2 1C1362 PCIE_C_TXP5 E28 PETP5 DMI_ZCOMP Y23 R1016 24.9_0402_1% Within 500 mils
R1756 0_0402_5% Y24 DMI_IRCOMP 1 2 ALS_EN# 2
DMI_IRCOMP +1.5VS
GLAN_RXN D27 G Q45
23 GLAN_RXN PERN6/GLAN_RXN
S

100K_0402_5% 3 1 GLAN_RXP D26 G3 USB20_N0 S

+5VALW 23 GLAN_RXP USB20_N0 28

3
PERP6/GLAN_RXP USBP0N
1 2 DPRSLPVR GLAN 23 GLAN_TXN 0.1U_0402_16V4Z 2 1 C1186 GLAN_TXN_C C29 G2 USB20_P0
USB20_P0 28 Right side RHU002N06_SOT323
R1604 Q130@ 0.1U_0402_16V4Z GLAN_TXP_C PETN6/GLAN_TXN USBP0P USB20_N1
23 GLAN_TXP 2 1 C1187 C28 PETP6/GLAN_TXP USBP1N H5 USB20_N1 30
RHU002N06_SOT323 USB20_P1 Fingerprint
G

H4 USB20_P1 30
2

USBP1P
2 1 ICH_RSVD 15_0402_5% 1 2 R1605 SPI_CLK_R C23 H2 0731 Elimanate glitch
@ R1568 PM_SLP_M# 30 SPI_CLK 15_0402_5% SPI_CS0#_R SPI_CLK USBP2N
1 2 R1606 B23 H1
1K_0402_5% 30 SPI_CS0# 15_0402_5% SPI_CS1#_R SPI_CS0# USBP2P +3VS
1 2 R1607 E22 J3 0809 Elimanate glitch
30 SPI_CS1# SPI_CS1# USBP3N
SPI

18 SPI_CS1#_R J2 25,31,34,35,43,44 PWR_GD

SPI_SI_R USBP3P USB20_N4
0601 add for SM bus 0_0402_5% 2 1 R1640 D23
SPI_MOSI USBP4N
K5 USB20_N4 28

2
30 SPI_SI 0_0402_5% 1 R1641 SPI_SO_R USB20_P4
30 SPI_SO
2 F21 SPI_MISO USBP4P K4
USB20_N5 USB20_P4 28 Left side
RP55 K2
USB_OC#6 USB_OC#0 USBP5N USB20_P5 USB20_N5 28
4 5 AJ19 K1 Left side 10K_0402_5% 10K_0402_5%
USB_OC#1 +3VALW USB_OC#1 OC0# USBP5P USB20_N6 USB20_P5 28
3 6 R352 1 2 AG16 L3 R1767 @ R434
28 BT_OFF OC1#/GPIO40 USBP6N USB20_N6 28
USB_OC#2 0_0402_5% USB_OC#2 USB20_P6
2 7 AG15 USB L2 USB20_P6 28 Bluetooth

1
USB_OC#4 WXMIT_OFF# OC2#/GPIO41 USBP6P USB20_N7
1 8 25 WXMIT_OFF# AE15 OC3#/GPIO42 USBP7N M5 USB20_N7 33 1 2 CK_PWRGD
USB_OC#4 AF15 M4 USB20_P7 Dock1 R147 @ 0_0402_5%
OC4#/GPIO43 USBP7P USB20_P7 33

1
10K_1206_8P4R_5% +3VS 0320 change USB_OC#5 USB20_N8 D
AG17 M2 USB20_N8 25
USB_OC#6 OC5#/GPIO29 USBP8N USB20_P8
AD12 M1 USB20_P8 25 WWAN 43 CLK_EN# 2 1 2 VRMPWRGD
OC6#/GPIO30 USBP8P

1
RP56 0110 Resolve +3vs leakage issue USB_OC#7 AJ18 N3 USB20_N9 G 1 R146 0_0402_5%
USB_OC#7 4 OC7#/GPIO31 USBP9N USB20_N9 33
5 1 2 IDE_RESET# USB_OC#8 AD14 N2 USB20_P9
USB20_P9 33 Dock2 Q20 S

3
A USB_OC#8 3 R11 8.2K_0402_5% USB_OC#9 OC8# USBP9P RHU002N06_SOT323 A
6 AH18
USB_OC#9 2 OC9#
7 1 2 NPCI_RST# USBRBIAS# F2 USBRBIAS 1 2 @ R1757
USB_OC#0 1 R3 8.2K_0402_5% 2 100K_0402_5%
8 F3

2
+3VALW +3VS USBRBIAS
10K_1206_8P4R_5% 1 2 MB_PWR R1019 22.6_0402_1%
R1608 R6 8.2K_0402_5% ICH8M REV 1.0 @ C1365
10K_0402_5% Within 500 mils 0.22U_0402_10V4Z
1

XMIT_OFF 1 2
1 2 ALS_EN# R1007 R1008
R1609 R16 8.2K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
10K_0402_5% 1 2 PM_BMBUSY# 10K_0402_5%
D57
10K_0402_5% Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
USB_OC#5 1 2 R9 8.2K_0402_5%
ICH8(3/4)_PM,USB,GPIO
2

R1810 PREP# 1 2 ISO_PREP#

24,26,33 PREP# THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
10K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
WXMIT_OFF# 1 2 Custom LA-3261P U MA 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
20070326 Add R1810 0529 add for SB GPI CH751H-40_SC76 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 20 of 55
5 4 3 2 1
 5 4 3 2 1

+RTCVCC U26E
20 mils A23
VSS[001] VSS[099]
K7

0.1U_0402_16V4Z

0.1U_0402_16V4Z
A5 VSS[002] VSS[100] L1
1 1 AA2 VSS[003] VSS[101] L13

C1188

C1189
AA7 L15
+VCCP VSS[004] VSS[102]
A25 VSS[005] VSS[103] L26
AB1 VSS[006] VSS[104] L27
2 2 AB24 L4
U26F 0.1U_0402_16V4Z VSS[007] VSS[105]
AC11 VSS[008] VSS[106] L5
AD25 A13 AC14 M12
VCCRTC VCC1_05[01] VSS[009] VSS[107]
VCC1_05[02] B13 AC25 VSS[010] VSS[108] M13
ICH_V5REF_RUN A16 C13 1 1 AC26 M14
V5REF[1] VCC1_05[03] C1192 C1193 0.1U_0402_16V4Z VSS[011] VSS[109]
T7 V5REF[2] VCC1_05[04] C14 AC27 VSS[012] VSS[110] M15
R1372 D14 AD17 M16
ICH_V5REF_SUS VCC1_05[05] VSS[013] VSS[111]
G4 V5REF_SUS VCC1_05[06] E14 AD20 VSS[014] VSS[112] M17
D 2 2 D
+1.5VS 1 2 40 mils 10U_0805_10V4Z
VCC1_05[07] F14 AD28 VSS[015] VSS[113] M23
1 AA25 VCC1_5_B[01] VCC1_05[08] G14 AD29 VSS[016] VSS[114] M28
CHB1608U301_0603 1 1 1 AA26 L11 AD3 M29
+ C1195 C1196 C1197 VCC1_5_B[02] VCC1_05[09] VSS[017] VSS[115]
AA27 L12 AD4 M3
VCC1_5_B[03] VCC1_05[10] VSS[018] VSS[116]

C1194
AB27 L14 AD6 N1
220U_D2_4VM VCC1_5_B[04] VCC1_05[11] VSS[019] VSS[117]
AB28 VCC1_5_B[05] VCC1_05[12] L16 AE1 VSS[020] VSS[118] N11
2 2 2 2 AB29 L17 CHB1608U301_0603 AE12 N12
+5VS +3VS VCC1_5_B[06] VCC1_05[13] R1370 VSS[021] VSS[119]
D28 VCC1_5_B[07] VCC1_05[14] L18 AE2 VSS[022] VSS[120] N13
10U_0805_10V4Z 2.2U_0603_6.3V4Z D29 M11 0.01U_0402_16V7K 1 2 +1.5VS AE22 N14
VCC1_5_B[08] VCC1_05[15] VSS[023] VSS[121]

CORE
E25 M18 AD1 N15
VCC1_5_B[09] VCC1_05[16] VSS[024] VSS[122]
1

E26 VCC1_5_B[10] VCC1_05[17] P11 1 1 AE25 VSS[025] VSS[123] N16

R1610 D55 E27 P18 C1199 10U_0805_10V4Z AE5 N17
VCC1_5_B[11] VCC1_05[18] VSS[026] VSS[124]
F24 VCC1_5_B[12] VCC1_05[19] T11 AE6 VSS[027] VSS[125] N18
100_0402_5% CH751H-40_SC76 F25 T18 C1198 AE9 N26
VCC1_5_B[13] VCC1_05[20] 2 2 0316 change design VSS[028] VSS[126]
20 mils G24 U11 AF14 N27
2

VCC1_5_B[14] VCC1_05[21] VSS[029] VSS[127]

H23 U18 AF16 N4
ICH_V5REF_RUN VCC1_5_B[15] VCC1_05[22] VSS[030] VSS[128]
H24 VCC1_5_B[16] VCC1_05[23] V11 AF18 VSS[031] VSS[129] N5
1 J23 V12 AF3 N6
C1190 VCC1_5_B[17] VCC1_05[24] VSS[032] VSS[130]
J24 VCC1_5_B[18] VCC1_05[25] V14 +1.25VS AF4 VSS[033] VSS[131] P12
K24 V16 AG5 P13
0.1U_0402_16V4Z VCC1_5_B[19] VCC1_05[26] VSS[034] VSS[132]
K25 V17 AG6 P14
2 VCC1_5_B[20] VCC1_05[27] VSS[035] VSS[133]

22U_0805_6.3VAM
L23 V18 AH10 P15
VCC1_5_B[21] VCC1_05[28] VSS[036] VSS[134]
L24 VCC1_5_B[22] 1 AH13 VSS[037] VSS[135] P16

VCCA3GP

C1201
L25 R29 0317 change value AH16 P17
VCC1_5_B[23] VCCDMIPLL VSS[038] VSS[136]
M24 AH19 P23
VCC1_5_B[24] VSS[039] VSS[137]
M25 VCC1_5_B[25] VCC_DMI[1] AE28 AH2 VSS[040] VSS[138] P28
N23 AE29 2 +VCCP AF28 P29
+5VALW +3VALW VCC1_5_B[26] VCC_DMI[2] VSS[041] VSS[139]
N24 AH22 R11
VCC1_5_B[27] VSS[042] VSS[140]
N25 VCC1_5_B[28] V_CPU_IO[1] AC23 AH24 VSS[043] VSS[141] R12
P24 VCC1_5_B[29] V_CPU_IO[2] AC24 AH26 VSS[044] VSS[142] R13
1

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P25 AH3 R14
R1611 D56 VCC1_5_B[30] 0.1U_0402_16V4Z +3VS VSS[045] VSS[143]
R24 AF29 1 1 1 AH4 R15
VCC1_5_B[31] VCC3_3[01] VSS[046] VSS[144]

C1202

C1203

C1204
C (DMI) C
R25 VCC1_5_B[32] 1 AH8 VSS[047] VSS[145] R16
10_0402_5% CH751H-40_SC76 R26 AD2 0.1U_0402_16V4Z +3VS AJ5 R17
VCC1_5_B[33] VCC3_3[02] VSS[048] VSS[146]
R27 1 (SATA) C1205 B11 R18
2

ICH_V5REF_SUS VCC1_5_B[34] 2 2 2 VSS[049] VSS[147]

T23 VCC1_5_B[35] VCC3_3[03] AC8 +3VS B14 VSS[050] VSS[148] R28
2

C1206
20 mils T24 AD8 B17 R4

VCCP_CORE
VCC1_5_B[36] VCC3_3[04] VSS[051] VSS[149]
1 T27 AE8 B2 T12
C1200 VCC1_5_B[37] VCC3_3[05] +3VS 2 VSS[052] VSS[150]
T28 VCC1_5_B[38] VCC3_3[06] AF8 B20 VSS[053] VSS[151] T13
T29 B22 T14
0.1U_0402_16V4Z VCC1_5_B[39] 0.1U_0402_16V4Z VSS[054] VSS[152]
U24 VCC1_5_B[40] VCC3_3[07] AA3 B8 VSS[055] VSS[153] T15
2 U25 U7 C24 T16
VCC1_5_B[41] VCC3_3[08] 1 VSS[056] VSS[154]
V23 V7 C1207 C26 T17
VCC1_5_B[42] VCC3_3[09] VSS[057] VSS[155]
V24 W1 C27 T2
VCC1_5_B[43] VCC3_3[10] VSS[058] VSS[156]
V25 W6 C6 U12

IDE
VCC1_5_B[44] VCC3_3[11] 2 +3VS VSS[059] VSS[157]
W25 W7 D12 U13
VCC1_5_B[45] VCC3_3[12] VSS[060] VSS[158]
R1366 Y25 Y7 D15 U14
VCC1_5_B[46] VCC3_3[13] VSS[061] VSS[159]
D18 U15
VSS[062] VSS[160]
+1.5VS 1 2 AJ6 A8 D2 U16
VCCSATAPLL VCC3_3[14] VSS[063] VSS[161]

0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1U_0603_10V4Z

B15 1 1 1 D4 U17
VCC3_3[15] VSS[064] VSS[162]
10U_0805_10V4Z

CHB1608U301_0603 AE7 B18 E21 U23

+1.5VS VCC1_5_A[01] VCC3_3[16] VSS[065] VSS[163]

C1208

C1209

C1210
1 1 AF7 VCC1_5_A[02] VCC3_3[17] B4 E24 VSS[066] VSS[164] U26
ARX
C1211

C1212

1 AG7 B9 E4 U27
0316 change design C1213 VCC1_5_A[03] VCC3_3[18] 2 2 2 VSS[067] VSS[165]
AH7 C15 E9 U3
VCC1_5_A[04] VCC3_3[19] VSS[068] VSS[166]
AJ7 D13 F15 U5
PCI

2 2 1U_0603_10V4Z VCC1_5_A[05] VCC3_3[20] VSS[069] VSS[167]

D5 E23 V13
2 VCC3_3[21] VSS[070] VSS[168]
AC1 E10 F28 V15
VCC1_5_A[06] VCC3_3[22] VSS[071] VSS[169]
AC2 E7 F29 V28
VCC1_5_A[07] VCC3_3[23] VSS[072] VSS[170]
ATX

AC3 VCC1_5_A[08] VCC3_3[24] F11 F7 VSS[073] VSS[171] V29

AC4 +3VS G1 W2
VCC1_5_A[09] 0.1U_0402_16V4Z VSS[074] VSS[172]
AC5 AC12 E2 W26
VCC1_5_A[10] VCCHDA VSS[075] VSS[173]
1 G10 W27
0.1U_0402_16V4Z VSS[076] VSS[174]
AC10 AD11 +3VALW G13 Y28
+1.5VS VCC1_5_A[11] VCCSUSHDA C1214 VSS[077] VSS[175]
1 AC9 1 G19 Y29
B C1216 VCC1_5_A[12] VSS[078] VSS[176] B
VCCSUS1_05[1] J6 G23 VSS[079] VSS[177] Y4
T28 C1215 2
AA5 VCC1_5_A[13] VCCSUS1_05[2] AF20 G25 VSS[080] VSS[178] AB4
1U_0603_10V4Z AA6 T29 G26 AB23
2 VCC1_5_A[14] 2 VSS[081] VSS[179]
VCCSUS1_5[1] AC16 VCCSUS1_5_ICH_1 G27 VSS[082] VSS[180] AB5
G12 T17 H25 AB6
VCC1_5_A[15] VCCSUS1_5_ICH_2 +3VALW VSS[083] VSS[181]
G17 J7 H28 AD5
VCC1_5_A[16] VCCSUS1_5[2] T18 VSS[084] VSS[182]
H7 H29 U4
VCC1_5_A[17] VSS[085] VSS[183]

0.1U_0402_16V4Z
C3 0.1U_0402_16V4Z H3 W24
VCCSUS3_3[01] VSS[086] VSS[184]
AC7 1 1 H6
VCC1_5_A[18] VSS[087] ICH GND1 1
AD7 VCC1_5_A[19] VCCSUS3_3[02] AC18 J1 VSS[088] VSS_NCTF[01] A1 2
C1217

C1218
AC21 J25 A2 R138 0_0402_5%
VCCSUS3_3[03] VSS[089] VSS_NCTF[02]
+1.5VS D1 AC22 J26 A28
VCCPSUS

VCCUSBPLL VCCSUS3_3[04] 2 2 VSS[090] VSS_NCTF[03]

+1.5VS VCCSUS3_3[05] AG20 J27 VSS[091] VSS_NCTF[04] A29 ICH GND2 1 2
1 1 F1 AH28 J4 AH1 R152 0_0402_5%
VCC1_5_A[20] VCCSUS3_3[06] VSS[092] VSS_NCTF[05]
USB CORE

C1219 C1220 L6 VCC1_5_A[21]

04/10 monitor SB crack J5 VSS[093] VSS_NCTF[06] AH29
L7 P6 +3VALW K23 AJ1 ICH GND3 1 2
VCC1_5_A[22] VCCSUS3_3[07] VSS[094] VSS_NCTF[07]
0.1U_0402_16V4Z 0.1U_0402_16V4Z M6
VCC1_5_A[23] VCCSUS3_3[08]
P7 1013 no install K28
VSS[095] VSS_NCTF[08]
AJ2 R153 0_0402_5%
2 2 M7 C1 K29 AJ28
VCC1_5_A[24] VCCSUS3_3[09] VSS[096] VSS_NCTF[09]
N7 1 1213 Install K3 AJ29 ICH GND4 1 2
VCCSUS3_3[10] C1222 VSS[097] VSS_NCTF[10] R137 0_0402_5%
+1.5VS W23 P1 K6 B1
VCC1_5_A[25] VCCSUS3_3[11] VSS[098] VSS_NCTF[11]
VCCSUS3_3[12]
P2 20070227 No install VSS_NCTF[12]
B29
T30 VCC_LAN1_05_INT_ICH_1 F17 P3 4.7U_0603_6.3V6M
VCCPUSB

+3VM 0316 change design T31 VCC_LAN1_05_INT_ICH_2 VCCLAN1_05[1] VCCSUS3_3[13] 2 ICH8M REV 1.0
G18 P4
VCCLAN1_05[2] VCCSUS3_3[14] +3VL
VCCSUS3_3[15] P5 1213 no install
F19 R1 +3VS +3VS +3VS 20070227 Install
VCCLAN3_3[1] VCCSUS3_3[16] +3VS
1 G20 R3
VCCLAN3_3[2] VCCSUS3_3[17]

2
C1223 CHB1608U301_0603
VCCSUS3_3[18] R5 20070228 Change to +3VL

100K_0402_5%

100K_0402_5%

100K_0402_5%
1 2 A24 R6 @ R1716 @ R1715
VCCGLANPLL VCCSUS3_3[19]
2

2
0.1U_0402_16V4Z R1365 4.7U_0805_10V4Z
R1371 CRACK_GPIO28 CRACK_GPIO28 CRACK_GPIO28
2 +1.5VS
GLAN POWER
2.2U_0603_6.3V4Z

1 1 +1.5VS 2 1 A26 G22 VCCCL1_05_ICH @ R1718 @ R1719

VCCGLAN1_5[1] VCCCL1_05 T19 100K_0402_5% @ R1717 100K_0402_5%
1 A27

1 1
C1224 CHB1608U301_0603 VCCGLAN1_5[2] 1U_0603_10V4Z 1 CRACK_GPIO28 11,31
B26 VCCGLAN1_5[3] VCCCL1_5 A22
1

1
A C1225 D D D D A
B27
1

1
2 2 VCCGLAN1_5[4]
C1229
10U_0805_10V4Z

C1228 B28 F20 ICH GND3 2 ICH GND4 2 ICH GND2 2 ICH GND1 2
2 VCCGLAN1_5[5] VCCCL3_3[1] +3VM
G21 G G G G
0316 change design VCCCL3_3[2] 2 @ Q124 @ Q125 @ Q126 @ Q127
+3VS B25 @ S S S S
3

3
VCCGLAN3_3 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323
ICH8M REV 1.0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(4/4)_POWER&GND
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 21 of 55
5 4 3 2 1
 5 4 3 2 1

+3V_U43 Multi Bay II connector

1 2
20 IDE_RESET#
C641 0.1U_0402_16V4Z conn@ JP5

14
JP45 conn@ 1
R301 1
S1 9 2

P
GND A 2
RX+ S2 SATA_TXP0 19 O 8 2 1 ODD_RST# 3 3
S3 PLT_RST_B# 2 1 10 33_0402_5% 4
RX- SATA_TXN0 19 B 4

G
S4 R1036 0_0402_5% 5 ODD_RST#
GND SATA_RXN0 5 PD_D8 PD_D[0..15] 19
S5 3900P_0402_50V7K 1 2 C474 U43C 6
SATA_RXN0_C 19

7
TX- SATA_RXP0 3900P_0402_50V7K 6 PD_D7
TX+ S6 1 2 C475 SATA_RXP0_C 19
SN74LVC08APW_TSSOP14
7 7
S7 2 1 8 PD_D9
GND 18,25 PCI_RST# 8
R1037 @ 0_0402_5% 9 PD_D6
D 9 PD_D10 D
close SATA connector 10 10
P1 11 PD_D5
3.3V 11 PD_D11
3.3V P2 12 12
P3 13 PD_D4
3.3V 13 PD_D12
P4 14
GND 14 PD_D3
GND P5 15 15
P6 16 PD_D13
GND 16 PD_D2
5V P7 17 17
P8 1U_0402_10V4Z 18 PD_D14
5V 10U_0805_10V4Z 0.1U_0402_16V4Z 18 PD_D1
P9 +5VS 19
5V 19 PD_D15
GND P10 20 20
P11 21 PD_D0
Rsv 21 PD_DREQ
GND P12 1 1 1 1 1 22 22 PD_DREQ# 19
P13 23
12V C1235 23 PD_IOR#
P14 24 PD_IOR# 19
12V C1232 C1234 C1236 C1233 24 PD_IOW#
P15 25 PD_IOW# 19
12V 2 2 2 2 2 25
26 26
27 PD_IORDY
GND
GND

PD_IORDY# 19
boss
boss

27 PD_DACK#
28 28 PD_DACK# 19
29 PD_IRQ PD_IRQ 19
0.1U_0402_16V4Z 1000P_0402_50V7K 29
30
26
25

24
23

30 PD_A1
31 PD_A1 19
OCTEK_SAT-22DD1G 31
32 32
33 PD_A0
33 PD_A0 19
34 PD_A2
34 PD_A2 19
35 PD_CS#1 PD_CS1# 19
35 PD_CS#3
36 PD_CS3# 19
36 MB2_LED#
37 MB2_LED# 19
37
04/10 change footprint 38 38
39 39
+3VS 40
40
41
C 41 C
42 42 +5VS_MB

1
43
RR72 43
44
4.7K_0402_5% 44 MBAY_DET#
45 45
46 46
47

2
47
48 48

1
MBAY_DET# 49
18 MBAY_DET# 49
1 50 R1032
C628 50 0_0402_5%
55 51
GND 51
56 GND 52 52
0.1U_0402_16V4Z 57 53

2
2 GND 53
58 GND 54 54

JAE_WM2M054JKB

0619 change +5VS

+5VS +5VS_MB
Q92
1109 Remove kensington circuit
AO4407_SO8
1 8

1
Kensington Conn R83 C640
1 2
3
7
6
1 1
C625
470K_0402_5% 5
10U_0805_10V4Z 0.1U_0402_16V4Z
2 C624 2 2

4
10U_0805_10V4Z
1 2

1
D
220K_0402_5% 1C633
20 MB_PWR 2
B G R93 B
Q38 S 0.1U_0402_16V4Z

3
RHU002N06_SOT323 2
Place close to JP29
+5VS_MB

+5VS_MB
1 1
C626 C627

1
R98 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
100_0402_5%

1 2
D
2
G
Q39 S

3
RHU002N06_SOT323
+3V_U43
ZZZ2 ZZZ3

14
12 Audio-wire PCB-MB
P
7,16,18,30 PLT_RST# A
11 PLT_RST_B#
O PLT_RST_B# 25,29,30
13 B
G

A A
U43D
7

SN74LVC08APW_TSSOP14

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 22 of 55
5 4 3 2 1
 5 4 3 2 1

1128 Install Q102,R1730, no install R1612,Q104,Q105.

@ R1612 0_1206_5%
1 2
+3VM 40 mils

S
1000P_0402_50V7K 3 1

D
+3VM_LAN

4.7U_0603_6.3V6M
1

C1242
SI2301BDS_SOT23

G
2

2
R1613 Q102
1M_0402_5% C1243
2
D 1 D

1
R1614
1 2

100K_0402_5%

1
D
20 mils
20 LAN_PHYPC 2 Q103 0.1U_0402_16V4Z +1.8VM
G BSS138_SOT23
S

3
2 2 2 2 2

1
4.7U_0603_6.3V6M C1245 C1246 C1247 470P_0402_50V7K

1
D R1730 C1244 C1248
31,38,39,40,44 ADP_PRES 2 0_0402_5%
G 1 1 1 1 1
@ Q104 S
3

2
RHU002N06_SOT323
0.1U_0402_16V4Z 470P_0402_50V7K
1
D

20,26,27,31,33,34,41,42,43,44 SLP_S3# 2
G
@Q105 S
3

RHU002N06_SOT323

20 mils +V1.0_LAN_M
4.7U_0603_6.3V6M 0.1U_0402_16V4Z

XTAL1 2 2 2 2 2
near U74 XTAL2 C1250 C1251 C1252 470P_0402_50V7K
C1249 C1253
C C

H5
H6
R1615 33_0402_5% U74 1 1 1 1 1
1 2 GLANCLK E2 J9

XTAL2-X2
XTAL1-X1
19 GLAN_CLK JKCLK-JCLK VSSA[17]-NC
VSSA[16]-NC J8
19 LAN_RSTSYNC E3 J5 0.1U_0402_16V4Z 470P_0402_50V7K
JRSTSYNC VSSA[15]-VSSA2
J3
LAN_TXD0 VSSA[14]-VSS
19 LAN_TXD0 D1 JTXD0 LCI VSSA[13]-NC J1
LAN_TXD1 F3 G9
19 LAN_TXD1 JTXD1 VSSA[12]-VSS
LAN_TXD2 F1 G8
19 LAN_TXD2 JTXD2 VSSA[11]-VSS
G6
LAN_RXD0 VSSA[10]-VSS
19 LAN_RXD0 D3 JRXD0 VSSA[09]-VSS F6 0620 fix to IVRD
LAN_RXD1 D2 E9
19 LAN_RXD1 JRXD1 VSSA[08]-VSS
LAN_RXD2 C1 D6
19 LAN_RXD2 JRXD2 VSSA[07]-VSS
C9
C490 0.1U_0402_16V4Z VSSA[06]-VSS +3VM_LAN Q106 +1.8VM
C8
GLAN_RXP_CH2 VSSA[05]-VSS BCP69_SOT223
20 GLAN_RXP 1 2 C7
GLAN_RXN_C J2 GLAN_TXP-NC VSSA[04]-VSS
20 GLAN_RXN 1 2 C6 4
C1319 0.1U_0402_16V4Z GLAN_TXN-NC VSSA[03]-VSSR 0.1U_0402_16V4Z
A9 3 2
VSSA[02]-NC
GLCI

10U_0805_10V4Z
GLAN_TXP J4 A8
20 GLAN_TXP GLAN_RXP-NC VSSA[01]-VSS
GLAN_TXN H4 F4 2 2 2 1
20 GLAN_TXN GLAN_RXN-NC VSS[04]-VSS
2

C1257
10N_0603_50V7K
E1 C1256
1.4K_0402_1% R1616 LAN_KBIAS_P VSS[03]-VSSP
G7 C4 1

1
LAN_KBIAS_N KBIAS_P-RBIAS100 VSS[02]-VSS C1254 C1255
H7 A1
KBIAS_N-RBIAS10 VSS[01]-NC 4.7U_0603_6.3V6M1 1 1 2
C1258
1

LED_LINK_LAN# +V1.0_LAN_M 2
20,24,33 LED_LINK_LAN# A4
LED0-LINK_UP_N VDD1P0[03]-VCCA
F7 0905
LED_ACT_LAN# B4 E8 R1618 0.1U_0402_16V4Z
24,33 LED_ACT_LAN# LED1-ACT_LED_N VDD1P0[02]-VCCT
A5 D7 1 2 LAN_CTRL_18
LED2-SPEED_LED_N VDD1P0[01]-VCCR +V1.0M_LAN
0_0603_5%
LAN_MDI0P B8 E5
24 LAN_MDI0P MDI_PLUS[0]-TDP VCCF1P0-VCC
LAN_MDI0N B9
B 24 LAN_MDI0N MDI_MINUS[0]-TDN B
0620 add for POWER ripple, close to chip
MDI

LAN_MDI1P D9 H3 R1619 0_0603_5%

24 LAN_MDI1P MDI_PLUS[1]-RDP VCCFC1P0-VCC
LAN_MDI1N D8 1 2
24 LAN_MDI1N MDI_MINUS[1]-RDN +3VM_LAN
F2 +3.3V_LAN C1363 1U_0402_6.3V4Z
LAN_MDI2P VCC3P3[02]-VCCP
24 LAN_MDI2P F9 B3 2 1
LAN_MDI2N MDI_PLUS[2]-NC VCC3P3[01]-VCC Q128
24 LAN_MDI2N F8
MDI_MINUS[2]-NC R1620 0_0603_5% +3VM_LAN +V1.0M_LAN
LAN_MDI3P H8 G5 +1.8VM_LAN 1 2 BCP69_SOT223
24 LAN_MDI3P MDI_PLUS[3]-NC VCC1P8[04]-NC +1.8VM
LAN_MDI3N H9 F5 R1734 0_0402_5% 4
24 LAN_MDI3N MDI_MINUS[3]-NC VCC1P8[03]-NC

10U_0805_10V4Z
D5 1 2 V1P_OUT 0.1U_0402_16V4Z 3 2 0905
VCC1P8[02]-NC C1364 1U_0402_6.3V4Z
VCC1P8[01]-NC C2
IEEE_TEST_P A7 2 1 2 2 2 1
IEEE_TEST_P-NC

C1359
1 2IEEE_TEST_N B7 IEEE_TEST_N-NC VCC1P0-VCCA2 G4 +V1.0_LAN_M
+V1.0_LAN_M

10N_0603_50V7K
1 2 LAN_KBIAS_P R1621 @ 0_0402_5% C1357 1

1
@ R1622 649_0402_1% J6 E4 4.7U_0603_6.3V6M
RSVD_J6-NC VCC[02] 1 1 1 2
closed to E6 pin J7
RSVD_J7-NC JTAG VCC[01]
D4 C1356
1 2 LAN_KBIAS_N C1360
@ R1623 619_0402_1% R1625 1.4K_0603_1% B1 V1P_OUT 2
V1P0_OUT-NC 0.1U_0402_16V4Z
2 1 E7
JTAG_TMS-ISOL_EXEC

RBIAS_P-NC C1358
JTAG_TCK-ISOL_TCK

E6
RBIAS_N-NC LAN_CTRL_10 LAN_CTRL_10
C3
JTAG_TDI-ISOL_TI

CTRL_10-NC
JTAG_TDO-TOUT

B2 LAN_CTRL_18
CTRL_18-NC
B5
RSVD_B5-NC
A6
RSVD_A6-ADV10/LAN_DIS_N LAN_THERM_D_P
C5 A2
RSVD_C5-NC THERM_D_P-NC LAN_THERM_D_N 1
1 2 B6 TEST_EN THERM_D_N-NC A3 2
R1627 100_0402_5% @ R1628 0_0603_5%

RU82566DM B0 Q870 BGA 81P

G1
H1
G3
G2

@ R1629 200_0402_5%
A A
1 2 +3VM_LAN
T68 PAD PAD T69
T70 PAD PAD T71
Y9 XTAL1
+3VM_LAN 1 2
@ R1634 200_0402_5%
1 2 XTAL2_R 1 2 XTAL2

R1804
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title
C1263 25MHZ_20P_1BG25000CK1A C1264 30_0402_5% 0104 Intel request Intel 82566 Nineveh
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
27P_0402_50V8J 27P_0402_50V8J Size Document Number R ev
1 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P UMA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 23 of 55
5 4 3 2 1
 5 4 3 2 1

LAN_MDI0N 12
T66
TD4- MX4- 13 MDO0- RJ-45 CONN.
0612 CHANGE
+1.8VM LAN ENERGY DET
LAN_MDI0P 11 14 MDO0+
TD4+ 1:1 MX4+ +3VM
2 1 TRM_CT 10 15 MCT0 2 R269 1
C330 TCT4 MCT4 75_0402_1%
0.1U_0402_16V4Z LAN_MDI1N 9 16 MDO1- 100K_0402_5% 200K_0402_5% 1.5K_0402_5%
TD3- MX3-

1
1

1
D
02/27 change D
@ R1636 C1265
LAN_MDI1P 8 17 MDO1+ R1635 R1637 0.1U_0402_16V4Z
TD3+ 1:1 MX3+ C344 C1266 0.01U_0402_16V7K 2

5
2 1 TRM_CT 7 18 MCT1 2 R270 1 1 2 U75

2
C327 TCT3 MCT3 75_0402_1% LAN_MDI0P 2 R55 1 ED_ACT
1 2 1

P
0.1U_0402_16V4Z LAN_MDI2N 6 MDO2- 1000P_1808_3KV7K 10K_0402_5% 10P_0402_50V8J IN+
TD2- MX2- 19 O 4 1 2
ED_VREF 3 ENERGY_DET 19
IN-

G
1
LAN_MDI1P 2 1 R69 1 2 1 R51 0_0402_5%

1
10K_0402_5% R1638

2
C1267 0.01U_0402_16V7K C1268 R1639
LAN_MDI2P 5 20 MDO2+ 100K_0402_5% 1.87K_0402_1% LMV331IDCKRG4_SC70-5~D
TD21+ 1:1 MX2+ 2

2
2 1 TRM_CT 4 21 MCT2 2 R271 1

2
C328 TCT2 MCT2 75_0402_1%
0.1U_0402_16V4Z LAN_MDI3N 3 22 MDO3-
TD1- MX1-
CAP closed to LAN_MDIO bus

LAN_MDI3P 2 23 MDO3+ 1113 Change R1639 to 1.4K based on Intel WW44

TD1+ 1:1 MX1+ C320
2 1 TRM_CT 1 24 MCT3 2 R272 1 1 2 1116 Intel recommend
C329 TCT1 MCT1 75_0402_1%
0.1U_0402_16V4Z 24HST1041A-3_24P 1000P_1808_3KV7K

0809 add for EMI request

0.1U_0402_16V4Z 1 2 C56 R50 1 2 49.9_0402_1% LAN_MDI0N 23 @ D72

C R63 1 49.9_0402_1% C
2 LAN_MDI0P 23
0.1U_0402_16V4Z 1 2 C54 R45 1 2 49.9_0402_1% LAN_MDI1N 23
R48 1 2 49.9_0402_1% MDO3- 1 5 MDO2+
LAN_MDI1P 23
0.1U_0402_16V4Z 1 2 C50 R42 1 2 49.9_0402_1% LAN_MDI2N 23
R44 1 2 49.9_0402_1% LAN_MDI2P 23
0.1U_0402_16V4Z 1 2 C49 R40 1 2 49.9_0402_1% LAN_MDI3N 23
R41 1 2 49.9_0402_1% LAN_MDI3P 23 2

MDO3+ 3 4 MDO2-
Layout Notice : Place
t er min ation as close as
Intel 82566 as possible
APL5301-18BC-TRL_SOT23-5

Note: MDO[3..0]+/- signals should route to JP4 first then to JP30.

@ D73
JP4
+3VM_LAN_LED R266 2 1 300_0402_5% 13
Yellow LED+ MDO1- MDO0-
1 5
LED_ACT_LAN# 14
23,33 LED_ACT_LAN# Yellow LED-
16
MDO3- SHLD1
33 MDO3- 8 PR4-
9 2
MDO3+ DETECT PIN1 CABLE_DETECT 20
33 MDO3+ 7
PR4+
MDO1- 6
33 MDO1- PR2- MDO1+
1 3 4 MDO0+
B MDO2- C579 B
33 MDO2- 5 PR3-
MDO2+ 4 0.1U_0402_16V4Z
33 MDO2+ PR3+ 2
MDO1+ 3 APL5301-18BC-TRL_SOT23-5
33 MDO1+ PR2+
MDO0- 2
33 MDO0- PR1-
10
MDO0+ DETCET PIN2
33 MDO0+ 1
PR1+
SHLD1 15
+3VM_LAN_LED R265 2 1 300_0402_5% 11 Green LED+
LED_LINK_LAN# 12
20,23,33 LED_LINK_LAN# Green LED-
FOX_JM36113-P1122-7F

conn@

LED_ACT_LAN# LED_LINK_LAN#

2 2
@ C1368 @ C1369 20 mils
300p_0402_25V 300p_0402_25V
1 1 +3VM_LAN +3VM_LAN_LED
S

3 1
1

Q60
R525 AO3413_SOT23
G
2

A A

1115 EMI REQUEST 100K_0402_5%

2

20,26,33 PREP# 2
G
Q61 S
Security Classification Compal Secret Data Compal Electronics, Inc.
3

RHU002N06_SOT323 Issued Date 2006/02/13 2006/07/26 Title

Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Magnetic & RJ45/RJ11
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 24 of 55
5 4 3 2 1
 A B C D E

B/B connector with PCI / LED / FIR / SC interface Mini-Express Card---WLAN

0824 Add +1.5VS_WLAN
0811 Isolate SLOT power from SYSTEM power.
0620 Update ROBSON SCHEMATIC +1.5VS_WLAN +3VALW +3VS +3VS_WLAN
0824 add 1394 signals
JP13 0830 Change 1394 signals +3VS_WLAN
XTPA0- 1 2 XTPB0- 0.01U_0402_16V7K 4.7U_0805_10V4Z R1778
28 XTPA0- XTPA0+ 1 2 XTPB0+ XTPB0- 28
28 XTPA0+ 3 3 4 4 XTPB0+ 28 1 2
5 6 0.1U_0402_16V4Z 1 1 1 1 0_1206_5%
CLK_PCIE_Rob# 5 6 PCI_PIRQG# C293 C294 C533 C954
15 CLK_PCIE_Rob# 7 7 8 8 PCI_PIRQG# 18
15 CLK_PCIE_Rob CLK_PCIE_Rob 9 10 PCI_PIRQD# 1 1
9 10 PCI_REQ2# PCI_PIRQD# 18
R37 0_0402_5% 11 12 C538 C542 0.1U_0402_16V4Z
20 PCIE_RXN4 PCIE_RXN4 2 NF_RXN 11 12 PCI_PLTRST# PCI_REQ2# 18 2 2 2 2 +1.5VS +1.5VS_WLAN
1 13 14 PCI_PLTRST# 18
20 PCIE_RXP4 PCIE_RXP4 2 NF_RXP 13 14 CLKREQ#_E
1 15 15 16 16 CLKREQ#_E 15
1 R36 0_0402_5% 17 18 PCI_PIRQE# 2 2 0.1U_0402_16V4Z R1785 1
20 PCIE_TXN4 PCIE_TXN4 17 18 PCI_PIRQC# PCI_PIRQE# 18
19 20 4.7U_0805_10V4Z 1 2
20 PCIE_TXP4 PCIE_TXP4 19 20 PCI_RST# PCI_PIRQC# 18
21 22 0_1206_5%
21 22 PCI_RST# 18,22
23 24 PCI_GNT2# conn@ 0821 Install R1364
CLK_PCI_PCM 23 24 SIRQ PCI_GNT2# 18 JP44
15 CLK_PCI_PCM 25 26 SIRQ 20,29,30,31
PCI_AD31 25 26 PWR_GD ICH_PCIE_WAKE# +3VS_WLAN
27 27 28 28 PWR_GD 20,31,34,35,43,44 20 ICH_PCIE_WAKE# 1 1 2 2
PCI_AD29 29 30 PCI_AD30 CH_DATA 3 4
PCI_AD27 29 30 PCI_AD28 28 CH_DATA CH_CLK 3 4 +1.5VS_WLAN
31 31 32 32 28 CH_CLK 5 5 6 6
PCI_AD25 33 34 PCI_AD26 1 2 CLKREQD#_MC 7 8
33 34 15 CLKREQ#_G 7 8
PCI_CBE#3 35 36 PCI_AD24 R1336 0_0402_5% 9 10
18 PCI_CBE#3 PCI_AD23 35 36 PCM_SPK CLK_PCIE_MCARD# 9 10
37 37 38 38 PCM_SPK 26 15 CLK_PCIE_MCARD# 11 11 12 12
PCI_AD21 39 40 PCI_AD22 CLK_PCIE_MCARD 13 14 0906 Remove debug resistors
PCI_AD19 39 40 PCI_AD20 15 CLK_PCIE_MCARD 13 14
41 41 42 42 15 15 16 16
PCI_AD17 43 44 PCI_PAR 0906 Remove debug resistors 17 18
PCI_CBE#2 43 44 PCI_AD18 PCI_PAR 18 17 18 XMIT_OFF#
18 PCI_CBE#2 45 46 15,30 CLK_DEBUG_PORT 19 20
PCI_IR DY# 45 46 PCI_AD16 R1348 0_0402_5% 19 20 0_0402_5%
18 PCI_IRDY# 47 48 21 22
PM_CLKRUN# 47 48 PCI_FRAME# PCIE_RXN2 PCIE_C_RXN2 21 22 R1363 PLT_RST_B# 22,29,30
49 49 50 50 PCI_FRAME# 18 20 PCIE_RXN2 1 2 23 23 24 24 1 2 +3VALW
20,29,30,31 PM_CLKRUN# PCI_SERR# PC I_TRDY# PCIE_RXP2 PCIE_C_RXP2
51 52 PCI_TRDY# 18 20 PCIE_RXP2 1 2 25 26 1 2 +3VM
18,31 PCI_SERR# PCI_PERR# 51 52 PCI_STOP# R1349 0_0402_5% 25 26 @ R1364 0_0402_5%
18 PCI_PERR# 53 53 54 54 PCI_STOP# 18 27 27 28 28
PCI_CBE#1 55 56 PCI_DEVSEL# 29 30
18 PCI_CBE#1 55 56 PCI_DEVSEL# 18 29 30 ICH_SMB_CLK 20
PCI_AD14 57 58 PCI_AD15 PCIE_TXN2 31 32
PCI_AD12 57 58 20 PCIE_TXN2 PCIE_TXP2 31 32 ICH_SMB_DATA 20
59 60 33 34
PCI_AD10 59 60 PCI_AD13 20 PCIE_TXP2 33 34
61 61 62 62
+3VS_WLAN
35 35 36 36 0612 change power plane
PCI_AD8 63 64 PCI_AD11 0821 Change +3VS to +3VS_WLAN 37 38
PCI_AD7 63 64 PCI_AD9 R197 37 38
65 66 2 1 0_0402_5% 39 40 @ R1754
PCI_AD5 65 66 PCI_CBE#0 20 CL_CLK1 39 40 WW_LED#_R
67 67 68 68 PCI_CBE#0 18 20 CL_DATA1
R195 2 1 0_0402_5% 41 41 42 42 1 2 WW_LED# WW_LED# 30
0_0402_5%
PCI_AD3 69 70 PCI_AD6 R194 2 1 0_0402_5% 43 44 WL_LED#
PCI_AD1 69 70 PCI_AD4 20 CL_RST#1 43 44 WP_LED#_R WL_LED# 30
71 72 45 46 1 2 WP_LED# WP_LED# 30
71 72 PCI_AD2 45 46 @ R1755
73 73 74 74 47 47 48 48
HDD_HALTLED# 75 76 PCI_AD0 49 50 0627 Add 0 ohm on PIN 42,46 0_0402_5%
20 HDD_HALTLED# 75 76 49 50
+3VL 77 78 51 52
WL_BLUE_LED# 77 78 IRRX 51 52
79 80 IRRX 29
2 30,32 WL_BLUE_LED# GREEN_BATLED# 79 80 IRTXOUT 2
19,31 GREEN_BATLED#
81 81 82 82 IRTXOUT 29 0622 change to support AMT 53 GND1GND2 54
AMBER_BATLED# 83 84 IRMODE 0627 PIN37,43 connected to GND
31 AMBER_BATLED# LED_STB# 83 84 IRMODE 29
85 86 MOLEX 67910-0002 52P
31,32,33 LED_STB# IDE_LED# 87
85 86
88 SC_CD# PIN39,41 connected to +3VS +3VALW
19 IDE_LED# 87 88 SC_CD# 28
89 89 90 90 +3VS
91 92 SC_CLK 0811 No install R1418,R1358,R1359,R1360
+1.5VS 91 92 SC_CLK 28
+3VS 93 94 SC_RST
93 94 SC_RST 28

1
95
95 96
96 +SC_PWR 0906 Remove debug resistors
97 98 SC_DATA R517
+5VS 97 98 SC_DATA 28

1
99 100
99 100 R516 @ 100K_0402_5%

2
101 102 @ 10K_0402_5% XMIT_OFF#
GND GND PC I_AD[0..31]
PCI_AD[0..31] 18 D74

1
D

20 XMIT_OFF 1 2 2
G
ACES_88394-1A71 CH751H-40_SC76 Q58 S

3
@ RHU002N06_SOT323
0731 Install R1383 and no install R1382, do not support wake on WWAN card 0811 HP request
1 2
0811 Isolate SLOT power from SYSTEM power. +3VS_WWAN
R1422 0_0402_5%

Mini-Express Card--WWAN 0.01U_0402_16V7K 4.7U_0805_10V4Z

+3VALW +3VS +3VS_WWAN +3VS +3VS_ACL +3VS_ACL_IO

JP46
R1779 C295
1
C540
1
C544
1
ACCELEROMETER R1355 R1356 +3VS_ACL
1 1 2 1 2 1 2
C959 1 2 0_1206_5% @ 0_0805_5% 0_0603_5%
1 2 2 2 2
3 4
3 4
5 6 2 1 1 1 1
3 2 5 6 UIM_PWR 0.1U_0402_16V4Z D64 C994 C995 C996 3
7 7 8 8
9 10 UIM_DATA CH751H-40_SC76
0.1U_0402_16V4Z 9 10 UIM_CLK @ 0.01U_0402_16V7K 10U_0805_10V4Z
11 12
11 12 UIM_RST 0313 change design 2 2 2
13 13 14 14
15 16 UIM_VPP +3VS U64
15 16 U72 0.1U_0402_16V4Z
17 18
17 18 M_WXMIT_OFF#
19 20 1 6
19 20 CH1 CH4
21 22 18 ACCEL_INT 1 16
21 22 INT/RDY GND
23 24 1 2 +3VALW 2 5 R1361
23 24 @R1382 0_0402_5% Vn Vp
25 25 26 26
27 27 28 28 1 2 +3VS_WWAN 3 CH2 CH3 4 2 SDD RES 15 1 2
+3VS_WWAN 29 30 R1383 0_0402_5%
29 30 S DIO(BR) NUP4301MR6T1 TSOP-6 0_0402_5%
31 31 32 32
33 34 +3VS 3 14
33 34 4,20 ICH_SM_DA SDA/SDI/SPC GND
35 35 36 36 USB20_N8 20
37 38 @ D13
37 38 USB20_P8 20
1 2 39 40 JP50 +3VS_ACL_IO 4 13 +3VS_ACL
R1071 39 40 WW_LED# JP? VDD_IO VDD
1 20_0603_5% 41 42 WW_LED# 30 3
R1073 0_0603_5% 41 42 UIM_PWR R1362
43 44 4 1 1
43 44 UIM_VPP GND VCC UIM_RST
45 46 5 2 2 4,20 ICH_SM_CLK 5 12 1 2 +3VS_ACL
45 46 UIM_DATA VPP RST UIM_CLK SCL/SPC RES
47 48 6 3
47 48 I/O CLK 10K_0402_5% 0_0402_5%
49 49 50 50 7 DET DAN217_SC59
51 52 C554 +3VS_ACL 2 1 6 11
51 52 CS VDD
0.1U_0402_16V4Z

4.7U_0805_10V4Z R1359 0619 Follow ST Demo circuit

53 54 R1357
GND1GND2
8 1 1 7 10 1 2 +3VS_ACL_IO
MOLEX 67910-0002 52P GND C960 NC RES
GND 9 0619 Follow ST Demo circuit
2

conn@ @ R1780 0_0402_5%

0821 Change +3VS to +3VS_WWAN 2 2
8
CK GND
9
10K_0402_5%

2
0811 Pins 37 and 43 connect to GND and remove +1.5VS D66
R1391
1

4 M_WXMIT_OFF# LIS3LV02DL-TR _LGA16 4

1 2 0_0402_5%
20 WXMIT_OFF# CH751H-40_SC76 TAITW_PMPAT6-06GLBS7N14N0
UIM_PWR
Must be placed in the center of the system.
1

0811 Reserve for SIM card does not meet rise time and a pull-up resistor is needed.
0116 Connected R1780.1 to UIM_PWR Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
0821 Delete SW1,C986,R521,D65,R200 Mini-Card/Mini-PCI/Accelerometer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 25 of 55
A B C D E
 A B C D E F G H

VDDA_CODEC V_CODEC

1
20,23,27,31,33,34,41,42,43,44 SLP_S3#

1
R329 +5VAMP
U18 R456
10K_0402_5% 1
C390 R341 IN 49.9K_0402_1% 1
1 5

2
10K_0402_5% MONO_IN OUT
1 2 1 2 1 2 2 2 3 1

2
C430 0.1U_0402_16V4Z + C548 C552 C551 EN + C309 C307
4
ADJ

1
D 0.1U_0402_16V4Z 150K_0402_1% 100P_0402_50V8J
2 2 GND

1
25 PCM_SPK 2 R330 C377 22U_B_10V 1U_0603_10V4Z 2 22U_B_10V 0.1U_0402_16V4Z
G 2 1 1 1 2 MIC5205BM5_SOT23-5 C553 R457 2 2
1 Q35 S 0.01U_0402_16V7K R258 1

3
RHU002N06_SOT323 1 0_0805_5% 0.01U_0402_16V7K 143K_0402_1%

2
1

2
VDDA_CODEC Place R258 between DGND & AGND & close to U14
1

R350
10K_0402_5% 10K_0402_5%
10K_0402_5% 0809 Add anti-pop circuit @
R1758 R1759 R1760
C396 R359 0_0402_5% @
2

1 2 1 2 2 1 2 1 1 2
@ C1366
1

D 0.1U_0402_16V4Z 150K_0402_1%

D
2 4.7U_0603_6.3V6M 1 3 3 1

S
20 SB_SPKR 27 R_C_HP HP_R_JACK 27
G 1 2
Q68 S RHU002N06_SOT323 Q135 Q136@
3

RHU002N06_SOT323 @ R1761 @ RHU002N06_SOT323

G
G
2

2
+5VS 1 2
300K_0402_5%

2
D RHU002N06_SOT323

G
@ R1762 RHU002N06_SOT323 RHU002N06_SOT323

G
+3VS 1 2 2 Q137@ @ Q138 @ Q139
10K_0402_5% G 27 L_C_HP 1 3 3 1 HP_L_JACK 27

D
S

S
3
Place close to U14 19,32 HDA_RST#_MDC 1 2
R1400 1 2 1 2 1 1 2
1K_0402_5% R1764
2 1 0316 change @ R1763 C1367 10K_0402_5% R1765 R1766
0.47U_0402_6.3V4Z @ 0_0402_5%
0_1206_5% 2 @ 10K_0402_5%
@
2 2
V_CODEC VDDA_CODEC +3VS
2 1
C409 0.1U_0402_16V4Z 0_0603_5% R1399
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_CODEC 1 2
0_0805_5%
2 1 R159 1 1 1 1 2 1 1 1
C427 0.1U_0402_16V4Z C395 C147 C417 C148 C402 C156 C175
C393
0.1U_0402_16V4Z 10U_0805_10V4Z
2 1 2 2 2 2 1 2 2 2

25

38

9
C431 0.1U_0402_16V4Z U14
0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z

AVDD1

AVDD2

DVDD1

DVDD2
GND GNDA 14 35 LINE_OUTL LINE_OUTL 27
T24 PAD AUX_L LINE_OUT_L
15 36 LINE_OUTR
AUX_R LINE_OUT_R LINE_OUTR 27
T21 PAD
INT_MIC C425 1 2 1U_0603_10V4Z 16 37 T20
27 INT_MIC MIC3 MONO_OUT PAD
C426 1 2 1U_0603_10V4Z 17 39 L_HP L_HP 27
MIC4 HP_LOUT_L

33 DLINE_IN_L R370 2 1 6.04K_0402_5% DLINE_IN_R_L C423 1 2 1U_0603_10V4Z DLINE_IN_RC_L 23 41 R_HP

R_HP 27
R375 2K_0402_5% LINE_IN_L HP_LOUT_R @ 10P_0402_25V8K
1 2 2 1 1 2
33 DLINE_IN_R R369 2 1 6.04K_0402_5% DLINE_IN_R_R C422 1 2 1U_0603_10V4Z D LINE_IN_RC_R 24 R1038 @ 33_0402_5% C1064
R374 2K_0402_5% LINE_IN_R
1 2 6 HDA_BITCLK_CODEC 19
BIT_CLK
18
T23 PAD CD_L HDA_SDIN0_CODEC R373 1
8 2 HDA_SDIN0 19
SDATA_IN 33_0402_5%
20
T25 PAD CD_R
3
0115 R370, R369 - change from 4.7k to 6.04k 3
19
R374, R375 - change from 4.7k to 2.00k T26 PAD CD_GND
43 R168 1 2 @ 4.7K_0402_5%
PORT_A_SNS 27
MIC1 MIC1_C GPIO_0
27 MIC1 1 2 21
MIC1 GPIO_1
44 R167 1 2 @ 4.7K_0402_5% PORT PLACE TO
C204 1U_0603_10V4Z 2 R136 1 2 10K_0402_5%
MIC2 MIC2_C GPIO_2
27 MIC2 1 2 22
MIC2 GPIO_3
3 R32 1 2 @ 4.7K_0402_5%
PREP# 20,24,33 MONO_OUT X
C205 1U_0603_10V4Z
SENSE_A 13 PORT A HP OUT, DOCK HP LO
SENSE_B SENSEA
VDDA_CODEC 1 2 34
SENSEB
R231 2.2K_0402_1% PORT B M/B MIC
1 2
R169 @ 0_0402_5% 27 AUD_REF PORT C DOCK LI
VREF
19 HDA_RST#_CODEC 11 1 1
RESET#
MIC_BIAS_B 28 T27 C424 C416 PORT D M/B SPK
19 HDA_SYNC_CODEC 10 29 T13 PAD
SYNC MIC_BIAS_C 1U_0603_10V4Z 0.1U_0402_16V4Z
MIC_BIAS_F 30 T12 PAD
2 2
PORT E X
19 HDA_SDOUT_CODEC 5 32 T11 PAD
VDDA_CODEC SDATA_OUT MIC_BIAS_D MONO_IN
PCBEEP
12 PAD PORT F Internal MIC
0620 change 31 T7 PAD
N/C T8 PAD
33
L53 1 N/C T10 PAD
27,31 EAPD 2 47 40
EAPD N/C
2

FBM-L10-160808-301-T_0603 45 T6 PAD
R969 NC T9 PAD
48 46
T22 PAD SPDIFO NC
2.67K_0402_1%
4 26
DVSS1 AVSS1
7 42
1

DVSS2 AVSS2
1 2 SENSE_A_A 27
R970 39.2K_0402_1% AD1981HDJSTZ-REEL_LQFP48
VDDA_CODEC
SENSE_A 1 2 SENSE_A_B 27
R972 20K_0402_1%
2

4 4
2

1 2 SENSE_A_C R974
R980 R973 10K_0402_1% @ 0_0402_5%
@ 0_0402_5% 2
1

Q97 D
1

C977 2 LINE_IN_SENSE
LINE_IN_SENSE 33
1

SENSE_B @ 1U_0402_6.3V4Z G 1
2

1 S C978
Security Classification Compal Secret Data Compal Electronics, Inc.
3

2N7002_SOT23 R988
0.1U_0402_16V4Z 2005/05/26 2006/07/26 Title
2 Issued Date Deciphered Date
AC97 CODEC AD1981B
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
100K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 26 of 55
A B C D E F G H
 A B C D E

AMP. FOR INTERNAL SPEAKER AMP. FOR INTERNAL MICROPHONE

+5VALW +5VAMP Place close to U14 audio CODEC D62
C230
1 2
R443 C659
1 2 10U_0805_10V4Z 2 680P_0402_50V7K
1 R190
C1098 1 0_1206_5% 1 1 1 1 3 1 2
C660 C539
C662 + conn@ @ MIC_REF VDDA_CODEC 100K_0402_5%
PACDN042_SOT23~D

0.1U_0402_16V4Z
10U_0805_10V4Z @ 0.1U_0402_16V4Z JP36
2 150U_D_6.3VM 2 2 2
2

100P_0402_50V8J
1U_0603_10V4Z INT_MIC_2 1
1

C441
1 C585 1

12

18
2 1

C446
10 dB U39 1 2
Keep 10 mil width ACES_85205-0200

PVDD1
PVDD2
VDD
C503 R1410 @ 1200P_0402_50V7K 2
LINE_C_OUTR 1 LINE_C_R_OUTR C1044 2
26 LINE_OUTR 1 2 2 5 2 1 2 1U_0603_10V4Z
INR BIAS U27A

8
0.1U_0402_16V4Z 10K_0402_5% R1405 1 2 LINE_C_R_OUTR VDDA_CODEC L57 TLV2462_SO8
15K_0402_5% 10 dB HLC0603CSCCR11JT_0603 3

P
C502 R1411 R_SPK+ R196 R193 C231 R388 + INT_MIC
OUTR+ 7 O 1
26 LINE_OUTL 1 2 LINE_C_OUTL 1 2 LINE_C_R_OUTL 1 1 2 INT_MIC_1 1 2 1 2 INT_MIC_3
1 2 1 2 INT_MIC_4 2
INL -

G
9 R_SPK- 3K_0402_5% 1
0.1U_0402_16V4Z 10K_0402_5% OUTR- 3K_0402_5% 1 C226 0.22U_0603_10V7K C571 10K_0402_5%

4
10 dB R1406 1 2 LINE_C_R_OUTL INT_MIC 26
R1407 15K_0402_5% 10 dB 68P_0402_50V8J
L_SPK+ 4.7U_0805_10V4Z 2
2 1 4 19
0_0402_5% MUTE OUTL+ 2
17 L_SPK-
OUTL-

3 C488
NC1
10 1 2
20,23,26,31,33,34,41,42,43,44 SLP_S3# R430 1 2 10K_0402_5% 14
SHDN
NC2
NC3
13
16
C471
0.01U_0402_16V7K
AMP. FOR EXTERNAL MICROPHONE 100P_0402_50V8J

PGND1
PGND2
PGND3
PGND4
PGND5
NC4
0620 change MUTE_LED# 1 2 R413
2 1 1 2
1

R1421 @ 0_0402_5% D
2 MAX9710ETP_QFN20 JJ_MIC_REF J_VDDA_CODEC 100K_0402_5%
26,31 EAPD

6
11
15
20
21
G
Q28 S
Place close to JP15
3

100P_0402_50V8J
@ RHU002N06_SOT323
1
1

C249
2 2
31 A_SD 2
G
Q32 S 2 U46A
3

RHU002N06_SOT323 MIC_REF

8
TLV2462_SO8
VDDA_CODEC VDDA_CODEC 3

P
+ J_MIC1
1 C982 C276 L58 R211
O 1
EXT_MICA 1 2 EXT_MICA_1 1 2 1 2 EXT_MICA_2 2
-

G
1

2
HLC0603CSCCR10JT_0603
Place close to U14 audio CODEC R426 4.7U_0805_10V4Z 0.22U_0603_10V7K 1 C57210K_0402_5%

4
R978 2
VDDA_CODEC 47K_0402_5% 100_0402_5%

8
68P_0402_50V8J
2

1
1

5 J_VDDA_CODEC 2

P
R995 + C489
7
O
1

100K_0402_5% 2 6 1 2
-
G

1
C493 R428 U27B
TLV2462_SO8 conn@ R427 100P_0402_50V8J
1 2

26 PORT_A_SNS Q48 47K_0402_5% JP9 R414

D RHU002N06_SOT323 4.7U_0805_10V4Z 1 MIC1 47K_0402_5%
1 1 2 1 JJ_MIC_REF 1 2
2

26 MIC1 R1424 0_0402_5%

2 2

2
G MIC2 2 JJ_MIC_REF J_VDDA_CODEC 100K_0402_5%
3 3
26 MIC2
S 4 4
3

1
VDDA_CODEC 5 2 1
26 SENSE_A_A MIC_REF 5 2 J_MIC_REF

100P_0402_50V8J
MIC_SENSE 6 6 C492 R429 R1423 @ 0_0402_5%
1

D R_HP
26 R_HP 7 7 1
1

VDDA_CODEC

C248
2 L_HP 8 8 47K_0402_5%
26 L_HP
Q49 G R423 9 9 4.7U_0805_10V4Z 1

2
RHU002N06_SOT323 S 10 10
3

33 DLINE_OUT_L
1

100K_0402_5% 11 11 2 U46B
R251 33 DLINE_OUT_R
VDDA_CODEC 12 12
2

8
TLV2462_SO8
3 33 DOCK_HPS# 100K_0402_5% ACES_87213-1200 3
5

P
+
1

D R255 C275 L61 R210 J_MIC2

7
2

Q44 DLINE_OUT_L EXT_MICB EXT_MICB_1 1 EXT_MICB_2 O

1 2 1 2 1 2 2 1 2 6
-

G
C527 G 1 1 HLC0603CSCCR10JT_0603 1
S C536 100K_0402_5% C526 0.22U_0603_10V7K 1 10K_0402_5% C470
3

4
0.1U_0603_16V4Z
2 2.2U_0603_6.3V4Z @ 1U_0603_10V4Z C575 0.1U_0402_16V4Z
2 2 68P_0402_50V8J 2
RHU002N06_SOT323 2

1116 Change R261 and R253 to 56.2 ohm VDDA_CODEC

20070227 Change R261 and R253 to 60.4 ohm 02/27 change
R261 CHB1608B121_0603
JP24

2
1 2 R_CR_HP 1 2 R_CRL_HP
26 HP_R_JACK
60.4_0805_1% L52 5 8 R979
J_DLINE_OUT_R 26 SENSE_A_B
7 47K_0402_5%
J_DLINE_OUT_L 4

1
D

1
R253 L51 3 Q50 2 MIC_SENSE
1 2 L_CR_HP 1 2 6 RHU002N06_SOT323 G 2
26 HP_L_JACK
60.4_0805_1% CHB1608B121_0603 L_CRL_HP 2 S
Place close to JP24 1 3 C984
JP15
J_R_HP 1 2 R_C_HP
+

R_C_HP 26 0.1U_0402_16V4Z
C577 150U_D_6.3VM 1 J_MIC_SENSE 5 8
1 1
1

C563 C564 SUYIN_010030FR006G101ZL_6P R424 7

J_L_HP 1 2 L_C_HP R445 R446 conn@ R418 3.9K_0402_1%
+

L_C_HP 26 4
C581 150U_D_6.3VM 470P_0402_50V7K 470P_0402_50V7K 1 2 1 2 EXT_MICB 1 2
2 2 J_VDDA_CODEC
1K_0402_1% 1K_0402_1% Place close to U14 470_0402_5% L46 3
U73 1 6 CHB1608B121_0603 6
2

CH1 CH4 EXT_MICA

1 2 1 2 1 2 2
2 5 +3VS R425 L47 1
Vn Vp 470_0402_5% R421 CHB1608B121_0603
4
1 1 4
3 4 conn@ JP27 3.9K_0402_1% C508 C522
CH2 CH3 J_MIC1 SUYIN_010030FR006G101ZL_6P
@ S DIO(BR) NUP4301MR6T1 TSOP-6 1 1 Place close to JP24 C487
1 1
C486 470P_0402_50V7K 470P_0402_50V7K conn@
2 2
3 J_MIC2 2 2
JP21 conn@ 3 10U_0805_10V4Z 10U_0805_10V4Z
4 4
L_SPK+ 1 5 conn@ JP28 2 2
1 5 J_MIC_REF
L_SPK- 2 6 J_MIC_SENSE 1 J_R_HP
R_SPK+ 2 6 1 J_L_HP
3 2
R_SPK- 100P_0402_50V8J 4
3
4
ACES_87213-0600 2
3 3
J_DLINE_OUT_L
Security Classification Compal Secret Data Compal Electronics, Inc.
1 1 1 1 4 4 Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
C506 C514 C507 C518 E&T_3801-04 J_DLINE_OUT_R
Place close to JP15 5 5
AMP & Audio Jack
6 6 J_VDDA_CODEC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
100P_0402_50V8J 100P_0402_50V8J Size Document Number R ev
2 2 2 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ACES_87213-0600 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P U MA 0.4
100P_0402_50V8J MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 27 of 55
A B C D E
 5 4 3 2 1

Left side USB CONNECTOR 1

Left side USB CONNECTOR 0
USB_VCCA

+5VALW USB_VCCA
U57

1
GND OUT
8 W=100mils JP23 conn@ conn@ JP25
2 7 0_0603_5% R604 1 1 0_0603_5% R606
IN OUT 1 1

1000P_0402_50V7K
150U_D_6.3VM

0.1U_0402_16V4Z
D USB20_N4 1 D
3 IN OUT 6 1 20 USB20_N4 2 USB20_N4_R 2 2 2 2 USB20_N5_R 1 2 USB20_N5 USB20_N5 20
1 4 5 1 1 USB20_P4 1 2 USB20_P4_R 3 3 USB20_P5_R 1 2 USB20_P5
EN# OC# 20 USB20_P4 3 3 USB20_P5 20

C567

C515

C519
C550 + 0_0603_5% R605 4 4 0_0603_5% R607
4 4
1 2 5 5
4.7U_0805_10V4Z G548A2P1U 0_0805_5% GND GND
6 6
2 2 2 2 R1790 GND GND
7 GND GND 7
8 8
GND GND
SUYIN_020173MR004S558ZL USB20_P5
30 S4_STATE S4_STATE USB20_P4 SUYIN_020173MR004S558ZL USB20_N5
USB20_N4
1 2 +5VALW 1101 update EMI request

2
R163 R1792

2
0621 change 10K_0402_5% 1 2
0_0805_5% D51
D52 PJDLC05_SOT23~D
PJDLC05_SOT23~D
1 2

1
0_0805_5%

1
R1791

0904 EMI request

Right side USB CONNECTOR 0
+5VALW
1394 connector
USB_VCCC
U65
C
1
GND OUT
8 W=60mils JP26 conn@
C
2 7 0_0603_5% R617 1
IN OUT 1000P_0402_50V7K 1
150U_D_6.3VM

0.1U_0402_16V4Z

3 6 1 1 2 USB20_N0_R 2
IN OUT 20 USB20_N0 2
1 4 5 1 1 1 2 USB20_P0_R 3
EN# OC# 20 USB20_P0 3
C569

C517

C558 + 0_0603_5% R614 4 4

C521

TPS2061IDGN_MSOP8~N 5 conn@
4.7U_0805_10V4Z GND
6 JP19
2 2 2 2 GND XTPB0- 0_0402_5% R_XTPB0- 1
7 GND 25 XTPB0- 1 2 R1696 XTPB0-
8 XTPB0+ 0_0402_5% 1 2 R1697 R_XTPB0+ 2
GND 25 XTPB0+ XTPA0- R_XTPA0- 3 XTPB0+
25 XTPA0- 1 2 XTPA0-
SUYIN_020173MR004S558ZL XTPA0+ 0_0402_5% 1 2 R1698 R_XTPA0+ 4
25 XTPA0+ XTPA0+
0_0402_5% R1699 5
+5VALW GND
6
GND
1 2 +5VALW 7 GND
R164 USB20_P0 8
GND
1

10K_0402_5% USB20_N0
AMP_440168-2

2
10K_0402_5%
2

S4_STATE R1 D61
PJDLC05_SOT23~D
1

20 S4_STATE# 2

1
G
Q132 S
3

RHU002N06_SOT323 0621 change

conn@ JP22
B 1 +3VAUX_BT B
R562
2 USB20_P6_R USB20_P6
3 2 1 0_0402_5% USB20_P6 20
USB20_N6_R 2 1 0_0402_5% USB20_N6
4 USB20_N6 20
R586
5 BT_LED 30
@ R458 1 2 1K_0402_5%
6 @ R459 1 1K_0402_5% CH_DATA 25
SMART Card connector +SC_PWR 7
8
2 CH_CLK 25

2
0612 no install
ACES_87212-0800 D53

@ PACDN042_SOT23~D
JP3 conn@ 1
1 C367
11 11

1
1 SC_CLK
2
3
2
3
12 12
13 13
SC_RST
SC_CLK 25
SC_RST 25 2
0.1U_0402_16V4Z BT Connector
4
4 14 14 SC_CD#
+SC_PWR
5
5 15 15 SC_CD# 25
6
6 16 16 +3VALW +3VAUX_BT
7
7 17 17 Q51 SI2301BDS_SOT23
8
8 18 18 SC_DATA
9
9 19 19 SC_DATA 25

D
10 10 20 20 3 1

ACES_85203-1002

G
1 1 1 1

2
C306 R518 C546 C545 C549
4.7U_0805_10V4Z
1U_0603_10V4Z 100K_0402_5% 0.1U_0402_16V4Z
2 2 2 2

2
0.01U_0402_16V7K

A C556 A
R454
20 BT_OFF 1 2 1 2
47K_0402_5%
0.1U_0402_16V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB & BT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 28 of 55
5 4 3 2 1
 A B C D E

1 1
+3VS
RP3
DCD#1 1 8
R I#1 2 7
CTS#1 3 6
DSR#1 4 5
+5VS
4.7K_1206_8P4R_5%

2
IRRX 1 2
R76 D36
1K_0402_5%
CH751H-40_SC76

1
+5VS_PRN

RXD1 33
RP51
U8 R64 1K_0402_5% LPD3 1 8
LPC_AD0 10 62 RXD1 1 2 LPD2 2 7
19,30,31 LPC_AD0 LAD0 RXD1
LPC_AD1 12 63 TXD1 LPD1 3 6

SERIAL I/F
19,30,31 LPC_AD1 LAD1 TXD1 TXD1 33
LPC_AD2 13 64 DSR#1 LPD0 4 5
19,30,31 LPC_AD2 LAD2 DSR1# DSR#1 33
LPC_AD3 14 1 RTS#1
19,30,31 LPC_AD3 LAD3 RTS1# RTS#1 33
2 CTS#1 4.7K_1206_8P4R_5%
RP6 LPC_FRAME# CTS1# DTR#1 CTS#1 33
19,30,31 LPC_FRAME# 15 3 DTR#1 33
SIO_GPIO12 LPC_DRQ#0 LFRAME# DTR1# R I#1 RP52
8 1 19 LPC_DRQ#0 16 4 RI#1 33
LDRQ# RI1#

LPC I/F
7 2 SIO_GPIO10 R108 1 2 0_0402_5% 5 DCD#1 LPD7 1 8
20,31 NPCI_RST# DCD1# DCD#1 33
6 3 SIO_GPIO44 R109 1 2 @ 0_0402_5% SIO_RST# 17 LPD6 2 7
SIO_GPIO43 22,25,30 PLT_RST_B# SIO_PD# PCI_RESET# IRRX LPD5
5 4 +3VS R99 1 2 10K_0402_5% 18 37 3 6
LPCPD# IRRX2 IRRX 25 LPD4
2
FIR IRTX2
38 IRTXOUT 25 4 5
2
10K_1206_8P4R_5% PM_CLKRUN# 19 39
20,25,30,31 PM_CLKRUN# CLK_PCI_SIO CLKRUN# IRMODE/IRRX3 IRMODE 25
R120 20 4.7K_1206_8P4R_5%
SIO_IRQ 15 CLK_PCI_SIO SIRQ PCI_CLK LPTINIT#
1 2 21 41
R121 10K_0402_5% 20,25,30,31 SIRQ SIO_PME# SER_IRQ INIT# LPTSLCTIN# LPTINIT# 33 RP53
+3VS 1 2 6 IO_PME# SLCTIN# 42 LPTSLCTIN# 33
1 2 SIO_DPIO45 R67 10K_0402_5% 44 LPD0 LPTACK# 1 8
CLK_14M_SIO PD0 LPD1 LPD0 33 LPTBUSY
10K_0402_5% 9 46 2 7
15 CLK_14M_SIO CLK14 PD1 LPD1 33
CLOCK 47 LPD2 LPTPE 3 6
PD2 LPD2 33
SIO_GPIO40 23 48 LPD3 LPTSLCT 4 5
GPIO40 PD3 LPD3 33

PARALLEL I/F
PID0 24 49 LPD4
+3VS PID1 GPIO41 PD4 LPD5 LPD4 33
25 50 4.7K_1206_8P4R_5%
SIO_GPIO43 GPIO42 PD5 LPD6 LPD5 33
R119 27 51
GPIO43 PD6 LPD6 33
1 2 C ARD_ID# SIO_GPIO44 28 53 LPD7 RP54

GPIO
GPIO44 PD7 LPD7 33
SIO_DPIO45 29 55 LPTSLCT 1 8
C ARD_ID# GPIO45 SLCT LPTPE LPTSLCT 33 LPTSTB#
10K_0402_5% 30 56 2 7
SER_SHD GPIO46 PE LPTBUSY LPTPE 33 LPTAFD#
33 SER_SHD 31 57 LPTBUSY 33 3 6
SIO_GPIO10 GPIO47 BUSY LPTACK# LPTERR#
32 58 LPTACK# 33 4 5
SIO_GPIO11 GPIO10 ACK# LPTERR#
33 59
SIO_GPIO12 GPIO11/SYSOPT ERROR# LPTAFD# LPTERR# 33 4.7K_1206_8P4R_5%
34 60
SIO_IRQ GPIO12/IO_SMI# ALF# LPTSTB# LPTAFD# 33
35 61 LPTSTB# 33
R68 GPIO13/IRQIN1 STROBE# R480
36 GPIO14/IRQIN2
1 2 EXPCRD_RST# EXPCRD_RST# 40 LPTSLCTIN# 1 2
33 EXPCRD_RST# GPIO23
10K_0402_5% 8 7 +3VS 4.7K_0402_5%
+3VS VSS VTR R481
22 11
R77 VSS VCC LPTINIT#
43
VSS POWER VCC
26 1 2
1 2 PID0 52 45
VSS VCC 4.7K_0402_5%
VCC 54 1 1 1 1
10K_0402_5% C84 C88 C76 C57
LPC47N217_STQFP64

R79 Base I/O Address 2 2 2 2

1 2 PID1 0 = 02Eh
3 * 1 = 04Eh 3
10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 4.7U_0805_10V4Z

R80
1 2 SIO_GPIO11

10K_0402_5%

R100
1 2 SIO_GPIO40

10K_0402_5% CLK_PCI_SIO CLK_14M_SIO

1
R96 R81
@ 10_0402_5% @ 10_0402_5%
2

2
1 1
C94 C70
@18P_0402_50V8J @10P_0402_25V8K
2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SUPER I/O LPC47N217
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 29 of 55
A B C D E
 5 4 3 2 1

0117 For SPI ROM debug

BIOS ROM +3VM R1811 0_0402_5%
20mils
Debug port JP52
2 1 1 Ground
1 U66 2
15,25 CLK_DEBUG_PORT LPC_PCI_CLK
C989 8 4 3
0.1U_0402_16V4Z VCC VSS @ R118 0_0402_5% Ground
19,29,31 LPC_FRAME# 4
SPI_WP# LPC_FRAME#
3 W +3VS 1 2 5 +V3S
2 @ R123 0_0402_5% 6
SPI_HOLD#_0 7,16,18,22 PLT_RST# LPC_RESET#
7 HOLD 1 2 7 +V3S
19,29,31LPC_AD0 8
SPI_CS0# LPC_AD0
20 SPI_CS0# 1 S 19,29,31LPC_AD1 9 LPC_AD1
D 47_0402_5% D
19,29,31LPC_AD2 10 LPC_AD2
SPI_CLK 1 2 R1290 SPI_CLK_0 6 11
C 19,29,31LPC_AD3 LPC_AD3
47_0402_5% R1291 B+ 12
SPI_SI VCC_3VA
1 2 R1294 SPI_SI_0 5 2 SPI_SO_L01 2 SPI_SO SPI_SO 20 13
D Q 15_0402_5% 31 STB_LED# PWR_LED#
14
S IC FL 32K AT26DF321-SU SOP 8P 2.7V 31 CAPS_LED# CAPS_LED#
31 NUM_LED# 15 NUM_LED#
31,35 VCC1_PWRGD 16
20mils R1288 SPI_CLK_L SPICLK VCC1_PWRGD
1 2 17
+3VM 1 2 SPI_HOLD#_0 SPI0 (32M*1) SPI_CS0# 2 1 SPICS0# 18
SPI_CLK
SPI_CS#

1
3.3K_0402_5% R1794 0_0402_5% SPI_SI_L 1 2 SPISI 19
20mils R1793 SPI_SO_L SPISO SPI_SI
1 2 20 SPI_SO
0_0402_5% SPI_SI_L 2 1 SPI_SI SPI_HOLD#_0 21
SPI_SI 20 SPI_HOLD#
+3VM 1 2 SPI_HOLD#_0 R170 0_0402_5% SPI_CS1# 22 Reserved
20mils 3.3K_0402_5% CLRP3 SHORT PADS 23

2
+3VM Reserved
@ R1292 0821 R1795 0_0402_5% R201 0_0402_5% 24
Reserved
R202 0_0402_5%
1 20mils SPI_CLK_L 2 1 SPI_CLK

SPI_SO_L
SPI_CLK 20
@ C993 @ U67
8 VCC 4 ACES_87216-2404_24P
VSS
0.1U_0402_16V4Z
2
0907 Add 0 ohm for SPI conn@
SPI_WP# 3
W
+3VM SPI_HOLD#_0 7 HOLD
0629 Change Pin3 to Pin23, change Pin24 to GND
1

SPI_CS1# 1
20 SPI_CS1# S
R1287 @ 47_0402_5%
3.3K_0402_5% SPI_CLK_L 1 2 R1296 SPI_CLK_1 6
@ 47_0402_5% C @ R1297
SPI_SI_L 1 2 R1295 SPI_SI_1 5 SPI_SO_L11
2 2
2

SPI_WP# D Q 15_0402_5%
SST25LF080A_SO8-200mil
1

C @ R1724 C

0_0402_5% SPI1 (16M*1) 0821 SPI1 no install

0906 SPI1 install
2

1116 SPI1 no install

+3VS

Q75
47K

3
DTA114YKA_SC59
Mini-PCIE Card LED
TPM1.2 10K 2 WW_LED# 25
+3VS+3VALW

0.1U_0402_16V4Z
1 1 1 1
+3VS BLUE
C1053 C1054 C1055 C1052

1
Base I/O Address 47K

3
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0 = 02Eh +3VS
2 2 2 2 * 1 = 04Eh
0.1U_0402_16V4Z
24
19
10

U69 10K 2 WL_LED# 25

R1377
VSB
VDD
VDD
VDD

Q88
4.7K_0402_5% DTA114YKA_SC59
LPC_AD0 26 28 LPC_PD# Q79 WL_BLUE_LED# 25,32
19,29,31 LPC_AD0 LPC_PD# 20
2

LPC_AD1 LAD0 LPCPD# +3VS RHU002N06_SOT323

19,29,31 LPC_AD1 23 9

1
LAD1 TESTB1/BADD

1
LPC_AD2 R1379 2 0_0402_5% D
19,29,31 LPC_AD2 20 8 1
LAD2 TEST1
1

LPC_AD3 17 R1378 2
19,29,31 LPC_AD3 LAD3 47K 28 BT_LED

3
B TPM_XTALO @ 4.7K_0402_5% G B
XTALO 14
13 TPM_XTALI 1 2 S
TPM_32K_CLK 31

3
XTALI

2
TPM R101 @ 0_0402_5%
CLK_PCI_TCG 21 SLB 9635 TT 1.1 PAD 10K 2 R505
15 CLK_PCI_TCG WP_LED# 25
2

LPC_FRAME# LCLK T41 100K_0402_5%

19,29,31 LPC_FRAME# 22 2
PLT_RST_B# LFRAME# GPIO2
22,25,29 PLT_RST_B# 16 6
SIRQ LRESET# GPIO T42 18P_0402_50V8J
20,25,29,31 SIRQ 27

1
PM_CLKRUN# SERIRQ PAD TPM_XTALI C1057 1 Q89 @
20,25,29,31 PM_CLKRUN# 15 2
CLKRUN# DTA114YKA_SC59
+3VS 1 2 7 1

1
PP NC
1

R1380 3 32.768KHZ_12.5P_1TJS125BJ2A251
NC

1
@ 4.7K_0402_5% R1381 D
12 1 NC 2
GND
GND
GND
GND

NC IN
1

WL_LED 2 Q78
R1409 4 3 G RHU002N06_SOT323
SLB9635TT_TSSOP28 OUT NC
S
4
11
18
25

3
2
0_0402_5% Y8
TPM_XTALO C1056 1 2 R504
2

10M_0402_5% 100K_0402_5%
18P_0402_50V8J

1
20070209 Add for FPR +3VS
+3VALW Q142 SI2301BDS_SOT23
@ R1808 Finger printer
S

3 1 1 2
1 0_0603_5%
C206
0.1U_0402_16V4Z
G
2

28 S4_STATE
2 JP38
0_0402_5% 1
A 1 A
20 USB20_N1
R1334 2 1 USB20_N1_R 2
2
20 USB20_P1
R1335 2 1USB20_P1_R 3 3
0_0402_5% 4 4
3

ACES_85205-0400
conn@
D54
@ PACDN042_SOT23~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TCG/BIOS ROM/PS2/LED/SW
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 30 of 55
5 4 3 2 1
 5 4 3 2 1

1213 Install R1646,C75 0_0402_5% CRACK_BGA 1 2 +3VL

CRACK_GPIO28 11,21
2 1 PWR_GD 0_0402_5%
1070@ +3VL @ R1642 RP1
2 1 PWR1 R1646 R1726 AB1A_CLK 1 8
+3VL
0_0603_5% R1477 1 2 1 +3VS 1013 no install R1726 AB1A_DATA 2 7
C39 1 1070@ 0_0402_5% 1213 Install R1726 AB1B_CLK 3 6
2 1 T32 T33 AB1B_DATA 4 5
+3VS
0_0603_5% R1478
2
0.1U_0402_16V4Z 0.1U_0402_16V4Z C75 PAD PAD 0621 Add PM_SLP_M#
1021@ 1 1 1 1 1 1070@ 4.7K_1206_8P4R_5%
C37 C51 C36 C34 2
C52 PM_SLP_M#
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z PM_SLP_M# 20,34,42,46
2 2 2 2 2 GPIO29 20
1 2 EAPD 26,27
+3VL R38 0_0402_5%
GPIO30 R141 1 2 0_0402_5%
D PWR1 1
AMT ADP_PRES 20 BIOS debug port D
RP58
1 8 KSI0 PCI_SERR# 18,25
1070@ +3VL Place under KB area

127
128

106

119

100
126
2 7 KSI3 10U_0805_10V4Z C1289

94
95
96
97

39
58
84

14

49

15

93
98
99
KSI2 U47 2 +3VL
3 6

1
4 5 KSI1 KSO[0..13]

VCC1
VCC1
VCC1
VCC1
VCC1

VCC1

VCC2

GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
CAP
NC
NC
NC
NC
NC
NC
32 KSO[0..13]
R575 JP43
10K_1206_8P4R_5% KSO0 21 124 KBC_PWR_ON
KSO1 KSO0 OUT0 GREEN_BATLED# KBC_PWR_ON 40 VCC1_PWRGD 1
20 125 10K_0402_5%
RP59 KSO2 KSO1 OUT1/IRQ8# GREEN_BATLED# 19,25 2
19

2
KSI7 KSO3 KSO2 BATSELB_A# D7 EC_GPIO9 3
1 8 18 KSO3 OUT7/SMI# 123 BATSELB_A# 39 4
2 7 KSI6 KSO4 17 122 KBRST# 1 2 CRACK_BGA
KSO4 OUT8/KBRST KB_RST# 19 5

General Purpose I/O Interface

3 6 KSI5 KSO5 16 121 A_SD
KSO5 OUT9/PWM2 A_SD 27 6

Keyboard/Mouse Interface
4 5 KSI4 KSO6 13 120 FAN_PWM CH751H-40_SC76
KSO7 KSO6 OUT10/PWM0 CHGCTRL FAN_PWM 4 @ ACES_85201-0602
12 118
10K_1206_8P4R_5% KSO8 KSO7 OUT11/PWM1 CHGCTRL 38,39
10
KSO9 KSO8 THM_MBAY#
9 KSO9 GPIO01 107 THM_MBAY# 37
KSO10 8 79 ON/OFFBTN_KBC# ON/OFFBTN_KBC# 32
KSO11 KSO10 GPIO02 LOW_BAT#
7 KSO11 GPIO03 80 LOW_BAT# 20
Pin3 250 : KSO12/OUT8/KBRST KSO12 6 81 KSO14 +3VL
KSO12/GPIO00/KBRST GPIO04/KSO14 KSO14 32
KSO13 5 83 KSO15
+5VS KSO13/GPIO18 GPIO05/KSO15 KSO15 32
THM_MAIN# 1 R600 2
32 KSI[0..7]
85 RSMRST_EC 4.7K_0402_5% 210K_0402_1%
R578 KSI0 GPIO07/PWM3 CRACK_BGA R20 1 ADP_PS1
29 KSI0 GPIO08/RXD 86 2 1 2
1 2 TP_CLK KSI1 28 87 EC_GPIO9 R18 1 2 R538 @ 100K_0402_5%
KSI1 GPIO09/TXD +3VL
KSI2 27 4.7K_0402_5% EC_GPIO27 1 R33 2
10K_0402_5% KSI3 KSI2 AB2A_DATA R156 0_0402_5% 100K_0402_5%
26 88 1 2 Cap_DAT 32
R580 KSI4 KSI3 GPIO11/AB2A_DATA AB2A_CLK R155 0_0402_5%
25 89 1 2 Cap_CLK 32
KSI4 GPIO12/AB2A_CLK
1 2 TP_DATA KSI5 24 KSI5 GPIO13/AB2B_DATA 90 AB2B_DATA R140 1 2 0_0402_5% ME_EC_DATA1 20

SMSC_1070_TQFP-128P
KSI6 23 91 AB2B_CLK R154 1 2 0_0402_5%
KSI6 GPIO14/AB2B_CLK ME_EC_CLK1 20
10K_0402_5% KSI7 22 92 BATCON
KSI7 GPIO15/FAN_TACH1 THM_MAIN# BATCON 39 R282 C92
101 D6 CH751H-40_SC76
C RP60 GPIO16/FAN_TACH2 A20M THM_MAIN# 37 CLK_14M_KBC1 C
GPIO17/A20M 102 1 2 2 1 2
KBD_CLK TP_CLK R581 1 GATEA20 19
1 8 32 TP_CLK 35 2 +3VL
KBD_DATA TP_DATA IMCLK NUM_LED# 10K_0402_5%
2 7 32 TP_DATA 36 103 NUM_LED# 30
PS2_CLK KBD_CLK IMDAT GPIO20/PS2CLK SLP_S3# 10_0402_5% 10P_0402_25V8K
3 6 33 KBD_CLK 38 KCLK GPIO21/PS2DAT 105 SLP_S3# 20,23,26,27,33,34,41,42,43,44
4 5 PS2_DATA KBD_DATA 40 4 T37 PAD @ @
33 KBD_DATA PS2_CLK KDAT GPIO24/KSO16 EC_GPIO27 2 Pin1 250 -- TEST Pin ( NC !! )
41 74 1 ADP_PRES 23,38,39,40,44
10K_1206_8P4R_5% 33 PS2_CLK PS2_DATA EMCLK GPIO27 Pin57 250 -- MODE
33 PS2_DATA 42 EMDAT D10 CH751H-40_SC76
R25
111 AB1A_DATA FWP# 1 2 PM_POK
AB1A_DATA AB1A_DATA 37
112 AB1A_CLK
AB1A_CLK AB1A_CLK 37
Access Bus Interface 10K_0402_5%
+3VS PM_CLKRUN# 55 109 AB1B_DATA
20,25,29,30 PM_CLKRUN# SIRQ CLKRUN# AB1B_DATA AB1B_CLK AB1B_DATA 37
20,25,29,30 SIRQ 57 110 AB1B_CLK 37
CLK_PCI_EC SER_IRQ Power Mgmt/SIRQ AB1B_CLK
15 CLK_PCI_EC 54
RUNSCI_EC# PCI_CLK Cap_INT
20 RUNSCI_EC# 76 73 Cap_INT 32
EC_SCI# PGM Strap/GPIO25
108 EA#
R1289 LPC_AD3 EA Strap#/GPIO26/KSO17 CLK_14M_KBC
19,29,30 LPC_AD3 51 59 CLK_14M_KBC 15
LAD[3] CLOCKI

Miscellaneous
1 2 RUNSCI_EC# 19,29,30 LPC_AD2
LPC_AD2 50 LAD[2] 32KHZ_OUT/GPIO22 75 32K_CLK
LPC_AD1 48 60 PM_POK
19,29,30 LPC_AD1 LAD[1] RESET_OUT#/GPIO06 PM_POK 43
10K_0402_5% LPC_AD0 46 LPC 78 PWR_GD
19,29,30 LPC_AD0 LAD[0] PWRGD VCC1_PWRGD PWR_GD 20,25,34,35,43,44
Bus 77 VCC1_PWRGD 30,35
LPC_FRAME# VCC1_PWRGD
19,29,30 LPC_FRAME# 52 61 ADP_PS0 44
PLT_RST# LFRAME# 24MHZ_OUT/GPIO19/WINDMON Pin50 250 -- 24MHz_Out
20,29 NPCI_RST# 53
LRESET# TEST +3VL
44 ADP_PS1 45 69 1 2
LPCPD#/GPIO23 TEST PIN Pin52 250 -- XOSEL R977 300_0402_5% JP31
Pin91 250 -- nDMS_LED
C R Y1 VCC1_PWRGD 1
70 116 ADP_ID 44
C R Y2 XTAL1 DMS_LED#/GPIO10 AMBER_BATLED# 2
1 2 71 113 AMBER_BATLED# 25 +3VL R58 1 2 100K_0402_5% NUM_LED#
CLK_PCI_EC XTAL2 BAT_LED# STB_LED# 3
115 STB_LED# 30
R59 1 2 100K_0402_5% STB_LED#
PWR_LED#/8051TX CAPS_LED# 4
R74 114 CAPS_LED# 30
R60 1 2 100K_0402_5% CAPS_LED#
FDD_LED#/8051RX 5
1

B @ 2M_0402_5% R75 B
68 VCC0 6
AGND

R86 2 1 +RTCVCC R62 250@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
120K_0402_5% @ R1783 0_0402_5%
@ 10_0402_5% 1 2 Remove from daughter board @ ACES_85201-0602
+3VL KBC1070_VTQFP128 @ R127
2

1
2
3
30
31
32
33
34
43
44

72

11
37
47
56
104
82
117

62
63
64
65
66
67
1

0_0402_5%
2 For KBC debugging used.
2

C80 Y2 1 2 AB1B_DATA
1 2 Cap_DAT
OUT
IN

1 1 @ R1784 0_0402_5% R1809

@ 10P_0402_50V8J 18P_0402_50V8J AB1B_CLK1 Cap_CLK
0_0402_5% 2
1 C350 C349 0821 2 1 0_0402_5%
@C661 @ C1317 @ R157
NC

NC

2 2 18P_0402_50V8J 0.1U_0402_16V4Z U82

1U_0603_10V4Z
2

1 2 STB_LED#
1107 Install R1784 1
A1 Y1
6 LED_STB# 25,32,33
1128 Install R1783
32.768KHZ_12.5P_1TJS125BJ2A251 0110 R1784 connected to +3VL RSMRST circuit 0619 change
20070226 Add R1809 to GND R1749 2
GND VCC
5 +3VL
R52 0_0402_5%
PGM 1 2 1 2 3 4
AGND FILTER 0821 Install R29 100K ohm @ 1K_0402_5%
RSMRST_EC
Q131 +3VALW
A2 Y2

3 1 NC7WZ07P6X_NL_SC70-6
C

PM_RSMRST# 20
C58 R29 1114 Eliminate glitch 0811 For OTS 214499
E

1 2 FWP# 1 2 @ BAV99DW-7_SOT363 @ MMBT3906_SOT23

+3V_U43
B

2 1
1 2

0.1U_0402_16V4Z 100K_0402_5%
5

R1796 @ 4.7K_0402_5%
D68B D68A @

14
+3VL BAV99DW-7_SOT363
R65
J3 1031 Modify circuit 20,25,34,35,43,44 PWR_GD 4

P
PGM 1 A
2 1 2 6 1 2
A
43 PGOOD_PU19 5
O R1800 PM_PWROK 7,20,45 A
R1751
3

G
NO SHORT PADS 1K_0402_5% 1 2 0_0402_5%
U43B

7
R28 @ 2.2K_0402_5% SN74LVC08APW_TSSOP14 VGATE 7,20
FWP# 2 1
32K_CLK R91 1 2 0_0402_5% @ 1K_0402_5%
ADP_EN 44
R97 1 2 @ 0_0402_5% TPM_32K_CLK 30
TEST
R78 Security Classification Compal Secret Data Compal Electronics, Inc.
2 1 Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title
@ 1K_0402_5%
R27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LPC47N1021
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
EA# 2 1 LA-3261P UMA 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1K_0402_5% MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 31 of 55
5 4 3 2 1
SWITCH BOARD. 0622 change 220P_0402_50V4Z
2 1
C749
LED_STB#
INT_KBD CONN.
220P_0402_50V4Z C750
2 1 ON /OFF# KSO[0..15]
31 KSO[0..15]
@ R21 0_0402_5%
Cap_RST# 1 2 KSI[0..7]
Cap_RST#_SB 20 31 KSI[0..7]
JP6
30 A30
Cap_INT 30 60
29 29 59 A29
0104 Change JP20 to FFC connector 28
28 58
A28

1
0901 Change Cap_RST#_SB to SB GPIO28 1 27 27 57 A27
R30 26 A26
26 56
0809 Connect Pin1 to +3VL, Pin2 to +3VS 10K_0402_5% C1 +3VALW 25 25 55 A25
10P_0402_50V8K @ JP20 KSO15 24 A24 KSO15
2 LID_SW# KSO10 24 54 KSO10
@ 9 9 1 LID_SW# 17,20 23 A23

2
1 KSO11 23 53 KSO11
10 10 2 2 22 22 52 A22
11 3 LED_STB# KSO14 21 A21 KSO14
+3VL +3VS 11 3 ON /OFF# LED_STB# 25,31,33 KSO13 21 51 KSO13
12 4 20 A20
12 4 KSO12 20 50 KSO12
13 5 19 A19
13 5 ON /OFF# LID_SW# KSO3 19 49 KSO3
14 6 18 A18
JP18 14 6 KSO6 18 48 KSO6
15 15 7 7 17 17 47 A17
16 16 8 KSO8 16 A16 KSO8
1 2 8 16 46

2
Cap_RST# KSO7 15 A15 KSO7
3 4 Cap_CLK 31 KSO4 15 45 KSO4
31 Cap_DAT Aces_85203-08421-11 14 A14
5 6 Cap_INT 31 KSO2 14 44 KSO2
WL_BLUE_LED# 25,30 D76 13 A13
7 8 KSI0 13 43 KSI0
9 10 12 12 42 A12
KSO1 11 A11 KSO1
ACES_85203-1002 PJDLC05_SOT23~D KSO5 11 41 KSO5
10 A10

1
KSI3 10 40 KSI3
conn@ 0829 Change to WL_BLUE_LED# 9 9 39 A9
KSI2 8 A8 KSI2
KSO0 8 38 KSO0
7 A7
KSI5 7 37 KSI5
6 6 36 A6
KSI4 KSI4
WL,Vol up,Vol down,Mute,Present button On/off ,information button KSO9
5
4
5
4
35
34
A5
A4 KSO9
KSI6 3 A3 KSI6
KSI7 3 33 KSI7
2 2 32 A2
KSI1 1 A1 KSI1
1 31
+3VS
conn@
FOX_GB1SV301-160K-7F

0.1U_0402_16V4Z 1

MDC 1.5 Conn. 1103 Connect pin2 to +3VS

2
C5 KSO9
KSI6
4
3
CP1
5
6
KSO2
KSO4
4
3
CP6
5
6
KSI7 2 7 KSO7 2 7
JP32 +3VS KSI1 1 8 KSO8 1 8

1 2 100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
HDA_SDOUT_MDC GND1 RES0
19 HDA_SDOUT_MDC 3 4
IAC_SDATA_OUT RES1 CP3 CP5
5 GND2 3.3V 6
19 HDA_SYNC_MDC R1313 HDA_SYNC_MDC 7 8 KSI2 4 5 KSO6 4 5
IAC_SYNC GND3
19 HDA_SDIN1 2 1HDA_SDIN1_MDC 9 10 KSO0 3 6 KSO3 3 6
33_0402_5% IAC_SDATA_IN GND4 HDA_BITCLK_MDC KSI5 KSO12
11 12 HDA_BITCLK_MDC 19 2 7 2 7
IAC_RESET# IAC_BITCLK KSI4 KSO13
1 8 1 8
HDA_RST#_MDC_R
100P_1206_8P4C_50V8 100P_1206_8P4C_50V8

13
14
15
16
17
18
19
20
19,26 HDA_RST#_MDC 1 2 CP7 CP2
13 TYCO_1-179396-2~D KSI3 4 5 KSO14 4 5
14
15
16
17
18
19
20
R1753 0_0402_5% KSO5 3 6 KSO11 3 6
KSO1 2 7 KSO10 2 7
0620 RESERVE FOR MDC Connector for MDC Rev1.5 KSI0 1 8 KSO15 1 8
conn@ 100P_1206_8P4C_50V8 100P_1206_8P4C_50V8

Power button +3VL

TrackPoint CONN. T/P BOARD.
+5VS
JP14 +5VS JP17
1

+5VS
R536 1 2 SP_CLK TP_DATA 1
3 4 31 TP_DATA 2
1

SP_DATA 1 TP_CLK 1
5 6 31 TP_CLK 3

2
R22 100K_0402_5% +5VS C321 C319
7 8 4
2

100K_0402_5% U5F ON/OFFBTN_KBC# ACES_87153-0801L D67 0.1U_0402_16V4Z SP_DATA 5 0.1U_0402_16V4Z

14

ON/OFFBTN_KBC# 31 2 6 2
SN74LVC14APWLE_TSSOP14
2

7
1

R26 D SP_CLK
P

+3VALW conn@ 8
ON /OFF# 13 TP_DATA
O 12 1
33 ON/OFF# 2 2

1
I G R8 @ PACDN042_SOT23~D TP_CLK ACES_87212-0800
G

1 100K_0402_5% 1 S 1 2
3

2
C23 C11 100K_0402_5% conn@
7

1U_0603_10V4Z 1U_0603_10V4Z 1 2 ON/OFFBTN# D58

2 2 ON/OFFBTN# 20
Q70 PJDLC05_SOT23~D
RHU002N06_SOT323 D42
CH751H-40_SOD323

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MDC/KBD/ON_OFF/LID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P UMA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 32 of 55
 A B C D E

+5VALW

1
DOCK CONN. 184PIN R529 20070226 Change RJ11 connector
100K_0402_5%
JP29

2
C746 @ 1000P_0402_50V4Z
L_RED 1 2 L10 SLP_S5#_5R DOCK_MOD_RING conn@
DOCK_MOD_TIP 2
C747 @ 1000P_0402_50V4Z KC FBM-L18-453215-900LMA90T_1812 Closed to dock JP30 1

1
L_GREEN D
1 2 VIN 2 1 DOCKVIN
C748 @ 1000P_0402_50V4Z 1 2 Q65
1 1 34 SLP_S5 1
L_BLUE 1 2 C72 C73 G E-T_3800-02_2P
DVI_TX2- R1479 1 2 100_0402_1% DVI_TX2+ S RHU002N06_SOT323

3
1000P_0402_50V7K 1000P_0402_50V7K DVI_TX1- R1480 1 2 100_0402_1% DVI_TX1+
2 2 DVI_CLK- R1481 1 2 100_0402_1% DVI_CLK+ SWAP
DVI_TX0- R1482 1 2 100_0402_1% DVI_TX0+

JP30B conn@
JP30A conn@
LPTACK# 46 128
29 LPTACK# 46 128
172 173 DOCKVIN 29 LPTBUSY LPTBUSY 47 129
G1 P1 LPTPE 47 129
29 LPTPE 48 48 130 130
LPTSLCT 49 131
29 LPTSLCT 49 131
LPD7 50 132
29 LPD7 50 132
ON /OFF# 1 83 DETECT LPD6 51 133
32 ON/OFF# 1 83 29 LPD6 51 133
2 84 LPD5 52 134 KBD_DATA
2 84 29 LPD5 52 134 KBD_DATA 31
MDO2+ 3 85 MDO3+ MDO3+ 24 29 LPD4 LPD4 53 135 KBD_CLK
24 MDO2+ MDO2- 3 85 MDO3- LPD3 53 135 CPPE# KBD_CLK 31
24 MDO2- 4 4 86 86 MDO3- 24 29 LPD3 54 54 136 136 CPPE# 15
5 87 LPD2 55 137 PS2_DATA
5 87 29 LPD2 55 137 PS2_DATA 31
MDO0+ 6 88 MDO1+ MDO1+ 24 29 LPD1 LPD1 56 138 PS2_CLK
24 MDO0+ MDO0- 6 88 MDO1- LPD0 56 138 DOCK_HPS# PS2_CLK 31
24 MDO0- 7 89 MDO1- 24 29 LPD0 57 139 DOCK_HPS# 27
7 89 LPTSLCTIN# 57 139
8 90 29 LPTSLCTIN# 58 140
LED_ACT_LAN#_DOCK 8 90 PWR_LED LPTINIT# 58 140 DLINE_IN_L
9 91 29 LPTINIT# 59 141 DLINE_IN_L 26
LED_LINK_LAN#_DOCK 9 91 SLP_S5#_5R 59 141 D LINE_IN_R
10 10 92 92 1 2 60 60 142 142 DLINE_IN_R 26
11 93 R515 1K_0402_5% 61 143
11 93 DVI_CLK 61 143 DLINE_OUT_L
16 D_VSYNC 12 94 DVI_CLK 16 62 144 DLINE_OUT_L 27
0314 change 12 94 DVI_DAT 62 144 DLINE_OUT_R
16 D_HSYNC 13 13 95 95 DVI_DAT 16 63 63 145 145 DLINE_OUT_R 27
1013 change DDC-DATA 14 96 64 146
16 D_DDCDATA 14 96 64 146
DDC_CLK 15 97 65 147
16 D_DDCCLK 15 97 65 147
16 DVI_DETECT DVI_DETECT 16 98 DVI_TX2- 66 148
16 98 DVI_TX2- 16 66 148
17 99 67 149 PCIE_TXP5
17 99 67 149 PCIE_TXP5 20
R1404 1 2 0_0603_5% DOCK_RED 18 100 DVI_TX2+ 68 150
9 RED DOCK_GRN 18 100 DVI_TX2+ 16 68 150 PCIE_TXN5
R1428 1 2 0_0603_5% 19 101 69 151 PCIE_TXN5 20
2 9 GREEN DOCK_BLU 19 101 69 151 2
R1429 1 2 0_0603_5% 20 102 70 152
9 BLUE 20 102 DVI_TX1- 70 152
21 103 DVI_TX1- 16 71 153
21 103 71 153 PCIE_RXP5_DOCK
9,16 COMP 22 104 20 USB20_N7 72 154 1 R1346 2 PCIE_RXP5 PCIE_RXP5 20
22 104 DVI_TX1+ 72 154 0_0402_5%
9,16 CRMA 23 23 105 105 DVI_TX1+ 16 73 73 155 155
24 106 74 156 PCIE_RXN5_DOCK 1 R1347 2 PCIE_RXN5
9,16 LUMA 24 106 20 USB20_P7 74 156 PCIE_RXN5 20
25 107 75 157 0_0402_5%
25 107 DVI_CLK- 75 157
26 26 108 108 DVI_CLK- 16 20 USB20_N9 76 76 158 158
27 109 77 159 CLK_PCIE_DOCK
26 LINE_IN_SENSE 27 109 DVI_CLK+ 77 159 CLK_PCIE_DOCK 15
28 28 110 110 DVI_CLK+ 16 20 USB20_P9 78 78 160 160
29 111 79 161 CLK_PCIE_DOCK#
44 ACOCP_EN# 29 111 SER_SHD 79 161 CLK_PCIE_DOCK# 15
30 30 112 112 29 SER_SHD 80 80 162 162
31 113 DVI_TX0- EXPCRD_RST# 81 163 PREP#
31 113 DVI_TX0- 16 29 EXPCRD_RST# 81 163 PREP# 20,24,26
32 114 DETECT 82 164 VA_ON#
32 114 DVI_TX0+ 82 164
33 115 DVI_TX0+ 16
33 115

1
DCD#1 34 116 176 178 1
29 DCD#1 R I#1 34 116 DOCK_ADP_SIGNAL GND GND
35 117 169 180 R66 C59
29 RI#1 35 117 GND GND
DTR#1 36 118 D OCK_ID 175 182
29 DTR#1 36 118 DOCK_ID 20 GND GND
CTS#1 37 119 179 174 1K_0402_5% 0.1U_0402_16V4Z
29 CTS#1 37 119 +3VS GND GND 2
RTS#1 38 120 181 171
29 RTS#1

2
DSR#1 38 120 GND GND
29 DSR#1 39 39 121 121 R1387 177 GND GND 170
TXD1 40 122 +5VS
29 TXD1 40 122 C678
RXD1 41 123 D OCK_ID 1 2
29 RXD1 41 123

+
42 124 165 167 1 2
LPTSTB# 42 124 @ 10K_0402_5% G2 P2
29 LPTSTB# 43 125
LPTAFD# 43 125 ADP_SIGNAL @ 22U_1206_10V4Z
29 LPTAFD# 44 126
LPTERR# 44 126 DOCK_MOD_RING DOCK_MOD_TIP
29 LPTERR# 45 127 R1401 166 168
45 127 RING TIP

2
DOCK_ADP_SIGNAL 1 2
JAE_SP03-14588-PCL03 JAE_SP03-14588-PCL03
1K_0402_1% D59
@ PACDN042_SOT23~D
3 3

1
1013 Add CRT circuit
Closed to JP30
+3VS +3VS
+3VS
C360
C366 C365
2 1
1 2 2 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z
U52 0.1U_0402_16V4Z
U51 U50
5 VCC
5 VCC 5
VCC
9 BLUE 1
L_BLUE A
16 L_BLUE 2 9 GREEN 1 9 RED 1
B L_GREEN A L_RED A
16 L_GREEN 2 16 L_RED 2
ISO_PREP# B B
20 ISO_PREP# 4
OE ISO_PREP# ISO_PREP#
4 OE 4 OE
3
GND
3 GND 3 GND
FSA66P5X_SC70-5
FSA66P5X_SC70-5 FSA66P5X_SC70-5

R1805 +3VALW
+3VM_LAN LED_ACT_LAN#_DOCK_R 1 2 LED_ACT_LAN#_DOCK
0_0402_5%
1

4 D 4
R527
C1372 0108 EMI request
2 1 2 Q62 @ 100P_0402_50V8J R526
10K_0402_5% G RHU002N06_SOT323 2 1
S 10K_0402_5%
3

LED_ACT_LAN#
LED_ACT_LAN# 23,24
2

R1806 PWR_LED
LED_LINK_LAN#_DOCK_R 1 2LED_LINK_LAN#_DOCK Security Classification Compal Secret Data Compal Electronics, Inc.
1

0_0402_5% D
1

D
C1373 25,31,32 LED_STB# 2 Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title
2 Q63 @ 100P_0402_50V8J G
G RHU002N06_SOT323 2 1 Q59 S Docking CONN.
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S RHU002N06_SOT323 Size Document Number R ev
3

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LED_LINK_LAN# LA-3261P U MA 0.4
LED_LINK_LAN# 20,23,24 20,23,26,27,31,34,41,42,43,44 SLP_S3# DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 33 of 55
A B C D E
 A B C D E

+1.25VM to +1.25VS Transfer +3VALW to +3VM Transfer +3VALW +3VM

U78
B+ 8 1
+1.25VM +1.25VS D S
7 D S 2
+3VALW C1273 6 3
1 D S

1
U77 10U_0805_10V4Z 5 4 1 1
10U_0805_10V4Z R1643 D G C1274 C1275
8 D S 1
7 2 1 0317 add 100K_0402_5% SI4800DY_SO8
D S

1
6 3 2 10U_0805_10V4Z
1 D S 2 2
C1270 5 4 + C254 R1647
1 1

2
D G C1271 C1272 330U_D2_2.5VM_R15 100K_0402_5% PM_SLP_M
1 SI4800DY_SO8 1

1
2 10U_0805_10V4Z 2 0.1U_0402_16V4Z

1
2 2 D R470
RU NON LAN_WOL_EN# 2 Q108
G BSS138_SOT23 470_0402_5%

1
0.1U_0402_16V4Z D +3VALW S

2
20,31,42,46 PM_SLP_M# 2 Q116 1
G C121

1
S

3
BSS138_SOT23 R1807 0.01U_0402_25V7Z
100K_0402_5% 2

+3VALW to +3VS Transfer 0119 Add R1807 and no stuff

1
D

20 LAN_WOL_EN 2 Q110
+3VALW +3VS G
B+ S

3
1
U13 BSS138_SOT23
8 1 10U_0805_10V4Z @ R630
D S
1

7
D S
2 0216 Install R1807 and non install R630 100K_0402_5%
R139 1 6 3
C127 D S
5 4 1 1

2
330K_0402_5% D G C132 C128
SI4800DY_SO8
2

2 10U_0805_10V4Z
2 2
RU NON
1

J34 0.1U_0402_16V4Z
R469 Discharge circuit-2 for V-M
RHU002N06_SOT323

SHORT PADS
1 2

470_0402_5%
2 D 2
2

SLP_S3 2 +1.25VM +1.05VM

1 +3VM
G C120
Q18 S
3

1
0.01U_0402_25V7Z

1
2 R631 R632
R633
470_0402_5% 470_0402_5%
470_0402_5%

1 2

1 2

1 2
D D
LAN_WOL_EN# LAN_WOL_EN# D
2 2
G G LAN_WOL_EN# 2
Q111 S Q112 S G
+5VALW to +5VS Transfer
3

3
RHU002N06_SOT323 RHU002N06_SOT323 Q113 S

3
RHU002N06_SOT323
+5VALW +5VS

U9 0718 Change net from PM_SLP_M# to LAN_WOL_EN#

8 1
D S
7 2
D S +3VL +5VALW
1 6 3
C86 D S +3VL
5 4 1 1
D G C71 C77

1
SI4800DY_SO8

1
2 10U_0805_10V4Z 10U_0805_10V4Z R125 R135
2 2 R129
RU NON 100K_0402_5% 100K_0402_5%
100K_0402_5%

2
0.1U_0402_16V4Z SLP_S3 SLP_S5
33 SLP_S5

2
SLP_S4
SLP_S4

1
3 D 3

1
SLP_S3# 2 D D
20,23,26,27,31,33,41,42,43,44 SLP_S3# SLP_S5#
G 2 2
20,42 SLP_S4# 20,42 SLP_S5#
Q19 S G G

3
RHU002N06_SOT323 Q23 S Q22 S

3
RHU002N06_SOT323 RHU002N06_SOT323

Discharge circuit-1
+1.8V

1
+0.9V +3VS
R1310
+1.5VS +2.5VS +5VS 0313 change
1

470_0402_5%
R186 R134

2
1

1
0313 change 470_0402_5% 470_0402_5% R151 R130 R116
1 2

470_0402_5% 470_0402_5% 470_0402_5% SLP_S4 1 2

D PWR_GD 20,25,31,35,43,44
R107 0_0402_5%
1 2

1 2

1 2
1

1
SLP_S4 1 Q27 D D
2 2
R1311 0_0402_5% G SLP_S3 2 D D D SLP_S5 1
C91 2 2
S G Q17 SLP_S3 2 SLP_S3 2 SLP_S3 2 @ R110 0_0402_5% G Q90
3

1 2 SLP_S5 1 2 S G Q47 G Q21 G Q16 S

+VCC_CORE +VCCP
3

3
4 @ R1312 0_0402_5% 4
S S S
3

3
0.1U_0402_16V4Z RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323
RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323
C184

+VCCP 1 2 +1.5VS

0.1U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title
C93
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
+1.5VS 1 2 +1.8V AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P UMA 0.4
0.1U_0402_16V4Z MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 34 of 55
A B C D E
PWR_OK circuit +3VS
1M_0402_5% R126
D71 CH751H-40_SC76 2 1 KBC PWR_OK circuit

1
+1.25VS 1 2
R47
+5VALW
2 1 10K_0402_5% +3VL
41 VCCP_POK
10K_0402_5% R285

2
8
20K_0402_5% U80A 20070227 Move R1803
J38 +3VL +3VL
2 1 R288 2 1 3

P
+5VS +

1
232K_0402_1% 1 1 2
O PWR_GD 20,25,31,34,43,44
R115 2 R24
-

G
+3VS 2 1
150K_0402_1% LM393M_SO8 SHORT PADS 100K_0402_5%

14

14
4
D69 R289 1.24VREF_393 U5D U5C

2
DDR_PGOOD 1 2 1 2

P
9 I O 8 5 I O 6 1 R1803 2 VCC1_PWRGD 30,31
CH751H-40_SC76 10K_0402_5%

1
R1747 1 0_0402_5%
C26 SN74LVC14APWLE_TSSOP14 R1802

7
1
1
R128 C32 0.1U_0402_16V4Z 100K_0402_5%
2

2
49.9K_0402_1% 1000P_0402_50V7K SN74LVC14APWLE_TSSOP14
2

2
1219 Add Schmitt Trigger to eliminate glitch and pull down resistor
0113 Change LMV331 to LM393, Delete R124 and C27

+3VALW R117

1 0_0402_5%
2 1 DDR_PGOOD
42 1.8PGOOD
R1752

1
10K_0402_5% D
2
1 2

G Q133
R284 C S RHU002N06_SOT323

3
+0.9V 2 1 2 Q134
3.3K_0402_5% B
E MMBT3904_SOT23
3

FM1 FM2 FM3 FM4

1 1 1 1
D70 +3VALW
R199
DDR_PGOOD 1 2 1M_0402_5%
1 2

1
CH751H-40_SC76 CF7 CF8 CF9 CF10 CF11 CF12 CF13 CF14
+5VALW R49 1 1 1 1 1 1 1 1
R1745 10K_0402_5%
R198
8

10K_0402_5% U80B
1 2 1 2 5
P

46 M_PROK

2
+
7 M_PWROK 7,20
20K_0402_5% O H1 H2 H3 H4 H5 H6 H7 H8 H9
+3VM 1 2 6
-
G

76.8K_0402_1% HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEAHOLEA HOLEA

LM393M_SO8
4

R1746
1.24VREF_393

1
1

1
C2
R39
1000P_0402_50V7K 56.2K_0402_1%
2 H10 H11 H12 H13 H14
2

HOLEB HOLEB HOLEB HOLEB HOLEB

R178
1 2
1.24VREF 1

1
10K_0402_5%
C33
1000P_0402_50V7K
2
H15 H16 H17
HOLEC HOLEC HOLEC

1
H18 H19 H20 H21 H22 H23 H24 H25
LAN_RST circuit HOLED HOLED HOLED HOLED HOLED HOLED HOLED HOLED

1
+3VL +3VL
Need be tune to
H27 H28 H32 H33 H34 H35 H36 H37
1 10msec time delay 1 HOLED HOLED HOLED HOLED HOLED HOLED HOLED HOLED
C991 C992
CH751H-40_SOD323
D60
0.1U_0402_16V4Z 0.1U_0402_16V4Z

1
2 2 1 2
14

14

R1732 R1350
P

+3VM 2 1 1 2 1 2 3 4 LAN_RST# 20
120K_0402_5% I O 100K_0402_1% I O
G

G
0.1U_0402_16V

U5A 1 SN74LVC14APWLE_TSSOP14
U5B
7

7
C990

SN74LVC14APWLE_TSSOP14 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
1113 Tie R1732.2 to 3VM instead of 3VM_LAN POK CKT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3261P U MA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 35 of 55
 5 4 3 2 1

D D

+B+ G965
ISL6269
AC VIN DC/DC +1.25VM +3VS LDO
Adapter VS (1.25V) (2.5V)
in Page46
Page37 Page41

+5VALWP
SWITCH
+1.25VM
ACOK APL5912
MAINPWON LDO +1.05VM
+2.5VS 1A
(1.05V)
+3VALWP 4A Page46
ENBL2 ENBL1
+5VS
B+ B+ PWR_GD
C MAX8734A C

DC/DC ISL6263
(3V/5V)
B+ VCC SHDN#
DC/DC
VCC_GFX
+5VALWP 4A (VCC_GFX)
VMB VIN Page40 Page45 ISL6260 &ISL6208
VS DC/DC
(CPU_CORE)
+3VLP 0.1A
Page43

BQ24703 MAX8743
Charger DC/DC +1.5VSP 4.2A
B+ (1.05V/1.5V) CPU_CORE
Page38
B
( 44A) B
+1.05V_VCCP 6.4A
SLP_S3# ENBL1/ENBL2 Page41 +5VALWP

BATSELB_A
Battery
Selector
Circuit BATSELB_A# VCC
Battery A Battery B
Page39
6 Cell 8 Cell TPS51116
B+ DC/DC +1.8VP 7A
VMB (+1.8VP/+0.9VSP)

SWITCH SWITCH SWITCH Battery Battery +0.9VP 2A

VMB_A VMB_B SLP_S5# S3/S5 Page42
Connector Connector
A A Page37 B Page37 A

BATT
BATT_A Title
POWER BLOCK DIAGRAM
BATT_B
Size Document Number Rev

Date: Tuesday, March 27, 2007 Sheet 36 of 55

5 4 3 2 1
 A B C D

PCN1 ADP_SIGNAL
9 GND6 SINGAL 5 VIN
8 GND5
1 PL1 1

7 1 SMB3025500YA_2P
GND4 PWR1
6 A DPIN 1 2
GND3

100P_0402_50V8J
4 GND2 PWR2 2

1000P_0402_50V7K
3 GND1

1
PC1

100P_0402_50V8J
1

1
PC4
FOX_JPD113E-LB103-7F PC2 PR1

PC3
1000P_0402_50V7K 15K_0402_5%

2
AB/I_A 38
VMB_A PL2 BATT_A
PCN2
FBM-L18-453215-900LMA90T_1812
BATT+ 1 1 2

2 EC_SMD_A
SMD EC_SMC_A PR2
SMC 3
2
RES 4 2 1 2

1
5 1M_0402_1%
TS PC5 PC6
6 1000P_0402_50V7K 0.01U_0402_50V4Z

2
GND +3VL
TYCO_C-1746706_6P
1

1
PR3
1K_0402_5% PR10
210K_0402_1%
2
1

2
PR4 PR5
THM_MAIN# 31
100_0402_5% 100_0402_5%
2

EC_SMD_A1 AB1A_DATA 31
EC_SMC_A1 AB1A_CLK 31
1

1
PC144
220P_0402_25V8K

PC143 PC145
220P_0402_25V8K 220P_0402_25V8K
2

3 3

VMB_B

PCN3 PL3 BATT_B

FBM-L18-453215-900LMA90T_1812
BATT+ 1 1 2

2 EC_SMD_B
SMD EC_SMC_B
SMC 3
1

4 AB /I_B 2 PR7 1
B/I TS_B 1K_0402_5% PC8 PC9
TS 5
1 2 1000P_0402_50V7K 0.01U_0402_50V4Z
+3VL
2

2
2

6 PR9
GND PR11 210K_0402_1%
SUYIN_20163S-06G1-K 1K_0402_5%
1
1

PR14 PR15
THM_MBAY# 31
100_0402_5%
100_0402_5%
2

EC_SMD_B1
AB1B_DATA 31
4 4

EC_SMC_B1
AB1B_CLK 31

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C ustom LA-3261P UMA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: Tuesday, March 27, 2007 Sheet 37 of 55
A B C D
 A B C D

1 1

VIN P2

BATT
P4 PQ2
PQ3 PQ4 AO4407_SO8
AO4407_SO8 AO4407_SO8 1 8
1 8 8 1 2 7
2 7 7 2 3 6
3 6 6 3 5
0.1U_0603_16V7K

PQ5 5 5

2
B+ P2
47K_0402_5%

DTA144EUA_SC70 PR17

4
1

3 1 PR398 0_0402_5%
4

4
1
PC12

PR16 @200K_0402_5% 1 2
2

47K

200K_0402_5%
PR20 PL4
47K

1
0.015_2512_1% FBM-L11-322513-151LMAT_1210
2

@150K_0402_5%
1 2 1 2
2

1
0_0402_5%
PR18
1

47P_0402_50V8J

PR19

PR399
ADP_PRES 23,31,39,40,44
2

CHG_B+
ACN 44
1
PC13

10U_1206_25V6M

4.7U_1206_25V6K
PR343
1

1 2
PR22 1 PR23

1
ACDRV# D 100_0402_1% 0_0402_5%
1

PC14

PC15
2 2 1
2

220K_0402_5% 2 PQ131 G

1
2

1U_0805_25V4Z
G PQ93 @RHU002N06_SOT323 S

1
S RHU002N06_SOT323 1 2
3

PC17
PR396
2 44 BATCAL# 0_0402_5% PC16 PD5 2

2
2

ADP_PRES 1 2 1U_0603_10V6K RLZ16B_LL34

2
PR21 1 2
2

3
2
1
150K_0402_5% PR24 PU2
PR397 1K_0402_1% 8 25 ACDRV#
@0_0402_5% ACN ACDRV#
9 22
1

ACP VCC D H_CHG PQ7

PD7 26 21 4
ACDET PWM# FDS4435_SO8
16
1

44 SRSET AC_CHG SRP

2 1 ADP_EN# 44 2 PR25 1 5 15
1K_0402_1% ENABLE SRN
28 12
ACSEL BATP
1SS355_SOD323
PR26 ALARM 19
ALARM BATDRV#
24 BATT
1 2 2
191K_0402_1% SRSET PR28
3 18 PL5

5
6
7
8
31,39 CHGCTRL ACSET VS
+3VL 2 PR27 1 27 ACPRES VHSP 20 0.015_1206_1%
100K_0402_5% 13 LX_CHG 1 2 1 2
BQ24703VREF IBAT

10U_1206_25V6M
137K_0402_1%
1U_0603_10V6K

4 6
VREF BATSET CV=12.6V(6 CELLS LI-ION)
2

100K_0402_1%

4.7U_1206_25V6K
1 10UH_PCMB104T-100MS_6A_20% 1
BATDEP
1

1
PC18

PR29

7
COMP GND
17 16.8V(8 CELL LI-ION)

1
PGND

3K_0402_1%

3K_0402_1%
PR30

PC19

PC20
10 23
NC1 NC4

1
11 14
2

2
NC2 NC3 2

PR31

PR32
CC=3A for 2.4AHr
1

4.7U_0805_6.3V6K

BQ24703_QFN28 PD8
2

29
EC31QS04
CC=3.57A for 2.55AHr

2
1

PC22

2
80.6K_0402_1%

PC21
1

1 2
Icharger=3A
2
1
1U_0603_10V6K
PC23

PR33

SE_CHG+
ACDET 0.1U_0402_16V7K
SE_CHG-
CELLSEL# =0,Vcharger= 12.6V
2

P2
PR34 CELLSEL# =1,Vcharger= 16.8V
2

+3VL +3VL
BATT
150P_0402_50V8J

1 2 PR35
3 150_0402_1% 3
1
100K_0603_1%

PC24

330K_0402_5%

1
4.7U_0805_6.3V6K
1 2
1

1
10K_0402_1%

PR44
2

VL
PR36

PR37

PC25 5.62K_0603_0.1%
BATT
PC26

0.1U_0402_10V6K
2

+3VL
2

1 2
AC detector PR39
2

2
8

2.15K_0402_1% PU3A PU4

High 11.689V 1

1
1 2 3 SN74LVC1G17DBVR_SOT23-5 PR380
P

+ 100K_0603_0.1% +3VL
Low 9.879V O
1 2
I O
4 ADP_PRES 23,31,39,40,44 PR42
1

12.4K_0603_1%

2 196K_0402_1%
- NC 1
G

PR384
PR40

1
LM393M_SO8 100K_0402_5%
4

2
+3VL
CELLSEL#

1
2

PR381 PR385
PR43 PR382 7.68K_0603_0.1% 330K_0402_5%

1
+3VL 25.5K_0402_1% D
4.7K_0402_5%
1

PR46 2

2
PR45 1 2 PR47 G
PR386
2

2
1

1
D

RHU002N06_SOT323
130K_0402_1% 1M_0402_5% 1 2 ALARM 39 37 AB/I_A S

PQ112 3
100P_0402_50V8J

PC27 100K_0402_5% 2 1 2 2

1
10K_0402_1%

@0.1U_0402_16V7K G
2

2
8

1
D D

RHU002N06_SOT323
PU3B PQ8 RHU002N06_SOT323 330K_0402_5% 44 S I_A#

PQ111 3
BQ24703VREF
PC28

PR48

5 2 PR360 2
P

+ G PR383 G
7 AC_CHG 39 2.8K_0603_0.1% CFET_B 39,44
2

O
1

RHU002N06_SOT323
10K_0603_0.1%

6 S 200K_0402_1% S
3

3
-
G
1

@47K_0402_1%

PQ110
22P_0402_50V8J

PR49
2
PR51

LM393M_SO8 100_0402_5%
4
1
PR50

PC29

VL
2

PR54
2

4 4

1 2 CELLSEL#
1

PQ10 D D
33K_0402_1% AC_CHG ACDET 2 2 PQ11
G G RHU002N06_SOT323
PU5 S S
3

1.24VREF RHU002N06_SOT323
4 REF CATHODE 3

Airline detector NC 2
Security Classification Compal Secret Data Compal Electronics, Inc.
High 17.521V Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
5 1
Low 16.871V ANODE NC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
APL1431LBBC_SOT23-5 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P UMA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 38 of 55
A B C D
 A B C D

+3VL

@0.1U_0402_10V6K
1
PC30
1 1

BATT_A

2
5
PU6 PD9
BATT_B PQ12

5
+3VL PU7 1 2

P
INB RHU002N06_SOT323
1 4 1

P
38 ALARM INB O PR55 PR56
4 2 3
O INA

G
47K_0402_5%
2 1 2 1 3 1 2 BATT_IN

S
INA

G
2

2
PR57
74LVC1G02_04_SOT353 RB715F_SOT323 100_0402_5% 0_0402_5%

0.1U_0603_50V4Z
74LVC1G02_04_SOT353 PD10

3
PQ13
1SS355_SOD323

G
2
RHU002N06_SOT323 PR58
PC31

1
PC32
1.5M_0402_5%

1
S

D
BATSELB_A 1 2 3 1

1
2
1000P_0402_50V7K PQ14 PD11
2

D RHU002N06_SOT323 +3VL
22K_0402_5%

G
2
LATCH
PR59

2 RLZ6.2C_LL34
G +3VL

2
S
3
1

1
PU8

NC
2 A Y 4
PQ15

G
PC33
1

RHU002N06_SOT323 D SN74LVC1G14DCKR_SC70-5 BATT

3
BATSELB_A# 1 2 2 1
G D
2

22K_0402_5%

1000P_0402_50V7K S PQ16 2 ADP_PRES 23,31,38,40,44

3

RHU002N06_SOT323 G
PR60

2
S 2
3

1
1

PMBT2222_SOT23
PR61
PQ17
470K_0402_5%

1
RHU002N06_SOT323 D
+3VL +3VL BATT_IN 2

1
C G

2
PQ18
2 S

3
B PR62

10K_0402_5%
E 470K_0402_5%

3
1
PQ19

PR63
PD12

1
RHU002N06_SOT323 D

1
CFET_A 1 2 2
G PR64

2
5

PU9 PU10 S 4.7K_0402_5%

PD13

3
1SS355_SOD323

5
P

NC

PR65

1
BATSELB_A# BATSELB_A PQ20 D
2 4 1 1 2

P
31 BATSELB_A#

2
A Y IN1
4 1 2 2
O
G

2 G RHU002N06_SOT323 SX34-40_SMA
IN2

G
SN74LVC1G14DCKR_SC70-5 S
3

3
10K_0402_5%

4
3

1
+3VL D
220P_0402_50V7K

SN74AHC1G08DCKR_SC70 PQ23 5 5
BATT_IN 2 3 6 6 3 PR66 BATT_A
1

PC34

G 2 7 7 2 470K_0402_5%
S 1 8 8 1

3
RHU002N06_SOT323 BATT
2

2
0.047U_0402_16V7K

PQ21 PQ22
2

470K_0402_5%

AO4407_SO8 AO4407_SO8
1

+3VL
PC35

PR70

PQ24 PQ25
3
+3VL AO4407_SO8 AO4407_SO8 3

1
1 8 8 1
2

PU11 2 7 7 2 PR67
1

1
SN74LVC1G14DCKR_SC70-5 3 6 6 3 470K_0402_5%
P

NC

PMBT2222_SOT23
2 4 PR68 5 5
A Y
2
220K_0402_5%

470K_0402_5%

2
G

BATT_B

4
2

470K_0402_5%
PR69
3

PR72
PR71 PU12 C
CHGCTRL PC180 PR342 PD15
1

PQ26
10K_0402_1% 2
1

PQ27

1
10K_0402_5%
1 2 1 2 2 1 B 1 2
P
1

G RHU002N06_SOT323 IN1 E PR73

38 AC_CHG 4

1
O

1
PR74
1000P_0402_50V7K 1K_0402_5% S BATSELB_A# 2 4.7K_0402_5%
PD16
3

IN2 SX34-40_SMA
G
470K_0402_5%

1SS355_SOD323

3 1
1

PQ94 1 2
3

2
PR344

RHU002N06_SOT323 SN74AHC1G08DCKR_SC70
PD14

CFET_B#
2

2
ADP_PRES 1SS355_SOD323 PQ29

1
RHU002N06_SOT323 D
PR75
2

1
PQ28 D
2
1 2 2 G
+3VL G RHU002N06_SOT323 S

3
10K_0402_5% S
3

38,44 CFET_B PQ30

CFET_B

1
RHU002N06_SOT323 D
PQ31 BATT_IN 2
5

PD17 D G
CFET_A 2 PU13 BATT_IN 2 S
P

3
1 2 4 G RHU002N06_SOT323
CFET_B I O BATCON 31
3 1 S
3

NC
G

4 4
1

100K_0402_5%

RB715F_SOT323 SN74LVC1G17DBVR_SOT23-5
3
PR77
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Battery selector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P UMA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 39 of 55
A B C D
 A B C D E

+3.3V/+5V

B+

1 1
2

PC36 PC37
PL6 0.1U_0603_50V4Z 0.1U_0603_50V4Z
FBM-L11-322513-151LMAT_1210 1 2 BST5B BST3B 1 2
B++

2
1

2200P_0402_50V7K

2200P_0402_50V7K
PD18
B++

10U_1206_25V6M

4.7U_1206_25V6K
CHP202U_SC70

8
7
6
5

5
6
7
8
1
1

1
PQ34 VL PQ35

D
D
D
D

D
D
D
D
PC38

PC39

PC41

PC42
AO4468_SO8 AO4468_SO8

1
2

2
2
2

G
S
S
S

S
S
S
PR79

47_0402_5%
D H5 0_0402_5%

1
2
3
4

4
3
2
1
1
PR80
LX5 PC40 LX3

1
0.1U_0603_50V4Z

2
B++

1
8
7
6
5

5
6
7
8
PQ126 PQ127

D
D
D
D

D
D
D
D
AO4468_SO8 AO4468_SO8

2
0.1U_0603_50V4Z
VL PR82

G
S
S
S

S
S
S
0_0402_5%
2VREF_1999
1
2
3
4

4
3
2
1
1

4.7U_0805_10V4Z

1
44 LX_5V

200K_0402_1% 200K_0402_1%

499K_0402_1% 200K_0402_1%
1U_0805_16V7K
1

2
PC44

PR83

PR84
PL7

1
4.7UH_SIQB745-4R7_4A_30% BST3A

PC45

PC46

2
2 2
2

2 1

2 1
18

20

13

17

PR86
BST5A 14

LD05

V+

TON

VCC
BST5

PR87
5
ILIM3 DL3
16 DH5

1
+5VALWP

1
15 PL8
DL5 LX5 PU14
19 11 4.7UH_SIQB745-4R7_4A_30%
DL5 ILIM5
21 OUT5 MAX8734EEI_QSOP28
9 28
FB5 BST3
@22U_1206_6.3V6M

@10.2K_0402_1%

1 26 D H3

2
N.C. DH3
2

B++ 24
DL3
PR88

6 27
SHDN# LX3
150U_B2_6.3VM

1 4 22
ON5 OUT3
1
47K_0402_5%

2VREF_1999 1 2 3
ON3
1

PC47

+ PR89 7
1

FB3
PC197

PR90

1 2 0_0402_5% 12 2 +3VALWP
0_0402_5% SKIP# PGOOD
2VREF_19998
2

@3.57K_0402_1%
PRO#
LDO3
PR91

GND
2

REF
2

2
0_0402_5%

PR93

150U_B2_6.3VM
PR92

PR94
1 2 1
1

@0_0402_5%

23

25

10

PC49
+

0.22U_0603_10V7K
PC48
0.1U_0603_50V4Z
1

2 1
1
MAINPWON

PC50
PGOOD

2
2

1
PR95 100K_0402_5%

0_0402_5%
4.7U_0805_10V4Z

PR96
VL 0_0402_5% PR242

+3VLP +3VALWP

1
1

1
3 3

2
PC51
PR97 +3VL

2
499K_0402_1%
2

+3VLP
1

+3VL
PR98 PJP1
100K_0402_5% 2 1
1

PAD-OPEN 2x2m
2

PC52
1

0.1U_0603_50V4Z D
2

PQ36 2
RHU002N06_SOT323 G
S RHU002N06_SOT323
3

D PQ37
2
G KBC_PWR_ON 31
S
3

RHU002N06_SOT323
1

D PQ77
2
G ADP_PRES 23,31,38,39,44
S
3

4 4

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
3.3V / 5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-3261P UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 40 of 55
A B C D E
 A B C D

PL9
MAX8743_B+ FBM-L11-322513-151LMAT_1210

10U_1206_25V6M
2 1 B+
1

1
2200P_0402_50V7K
+5VALW

PC53

PC54

2
PR99

2
8
7
6
5
2 0_0402_5%
PQ38

D
D
D
D
1 1
AO4468_SO8

1
G
S
S
S
1U_0805_25V4Z

1
2
3
4

2200P_0402_50V7K

4.7U_1206_25V6K
PC56

1
PD19

1
PC55

1
4.7U_0805_10V4Z

2
8
7
6
5

1
PR100

PC57

PC58
PQ40 20_0603_5%

D/K
D/K
D/K
D/K
AO4712_SO8 CHP202U_SC70

2
2
S/A
S/A
S/A
G
BST_1.5V_2 PQ39

BST_1.05V_2
1 8

1
2
3
4
DH_1.05V_2 BST_1.05V_1 D2 G2
1 2 2 7
PC59 D2 D1/S2/K
3 G1 D1/S2/K 6

0.1U_0603_50V4Z
0.1U_0603_50V4Z PR101 VCC_MAX8743 4 5
S1/A D1/S2/K

V+ 1U_0805_16V7K
0_0402_5% +1.5VSP
+1.05V_VCCP

1
2 1 2 1 PR102 PC62 PL11

PC60

PC61
0_0402_5% 0.1U_0603_50V4Z SI4914_SO8 3.3UH_SIQB74-3R3RF_4.8A_30%
220U_B2_2.5VM

1 3.3UH_MPL73-3R3_6A_20% 1 2 2 1 1 2

2
PL10

BST_1.5V_1

220U_B2_2.5VM
PC63

+ PR104

22
1

9
PU15 0_0402_5%

5.1K_0402_1%

PC66
PR103 25 21 1 2 DH_1.5V_2 +

UVP
VCC
BST1 VDD

1
2 2.2_0402_5%
1

PR105
5.1K_0402_1%

1 2 DH_1.05V_1 26 19
DH1 BST2 2
PR106

18 DH_1.5V_1
LX_1.05V DH2 LX_1.5V
27 LX1 LX2 17
DL_1.05V 24 20 DL_1.5V

2
DL1 DL2
2
16 2
2

CS2
28
CS1
1 OUT1 OUT2 15
FB2 14
2 12
FB1 ON2
1

PD30 7
PGOOD

10K_0402_1%
PR107 5 2 1
TON VCCP_POK 35

PR111
100K_0402_1% 1 2 11 PR108
ON1 0_0402_5%
13
ILIM2
3

SKIP
GND
OVP
2

REF
1SS355_SOD323 ILIM1

2
MAX8743EEI_QSOP28 PR113
PD31

23

10
20K_0402_1%
20,23,26,27,31,33,34,42,43,44 SLP_S3# 1 2 2 1 2 1
PR123 2VREF
@0.001U_0402_50V7M

0_0402_5% 2 1
1SS355_SOD323

100K_0402_1%
1

1
VCC_MAX8743 2 1 PR114
1

PC71

PR118
@0_0402_5% 20K_0402_1%

1
PR117

0.22U_0603_10V7K
PR116 100K_0402_1% 2 1
2

SLP_S3# 20,23,26,27,31,33,34,42,43,44

PC69
PR121

@0.001U_0402_50V7M
PR120 0_0402_5%

2
0_0402_5%

PC70
2
+3VALW

3 3

1
PJP11
PAD-OPEN 2x2m
1.5VSP/ +1.05V_VCCP/+2.5V +2.5VSP

2
PU26

1
2 3
PC134 VIN VO
10U_1206_6.3V6M 1 4 PR244

2
EN ADJ 13K_0603_1%

1
5 7

2
GND GND PC135
6 8 10U_1206_6.3V6M

2
GND GND

1
PR243
G965-18P1U_SO8
10K_0402_5% PR245
PJP2 PJP3 1 2 12K_0402_1%
20,23,26,27,31,33,34,42,43,44 SLP_S3#

@0.1U_0603_16V7K
+1.5VSP 1 2 +1.5VS +5VALWP 1 2 +5VALW

2
(4A,160mils ,Via NO.=8) (4.5A,180mils ,Via NO.= 9)

PC181
PAD-OPEN 3x3m
PAD-OPEN 4x4m
PJP5

2
PJP6 1 2
+3VALWP +3VALW
PAD-OPEN 4x4m (3A,120mils ,Via NO.= 6)
+1.05V_VCCP 1 2 +VCCP (6A,240mils ,Via NO.= 12) PAD-OPEN 4x4m
PJP13

PJP8 +1.25VMP
1 2
+1.25VM
(3A,40mils ,Via NO.= 6)
4
+0.9VP 1 2 +0.9V (2A,80mils ,Via NO.= 4) PAD-OPEN 4x4m 4

PJP9
PAD-OPEN 3x3m
+2.5VSP 2 1
+2.5VS (1A,40mils ,Via NO.= 2)
PJP14 PAD-OPEN 2x2m
VCCGFXP 1 2 VCCGFX (8A,240mils ,Via NO.= 16)
PAD-OPEN 4x4m Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
PJP15
+1.05VMP
2 1
+1.05VM (1A,40mils ,Via NO.= 2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2.5VALW/1.5VS/1.05VCCP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
PAD-OPEN 2x2m DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P UMA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 41 of 55
A B C D
 5 4 3 2 1

D D

DDR_B+ PL12
FBM-L11-322513-151LMAT_1210
+1.8V 2 1 B+

2200P_0402_50V7K
1

1
1

0_1206_5%

PC72
PC73

5
6
7
8
PR124
10U_1206_25V6M

2
PQ45 2

D
D
D
D
AO4468_SO8
PR125 PC74

2
0_0402_5% 0.1U_0603_50V4Z

12
7

G
S
S
S
PU17 BST_1.8V_1
1 2 BST_1.8V_2 1 2
PR126

NC

NC

4
3
2
1
10U_0805_10V4Z
0_0402_5%
1

PC76
PC75 23 22 DH_1.8V_1
1 2 DH_1.8V_2 +1.8V
10U_0805_10V4Z VLDOIN VBST 2.2UH_IHLP-2525CZ-01_8A_+-20%
2

24 21 LX_1.8V 1 2
VTT DRVH
C
+0.9VP PL13 1
C

5
6
7
8
1 VTTGND LL 20
DL_1.8V + PC78

D
D
D
D
PQ46 220U_D2_4VY
1

2 19 AO4712_SO8
PC79 VTTSNS DRVL 2

G
S
S
S
22U_1206_6.3V6M
2

3 18

4
3
2
1
GND PGND

22P_0402_50V8J
PR127

0.001U_0402_50V7M
0_0402_5%

1
20K_0603_1%
1 2 4 MODE CS 16

1
7,13,14 V_DDR_MCH_REF
0.033U_0402_16V7K

PC80
14.3K_0603_0.1%
1

PC83

PR129
PR128
PC81

5 14

2
VTTREF V5FILT

4.7U_0805_10V4Z
2

2
1

2
PC82
6 TPS51116RGE_QFN24 13 PR130
COMP PGOOD 3_0402_5%

2
2 1 +5VALWP
+5VALW 8 VDDQSNS S5 11
PR131

Thermal pad
2 1 @0_0402_5%
SLP_S5# 20,34
CS_GND
9 VDDQSET S3 10
B PR132 B

V5IN
2 1 0_0402_5%
SLP_S4# 20,34
PR133
17

25

15
2 1 @0_0402_5%
SLP_S3# 20,23,26,27,31,33,34,41,43,44
PR134
2 1 @0_0402_5%
SLP_S4# 20,34

PR387
2 1 0_0402_5%
PM_SLP_M# 20,31,34,46
1 2 +3VALW

1
@0.001U_0402_50V7M
PR294

@0.001U_0402_50V7M
100K_0402_5%
10K_0603_0.1%
1

PC84

1
PR135

PC85
2

2
1 2 1.8PGOOD 35

2
PR317
0_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8V/0.9VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-3261P UMA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 42 of 55
5 4 3 2 1
 8 7 6 5 4 3 2 1

+CPU_B+ PL15
FBM-L18-453215-900LMA90T_1812
1 2 B+

2200P_0402_50V7K

4.7U_1206_25V6K
0.01U_0402_50V4Z

47U_25V_M
H 1 H

PC148
10U_1206_25V6M
+
1

1
PC100

PC103
PQ50

PC101

PC102
5
SI7840DP_SO8 2

2
2

+CPU_B+

1DH_CPU1_M
PR148
+5VS 2_0402_5% 4
2 1

BST_C PU1_1

BST_C PU1_2
2

1U_0603_10V6K
PR149 PR346

3
2
1
1
PC104
10_0603_5% 0_0402_5%

0.01U_0402_25V7K
PC105

2
P U18 0.22U_0603_10V7K

2
G 5 1 1 2 PL16 G
VCC BOOT
6 8 D H _ CPU1 .36UH_MPC1040LR36_ 24A_20%
FCCM UGATE

1
PC106
2 7 LX_CPU1 1 2 + VCC_CORE
PWM PHASE

4.7_1206_5%

2
3 4

2
GND LGATE

8
7
6
5

8
7
6
5
IRF7832Z_SO8

IRF7832Z_SO8
PR150

1
ISL6208CRZ-T_QFN8 <BOM Structure> 10_0402_1%

D
D
D
D

D
D
D
D
+5VS

PQ52

PQ53
PR151 PC107

PR347
10K_0402_1% 0.22U_0603_16V7K

1
+3VS

10_0603_5%
1 2 2 1

G
S
S
S

S
S
S

2 2

680P_0603_50V7K
1
2
3
4

1
2
3
4

2
PR152
PR153
1 5.11K_0402_1% 2 PR154 1

1
2
1U_0603_10V6K

@0_0402_5%

1
1

F PR155 F

PC182
PC108

1.91K_0603_1% VSUM VO
2

D L_CPU1

1
+VCCP
PGOOD_PU19 31 +CPU_B+

PC109 +5VS
1

2 1 N TC
PR370
19

20

18

39

40

2200P_0402_50V7K

4.7U_1206_25V6K
0.01U_0402_50V4Z
0.01U_0402_16V7K 68_0402_5% ISL6260CRZ-T_QFN40 PR157
2_0402_5% PQ54

3V3
VDD

VIN

PGOOD
VSS

PR158 SI7840DP_SO8

1DH_CPU2_M
2 1 1
2

1
PC110
1U_0603_10V6K

BST_C PU2_1
0_0402_5%

BST_C PU2_2

PC111

PC112
2 1 4 PC113
4 H_PROCHOT# VR_TT#

PC114
4 10U_1206_25V6M

2
2 PR1591 3 27 PW M1 2
147K_0402_1% PH 2 RBIAS PWM1

2
E E
2 PR160 1 2 1 N TC 5
4.22K_0603_1% PC115 NTC PC116

3
2
1
2 1 470KB_0402_5%_ERTJ0EV474J 6 23 ISEN1 P U20 0.22U_0603_10V7K PR348
SOFT ISEN1 0_0402_5% PL17
5 1 1 2
0.015U_0402_16V7K P U19 VCC BOOT

2
2 PR1611 28 6 8 D H _ CPU2 .36UH_MPC1040LR36_ 24A_20%
5 C PU_VID0 VID0 FCCM UGATE
2 PR162 1 0_0402_5% 29
5 C PU_VID1 0_0402_5% VID1
2 PR163 1 30 26 PW M2 2 7 LX_CPU2 1 2 + VCC_CORE
5 C PU_VID2 VID2 PWM2 PWM PHASE
2 PR164 1 0_0402_5% 31

4.7_1206_5%
5 C PU_VID3 VID3

2
0_0402_5% 2 PR165 1 32 3 4
5 C PU_VID4 VID4 GND LGATE

8
7
6
5

8
7
6
5
IRF7832Z_SO8

IRF7832Z_SO8
2 PR166 1 0_0402_5% 33 PR167
5 C PU_VID5 VID5

1
0_0402_5% 2 PR168 1 34 22 ISEN2 ISL6208CRZ-T_QFN8 <BOM Structure> 10_0402_1%

D
D
D
D

D
D
D
D
5 C PU_VID6 VID6 ISEN2

PQ56

PQ57
0_0402_5% PR170 PC117

PR349
2 PR169 1 37 10K_0402_1% 0.22U_0603_16V7K

1
5,7,19 H_DPRSTP# 0_0402_5% DPRSTP#
1 2 2 1

G
S
S
S

S
S
S
2 PR171 1 36 41

2 2
7,20 DPRSLPVR DPRSLPVR CS_GND

680P_0603_50V7K
1
2
3
4

1
2
3
4

2
2 PR172 1 499_0402_1% 1
D
5 H_PSI# 0_0402_5% PSI# PR173 D
31 PM_POK 2 PR174 1 2 24 5.11K_0402_1% 2 PR175 1

1
0_0402_5% PGD_IN FCCM
38 PR177 @0_0402_5%

1
20 CLK_EN# CLK_EN#
2 1 +5VS

PC183
20,23,26,27,31,33,34,41,42,44 SLP_S3# 1
PR328
2 35 0_0402_5% VSUM VO
@100_0402_5% 2 PR178 1 VR_ON
20,25,31,34,35,44 PWR_GD
0_0402_5% 12 25 D L_CPU2
5 VCCSENSE PR318 VSEN PWM3
@27.4_0402_1% 13
+ VCC_CORE RTN
2 1 2 1
PR179 PC118 21
@10_0402_1% ISEN3
2 1 11
PR180 PC119 VDIFF
@10_0402_1% 1000P_0402_50V7K 2 1
2 1 10
1000P_0402_50V7K FB PR181
7 2 1
OCSET 11.5K_0402_1%
9
C 5 VSSSENSE COMP C
PR182 PC120 17 VSUM
VSUM
1.96K_0402_1%

PR319 180_0603_1% 1800P_0402_50V7K PR183 8

VW
1
@1000P_0402_50V7K

@27.4_0402_1% 2 1 1 2 2 1
PR185
DROOP

2 1 2 PR184 1 0_0402_5%
1.2K_0402_1%
DFB

0.22U_0603_10V7K
VO

PC122
4.53K_0402_1%

2
2
PR186

PC123

1 2 2 PR187 1
14

15

16

51K_0603_1%
1

PC124 PC121
2

1 2 0.022U_0402_16V7K
0.1U_0402_16V7K

10KB_0603_5%_ERTJ1VR103J

220P_0402_25V8K PC125 VO
2 1

1000P_0402_50V7K
1
PC126

PR188
2 1
1

B B
@1K_0402_1%

6.98K_0402_1% PR190 PR191

2

PH 3

6.34K_0603_1% 1K_0402_1%
PR189

2 1 2 1

PR179,PR180 are for test need when M/B is without CPU

2

R1269,R1270 are same funtion with PR179,PR180

PC127
Layout Note: Use27.4 Ohm(PR318,PR319) routing for Vssense and
2 1
Vccsense
330P_0402_50V7K

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-3261P UMA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 43 of 55
8 7 6 5 4 3 2 1
 5 4 3 2 1

PQ72 +5VS
+5VS PD20 NDS0610_NL_SOT23-3
+3VS CH751H-40_SOD323
1 2 1 2 1 3

S
1
+5VS
PR259 PD21
PR193

1
PU22A 1M_0402_1% CH751H-40_SOD323

G
2
8

1U_0805_16V7K
PR194 PR192 1 2

PC128
D 3 330K_0402_5% PR256 133K_0402_1% D

2
+ 100K_0402_5% PR257
1 0 2 1
P4

220K_0402_5%
2 10K_0402_5%

2
-
G

220K_0402_5%
PU22B PU21B PU21A 10K_0402_5%
PR197

2
2

0_0402_5%

0_0402_5%
LM358A_SO8 5 3

P
4

2
+ +

1
PR196

PR195
1 2 5 + O 7 O 1

PR251

PR252
6.81K_0402_1% 7 6 2
0 - -

G
1 2 1 2 6 PR208

2
PR199 PR200 - LM393M_SO8 LM393M_SO8 10_0402_5%
1

4
10K_0402_1% 100K_0603_0.5% PR201

2
1
2K_0402_5%
LM358A_SO8 1 2

2
PR202
0_0402_5% 1 2

1
1U_0805_50V4Z

80.6K_0402_1%
PR203
PQ70
1

PC130

0.027U_0402_16V7K
1 2 604K_0603_1% LX_5V 40
DTA144EUA_SC70

PR205
MMBT3906_SOT23
2
PC129 V IN
2

1
PC131
39.2K_0402_1%

PQ58
0.22U_0603_16V7K

2
3
7.87K_0402_1%
E
3 1

2
B
2

2
PR206

PR260
PR207 PD28

47K
C
3.9K_0402_5% 1SS355_SOD323

47K
1
PU23

1 2

1 2

1
PD22
D @CH751H-40_SOD323
4 REF CATHODE 3

1
2 1 2 PR254
PR211

PR210

422_0603_1%
2 G PW R_GD 20,25,31,34,35,43 150K_0402_5% PR253
NC
0.1U_0402_16V7K

RHU002N06_SOT323
PQ73

1SS355_SOD323
S 1 2 OCP# 4,20 210K_0402_1%

3
1

2
PC132

5 1 0_0402_5%

2 2
ANODE NC

P D24
C C

2
2

1
APL1431LBBC_SOT23-5

470K_0402_5%
2 PQ60 PD27 ADP_SIGNAL

1
G 1SS355_SOD323 +3VS
RHU002N06_SOT323
1

PR215
S PR255 PD26

1
1
PR212
D

1
33 ACOCP_EN#

RHU002N06_SOT323
0_0402_5% PR261 1 2 1 2 PQ71

1
B+ 1M_0402_1% 2
G
2

PQ61 1K_0402_5% 1SS355_SOD323

S

3
1

MMBT3904_SOT323 C CFET_B 38,39

D D D
1

1
RHU002N06_SOT323

23,31,38,39,40 ADP_PRES
2
23,31,38,39,40 ADP_PRES I_A# 38PQ74
B 2 2 2
ADP_PRES 23,31,38,39,40
PQ113

PR217 E G G G
3

47.5K_0402_1% PQ92 S S S RHU002N06_SOT323

3

3
1 2 RHU002N06_SOT323

1
PR265
PQ62
47K_0402_5%
ADP_SIGNAL NDS0610_NL_SOT23-3
PD25

2
3.9K_0402_5%

3900P_0402_50V7K
S

3 1 2 1

1
1

PR214
V IN 1SS355_SOD323

PC147
G
2
1

V IN
1

PR223 +3VL 2

1
137K_0402_1% PR224 +3VS
B 22.6K_0402_1% B

1
PC146
2

2
8

PU25A 1U_0603_10V6K PC133

2

1
0.1U_0603_16V7K PR219 +5VS
3
P

PR216

2
+ PR221 1M_0402_5% PR218
O 1
2 10K_0402_5% 2 1 1 2 10K_0402_5%
-
G
1

PR236 LM393M_SO8 PR220

4

2
470K_0402_5%

8
10K_0402_1% 10K_0402_5% PU24A
+3VS
1 2 3

P
ADP_ID 31 A CN 38 + ADP_PS0 31
1
2

PR229 O
BATCAL# 38 2 -

G
1
1M_0402_5%
1 2 PR222 LM393M_SO8

4
38 SRSET 71.5K_0402_1% +3VS
D
1

2
1

V IN PR238 PQ95 PR225

20,23,26,27,31,33,34,41,42,43 SLP_S3# 2

2
PR235 1M_0402_5% G RHU002N06_SOT323 @100K_0402_5% PR226 +5VS

1
10K_0402_1% V IN S 1M_0402_5%
1 2
3
1

1
+3VL
1 2
1

PR258 PR228 PR227

2

29.4K_0402_1% PU25B 21K_0603_1% PR232 10K_0402_5%

1

8
5 PR230 21K_0603_1% PU24B
P

2
+ 47K_0402_5%
7 1 2 5

P
2

1 2
O PR231 PR233 +
6 - O 7
G

D
1

220K_0402_5% 100K_0402_5% C 6 ADP_PS1 31

2

G
47K_0402_5%

2 LM393M_SO8 1 2 2 PQ63 PR234

4

2
1

G B MMBT3904_SOT323 3.48K_0402_1% LM393M_SO8

ADP_EN 31

4
D
1

1
PR237
0_0402_5%

S PQ65 E
3

A A
1
PR240

@RHU002N06_SOT323 2 PQ64

2
PR241 G RHU002N06_SOT323
1

220K_0402_5%

10K_0402_1% S
2

PD23
2

PR239
2

1 2 Security Classification Compal Secret Data Compal Electronics, Inc.

2

1SS355_SOD323 Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADP_OCP
ADP_EN# 38 Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C ustom LA-3261P UMA
2005.8.20 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: Tuesday, March 27, 2007 Sheet 44 of 55
5 4 3 2 1
 5 4 3 2 1

+3VS

1
PR326
30K_0402_1%

GFX_B+
PR327

2
D
1 2 VGAVR_ON GFX_B+ PL18 D
+5VS FBM-L11-322513-151LMAT_1210
0_0402_5%

1
PQ80 D
2 1 B+

1
7 DFGT_VR_EN 2

2200P_0402_50V7K

10U_1206_25V6M
G @RHU002N06_SOT323 PR295

1
S PR296 10_0402_5%

0.01U_0402_25V7K

PC151

PC152
10_0402_5% PC153
4.7U_1206_25V6K

2
2
+3VS

1
PC166
1
1
PC167

5
6
7
8
PR297 1U_0603_10V6K

2
1.91K_0402_1% PQ78

D
D
D
D
AO4468_SO8

15
PR324 PU30

2
@0_0402_5% 16 14 PR272

VSS
7,20,31 PM_PWROK VCC VIN

G
S
S
S
1 2 31 2.2_0402_5% DH_GFX
PGOOD BST_GFX 1
17 2

4
3
2
1
PR298 0_0402_5% BOOT
1 2 27 D4
7 DFGT_VID_3

1
PR299 1 2 0_0402_5% 26 18 VCCGFXP
7 DFGT_VID_2 PR300 0_0402_5% D3 UGATE PC156 1.5UH_IHLP-2525CZ-01_9A_+-20%_15mohm
1 2 25 D2
7 DFGT_VID_1 PR301 0_0402_5% 0.22U_0603_10V7K
1 2 24

2
C 7 DFGT_VID_0 D1 C
PR302 1 2 0_0402_5% 23 19 LX_GFX 1 2
D0 PHASE
+3VS @0_0402_5% +3VS PR303 1 2 10K_0402_5% PL19

5
6
7
8

@SX34_SMA

330U_D2E_2.5VM_R9
10K_0402_5% 1 PR320 2 30 21 1
SPIR LGATE

1
1 PR304 2 32 PQ79

D
D
D
D
+5VS FDE +

PD29

PC157
1 PR305 2VGAVR_ON29 VR_ON PGND 20 AO4712_SO8
7 DFGT_VR_EN

1
PR321 2 1
PR325 100K_0402_1% 0_0402_5% 13 PR279 PR311
VSUM

G
2

S
S
S
1 2 22 @ 7.68K_0805_1% 0_0402_5%

2
PVCC PH4
12

4
3
2
1
1_0402_5% VO PR281
1 2 1

2
RBIAS
1

PR306 28 1 PR307 2 DL_GFX 1 2 1 2

PC168 PC169 150K_0402_1% I2UA
2.2U_0603_6.3V6K 2 1 0.01U_0402_25V7K 2 20K_0402_1% 3.57K_0402_1% 10KB_0603_5%_ERTJ1VR103J
2

PR308 SOFT
DFB 11
VCC_PRM 1 2 3 1 PR309 2
12.4K_0603_1% OCSET 4.53K_0402_1%
DROOP 10
1 2 PC170
1000P_0402_50V7K 4 8 1 2 PC160
VW VSEN 0.033U_0402_16V7K
1 2
PR310 6.98K_0402_1% 5 9 1 2
COMP RTN
VDIFF

VSUM1 PC179
6 VCC_PRM 0.022U_0402_16V7K
EP

FB
B B
ISL6263_QFN32
7

33
180P_0402_50V8J

1
1 PR312 2 1 PR313 2
1

1K_0402_1% PC172
PC174

PC173 1.91K_0402_1% 0.1U_0402_16V7K

2
68P_0402_50V8J PR314 1 2 PC175
2

330P_0402_50V7K
2 1 PR286
1

1 2
PR315 0_0402_5% VCCGFX
2.21K_0402_1%
1

374_0402_1%
PR316 PC176
PC177 1000P_0402_50V7K PR288
2

2 1 2 1 1 2
0_0402_5%
1000P_0402_50V7K

4.99K_0402_1% 560P_0402_50V7K
1

1
PC164

Parellel from VCCGFX and GND underneath GMCH at Interface Power pin
PC178
1000P_0402_50V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VCCGFX
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-3261P UMA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 45 of 55
5 4 3 2 1
 5 4 3 2 1

B+_6269

PL20
D FBM-L11-322513-151LMAT_1210 D
2 1
B+

+6269_VCC

1
PC89 PR136

1
4.7U_1206_25V6K 1 2 BOOT1 1 2 PC90

2
PR137 0_0402_5% 0.1U_0402_16V7K
10K_0402_5%

BOOT
+5VALW

1
PR138
0_0402_5% UG

16

15

14

13
PU28 PQ47
17 1 PR139 2 1 8

UG

BOOT
PHASE
PGOOD
+6269_VCC

2
GND 2.2_0603_5% D2 G2
2 7
D2 D1/S2/K
3 6
G1 D1/S2/K
1 12 1 2 PC91 4 5
VIN PVCC S1/A D1/S2/K
+6269_VCC +1.25VMP
2.2U_0603_6.3V6K
SI4914_SO8
2 11 LG
VCC LG PL14

1
LX6269 1 2
PC92

220U_B2_2.5VM
2.2U_0603_6.3V6K 3 10 3.3UH_MPL73-3R3_6A_20% 1

2
FCCM PGND

PC142
+
C PR249 C
PR141
1 2 4 9 1 2
20,31,34,42 PM_SLP_M# EN ISEN 7.5K_0402_1% 2

COMP

TEST
0_0402_5%

VO
FB
5

8
ISL6269ACRZ-T_QFN16

150K_0402_1%
1

1
10P_0402_50V8J
1

1
PR142

57.6K_0402_1%
PC95

PR143
PC96
0.01U_0402_16V7K

2
2

2
1
PC97
1000P_0402_50V7K
2
PR144
1 2

12K_0402_1%

1
+5VALW
PR147
11K_0402_1%
B +3VALW B

1
2

PC139 +1.25VM

1
1U_0603_10V6K

2
PR293
@10K_0402_1%

6
PU27

1
5

VCNTL
2
VIN PC138
1 2 7
35 M_PROK PR323 POK
9 10U_1206_6.3V6M

2
0_0402_5% VIN
3
VOUT

20,31,34,42 PM_SLP_M# 1 2 8
EN VOUT
4 +1.05VMP
PR292

GND

1
0_0402_5% 2
FB PC141
APL5912-KAC-TRL_SO8 22U_1206_6.3V6M

2
1

1
PR247
47K_0402_1% PC140

2
27P_0402_50V8J

2
1
PR248
150K_0402_1%

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.25VMP/+1.05VMP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P U MA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 46 of 55
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) for Power Circuit (1)

Request
Reque st
Item
It em Page# T itle D ate Issue
Is sue Description Solution
So lution Description R ev.
O wner
D No install PR131 and install PR132 D
1 Page42 1.8V/0.9V 3/9/2006 HP RL Change SLP_S5# at PR134.1 to SLP_S4#
Power Sequence DB
No install PR133 and install PR134
Add a 0 ohm resistor PR317 (no stuff) on M_PWROK
2 Page45 VCCGFX 3/9/2006 Compal MAX8776 VID table can't meet Intel VID SPEC Change VCCGFX IC solution from MAX8776 to ISL6263 DB
Add 27.4 ohm pull-down (no stuff) on
VCCSENSE & VSSSENSE near VR DB
3 Page43 CPU_CORE 3/10/2006 HP RL

Add a 0 ohm resistor PR323 (install) on M_PWROK DB

4 Page46 1.25VM/1.05VM 3/9/2006 HP RL M_PWROK change PR293 pin1 to +3VL

5 Page46 1.25VM/1.05VM 4/10/2006 Compal Correct 1.25VM voltage setting Change PR144 to 12K and PR147 to 11K. DB1-A

6 Page45 VCCGFX 4/10/2006 Compal Power Sequence Add a 0ohm PR324 (no stuff) on PM_PWROK DB1-A
In S3 state, DFGT_VR_EN will no be actively driven,
7 Page45 VCCGFX 4/24/2006 Compal it is better to have a pull down resistor on DFGT_VR_EN. Add a 30Kohm PR325 DB1-A
C C

8 Page42 1.8V/0.9V 5/15/2006 HP MJ Power Sequence Change 1.5S to 1.8V in page 42 at pin 23 (VLDOIN) DB1-B

9 Page46 1.25VM/1.05VM 5/15/2006 HP MJ Power Good Add PU34 DB2

10 Page38 Charge 5/15/2006 compal For reducing charge temperture. Change PL5 from 8.2uh MPL73-8R2 to 10UH_PCMB104T-100 DB2
Change PR28 from 0.015_2512 to 0.015_1206
investigate that SLP_S3# connect VR_ON
11 Page43 CPU_CORE 6/5/2006 HP MJ Power Sequence DB2
and PM_POK connect PGD_IN
12 Page41 VCCP&1.5VS 6/5/2006 compal Swap +1.05V_VCCP and +1.5VS location Change PR107 from 100k to 10K,PR111 from 10K to 100K. DB2
for improving power plane.
P38 : remove PR52, PR38, PR41,PR53, PQ9
13 Page37,38,44 6/22/2006 HP MJ Chimay support for new battery cell chemistries P39 :remove PR262, PR263, PR264, PR76, PQ75, PQ76, PQ32 DB2
P37: Add PQ81~PQ91 PR329~PR341,PD32~PD36
P38 :Add PD37
P44 :Add PQ92,PD38,PD39
B B

14 Page41 2.5VALW/1.5VS 8/17/2006 HP MJ For sequence fine tune Add PC181 but not be installed SI
/1.05VCCP

15 Page43 CPU_CORE 8/17/2006 HP RL Add 68ohm pull up to +VCCP at PU19.4 Add PR345 as 68ohm between +VCCP and PU19.4 SI
per Intel DG1.0 sec. 4.4.1.3 Figure 50

Change PR223 from 180K to 182K,

16 Page44 ADP_OCP 11/08/2006 HP RL Identify 65W adapter as full adapter PR258 from 29.4K to 22.6K SI2

17 Page43 CPU_CORE 11/08/2006 compal For EMI concern, add snabber Add PR349 and PR347 as 4.7ohm, SI2
Add PC183 and PC182 as 680pF
Change boost resistor (PR148 and PR157)from 0 to 2 ohm

18 Page38 Charge 11/08/2006 compal Base on "Energy STAR" spec, reduce S5 and S3 Uninstall PQ11 SI2
power consumption (AC mode)

19 Page42 1.8V/0.9V 11/13/2006 HP Add PM_SLP_M# sequence Add PR387 SI2

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
PWR PIR Sheet (1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 47 of 55
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) for Power Circuit (2)

Request
Reque st
Item
It em Page# T itle D ate Issue
Is sue Description Solution
So lution Description R ev.
O wner
D No install PC122 D
20 Page43 CPU_CORE 2/28/2007 Compal Fine tune CPU CORE solution Change PR185 from 3K to 1.96K MV
Change PR190 from 6.19K to 6.34K

21 Page44 ADP_OCP 2/28/2007 HP System identity Change PR223 from 182K to 137K MV
Change PR258 from 22.6K to 29.4K

22 Page38 Charger 3/1/2007 Compal Reserve circuit for testing Energy STAR Reserve PR397, PR398, PR399 and PQ131 MV
Add PR396 as 0 ohm.

C C

B B

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
PWR PIR Sheet (1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 48 of 55
5 4 3 2 1
 5 4 3 2 1

I tem Fixed Iss ue Rea son for change PA GE Mod ify List M. B. V er.
For DB1-B
<2006.03.29> 1 Reserve resisters on Debug ports 30 Add R170, R201, R202 and CLRP3 jopen 0.2

2
SATA footprint is wrong SATA connector's PCB footprint is wrong 22 change to OCTEK_SAT-22DD1G_22P 0.2

D D
<2006.04.10> 1 follow Intel suggestion for XDP_DBRESET# 4, 20 R243 no install and R1589 install (XDP_DBRESET#) 0.2

2 0.2
Change component' s footprint for supply and layout easy 07 R1443 change from 0603 size to 0402

3 10 R1465 install and R1467 no install 0.2

+VCC_PEG should be 1.05V instead of 1.25V for Creatline

Add Q118, Q119, Q120, Q121, Q122, Q123, R1700, R1701, R1702
0.2
4 Monitor NB cracked pins 11 R1703, R1704, R1705, R1706, R1707, R1708, R1709, R1710, R1711

Add Q124, Q125, Q126, Q127, R1716, R1712, R1713, R1717

5 Monitor SB cracked pins 21 0.2
R1718, R1714, R1719, R1715

Delete Q102, R178 and Q115

0.2
6 SPI BIOS can not flash. For SPI BIOS flash issue 23 Q102 pin1 short to pin3-->+3VM connect to +3VM_LAN
PLT_RST# connect to PM_LAN_EN
C C

<2006.04.21> For LAN link status 18 change PCI_PIRQG to LED_LINK_LAN# and add R1727 0 ohm 0.2
1

For LAN active status 23 Add LED_ACT_LAN# this net

2 0.2

For ADP_PRES new design 20 add D68 and disconnect LED_LINK_LAN#

3 0.2

4 For LAN net name change net name from LAN_RST to LAN_RSTSYNC
19 change net name from LANLINK_STATUS# to LED_LINK_LAN#
0.2

5
For Compal Fan design 4 change Fan connector pin 1 and pin4 0.2

<2006.04.24> For NIC RST 20 change net name from PM_LAN_EN to LAN_RST#
1
35 Add a Resister R1722( 0 ohm), R1732, R1731(no install)
B
0.2 B
change net name from PGD_IN to LAN_RST#
Install C991, C990, C992, D60, R1350

For DB1-C Adjust C990 and R1350 value to 0.1uF and 100K ohm.

<2006.05.15> System can not power on For RTC CLK 19 add R1733 0.3
1

23 modify LAN relative schematics 0.3

2 LAN can not work For LAN function

3 For PWR OK 35 Change R124 pin2's voltage from 0.9v to 1.24VREF

0.3
Change R1732 pin2's voltage from 3VM to 3VM_LAN

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P UMA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 49 of 55
5 4 3 2 1
 5 4 3 2 1

I tem Fixed Iss ue Rea son for change PA GE Mod ify List M. B. V er.
For DB2
<2006.05.29> 1 Add new feature (Kill switch) 22 Add R1736, jp53, R1737 and Q129 0.4

2 11 delete R1700, R1707, R1705-->NB

modify CRACK_GPIO28 circuits 0.4
21 delete R1712, R1713, R1714-->SB
D D

3 Change pull up for CK505 strapping 15 on R1108, R1690, R1245 from +3.3VM_CK505 to +3VS 0.4

4
for LAN IVRI thermal protect and limit current. 23 add R1 0.4

5 20 addR3, R6, R9, R11, R15 0.4

Add resisters for GPI pins floating

6
Change KBC RST pin 31 change from PLT_RST# to NCPI_RST# 0.4

7 Change to USB port assignments 28 Move Dock1 from USB8 to USB7 and move WWAN from USB3 to USB8 0.4

Updated Changes:
<2006.06.12> PCIe - port1 = Free
1 New PCIE assignments PCIe - port2 = WLAN
PCIe - port3 = Free
20 PCIe - port4 = Robson
C C
PCIe - port5 = Docking
PCIe - port6 = Intel LOM is fixed at this location

2 Change SW design to Capsense SW. 32 Change SW Connector JP18 type and relative circuits

3 Add new feature (Robson) 15 Add R5, R13 on SRC6 and R14, R17 on CLKREQ_E#

Change GPIO pins 18 change GPIO4(SB) from LED_LINK_LAN# to PCI_PIRQG#

4
20 change GPIO1(SB) from CB_PE# to LANLINK_STATUS#(i)

5 Change HP debug port power source 30 Add R1740, R1741 and connect to +3vs

CRACK_GPIO28 from GPIO28(KBC) to GPIO8(KBC)

Change KBC 1070 GPIO pins 31
6 add R155, R156, R18, R20 and their signals connect to JP18
Add Cap_INT on GPIO25(KBC)

B
7 change WALN power source 25 change from +3valw to +3vM B

8 Change U75 power source for LAN function 23 U75 should be powered by V3.3M instead of 1.8VM

9
From S5 to S4_STATE# to control USB power
Change USB power switch control pin 28

10 For support 2GB DIMMs 7 BJ29 pin and BE24 pin (NB)connect to DDR DIMMA, B(A14 pin)
13, 14

11 For Crestline sightings requires 7 add a 0ohm R1759 on pin N20(NB).

Modify PWROK circuits for All power source check 35 Change R1732 pin2's voltage from 3VM to 3VM_LAN

<2006.06.14>
A 1 A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P UMA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 50 of 55
5 4 3 2 1
 5 4 3 2 1

I tem Fixed Iss ue Rea son for change PA GE Mod ify List M. B. V er.
For DB2
<2006.06.19> 1 Add Intel RSMRST circuit 31 Add R1749, R1750, R1751 and Q131, D68 0.4

2 25
Change resister value meet G-vendor suggestion change R1359, R1362 VALUE 0.4

D D

3 Kill switch design change 22 change R1736 pin2 contact to +RTCVCC 0.4

<2006.06.20> 1 Change PWR_OK circuit 35 delete R157 and PGD_IN net 0.4

32 Reserve R1753 0 ohm 0.4

2 Reserve resister on HDA _RST#_MDC

3 delete two components on Debug part 21 30 delete R1740, R1741 0.4

4 Control Audio volume when boot 28 add EAPD link to KBC GPIO31 0.4

5 Add new feature -->Robson 25 Add and change JP13 pin assignment for Robson

6 Fix LAN power circuit to IVRD 23 Delete R1 (0.68ohm), R1624, and install R1734
C C
7 improve LAN Power ripple 23 Add C1364, C1363 on +3V_LAN and +1.8VM_LAN

8 improve DVI issue 16 Add SDVO_CLK/Data net name to NB SDVO_CLK/ Data pins

<2006.06.21> 1 Change USB control signal 28 Change control signal name to S4_STATE and add Q132

2 Isolate power noise for NB 10 change R1453, R1456 from Resister to bead

<2006.06.22> 1 Hold RESET to modem 32 Install R1753

2 Enable WLAN for AMT 25 Install R194, R195 and R197

3 Improve TV-out signals and fix TV garbage issue 10 change R175, R176, R177 from150 ohm to 75 ohm

4 follow Intel Demo circuit for XDP 28 Change pull up R1589 value for XDP_DBRESET# from 10K to 1K

<2006.06.23> 1 Chnage Fan Connector pins' count 4 Chnage JP8 from 4pins to 3 pins.

2 delete MDC disable reserve part 32 delete U43B

B B

3 Implement STB_LED# driver 31 add U43B

4 Modify power OK circuit 35 add Q134, Q133, R39, C2

Delete R286, R127, C30, R117, R35, R34, R118, U79

For Non-link part (INV_PWM from KBC to LCD) 17 delete R131

5

6 Delete Repeated function circuit 11 Delete D21,R520

<2006.07.18> 1 For C-status 20 Install R179 0.5

2 For discharge issue 34 Change discharge circuit net from PM_SLP_M# to LAN_WOL_EN# 0.5

3 HP request 31 Install R155,R156 and un-install R127,R157 0.5

<2006.07.31> 1 Do not support wake on WWAN card 25 Install R1383 and no install R1382 0.5

A
<2006.08.09> 1 Add anti-pop circuit 26 Add anti-pop circuit 0.5 A

2 Eliminate glitch 20 Add R1767, no install R434, C1365, R1757 0.5

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3261P UMA 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 51 of 55
5 4 3 2 1
 5 4 3 2 1

I tem Fixed Iss ue Rea son for change PA GE Mod ify List M. B. V er.

HP request 32 Connect JP18 pin1 to +3VL, pin2 to +3VS 0.5

3

4 EMI request 24 Add D72 and D73 for EMI request 0.5

D D

5 Add MAX9511 9,16,33 Add MAX9511 0.5

<2006.08.11> 1 For OTS 214499 31 Add U82 0.5

2 HP request 25 No install R1418,R1358,R1359,R1360 0.5

JP44 PIN37,43 connected to GND

3 HP request 25 JP44 PIN39,41 connected to +3VS 0.5

4 HP request 25 Isolate SLOT power from SYSTEM power. 0.5

5 HP request 25 Remove 1.5V from WWAN slot 0.5

C 6 HP request 25 Install schottkey diode D74 0.5 C

7 SIM I/O pull-up footprint is requested. 25 Add R1780 and no install 0.5

<2006.08.21> 1 HP request 25 change +3VS to +3VS_WLAN ,Change +3VS on R1383.2 to +3VS_WWAN 0.5
Change +3VS on R1071.1 and R1703.1 to +3VS_WWAN

2 HP request 9 Changes for MAX9511 0.5

3 HP request 25 Remove SW1,C986,R521,D65,R200 0.5

4 HP request 30 Need to connect SPI_HOLD#_0 and SPI_HOLD#_1 together. 0.5

5 HP request 31 Item 191,192,193 0.5

B B

6 HP request 25 Install R1363 and NO INSTALL R1364 0.5

<2006.08.23> 1 HP request 19 Move D75 to SB and delete R1782 0.5

2 HP request 25 Add 1394 signals on M/B 0.5

<2006.08.25> 1 HP request 25 Add a 0 ohm 0805 on 1.5VS to WLAN mini card connector 0.5

2 20 Swap GPIO01 and GPIO11 connections. 0.5

<2006.08.29> 1 OTS issue 32 Change JP18 pin8 to WL_BLUE_LED# 0.5

A A
<2006.08.30> 1 16 Change R142, R144 to 3.9K ohm 0.5

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3261P_UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 52 of 55
5 4 3 2 1
 5 4 3 2 1

I tem Fixed Iss ue Rea son for change PA GE Mod ify List M. B. V er.

Intel update 7 Add R1786,R1787,R1788,R1789 0.5

3

<2006.09.01> Remove R23 and NPCI_RST# connection

1 HP request 32 0.5
Remove PLT_RST# connection to R21.2 and connect GPIO28 from ICH8
D D
<2006.09.04> 1 EMI request 28 Add R1790,R1791,R1792 0.5

<2006.09.06> 1 HP request 23 Change C1257 and C1359 to 10uF 0805 0.5

2 HP request 25 Remove R1412,1413,1414,1415,1416,1417 0.5

3 HP request 25 Remove R1418,1358,1353,1360 0.5

4 HP request 30 Add 0 ohm for SPI, R1793,1794,1795 0.5

<2006.10.13> 1 HP request (MAX9511 issue) 9,16,33 Remove MAX9511 from CRT circuit 0.6

C 2 11,21,31 No install BGA crack circuit 0.6 C

3 32 Change KB connector 0.6

<2006.10.31> 1 31 Change RSMRST circuit, add R1796 0.6

<2006.11.01> 1 Auto power on issue 20 Auto power on issue(add Q140, R1797) 0.6

2 1394 issue 28 Modify EMI request 0.6

<2006.11.03> 1 HP request 32 Connect JP32 pin2 to +3VS 0.6

<2006.11.07> 1 HP request 31 Install R1784, no install R1783 0.6

B B

2 Intel document 10 Change R1471 to 100 ohm 0.6

<2006.11.09> 1 Layout space 22 Remove kensinton circuit 0.6

<2006.11.11> 1 HP request 15 Add CLRP4 and CLRP5 for FSB 667/800 select 0.6

<2006.11.13> 1 HP request 35 Tie R1732.2 to 3VM instead of 3VM_LAN 0.6

2 HP request 24 Change R1639 to 1.4K based on Intel WW44 0.6

3 HP request 4 Add resistors in series with the diode signals going to ADM1032. 0.6

A A
4 HP request 31 Eliminate glitch circuit, install R1483 and no install R1484 0.6

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3261P_UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 53 of 55
5 4 3 2 1
 5 4 3 2 1

I tem Fixed Iss ue Rea son for change PA GE Mod ify List M. B. V er.

<2006.11.16> 1 HP request
10 Change R1468, R1472, R1473 to bead 0.6

2 HP request 24 Change R1639 to 1.87K ohm 0.6

D D

3 HP request 27 Change R261 and R253 to 56.2 ohms 1%. 0.6

<2006.11.28> 1 HP request 23 Install Q102,R1730, no install R1612,Q104,Q105. 0.6

2 HP request 7 Install R1739 0.6

<2006.12.19> 1 HP request 35 Add Schmitt Trigger to eliminate glitch 0.7

2 HP request 31 Install R1646,C75 0.7

3 HP request 19 Update GPIO33 circuit 0.7

C
<2006.12.26> 1 HP request 7 Add C and no install 0.7 C

2 Chrontel request 16 Add C for DVI I2C 0.7

<2007.01.02> 1 ME request 25 Change JP50 for rewrok 0.7

<2007.01.04> 1 Intel request 23 Add R1804 0.7

2 ME request 32 Change JP20 to FFC connector 0.7

<2007.01.08> 1 EMI request 33 Add R1805,R1806 0 ohm, reserve C1372, C1373 0.7

<2007.01.10> 1 HP request 31 R1783 connected to +3VL 0.7

B B

<2007.01.13> 1 Compal request 35 Change LMV331 to LM393, delete R124 and C27 0.7

<2007.01.15> R370, R369 - change from 4.7k to 6.04k

1 HP request 26 R374, R375 - change from 4.7k to 2.00k 0.7

<2007.01.16> 1 HP request 25 Connected R1780.2 to UIM_PWR 0.7

<2007.01.17> 1 HP request 30 Add pad for BIOS debug 0.7

<2007.01.19> 1 HP request 34 Add R1807 and no stuff 0.7

2 CRT wavy issue 10 Add C1374 for CRT wavy issue 0.7

A <2007.02.09> 1 CRT wavy issue 17 Add 10uFX2 for CRT wavy issue(C586, C1376) 0.9 A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3261P_UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 54 of 55
5 4 3 2 1
 5 4 3 2 1

I tem Fixed Iss ue Rea son for change PA GE Mod ify List M. B. V er.

<2007.02.09> 2 HP request
30 Add Q142 for FPR 0.9

D D
<2007.02.16> 1 +3VM_LAN leakage 20 Add U83 for auto boot and leakage issue 0.9

2 Compal request 15 Delete CLPR4, CLRP5 0.9

3 HP request 34 Install R1807 and non install R630 0.9

4 LVDS sequence issue 17 Change C28 to 0.1uF 0.9

5 HP request 31 Add R1809 to GND 0.9

<2007.02.26> 1 Safety request 33 Change RJ11 connector 0.9

C
<2007.02.27> 1 HP request 27 Change R261 and R253 to 60.4 ohm 0.9 C

2 HP request 35 Move R1803 0.9

<2007.02.28> 1 HP request 11,21 Change to +3VL 0.9

<2007.03.01> 1 HP request 10 CRT wavy issue -- add C1374 0.9

2 HP request 15 Add CAP for WWAN issue 0.9

B B

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2005/04/06 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3261P_UMA 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 27, 2007 Sheet 55 of 55
5 4 3 2 1