Quick Guide www.support.model.com ModelSim 6.

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ModelSim 6.4 SUPPORT Quick Guide

Key Commands applies stimulus to VHDL signals and Verilog nets

history
deletes a design unit from a specified library
vdir
add memory lists the commands executed during the current session lists the contents of a design library
opens the specified memory in the MDI frame of the Main window next verror
add testbrowser continues a search; see the search command prints a detailed description of a message number
adds .ucdb files to the Test Management Browser noforce vgencomp
add watch removes the effect of any active force commands on the selected object writes a Verilog module’s equivalent VHDL component declaration to
adds signals or variables to the Watch window notepad standard output
add wave opens a simple text editor view
adds VHDL signals and variables, and Verilog nets and registers to the printenv opens a QuestaSim window and brings it to the front of the display
Wave window echoes to the Main window the current names and values of all environment vlib
alias variables creates a design library
creates a new Tcl procedure that evaluates the specified commands profile on vlog
change enables runtime profiling of where your simulation is spending its time and compiles Verilog design units and SystemVerilog extensions
modifies the value of a VHDL variable or Verilog register variable where memory is allocated vmake
checkpoint property list creates a makefile that can be used to reconstruct the specified library
saves the state of your simulation changes one or more properties of the specified signal, net, or register in the vmap
compare add List Window defines a mapping between a logical library name and a directory
compares signals in a reference design against signals in a test design property wave vopt
configure changes one or more properties of the specified signal, net, or register in the produces an optimized version of your design
invokes the List or Wave widget configure command for the current Wave Window vsim
default List or Wave window pwd loads a new design into the simulator
displays the current directory path in the Main window when
COVERAGE ------ qverilog instructs QuestaSim to perform actions when the specified conditions are
compiles, optimizes, and simulates a Verilog or SystemVerilog design in met
coverage attribute one step where
displays attributes in the currently loaded database radix displays information about the system environment
coverage clear specifies the default radix to be used wlf2log
clears all coverage data obtained during previous run commands report translates a QuestaSim WLF file to a QuickSim II logfile
coverage diff displays the value of all simulator control variables, or the value of any wlf2vcd
reports the coverage differences between two test runs simulator state variables relevant to the current simulation translates a QuestaSim WLF file to a VCD file
coverage file restart wlfman
sets the name of the coverage data file to be automatically saved at the reloads the design elements and resets the simulation time to zero outputs information about or a new WLF file from an existing WLF file
end of simulation restore xml2ucdb
coverage goal restores the state of a simulation that was saved with a checkpoint creates an HTML report of code coverage from a .ucdb file
Sets the value of UCDB-wide goals command during the current invocation of vsim
coverage ranktest resume RED text = ModelSim SE only.
ranks coverage data according to user-specified tests resumes execution of a macro file after a pause command or a breakpoint
coverage report right
produces a textual output of the coverage statistics that have been searches right (next) for signal transitions or values in the specified Wave
gathered up to this point window
coverage summaryinfo run
prints coverage numbers of the specified coverage types without loading advances the simulation by the specified number of timesteps
the entire database sccom
coverage tag compiles SystemC design units
adds or removes tags from specified objects sdfcom
coverage testnames compiles SDF files
displays test names in the current UCDB file loaded search
searches the specified window for one or more objects matching
------ the specified pattern(s)
seetime
delete scrolls the List or Wave window to make the specified time visible
removes objects from either the List or Wave window ucdb2html
converts a .ucdb file into HTML
do vcd dumpports
executes commands contained in a macro file creates a VCD file that captures port driver data
drivers vcd2wlf
displays in the Main window the current value and scheduled future translates VCD files into WLF files
values for all the drivers of a specified VHDL signal or Verilog net vcom
dumplog64 compiles VHDL design units
dumps the contents of the vsim.wlf file in a readable format vcover attribute
echo displays attributes in the currently loaded database
displays a specified message in the Main window vcover merge
edit merges multiple code coverage data files offline
invokes the editor specified by the EDITOR environment variable vcover ranktest
environment ranks the specified input files according to their contribution to cumulative
displays or changes the current dataset and region environment coverage
examine vcover report
examines one or more objects, and displays current values (or the values reports on multiple code coverage data files offline
at a specified previous time) in the Main window vcover stats
find produces summary statistics from multiple coverage data files
displays the full pathnames of all objects in the design whose names vcover testnames
match the name specification you provide displays test names in the current UCDB file loaded
force vdel
 www.mentor.com/training_and_services www.model.com/products ModelSim 6.4
TRAINING PRODUCTS Quick Guide

Key Command Arguments 2. Optimized designs simulate faster, while non-optimized designs provide -coverage Enables statistics collection
object visibility for debugging.
Use <command> -help for a full list. Key Arguments to vopt
3. Use +acc with vopt or vsim -voptargs with +acc for selective design object
-cover bcefsx Specifies coverage type(s)
visibility during debugging.
-nocover Disable coverage on all source files
QVERILOG 4. Read “Optimizing Designs with vopt” in the User’s Manual for additional
information.
The qverilog command compiles, optimizes, and simulates Verilog and
SystemVerilog designs in a single step.
Quick Guide Wave Window
Key arguments to vopt
1. automatic work library creation -o <name> Optimized design name add wave <item> Wave specific signals/nets
2. support for all standard vlog arguments <design> Top-level design unit add wave * Wave signals/nets in scope
3. support for C/C++ files via the SystemVerilog DPI [+acc=[<spec>]+[<module>]] Enable design object visibility add wave -r /* Wave all signals/nets in design
4. implicit “run -all; quit” unless using -i, -gui, -do (see -R below) -cover bcefsx Specifies coverage type(s) add wave abus(31:15) Wave a slice of a bus
5. vopt performance invoked (see the vopt section of this guide) -nocover Disable coverage on all source files view wave Display wave window
Key arguments to qverilog
<filename> Verilog source code file to compile, one is
-g
-G Questa SV/AFV 6.3
Assigns a value to generics and parameters with no value
Forces value assignment for generics and parameters
view wave -new
write wave
Display additional wave window
Print wave window to file
required Key arguments to vsim <left mouse button> Select signal / Place cursor
[-R <sim_options>] vsim command options applied to simulation [-vopt] Run vopt if not automatically invoked <middle mouse button> Zoom options
[-voptargs=”<args>”] Arguments passed to vopt, use +acc args for <right mouse button> Context Menu
SCCOM design visibility <ctrl-f> Find next item
<tab> (go right) Search forward for next edge
-link Links source code, required modelsim.ini variable <shift-tab> (go left) Search backward for next edge
[CPP option] C++ compiler option VoptFlow = 1 Set vopt optimized flow as default i or + | o or - Zoom in | Zoom out
[-g] Compile with debugging info VoptFlow = 0 Set non-optimized flow as default f | l Zoom full | Zoom Last
-vv Echo subprocess invocations on stdout
[-scv] Includes SystemC verification library Key modelsim.ini variables
VSIM
<filename(s)> SystemC files to be compiled WLF* Waveform management variables
WLFCacheSize Change default or disable WLF file cache
[-c ] Run in cmd line mode
VCOM
[-coverage] Invoke Code Coverage RED text = ModelSim SE only.
[-2002] [-93] [-87] Choose VHDL 2002,1993, or 1987 [-do “cmd” | <file>] Run cmd or file at startup
[-check_synthesis] Turn on synthesis checker [-elab] Create elaboration file
[-debugVA] Print VITAL opt status [-f <filename>] Pass in args from file
[-explicit] Resolve ambiguous overloads [-g|G<name=value>] Set VHDL Generic values
[-help] Display vcom syntax help [-hazards] Enable hazard checking
[-f <filename>] Pass in arguments from file [-help] Display vsim syntax help
[-norangecheck] Disable run time range checks [-l <logfile>] Save transcript to log file
[-nodebug] Hide internal variables & structure [-load_elab] Simulate an elaboration file
[-novitalcheck] Disable VITAL95 checking [+notimingchecks] Disable timing checks
[-nowarn <#>] Disable individual warning msg [-quiet] Disable loading messages
[-quiet] Disable loading messages [-restore <filename>] Restore a simulation
[-refresh] Regenerate library image [-sdf{min|typ|max} <region>=<sdffile>] Apply SDF timing data e.g.,
[-version] Returns vcom version sdfmin /top=MySDF.txt
[-work <libname>] Specify work library [-sdfnowarn] Disable SDF warnings
<filename(s)> VHDL file(s) to be compiled [-t [<mult>]<unit>] Time resolution
[-vcdstim [<instance>=]<filename>] Stimulate the top-level design or
VLOG instances from an Extended VCD file
[-vlog95compat] Disable Verilog 2001 keywords [-version] Returns vsim version
[-compat] Disable event order optimizations [-vopt] Run vopt automatically
[-f <filename>] Pass in arguments from file [-novopt] Disables automatic vopt run
[-hazards] Enable run-time hazard checking [-voptargs=”<args>”] Arguments to pass to vopt
[-help] Display vlog syntax help [-view <filename>] Log file for VSIM to view
[-nodebug] Hide internal variables & structure [-wlf <filename>] Log file to create
[-quiet] Disable loading messages [<libname>.<design_unit> Configuration, Module, Entity/Arch, or
[-R <simargs>] Invoke VSIM after compile optimized design to simulate
[-refresh] Regenerate lib to current version [-wlfcachesize] Specify WLF reader cache size (per WLF file.)
[-sv] Enables SystemVerilog keywords [-wlfslim <size>] Specify the number of Megabytes to be saved in
[-version] Returns vlog version event log file
[-v <library_file>] Specify Verilog source library [-wlftlim <duration>] Specify the duration of time to be saved in
[-work <libname>] Specify work library event log file
<filename(s)> Verilog file(s) to be compiled 8005 SW Boeckman Road
Code Coverage Wilsonville, OR 97070
VOPT Phone: 503.685.0820
Key Arguments to vcom/vlog
Design optimization options -cover bcefsx Specifies coverage type(s) Toll free: 877.744.6699
1. The VoptFlow modelsim.ini variable (below) sets the default design Fax: 503.685.0910
Key Arguments to vsim
optimization on (1) or off (0). Copyright © 2008 Mentor Graphics Corporation 1026660