Serial Peripheral Interface

LPC2148 SoC
 Introduction
SPI is a full duplex serial interface.

It can handle multiple masters and slaves being connected to a given bus.

Only a single master and a single slave can communicate on the interface during a given
data transfer.

During a data transfer the master always sends 8 to 16 bits of data to the slave, and the
slave always sends a byte of data to the master.
Ring Buffer
SPI data to CPOL, CPHA relationship
SPI CPOL, CPHA Significance (AT93C46 EEPROM)

http://ww1.microchip.com/downloads/en/DeviceDoc/doc5140.pdf
The Read (READ) instruction contains the address code for the memory location to be read.
After the instruction and address are decoded, data from the selected memory location is
available at the serial output pin DO. Output data changes are synchronized with the rising
edges of serial clock SK.
SPI CPOL, CPHA Significance (W25Q64 FLASH)
READ instruction (03h) is initiated by driving the CS pin low and shifting out instruction (03h)
and 24-bit address (A23-A0) on DI pin.The instruction code and address bits are latched on the
rising edge of the CLK input. Data is shifted out on DO at falling edge of the CLK pin.
SPI0 Registers in LPC2148
 MASTER OPERATION
The following sequence describes how one should process a data transfer with the SPI block when it
is set up to be the master. This process assumes that any prior data transfer has already completed

1. Set the SPI clock counter register to the desired clock rate.
2. Set the SPI control register to the desired settings.
3. Write the data to transmitted to the SPI data register. This write starts the SPI data
transfer.
4. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set
after the last cycle of the SPI data transfer.
5. Read the SPI status register.
6. Read the received data from the SPI data register (optional).
7. Go to step 3 if more data is required to transmit.