Basics of UART Communication

From: Circuit Basics

UART stands for Universal Asynchronous Receiver/Transmitter. It’s not a

communication protocol like SPI and I2C, but a physical circuit in a
microcontroller, or a stand-alone IC. A UART’s main purpose is to transmit
and receive serial data.

Introduction to UART Communication

In UART communication, two UARTs communicate directly with each other.

The transmitting UART converts parallel data from a controlling device like a
CPU into serial form, transmits it in serial to the receiving UART, which then
converts the serial data back into parallel data for the receiving device. Only
two wires are needed to transmit data between two UARTs. Data flows
from the Tx pin of the transmitting UART to the Rx pin of the receiving UART:

UARTs transmit data asynchronously, which means there is no clock signal to

synchronize the output of bits from the transmitting UART to the sampling of
bits by the receiving UART. Instead of a clock signal, the transmitting UART
adds start and stop bits to the data packet being transferred. These bits define
the beginning and end of the data packet so the receiving UART knows when
to start reading the bits.
When the receiving UART detects a start bit, it starts to read the incoming
bits at a specific frequency known as the baud rate. Baud rate is a measure of
the speed of data transfer, expressed in bits per second (bps). Both UARTs
must operate at about the same baud rate. The baud rate between the
transmitting and receiving UARTs can only differ by about 10% before the
timing of bits gets too far off.

Both UARTs must also must be configured to transmit and receive the same
data packet structure.

How UART Works

The UART that is going to transmit data receives the data from a data bus.
The data bus is used to send data to the UART by another device like a CPU,
memory, or microcontroller. Data is transferred from the data bus to the
transmitting UART in parallel form. After the transmitting UART gets
the parallel data from the data bus, it adds a start bit, a parity bit, and a stop
bit, creating the data packet. Next, the data packet is output serially, bit by bit
at the Tx pin. The receiving UART reads the data packet bit by bit at its Rx
pin. The receiving UART then converts the data back into parallel
  form and
removes the start bit, parity bit, and stop bits. Finally, the receiving
  UART
transfers the data packet in parallel to the data bus on the receiving end:
 
 

   
 
   
UART transmitted data is organized into packets. Each packet contains 1 start
bit, 5 to 9 data bits (depending on the UART), an optional parity bit, and 1 or 2
stop bits:

Start Bit

The UART data transmission line is normally held at a high voltage level when
it’s not transmitting data. To start the transfer of data, the transmitting UART
pulls the transmission line from high to low for one clock cycle. When the
receiving UART detects the high to low voltage transition, it begins reading the
bits in the data frame at the frequency of the baud rate.

Data Frame

The data frame contains the actual data being transferred. It can be 5 bits up
to 8 bits long if a parity bit is used. If no parity bit is used, the data frame can
be 9 bits long. In most cases, the data is sent with the least significant bit first.

Parity

Parity describes the evenness or oddness of a number. The parity bit is a way
for the receiving UART to tell if any data has changed during transmission.
Bits can be changed by electromagnetic radiation, mismatched baud rates, or
long distance data transfers. After the receiving UART reads the data frame, it
counts the number of bits with a value of 1 and checks if the total is an even
or odd number. If the parity bit is a 0 (even parity), the 1 bits in the data frame
should total to an even number. If the parity bit is a 1 (odd parity), the 1 bits in
the data frame should total to an odd number. When the parity bit matches the
data, the UART knows that the transmission was free of errors. But if the
parity bit is a 0, and the total is odd; or the parity bit is a 1, and the total is
even, the UART knows that bits in the data frame have changed.

Stop Bits

To signal the end of the data packet, the sending UART drives the data
transmission line from a low voltage to a high voltage for at least two bit
durations.

Steps of UART Transmission

1. The transmitting UART receives data in parallel from the data bus:

2. The transmitting UART adds the start bit, parity bit, and the stop bit(s) to the
data frame:
3. The entire packet is sent serially from the transmitting UART to the
receiving UART. The receiving UART samples the data line at the pre-
configured baud rate:

4.  The receiving UART discards the start bit, parity bit, and stop bit from the
data frame:

5. The receiving UART converts the serial data back into parallel and transfers
it to the data bus on the receiving end:
Advantages and Disadvantages of UARTs

No communication protocol is perfect, but UARTs are pretty good at what they
do. Here are some pros and cons to help you decide whether or not they fit
the needs of your project:

Advantages

Only uses two wires

No clock signal is necessary

Has a parity bit to allow for error checking

The structure of the data packet can be changed as long as both sides are set
up for it

Well documented and widely used method

Disadvantages

The size of the data frame is limited to a maximum of 9 bits

Doesn’t support multiple slave or multiple master systems

The baud rates of each UART must be within 10% of each  other

   
 
Introduction to SPI Interface
By Piyu Dhaker

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Serial peripheral interface (SPI) is one of the most widely used interfaces
between microcontroller and peripheral ICs such as sensors, ADCs, DACs,
shift registers, SRAM, and others. This article provides a brief description
of the SPI interface followed by an introduction to Analog Devices’ SPI
enabled switches and muxes, and how they help reduce the number of
digital GPIOs in system board design.
SPI is a synchronous, full duplex master-slave-based interface. The data
from the master or the slave is synchronized on the rising or falling clock
edge. Both master and slave can transmit data at the same time. The SPI
interface can be either 3-wire or 4-wire. This article focuses on the popular
4-wire SPI interface.
Interface
Data Transmission
To begin SPI communication, the master must send the clock signal and
select the slave by enabling the CS signal. Usually chip select is an active
low signal; hence, the master must send a logic 0 on this signal to select
the slave. SPI is a full-duplex interface; both master and slave can send
data at the same time via the MOSI and MISO lines respectively. During SPI
communication, the data is simultaneously transmitted (shifted out serially
onto the MOSI/SDO bus) and received (the data on the bus (MISO/SDI) is
sampled or read in). The serial clock edge synchronizes the shifting and
sampling of the data. The SPI interface provides the user with flexibility to
select the rising or falling edge of the clock to sample and/or shift the data.
Please refer to the device data sheet to determine the number of data bits
transmitted using the SPI interface.

SPI CS CS SPI Clock Polarity and Clock Phase

Master Slave In SPI, the master can select the clock polarity and clock phase. The CPOL
SCLK SCLK
bit sets the polarity of the clock signal during the idle state. The idle state is
MOSI SDI defined as the period when CS is high and transitioning to low at the start
MISO SDO
of the transmission and when CS is low and transitioning to high at the
end of the transmission. The CPHA bit selects the clock phase. Depending
on the CPHA bit, the rising or falling clock edge is used to sample and/or
Figure 1. SPI configuration with master and a slave.
shift the data. The master must select the clock polarity and clock phase,
4-wire SPI devices have four signals: as per the requirement of the slave. Depending on the CPOL and CPHA bit
selection, four SPI modes are available. Table 1 shows the four SPI modes.
XX Clock (SPI CLK, SCLK)
XX Chip select (CS) Table 1. SPI Modes with CPOL and CPHA
XX Master out, slave in (MOSI) Clock
SPI CPHA Clock Phase Used to Sample
CPOL Polarity in
XX Master in, slave out (MISO) Mode
Idle State
and/or Shift the Data

The device that generates the clock signal is called the master. Data Data sampled on rising edge and
0 0 0 Logic low
transmitted between the master and the slave is synchronized to the shifted out on the falling edge
clock generated by the master. SPI devices support much higher clock Data sampled on the falling edge
frequencies compared to I2C interfaces. Users should consult the product 1 0 1 Logic low
and shifted out on the rising edge
data sheet for the clock frequency specification of the SPI interface. Data sampled on the falling edge
2 1 1 Logic high
and shifted out on the rising edge
SPI interfaces can have only one master and can have one or multiple slaves.
Figure 1 shows the SPI connection between the master and the slave. 0 Data sampled on the rising edge
3 1 Logic high
and shifted out on the falling edge
The chip select signal from the master is used to select the slave. This is
normally an active low signal and is pulled high to disconnect the slave Figure 2 through Figure 5 show an example of communication in four SPI
from the SPI bus. When multiple slaves are used, an individual chip select modes. In these examples, the data is shown on the MOSI and MISO line.
signal for each slave is required from the master. In this article, the chip The start and end of transmission is indicated by the dotted green line, the
select signal is always an active low signal. sampling edge is indicated in orange, and the shifting edge is indicated
in blue. Please note these figures are for illustration purpose only. For
MOSI and MISO are the data lines. MOSI transmits data from the master to successful SPI communications, users must refer to the product data
the slave and MISO transmits data from the slave to the master. sheet and ensure that the timing specifications for the part are met.

Analog Dialogue 52-09, September 2018 analogdialogue.com 1

 nCS

CLK

MOSI
xxxx 1 0 1 0 0 1 0 1 xxxx
0xA5

MISO
Hi-Z 1 0 1 1 1 0 1 0 Hi-Z
0xBA

Figure 2. SPI Mode 0, CPOL = 0, CPHA = 0: CLK idle state = low, data sampled on rising edge and shifted on falling edge.

nCS

CLK

MOSI xxxx 1 0 1 0 0 1 0 1 xxxx

MISO Hi-Z Hi-Z

1 0 1 1 1 0 1 0

Figure 3. SPI Mode 1, CPOL = 0, CPHA = 1: CLK idle state = low, data sampled on the falling edge and shifted on the rising edge.

nCS

CLK

MOSI xxxx xxxx

0xA5 1 0 1 0 0 1 0 1

MISO
Hi-Z Hi-Z
0xBA 1 0 1 1 1 0 1 0

Figure 4. SPI Mode 2, CPOL = 1, CPHA = 1: CLK idle state = high, data sampled on the falling edge and shifted on the rising edge.

nCS

CLK

MOSI
xxxx xxxx
0xA5 1 0 1 0 0 1 0 1

MISO
Hi-Z Hi-Z
0xBA 1 0 1 1 1 0 1 0

Figure 5. SPI Mode 3, CPOL = 1, CPHA = 0: CLK idle state = high, data sampled on the rising edge and shifted on the falling edge.

Figure 3 shows the timing diagram for SPI Mode 1. In this mode, clock polar-
ity is 0, which indicates that the idle state of the clock signal is low. The clock
phase in this mode is 1, which indicates that the data is sampled on the
falling edge (shown by the orange dotted line) and the data is shifted on the
rising edge (shown by the dotted blue line) of the clock signal.
Figure 5 shows the timing diagram for SPI Mode 3. In this mode, the clock
polarity is 1, which indicates that the idle state of the clock signal is high.
The clock phase in this mode is 0, which indicates that the data is sampled
on the rising edge (shown by the orange dotted line) and the data is shifted
on the falling edge (shown by the dotted blue line) of the clock signal.

Figure 4 shows the timing diagram for SPI Mode 2. In this mode, the clock Multislave Configuration
polarity is 1, which indicates that the idle state of the clock signal is high. The
clock phase in this mode is 1, which indicates that the data is sampled on Multiple slaves can be used with a single SPI master. The slaves can be
the falling edge (shown by the orange dotted line) and the data is shifted on connected in regular mode or daisy-chain mode.
the rising edge (shown by the dotted blue line) of the clock signal.

2 Analog Dialogue 52-09, September 2018

 SPI CS3
Master CS2

CS1 CS CS CS

SCLK SPI SCLK SPI SCLK SPI

Slave Slave Slave
SDI SDI SDI
SDO SDO SDO
ADGS1412 ADGS1412 ADGS1412

SCLK
MOSI
MISO

Figure 6. Multislave SPI configuration.

Regular SPI Mode:
In regular mode, an individual chip select for each slave is required from
the master. Once the chip select signal is enabled (pulled low) by the
master, the clock and data on the MOSI/MISO lines are available for the
selected slave. If multiple chip select signals are enabled, the data on the
MISO line is corrupted, as there is no way for the master to identify which
slave is transmitting the data.
As can be seen from Figure 6, as the number of slaves increases, the
number of chip select lines from the master increases. This can quickly
add to the number of inputs and outputs needed from the master and limit
the number of slaves that can be used. There are different techniques
that can be used to increase the number of slaves in regular mode; for
example, using a mux to generate a chip select signal.
In daisy-chain mode, the slaves are configured such that the chip select
signal for all slaves is tied together and data propagates from one slave to
the next. In this configuration, all slaves receive the same SPI clock at the
same time. The data from the master is directly connected to the first slave
and that slave provides data to the next slave and so on.
In this method, as data is propagated from one slave to the next, the
number of clock cycles required to transmit data is proportional to the
slave position in the daisy chain. For example, in Figure 7, in an 8-bit
system, 24 clock pulses are required for the data to be available on the 3rd
slave, compared to only eight clock pulses in regular SPI mode. Figure 8
shows the clock cycles and data propagating through the daisy chain.
Daisy-chain mode is not necessarily supported by all SPI devices. Please
refer to the product data sheet to confirm if daisy chain is available.

Daisy-Chain Method: CLK

Eight Eight Eight
Clocks Clocks Clocks
SPI
CS CS SPI
Master
Slave SDIN1 0xA5 0x5A 0x0A
SCLK SCLK

MOSI SDI

MISO SDOUT1
SDO X 0xA5 0x5A
SDIN2

SDOUT2
SDI X X 0xA5
SDIN3
CS
SPI
SCLK Slave
Figure 8. Daisy-chain configuration: data propagation.
SDO
Analog Devices SPI Enabled Switches and Muxes
The newest generation of ADI SPI enabled switches offer significant space
saving without compromise to the precision switch performance. This
section of the article discusses a case study of how SPI enabled switches
SDI
or muxes can significantly simplify the system-level design and reduce the
CS
SPI
number of GPIOs required.
SCLK Slave
The ADG1412 is a quad, single-pole, single-throw (SPST) switch, which
SDO requires four GPIOs connected to the control input of each switch. Figure 9
shows the connection between the microcontroller and one ADG1412.
Figure 7. Multislave SPI daisy-chain configuration.

Analog Dialogue 52-09, September 2018 3

 configuration, four ADG1412s are used. This system would require 16 GPIOs,
Micro- limiting the available GPIOs in a standard microcontroller. Figure 10 shows
controller
the connection of four ADG1412s using the 16 GPIOs of the microcontroller.

One approach to reduce the number of GPIOs is to use a serial-to-parallel

converter, as shown in Figure 11. This device outputs parallel signals
GPIOs that can be connected to the switch control inputs and the device can
SPI Master be configured by serial interface SPI. The drawback of this method is an
increase in the bill of material by introducing an additional component.

An alternative method is to use SPI controlled switches. This method

ADG1412 provides the benefit of reducing the number of GPIOs required and also
Inputs Outputs
eliminates the overhead of additional serial-to-parallel converter. As shown
SPI in Figure 12, instead of 16 microcontroller GPIOS, only seven microcontroller
Slave GPIOs are needed to provide the SPI signals to the four ADGS1412s.
Figure 9. Microcontroller GPIO as control signals for the switch.
The switches can be configured in daisy-chain configuration to further
As the number of switches on the board increases, the number of required optimize the GPIO count. In daisy-chain configuration, irrespective of the
GPIOs increases significantly. For example, when designing a test instru- number of switches used in the system, only four GPIOs are used from
mentation system and a large number of switches are used to increase the master (microcontroller).
the number of channels in the system. In a 4 × 4 cross-point matrix

Micro-
controller
GPIOs

SPI Master

ADG1412 ADG1412 ADG1412 ADG1412

SPI SPI SPI SPI

Slave Slave Slave Slave

Figure 10. In a multislave configuration, the number of GPIOs needed increases tremendously.

Micro-
controller

CS Serial to
CLK Parallel
MOSI Converter
MISO

SPI Master

ADG1412 ADG1412 ADG1412 ADG1412

SPI SPI SPI SPI

Slave Slave Slave Slave

Figure 11. Multislave switches using a serial-to-parallel converter.

4 Analog Dialogue 52-09, September 2018

 CS4
SPI CS3
Master CS2

CS CS CS
CS1 CS

SCLK SPI SCLK SPI SCLK SPI SCLK SPI

Slave Slave Slave Slave
SDI SDI SDI SDI
Microcontroller
SDO SDO SDO SDO
ADGS1412 ADGS1412 ADGS1412 ADGS1412

SCLK

MOSI
MISO

Figure 12. SPI enabled switches save up microcontroller GPIOs.

Figure 13 is for illustration purposes. The ADGS1412 data sheet recom-

SPI
CS CS SPI mends a pull-up resistor on the SDO pin. Please refer to the ADGS1412
Master
Slave data sheet for further details on daisy-chain mode. For the sake of sim-
SCLK SCLK
plicity, four switches have been used in this example. As the number of
MOSI SDI
ADGS1412
switches increase in a system, the benefits of board simplicity and space
MISO SDO saving is significant. The ADI SPI enabled switches provide a 20% overall
Microcontroller board space reduction in a 4 × 8 crosspoint configuration with eight quad
SPST switches on a 6-layer board. The article “Precision SPI Switch Con-
figuration Increases Channel Density” provides detail on how precision SPI
SDI switch configuration increases channel density.
CS
SPI
SCLK
Slave Analog Devices offers several SPI enabled switches and multiplexers. For
ADGS1412 more information visit here.
SDO
References
ADuCM3029 data sheet. Analog Devices, Inc., March 2017.
SDI
CS Nugent, Stephen. “Precision SPI Switch Configuration Increases Channel
SPI
Slave
Density.” Analog Dialogue, May 2017.
SCLK
ADGS1412 Usach, Miguel. AN-1248 Application Note: SPI Interface.
SDO Analog Devices, Inc., September 2015.

SDI
CS
SPI
Slave
SCLK
ADGS1412
SDO

Figure 13. SPI enabled switches configured in a daisy chain to further

optimize the GPIOs.

Piyu Dhaker
Piyu Dhaker [piyu.dhaker@analog.com] is an applications engineer in the
North America Central Applications Group of Analog Devices. She graduated
from San Jose State University in 2007 with a master’s degree in electrical
engineering. Piyu joined the North America Central Applications Group in June
2017. She also previously worked in the Automotive Power Train Group and
Power Management Group within ADI.

Analog Dialogue 52-09, September 2018 5

 1

18.Serial communication - SPI

Some sensors implement SPI (Serial Peripheral Interface) protocol for data transfer. An example of
communication between a microcontroller and an accelerometer sensor using the SPI interface will be
demonstrated in this example.

18.1. The SPI protocol and hardware

The SPI protocol defines a bus with four
SCK
wires (four signals) and a common ground. MASTER SLAVE 1
There is one master device controlling the MOSI

activity on the bus, and one active slave device. MISO

The slave is active only when the signal Slave SS1

Select (SS) enables it; this signal is provided by SS2
the master. There can be more than one slave
connected to the SPI bus, but each slave SLAVE 2

requires its own Slave Select (SS1, SS2, …)

signal, see Fig. 18.1. Data gets transferred
serially bit-by-bit. There are two signals to carry
information, one from master to slave (MOSI, Fig. 18.1: The SPI bus can be used to transfer data
Master Output Slave Input, driven by master), between the master and the slave using four wires.
and one for the opposite direction (MISO,
Master Input Slave Output, driven by slave). The last signal SCLK (Serial CLocK) assures the time
synchronization between master and slave, and is always driven by master. There are streamlined
versions of the SPI bus using only one signal to transfer data, but the direction of data must be reversed
on request; we will not use this kind of data transfer in this example.
The speed of data transfer is higher than with I2C bus, since the slave is selected using a hardware
signal and there is no need to transfer the address of the slave. However, this requires multiple Slave
Select signals if more than one slave is connected to the bus, and therefore more pins at the
microcontroller. The speed of transfer can also be higher due to the device outputs which are able to
force signals low or high, contrary to the open-drain outputs used at I2C which can force signals low
only. The logic levels are depend on the power supply for the devices connected to the SPI bus. The
achievable speed of transmission conforms to the slowest device on the bus, as with I2C bus.
The SPI protocol is less strict that the I2C protocol due to the fact that it was implemented first by
several different companies and standardized only later. Variants of clock polarities, edge
synchronizations, and even number of bits per transfer are used, and the designer should adopt its
hardware to the SPI devices used. The microcontroller used here can implement some possible variants
of the standard, and the variant implemented in the accelerometer LIS3LV02DQ is one of them.
The timing diagram of the required signals for the communication with the accelerometer chip is
given in Fig. 18.2, the writing from master to slave being shown in the upper half. Slave select signal SS
must first be forced low by the master, then a series of 2 times eight clock pulses (low-to-high
 Serial communication – SPI 2

transitions) are issued by the master at the SCK line. After this the signal SCK stays high, followed by
the signal slave select SS. The value of the signal MOSI is clocked into the slave on positive edge of the
clock signal SCK, and the MOSI signal can change either before or after the clocking edge, see the
datasheet on LIS3LV02DQ for details. The first eight bits start with a bit to define either writing to slave
(low) or reading from slave (high); this bit is low here. The next bit is fixed to zero, followed by six bits
of address. This is the address to be used by the slave device to select one of its internal locations for
writing, not the address of the slave on the bus, as with I2C bus. Here, with SPI bus, the device is
selected using the Slave Select signal! Next eight bits are simply the byte as it is supposed to be written
into the slave. In the diagram address 0x21 is selected for writing, and value 0x40 is written. The signal
MISO is not used during writing, and is not shown.

SS WRITE FROM MASTER TO SLAVE

SCK

MOSI 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0
RW

MS

D7

D6

D5

D4

D3

D2

D1

D0
A5

A4

A3

A2

A1

A0

SS READ FROM SLAVE TO MASTER

SCK

MOSI 1 0 1 0 1 0 0 0 X
RW

MS

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0
MISO 1 0 1 0 1 1 0 0
D7

D6

D5

D4

D3

D2

D1

D0

Figure 18.2: SPI bus signals during the writing into the slave (top), and reading from the slave (bottom)

The timing diagram for reading is given in the same figure, bottom half. The Slave Select signal and
the 16 rising edges of the clock are the same as for writing, signals MOSI and MISO differ. The master
first sends a command to read from the slave by forcing the first bit of the first byte at MOSI line high,
and then pulling the same line low during the second bit. Next come six bits of address within the slave,
here 0x28. After the first byte the MOSI signal is not important anymore. It can be left floating as shown
in the figure, but it can also have any other logic value; its value will be ignored by the slave. However,
clock pulses are still coming, and the slave now drives the MISO signal returning the byte to be read,
shown as 0xAC. This sequence should be accepted by the SPI block within the microcontroller and
combined into a byte.

18.2. The SPI protocol - writing

The Discovery board exposes pins associated with SPI block 2, making them available to the user.
Additionally, the BaseBoard provides two connectors for SPI slaves both having separate, hardware
defined Slave Select signals; the one we will use in this example is taken from port B, pin 12. Signals
SCK, MOSI and MISO are available as alternate function at pins 13 to 15. It is convenient to summarize
the steps for writing into:
1. Enable the Slave Select signal (port B, pin 12) by pulling it low.
2. Wait some time.
3. Send address and data from master to the slave using the SPI2 block; this is done by a call to a
CMSIS function “SPI_I2S_SendData()”, which simply writes 16 bits into the data register DR of
 Serial communication – SPI 3

the SPI2 block. Do not miss to keep the MSB of the 16 bit low, since this indicates “write” to the
slave. The CMSIS function can be replaced by a hard-coded write into register SPI2->DR, as
shown in this example.
4. Wait some time for all bits to be transferred to slave.
5. Disable the Slave Select signal (port B, pin 12) by pulling it high.
These steps are implemented in the function “LIS_write()” below:
void LIS_write (char address, char data) {
GPIOB->BSRRH = BIT_12; // step 1
for (int i = 0; i < 150; i++) {}; // waste time // step 2
SPI2->DR = ((unsigned short)(address & 0x3f) << 8) + (unsigned short)(data); // step 3
for (int i = 0; i < 1200; i++) {}; // waste time // step 4
GPIOB->BSRRL = BIT_12; // step 5
}

Step 3 here may need additional discussion. The address must be a six bit value. However, since the
‘address’ is an argument to this function, an unwary user might specify more than six bits, and it is best
to clip it to six bits by AND-ing it with 0x3f. This address must come to upper eight positions of the data
register, so the software converts is into unsigned short integer, and shifts it for eight places. Finally,
the ‘data’ is added to lower eight positions of the final value to be written into the ‘SPI2->DR’.
The waiting in steps 2 and 4 is done by an empty loop, and is not very efficient and precise.

18.3. The SPI protocol – reading

Similarly, the steps required for reading from the slave can be summarized into:
1. Enable the Slave Select signal (port B, pin 12) by pulling it low.
2. Wait some time.
3. Send address from master to slave using the SPI2 block, the address must occupy the upper 8
bits of the short integer passed to a CMSIS function call “SPI_I2S_SendData()”, which simply
writes 16 bits into the data register DR of the SPI2 block. Do not miss to keep the MSB of the
16 bit high, since this indicates to read from the slave. The CMSIS function can be avoided by a
hard-coded write into the register SPI2->DR.
4. Wait some time for all bits to be transferred to slave.
5. Disable the Slave Select signal (port B, pin 12) by pulling it high.
6. Read the content of the data register SPI2->DR in the SPI2 block, it contains the value returned
by the slave. A CMSIS function “SPI_I2S_ReceiveData()” could be used instead of the hard-
coded read from the register.
These steps are implemented in the function “LIS_read()” below:
short LIS_read (char address) {
GPIOB->BSRRH = BIT_12; // step 1
for (int i = 0; i < 150; i++) {}; // waste time // step 2
SPI2->DR = ((unsigned short )(address & 0x3f) << 8) + 0x8000; // step 3
for (int i = 0; i < 1200; i++) {}; // waste time // step 4
GPIOB->BSRRL = BIT_12; // step 5
return (SPI2->DR & 0xff); // step 6
}

The step 3 might need additional discussion. The address of the register within the SPI slave must
be reside in the upper eight bits of the unsigned short integer to be written into the register SPI2-DR,
and this is accomplished by shifting it to the left for eight places. However, the MSB of the shifted value
must he high to signal reading from the SPI slave, and this is achieved by OR-ing the result of shifting
with 0x8000.
 Serial communication – SPI 4

The value obtained from the SPI slave is available in the SPI2->DR register, and only lower eight bits
are to be used; those are isolated by an AND function and argument of 0xff.
Once we have functions to write and read the SPI bus we are ready to see the program to
communicate with the accelerometer and pass results on the screen. The listing is given below.
#include "stm32f4xx_rcc.c"
#include "stm32f4xx_gpio.c"
#include "stm32f4xx_spi.c"
#include "LCD2x16.c"
#include "dd.h"

int main () {
SPI2init(); // SPI2 init // 8
LCD_init(); // Init LCD
LCD_string("SPI demo Z", 0); // write title
LCD_string("X Y", 0x40); // write title

LIS_write (0x20,0xc7); // 13

while (1) {
short xLSB = LIS_read(0x28); short xMSB = LIS_read(0x29) << 8; // 16
short yLSB = LIS_read(0x2a); short yMSB = LIS_read(0x2b) << 8; // 17
short zLSB = LIS_read(0x2c); short zMSB = LIS_read(0x2d) << 8; // 18
LCD_sInt16((xLSB + xMSB), 0x41, 0x01); // show acc x // 19
LCD_sInt16((yLSB + yMSB), 0x4a, 0x01); // show acc y // 20
LCD_sInt16((zLSB + zMSB), 0x0a, 0x01); // show acc z // 21
for (int i = 0; i < 10000000; i++) {}; // waste time
};
}

The listing starts with the inclusion of necessary source files, and the execution starts with the
function “main()”. A function to configure the SPI2 block is called in line 8, the content of this function
will be discussed last. The function for the configuration and initialization of the LCD screen is called
next, followed by two commands to write introductory strings to the LCD.
The accelerometer sensor is turned on and configured by a single write in line 13. As in the previous
chapter: value 0xc7 must be written to sensor at address 0x20 in order for sensor to operate.
The execution proceeds with the loop, where the content of six registers within the sensor are read
periodically using the derived function for reading the SPI bus, these are lines 16 to 18. Next the results
obtained are combined and written to the LCD screen at appropriate positions.
The loop terminates with an empty ‘for’ loop to waste some time and to reduce the frequency of
results being written to the LCD.
Lines 16 to 18 need some discussion. The datasheet of the accelerometer specifies that the result
of the measurement is available in registers 0x28 (LSB) and 0x29 (MSB) for the acceleration in x-axis.
Registers 0x2a (LSB) and 0x2b (MSB) hold the result for y-axis, and registers 0x2c (LSB) and 0x2d (MSB)
hold the result for z-axis. These bytes are read from the relevant registers one by one and stored in six
short integers ‘xLSB’, ‘xMSB’, ‘yLSB’... These integers are then combined to form complete results for
accelerations in each of the three axes.
The configuration procedure for the SPI block 2 is discussed last. Its listing is given below, and it
consists of two parts. The main part is called “SPI2init()”, and is used to configure the SPI block.
However, the SPI signals must be assigned to pins on the microprocessor, and this is done in the
function “GPIOBinit_SPI2()” which is called from the “SPI2init()”.
void GPIOBinit_SPI2(void) {
GPIO_InitTypeDef GPIO_InitStructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); // 3
 Serial communication – SPI 5

GPIOB->BSRRL = BIT_14 | BIT_13 | BIT_12 | BIT_11; // 5

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; // 7

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; // 8
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; // 9
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; // 10
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; // 11
GPIO_Init(GPIOB, &GPIO_InitStructure); // 12

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12; // PB12, PB12: SPI_SEL // 14

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; // 15
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; // 16
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; // 17
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; // 18
GPIO_Init(GPIOB, &GPIO_InitStructure); // 19

GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_SPI2); // PB13:SPI2_SCK // 21

GPIO_PinAFConfig(GPIOB, GPIO_PinSource14, GPIO_AF_SPI2); // PB14:SPI2_MISO // 22
GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_SPI2); // PB15:SPI2_MOSI // 23
}

void SPI2init(void) { //
SPI_InitTypeDef SPI_InitStructure;
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); // 3
GPIOBinit_SPI2(); // GPIO clock enable, digital pin definitions // 4

SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; // 6
SPI_InitStructure.SPI_Mode = SPI_Mode_Master; // 7
SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b; // 8
SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; // 9
SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; // 10
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; // 11
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64; // 12
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; // 13
SPI_InitStructure.SPI_CRCPolynomial = 7; // 14
SPI_Init(SPI2, &SPI_InitStructure); // 15

SPI_Cmd(SPI2, ENABLE); // 17
}

The configuration of the SPI block is initiated by the call of the function “SPI2init()”. The function
“SPI_Init()” from a CMSIS library will be used for the configuration as described in the source file
“stm32f4xx_spi.c”. This function requires the use of the data structure ‘SPI_InitStructure’, which is
defined in the header file “stm324xx_spi.h”, lines 54 to 85.
The clock for the block SPI2 is enabled in line 3, then the function that deals with pin configuration
at port B is called; this will be discussed later. The data structure is initialized in lines 6 to 14 as follows.
- Member ‘.SPI_Direction’ defines the number of wires used for the transmission and the
direction of data transfer, see the Reference manual RM0090, pg. 863 for details. We are going
to use three lines, one for the clock signal, one to send data from the microcontroller to the
accelerometer chip, and one to receive data into the microcontroller from the accelerometer
chip. The synonymous for this in CMSIS is the keyword ‘SPI_Direction_2Lines_FullDuplex’.
Alternative keywords are listed in the header file, lines 151 to 154.
 Serial communication – SPI 6

- Member ‘.SPI_Mode’ defines the mode of operation for the block SPI; it can be either master
or slave. In our case the microcontroller is taking the complete control over the SPI bus, and
this is accomplished by making the SPI block the master of the bus.
- Member ‘.SPI_DataSize’ defines the length of the message sent in one package. It can be either
8 or 16 bits, here we opt for 16 bits by initializing the member with the keyword
‘SPI_DataSize_16b’.
- Members ‘.SPI_CPOL’ and ‘.SPI_CPHA’ define the relation of the polarity of the clock signal SCL
and the edge of this signal to be used for clocking of data, see the details in the Reference
manual RM0090, pages 857 and 858. The sensor used in our experiment requires signals as
given in Fig. 18.2, and this is accomplished by initializing these two members as ‘SPI_CPOL_High’
and ‘SPI_CPHA_2Edge’.
- Member ‘.SPI_NSS’ defines the generation of the slave select signal. We intend to generate this
signal by software, and this is accomplished by initializing this member with ‘SPI_NSS_Soft’.
- Member ‘.SPI_BaudRatePrescaler’ defines the speed of transmission. We arbitrary select one
of the division ratios in this experiment as ‘SPI_BaudRatePrescaler_64’. Note that the slave
select signal is managed by software and a software delay is used to align the select signal.
Using different value for the prescaler requires the change in the delay loops as well.
- Member ‘.SPI_FirstBit’ defines the order the bits are sent to the slave. The chain can start with
the MSB or the LSB, and the accelerometer chip used in this experiment requires MSB to be
sent first.
- Member ‘.SPI_CRCPolynomial’ is not used here since we do not use any error checking.
Nevertheless, this member is initialized to 7.
Following the initialization of data structure the block gets configured by a call in line 15. The
configuration is followed by a call in line 17 that enables the block SPI for the use.
The complete list of special functions that can be assigned to pins is given in table 9, pg. 60 and on,
in the datasheet of the microcontroller (DM00037051). Following this table the SPI signals for block 2
are available at port B, pins 12 to 15; these pins need to be configured before use, and this is done in
function “GPIOBinit_SPI2”. The function starts with the definition of the data structure and enabling
of the clock for port B. Since the initial state of all lines is supposed to be high all pins are initialized to
logic high in line 5.
Pins 13, 14 and 15 are used for SPI signals SCK, MISO and MOSI respectively. These pins are
designated as outputs (lines 7 to 12), and alternate functions are selected for them (lines 21 to 23).
The rest of the initialization of the data structure and function call itself follow the usual pattern for
pin configuration.
There are two slave select pins 11 and 12; pin 12 is used in this example since only one of the SPI
connectors is utilized. These pins are designated as outputs in lines 14 to 19.
Finally the alternate function for pins 13 to 15 is selected in lines 21 to 23.
 AN10216-01 I2C Manual

OVERVIEW

Description

Philips Semiconductors developed the I2C bus over 20 years ago and has an extensive collection of specific use and
general purpose devices. This application note was developed from the 3 hour long I2C Overview TecForum presentation
at DesignCon 2003 in San Jose, CA on 27 January 2003 and provides a broad overview of how the I2C bus compares to
other serial buses, how the I2C bus works, ways to overcome previous limitations, new uses of I2C such as in the
Intelligent Platform Management Interface, overview of the various different categories of I2C devices and patent/royalty
information. Full size Slides are posted as a PDF file on the Philips Logic I2C collateral web site as DesignCon 2003
TecForum I2C Bus Overview PDF file. Place holder and title slides have been removed from this application note and
some slides with all text have been incorporated into the application note speaker notes.

three shared signal lines, for bit timing, data, and R/W.
Serial Bus Overview The selection of communicating partners is made with
one separate wire for each chip. As the number of chips
Co
m
m
grows, so do the selection wires. The next stage is to
un use multiplexing of the selection wires and call them an
ic
at
io
n er address bus.
s sum
Con
If there are 8 address wires we can select any one of
otiv
e IEEE1394 256 devices by using a ‘one of 256’ decoder IC. In a
tom
Au
SERIAL parallel bus system there could be 8 or 16 (or more)
BUSES data wires. Taken to the next step, we can share the
function of the wires between addresses and data but it
UART starts to take quite a bit of hardware and worst is, we
In
du
s
still have lots of wires. We can take a different
tri
SPI a l approach and try to eliminate all except the data wiring
BUS itself. Then we need to multiplex the data, the selection
DesignCon 2003 TecForum I2C Bus Overview 5 (address), and the direction info - read/write. We need
to develop relatively complex rules for that, but we save
Slide 5 on those wires. This presentation covers buses that use
only one or two data lines so that they are still attractive
for sending data over reasonable distances - at least a
General concept for Serial communications few meters, but perhaps even km.
SCL
SDA
Typical Signaling Characteristics
Parallel to Serial

select 3
Shift Register

select 2
select 1
READ
or enable Shift Reg# enable Shift Reg# enable Shift Reg#
WRITE? // to Ser. // to Ser. // to Ser.
R/W R/W R/W
“MASTER” SLAVE 1 SLAVE 2 SLAVE 3
DATA
LVTTL
• A point to point communication does not require a Select control signal
RS422/485 I2C
• An asynchronous communication does not have a Clock signal I2C SMBus
• Data, Select and R/W signals can share the same line, depending on the protocol I2C
PECL 1394
• Notice that Slave 1 cannot communicate with Slave 2 or 3 (except via the ‘master’) LVPECL LVDS GTL+
Only the ‘master’ can start communicating. Slaves can ‘only speak when spoken to’
DesignCon 2003 TecForum I2C Bus Overview 6
CML

LVT 5V 3.3 V 2.5 V GTL

GTLP
Slide 6 LVC

DesignCon 2003 TecForum I2C Bus Overview 7

Buses come in two forms, serial and parallel. The data

and/or addresses can be sent over 1 wire, bit after bit, or Slide 7
over 8 or 32 wires at once. Always there has to be some
way to share the common wiring, some rules, and some Devices can communicate differentially or single ended
synchronization. Slide 6 shows a serial data bus with with various signal characteristics as shown in Slide 7.

4
 AN10216-01 I2C Manual
also because it may be used within the PC software as a
general data path that USB drivers can use.
Transmission Standards
Terminology for USB: The use of older terms such as
2500 the spec version 1.1 and 2.0 is now discouraged. There
is just “USB” (meaning the original 12 Mbits/sec and
Data Transfer Rate (Mbps)

CML
655
400 1.5 Mbits/sec speeds of USB version 1.1) and Hi-Speed
GTLP
BTL
ETL 35
1394.a LVD
ECL S =RS-6
/PEC 4
USB meaning the faster 480 Mbits/sec option included
L/LV 4
10
PEC
L in spec version 2.0. Parts conforming to or capable of
General RS-422 the 480 Mbits/sec are certified as Hi-Speed USB and
Purpose 1
Logic RS-485
will then feature the logo with the red stripe “Hi-Speed”
0.1
I2C
fitted above the standard USB logo. The reason to avoid
RS-232 RS-423
use of the new spec version 2.0 as a generic name is
0.5 0 10 100 1000 that this version includes all the older versions and
Backplane Length (meters) Cable Length (meters)
speeds as well as the new Hi-Speed specs. So USB 2.0
DesignCon 2003 TecForum I2C Bus Overview 8
compliance does NOT imply Hi-Speed (480 Mbits/sec).
ICs can be compliant with USB 2.0 specifications yet
Slide 8 only be capable of the older ‘full speed’ or 12
Mbits/sec.
The various data transmission rates vs length or cable
or backplane length of the different transmission
standards are shown in Slide 8.
Bus characteristics compared
Data rat e Len gth No d es Node number
Bu s
(bits / sec) ( meter s) Length limiting f actor Typ.number limiting f actor

Speed of various connectivity methods (bits/sec) I2 C

I2C w ith buf fer
400k
400k
2
100
w iring capacitance
propagation delays
20
an y
400pF max
no limit
I2 C high speed 3.4M 0.5 w iring capacitance 5 100pF max
CAN 1 w ire 33k 100 total capacitance 32
load resistance and
CAN (1 Wire) 33 kHz (typ) 5k 10km
transceiver cur r ent
CA N diff erential propagation delays 100
I2C (‘Industrial’, and SMBus)
125k 500
100 kHz 1M 40
drive

SPI 110 kHz (original speed) USB (low - speed, 1.1) 1.5M 3 cable specs 2 bus specs
CAN (fault tolerant) 125 kHz USB ( full - speed, 1.1) 1.5/12M
25 5 cables linking 6 nodes 127 bus and hub specs
I2C 400 kHz Hi- Spe ed USB (2.0) 480M ( 5m cable node to node)
IEEE-1394 100 to 400M+ 72 16 hops, 4.5M each 63 6-bit address
CAN (high speed) 1 MHz
I2C ‘High Speed mode’ 3.4 MHz
USB (1.1) 1.5 MHz or 12 MHz
SCSI (parallel bus) 40 MHz
Fast SCSI 8-80 MHz
Ultra SCSI-3 18-160 MHz
Firewire / IEEE1394 400 MHz DesignCon 2003 TecForum I2C Bus Overview 10

Hi-Speed USB (2.0) 480 MHz

Slide 10
DesignCon 2003 TecForum I2C Bus Overview 9

In Slide 10 we look at three important characteristics:

Slide 9 • Speed, or data rate
• Number of devices allowed to be connected (to
Increasing fast serial transmission specifications are share the bus wires)
shown in Slide 9. Proper treatment of the 480 MHz • Total length of the wiring
version of USB - trying to beat the emerging 400 MHz
1394a spec - that is looking to an improved ‘b’ spec - - Numbers are supposed to be realistic estimates but are
etc is beyond the scope of this presentation. Philips is based on meeting bus specifications. But rules are made
developing leading-edge components to support both to be broken! When buffered, I2C can be limited by
USB and 1394 buses. wiring propagation delays but it is still possible to run
much longer distances by using slower clock rates and
Today the path forward in USB is built on “OTG” (On maybe also compromising the bus rise and fall-time
The Go) applications but the costs and complexity of specifications on the buffered bus because it is not
this are probably beyond the limits of many customers. bound to conform to I2C specifications.
If designers are identified as designing for large
international markets then please contact the USB The figure in Slide 10 limiting I2C range by
group for additional support, particularly of Host and propagation delays is conservative and allows for
OTG solutions. Apologies for inclusion of the parallel published response delays in chips like older E2
SCSI bus. It is intended for comparison purposes and memories. Measured chip responses are typically <
700 ns and that allows for long cable delays and/or

5
 AN10216-01 I2C Manual
operation well above 100 kHz with the P82B96. The all the bits and rebuilds the (parallel) byte and puts it in
theoretical round-trip delay on 100 m of cable is only a buffer.
approx 1 µs and the maximum allowed delay, assuming
zero delays in ICs, is about 3 µs at 100 kHz. The Along with converting between serial and parallel, the
figures for CAN are not quite as conservative; they are UART does some other things as a byproduct (side
the ‘often quoted values’. The round trip delay in 10 effect) of its primary task. The voltage used to represent
km cable is about 0.1 ms while 5 kbps implies 0.2 ms bits is also converted (changed). Extra bits (called start
nominal bit time, and a need to sample during the and stop bits) are added to each byte before it is
second half of the bit time. That is under the user’s transmitted. Also, while the flow rate (in bytes/s) on the
control, but needs attention. parallel bus speed inside the computer is very high, the
flow rate out the UART on the serial port side of it is
USB 2 and IEEE-1394 are still ‘emerging standards’. much lower. The UART has a fixed set of rates
Figures quoted may not be practical; they are just based (speeds) that it can use at its serial port interface.
on the specification restrictions.
UART - Applications
UART Overview
Server
Public
LAN / Private
application
Server Client
Client
Telephone / Internet
Processor Digital
Processor
What is UART? Network
Serial Interface
Parallel
Interface
Processor
Processor

tt t tt tt
(Universal Asynchronous Receiver Transmitter) Datacom
Datacom r rModem Analog or Digital Modem
Modemrr
Datacom
rr Datacom
controller r Modem controller
controller x
x x xx xx controller
• Communication standard implemented in the 60’s. WAN application Serial Interface
• Simple, universal, well understood and well supported. Appliance Terminals
• Slow speed communication standard: up to 1 Mbits/s • Entertainment
• Asynchronous means that the data clock is not included in • Home Security
the data: Sender and Receiver must agree on timing Cash
parameters in advance. register • Robotics
Display
• “Start” and “Stop” bits indicates the data to be sent Address • Automotive
Micro Memory Interface to
Micro Data
• Parity information can also be sent contr.
contr.
UART
Memory
Server • Cellular
DUART
DUART
SC28L92
SC28L92 • Medical
Bar code
0 1 2 3 4 5 6 7 Printer
reader
2
DesignCon 2003 TecForum I C Bus Overview 12

Start bit 8 Bit Data Stop bit

Parity Information
DesignCon 2003 TecForum I2C Bus Overview 11
Slide 12

Slide 11 SPI Overview

UARTs (Universal Asynchronous Receiver What is SPI?

Transmitter) are serial chips on your PC motherboard • Serial Peripheral Interface (SPI) is a 4-wire full-duplex
(or on an internal modem card). The UART function synchronous serial data link:
may also be done on a chip that does other things as – SCLK: Serial Clock
– MOSI: Master Out Slave In - Data from Master to Slave
well. On older computers like many 486's, the chips – MISO: Master In Slave Out - Data from Slave to Master
were on the disk IO controller card. Still older – SS: Slave Select
computers have dedicated serial boards. • Originally developed by Motorola
• Used for connecting peripherals to each other and to
microprocessors
The UARTs purpose is to convert bytes from the PC's
• Shift register that serially transmits data to other SPI devices
parallel bus to a serial bit-stream. The cable going out • Actually a “3 + n” wire interface with n = number of devices
of the serial port is serial and has only one wire for each • Only one master active at a time
direction of flow. The serial port sends out a stream of • Various Speed transfers (function of the system clock)
bits, one bit at a time. Conversely, the bit stream that
DesignCon 2003 TecForum I2C Bus Overview
enters the serial port via the external cable is converted
13

to parallel bytes that the computer can understand.

UARTs deal with data in byte-sized pieces, which is
conveniently also the size of ASCII characters.
Say you have a terminal hooked up to your PC. When
you type a character, the terminal gives that character to
its transmitter (also a UART). The transmitter sends
that byte out onto the serial line, one bit at a time, at a
specific rate. On the PC end, the receiving UART takes
Slide 13
The Serial Peripheral Interface (SPI) circuit is a
synchronous serial data link that is standard across
many Motorola microprocessors and other peripheral
chips. It provides support for a high bandwidth (1 mega
baud) network connection amongst CPUs and other
devices supporting the SPI.

6
 AN10216-01 I2C Manual
synchronized by the serial clock (SCLK). One bit of
SPI - How are the connected devices recognized? data is transferred for each clock cycle. Four clock
SCLK SCLK SLAVE 1 modes are defined for the SPI bus by the value of the
MOSI MOSI
MISO MISO clock polarity and the clock phase bits. The clock
SS 1
SS 2
SS
polarity determines the level of the clock idle state and
SS 3 SCLK
MOSI
SLAVE 2 the clock phase determines which clock edge places
MASTER
MISO
SS
new data on the bus. Any hardware device capable of
SLAVE 3
operation in more than one mode will have some
SCLK
MOSI method of selecting the value of these bits.
MISO
SS
• Simple transfer scheme, 8 or 16 bits CAN Overview
• Allows many devices to use SPI through the addition of a shift register
• Full duplex communications
What is CAN ? (Controller Area Network)
• Number of wires proportional to the number of devices in the bus
DesignCon 2003 TecForum I2C Bus Overview 14 • Proposed by Bosch with automotive applications in mind
(and promoted by CIA - of Germany - for industrial
applications)
Slide 14 • Relatively complex coding of the messages
• Relatively accurate and (usually) fixed timing
The SPI is essentially a “three-wire plus slave selects” • All modules participate in every communication
serial bus for eight or sixteen bit data transfer • Content-oriented (message) addressing scheme
applications. The three wires carry information between
devices connected to the bus. Each device on the bus
acts simultaneously as a transmitter and receiver. Two
of the three lines transfer data (one line for each
Filter Frame Filter
direction) and the third is a serial clock. Some devices
may be only transmitters while others only receivers. DesignCon 2003 TecForum I2C Bus Overview 15

Generally, a device that transmits usually possesses the

capability to receive data also. An SPI display is an Slide 15
example of a receive-only device while EEPROM is a
receiver and transmit device. CAN objective is to achieve reliable communications in
The devices connected to the SPI bus may be classified relatively critical control system applications e.g.
as Master or Slave devices. A master device initiates an engine management or anti-lock brakes. There are
information transfer on the bus and generates clock and several aspects to reliability - availability of the bus
control signals. A slave device is controlled by the when important data needs to be sent, the possibility of
master through a slave select (chip enable) line and is bits in a message being corrupted by noise etc., and
active only when selected. Generally, a dedicated select electrical/mechanical failure modes in the wiring.
line is required for each slave device. The same device At least a ceramic resonator and possibly a quartz
can possess the functionality of a master and a slave but crystal are needed to generate the accurate timing
at any point of time, only one master can control the needed. The clock and data are combined and 6 ‘high’
bus in a multi-master mode configuration. Any slave bits in succession is interpreted as a bus error. So the
device that is not selected must release (make it high clock and bit timings are important. All connected
impedance) the slave output line. modules must use the same timings. All modules are
The SPI bus employs a simple shift register data looking for any error in the data at any point on the
transfer scheme: Data is clocked out of and into the wiring and will report that error so the message can be
active devices in a first-in, first-out fashion. It is in this re-sent etc.
manner that SPI devices transmit and receive in full
duplex mode.
All lines on the SPI bus are unidirectional: The signal
on the clock line (SCLK) is generated by the master and
is primarily used to synchronize data transfer. The
master-out, slave-in (MOSI) line carries data from the
master to the slave and the master-in, slave-out (MISO)
line carries data from the slave to the master. Each
slave device is selected by the master via individual
select lines. Information on the SPI bus can be
transferred at a rate of near zero bits per second to 1
Mbits per second. Data transfer is usually performed in
eight/sixteen bit blocks. All data transfer is

7
 AN10216-01 I2C Manual
CAN protocol
Start Of Frame
Identifier
Remote Transmission Request
Identifier Extension
Data Length Code
Data
Cyclic Redundancy Check
Acknowledge
End Of Frame
Intermission Frame
Space
• Very intelligent controller requested to generate such protocol
DesignCon 2003 TecForum I2C Bus Overview
Slide 16
Like I2C, the CAN bus wires are pulled by resistors to
their resting state called a ‘recessive’ state. When a
transceiver drives the bus it forces a voltage called the
‘dominant’ state. The identifier indicates the meaning
of the data, not the intended recipient. So all nodes
receive and ‘filter’ this identifier and can decide
whether to act on the data or not. So the bus is using
‘multicast’ - many modules can act on the message, and
all modules are checking the message for transmission
errors. Arbitration is ‘bit wise’ like I2C - the module
forcing a ‘1’ beats a module trying for a ‘0’ and the
loser withdraws to try again later.
- DLC: data length code
- CRC: cyclic redundancy check (remainder of a
division calculation). All devices that pass the CRC
will acknowledge or will generate an error flag
after the data frame finishes.
- ACK: acknowledge.
- Error frame: (at least) 6 consecutive dominant bits
then 7 recessive bits.
A message ‘filter’ can be programmed to test the 11-bit
identifier and one or two bytes of the data (In general
up to 32 bits) to decide whether to accept the message
and issue an interrupt. It could also look at all of the
29-bit identifier.
CAN Bus Advantages
• Accepted standard for Automotive and industrial applications
– interfacing between various vendors easier to implement
• Freedom to select suitable hardware
– differential or 1 wire bus
• Secure communications, high Level of error detection
– 15 bit CRC messages (Cyclic Redundancy Check)
– Reporting / logging
– Faulty devices can disconnect themselves
– Low latency time
– Configuration flexibility
• High degree of EMC immunity (when using Si-On-Insulator
technology)
16 DesignCon 2003 TecForum I2C Bus Overview 17
Slide 17
I2C products from many manufacturers are all
compatible but CAN hardware will be selected and
dedicated for each particular system design. Some CAN
transceivers will be compatible with others, but that is
more likely to be the exception than the rule. CAN
designs are usually individual systems that are not
intended to be modified. Philips parts greatly enhance
the feature of reliability by their ability to use part-
broken bus wiring and disconnect themselves if they are
recording too many bus errors.
There are several aspects to reliability - availability of
the bus when important data needs to be sent, the
possibility of bits in a message being corrupted by noise
etc., and the consequences of electrical/mechanical
failure modes in the wiring. All these aspects are treated
seriously by the CAN specifications and the suppliers
of the interface ICs - for example Philips believes
conventional high voltage IC processes are not good
enough and uses Silicon-on-insulator technology to
increase ruggedness and avoid the alternative of using
common-mode chokes for protection. To give an
example of immunity, a transceiver on 5 V must be able
to cope with jump-start and load-dump voltages on its
supply or bus wires. That is 40 V on the supply and +/-
40 V on the bus lines, plus transients of –150 V/+100 V
capacitively coupled from a pulse generator in a test
circuit!
8

USB Overview
What is USB ? (Universal Serial Bus)
• Originally a standard for connecting PCs to peripherals
• Defined by Intel, Microsoft, …
• Intended to replace the large number of legacy ports in the PC
• Single master (= Host) system with up to 127 peripherals
• Simple plug and play; no need to open the PC
• Standardized plugs, ports, cables
• Has over 99% penetration on all new PCs
• Adapting to new requirements for flexibility of Host function
– New Hardware/Software allows dynamic exchanging of Host/Slave
roles
– PC is no longer the only system Host. Can be a camera or a printer.
DesignCon 2003 TecForum I2C Bus Overview
Slide 18
USB is the most complex of the buses presented here.
While its hardware and transceivers are relatively
simple, its software is complex and is able to efficiently
service many different applications with very different
data rates and requirements. It has a 12 Mbps rate (with
200 Mbps planned) over a twisted pair with a 4-pin
connector (2 wires are power supply). It also is limited
to short distances of at most 5 meters (depends on
configuration). Linux supports the bus, although not all
devices that can plug into the bus are supported. It is
synchronous and transmits in special packets like a
network. Just like a network, it can have several devices
attached to it. Each device on it gets a time-slice of
exclusive use for a short time. A device can also be
guaranteed the use of the bus at fixed intervals. One
device can monopolize it if no other device wants to use
it.
USB Topology (original concept, USB1.1, USB2.0)
¾ Host
− One PC host per system
− Provides power to peripherals Host
5m
¾ Hub
− Provides ports for connecting more
PC 5m
peripheral devices. 5m 5m
− Provides power, terminations
− External supply or Bus Powered
¾ Device, Interfaces and Endpoints
− Device is a collection of data
interface(s)
Device
− Interface is a collection of
endpoints (data channels)
− Endpoint associated with FIFO(s) -
for data I/O interfacing
DesignCon 2003 TecForum I2C Bus Overview
Slide 19
Slide 19 shows a typical USB configuration.
AN10216-01 I2C Manual
USB Bus Advantages
• Hot pluggable, no need to open cabinets
• Automatic configuration
• Up to 127 devices can be connected together
• Push for USB to become THE standard on PCs
– standard for iMac, supported by Windows, now on > 99%of PCs
• Interfaces (bridges) to other communication channels
exist
– USB to serial port (serial port vanishing from laptops)
– USB to IrDA or to Ethernet
• Extreme volumes force down IC and hardware prices
• Protocol is evolving fast
DesignCon 2003 TecForum I2C Bus Overview 20
18
Slide 20
USB aims at mass-market products and design-ins may
be less convenient for small users. The serial port is
vanishing from the laptop and gone from iMac. There
are hardware bridges available from USB to other
communication channels but there can be higher power
consumption to go this way. Philips is innovating its
USB products to minimize power and offer maximum
flexibility in system design.
Versions of USB specification
• USB 1.1
– Established, large PC peripheral markets
– Well controlled hardware, special 4-pin plugs/sockets
– 12MBits/sec (normal) or 1.5Mbits/sec (low speed) data rate
• USB 2.0
– Challenging IEEE1394/Firewire for video possibilities
– 480 MHz clock for Hi-Speed means it’s real “UHF” transmission
– Hi-Speed option needs more complex chip hardware and software
– Hi-Speed component prices about x 2 compared to full speed
• USB “OTG” (On The Go) Supplement
– New hardware - smaller 5-pin plugs/sockets
– Lower power (reduced or no bus-powering)
Monitor DesignCon 2003 TecForum I2C Bus Overview 21
Hub
Slide 21
5m
For USB 1.1 and 2.0 the hardware is well established.
The shape of the plug/socket at Host end is different
from the shape at the peripheral end. USB is always a
single point-to-point link over the cable. To allow
connection of multiple peripherals a HUB is introduced.
The Hub functions to multiplex the data from the
19 ‘downstream’ peripherals into one ‘upstream’ data
linkage to the Host. In Hi-Speed systems it is necessary
for the system to start communicating as a normal USB
1.1 system and then additional hardware (faster
transceivers etc) is activated to allow a higher speed.
The Hi-Speed system is much more complex
(hardware/software) than normal USB (1.1). For USB
9
 AN10216-01 I2C Manual
and Hi-Speed the development of ‘stand-alone’ Host
ICs such as ISP1161 and ISP1561 allowed the Host
function to be embedded in products such as Digital
Still Cameras or printers so that more direct transfer of
data was possible without using the path Camera → PC
→ Printer under control of the PC as the host. That two
step transfer involves connecting the camera to the PC
(one USB cable) and also the PC to the printer (second
USB cable). The goal is to do without the PC.
The next step involved the shrinking of the USB
connector hardware, to make it more compatible with
small products like digital cameras, and making
provision (extra pin) for dynamic exchanging of Host
and slave device functions without removing the USB
cable for reversing the master/slave connectors. The
new hardware and USB specification version is called
“On The Go” (OTG). The OTG specification no longer
requires the Host to provide the 1/2 A power supply to
peripherals and indeed allows arbitration to determine
whether Host or peripheral (or neither) will provide the
system power.
1394 Overview
What is IEEE1394 ?
• A bus standard devised to handle the high data throughput
requirements of MPEG-2 and DVD
– Video requires constant transfer rates with guaranteed bandwidth
– Data rates 100, 200, 400 Mbits/sec and looking to 3.2 Gb/s
• Also known as “Firewire” bus (registered trademark of Apple)
• Automatically re-configures itself as each device is added
– True plug & play
– Hot-plugging of devices allowed
• Up to 63 devices, 4.5 m cable ‘hops’, with max. 16 hops
• Bandwidth guaranteed
DesignCon 2003 TecForum I2C Bus Overview
Slide 22
1394 may claim to be more proven or established than
USB but both are ‘emerging’ specifications that are
trying to out-do each other! Philips strongly supports
BOTH. 1394 was chosen by Philips as the bus to link
set-top boxes, DVD, and digital TVs. 1394 has an ’a’
version taking it to 400 Mb/sec and more recently a ‘b’
version for higher speed and to allow longer cable runs,
perhaps 100 meter hops!
1394 sends information over a PAIR of twisted pairs.
One for data, the other is the clocking strobe. The clock
is simply recovered by an Ex-Or of the data and strobe
line signals. No PLL is needed. There is provision for
lots of remote device powering via the cable if the 6-pin
plug connection version is used. The power wires are
specified to well over 1A at 8-30 volts (approx) -
leading to some unkind references to a ‘fire’ wire!
1394 software or message format consists of timeslots
within which the data is sent in blocks or ‘channels’.
For real-time data transfer it is possible to guarantee the
availability of one or more channels to guarantee a
certain data rate. This is important for video because
it’s no good sending a packet of corrected data after a
blank has appeared on the screen!
Microsoft says, “IEEE 1394 defines a single
interconnection bus that serves many purposes and user
scenarios. In addition to its adoption by the consumer
electronics industry, PC vendors—including Compaq,
Dell, IBM, Fujitsu, Toshiba, Sony, NEC, and
Gateway—are now shipping Windows-based PCs with
1394 buses.
The IEEE 1394 bus complements the Universal Serial
Bus (USB) and is particularly optimized for connecting
digital media devices and high-speed storage devices to
a PC. It is a peer-to-peer bus. Devices have more built-
in intelligence than USB devices, and they run
independently of the processor, resulting in better
performance.
The 100-, 200-, and 400-Mbps transfer rates currently
specified in the IEEE 1394a standard and the proposed
enhancements in 1394b are well suited to meeting the
throughput requirements of multiple streaming
input/output devices connected to a single PC. The
licensing fee for use of patented IEEE 1394 technology
has been established at US $0.25 per system.
With connectivity for storage, scanners, printers, and
other types of consumer A/V devices, IEEE 1394 gives
users all the benefits of a great legacy-free connector—
22 a true Plug and Play experience and hassle-free PC
connectivity.”
1394 Topology
• Physical layer
– Analog interface to the cable
– Simple repeater
– Performs bus arbitration
• Link layer
– Assembles and dis-assembles bus packets
– Handles response and acknowledgment functions
• Host controller
– Implements higher levels of the protocol
DesignCon 2003 TecForum I2C Bus Overview 23
Slide 23
10
 AN10216-01 I2C Manual
I2C Overview
What is I2C ? (Inter-IC)
• Originally, bus defined by Philips providing a simple way to
talk between IC’s by using a minimum number of pins
• A set of specifications to build a simple universal bus
guaranteeing compatibility of parts (ICs) from different
manufacturers:
– Simple Hardware standards
– Simple Software protocol standard
• No specific wiring or connectors - most often it’s just PCB
tracks
• Has become a recognised standard throughout our industry
and is used now by ALL major IC manufacturers
DesignCon 2003 TecForum I2C Bus Overview
24
Slide 24
Originally, the I2C bus was designed to link a small
number of devices on a single card, such as to manage
the tuning of a car radio or TV. The maximum
allowable capacitance was set at 400 pF to allow proper
rise and fall times for optimum clock and data signal
integrity with a top speed of 100 kbps. In 1992 the
standard bus speed was increased to 400 kbps, to keep
up with the ever-increasing performance requirements
of new ICs. The 1998 I2C specification, increased top
speed to 3.4 Mbits/sec. All I2C devices are designed to
be able to communicate together on the same two-wire
bus and system functional architecture is limited only
by the imagination of the designer.
But while its application to bus lengths within the
confines of consumer products such as PCs, cellular
phones, car radios or TV sets grew quickly, only a few
system integrators were using it to span a room or a
building. The I2C bus is now being increasingly used in
multiple card systems, such as a blade servers, where
the I2C bus to each card needs to be isolatable to allow
for card insertion and removal while the rest of the
system is in operation, or in systems where many more
devices need to be located onto the same card, where
the total device and trace capacitance would have
exceeded 400 pF.
New bus extension & control devices help expand the
I2C bus beyond the 400 pF limit of about 20 devices
and allow control of more devices, even those with the
same address. These new devices are popular with
designers as they continue to expand and increase the
range of use of I2C devices in maintenance and control
applications.
I2C Features
• Only two bus lines are required: a serial data line
(SDA) and a serial clock line (SCL).
11
• Each device connected to the bus is software
addressable by a unique address and simple
master/slave relationships exist at all times;
masters can operate as master-transmitters or as
master-receivers.
• It’s a true multi-master bus including collision
detection and arbitration to prevent data corruption
if two or more masters simultaneously initiate data
transfer.
• Serial, 8-bit oriented, bi-directional data transfers
can be made at up to 100 kbit/s in the Standard-
mode, up to 400 kbit/s in the Fast-mode, or up to
3.4 Mbit/s in the High-speed mode.
• On-chip filtering (50 ns) rejects spikes on the bus
data line to preserve data integrity.
•
The number of ICs that can be connected to the
same bus segment is limited only by the maximum
bus capacitive loading of 400 pF.
I2C Bus - Software
• Simple procedures that allow communication to start, to
achieve data transfer, and to stop
– Described in the Philips protocol (rules)
– Message serial data format is very simple
– Often generated by simple software in general purpose micro
– Dedicated peripheral devices contain a complete interface
– Multi-master capable with arbitration feature
• Each IC on the bus is identified by its own address code
– Address has to be unique
• The master IC that initiates communication provides the clock
signal (SCL)
– There is a maximum clock frequency but NO MINIMUM SPEED
DesignCon 2003 TecForum I2C Bus Overview 25
Slide 25
I2C Communication Procedure
One IC that wants to talk to another must:
1) Wait until it sees no activity on the I2C bus. SDA
and SCL are both high. The bus is 'free'.
2) Put a message on the bus that says 'its mine' - I
have STARTED to use the bus. All other ICs then
LISTEN to the bus data to see whether they might
be the one who will be called up (addressed).
3) Provide on the CLOCK (SCL) wire a clock signal.
It will be used by all the ICs as the reference time
at which each bit of DATA on the data (SDA) wire
will be correct (valid) and can be used. The data on
the data wire (SDA) must be valid at the time the
clock wire (SCL) switches from 'low' to 'high'
voltage.
4) Put out in serial form the unique binary 'address'
(name) of the IC that it wants to communicate
with.
5) Put a message (one bit) on the bus telling whether
it wants to SEND or RECEIVE data from the other
chip. (The read/write wire is gone!)
 AN10216-01 I2C Manual
6) Ask the other IC to ACKNOWLEDGE (using one But several Masters could control one Slave, at
bit) that it recognized its address and is ready to different times. Any ‘smart’ communications must be
communicate. via the transferred DATA, perhaps used as address info.
7) After the other IC acknowledges all is OK, data The I2C bus protocol does not allow for very complex
can be transferred. systems. It’s a ‘keep it simple’ bus. But of course
8) The first IC sends or receives as many 8-bit words system designers are free to innovate to provide the
of data as it wants. After every 8-bit data word the complex systems - based on the simple bus.
sending IC expects the receiving IC to
acknowledge the transfer is going OK. Serial Bus Comparison Summary
9) When all the data is finished the first chip must
free up the bus and it does that by a special Pros and Cons of the different buses
message called 'STOP'. It is just one bit of CAN USB SPI
UART I2 C
information transferred by a special 'wiggling' of
• Well Known • Secure • Fast • Fast • Simple
the SDA/SCL wires of the bus. • Cost effective • Fast • Plug&Play HW • Universally • Well known
accepted
• Simple • Simple • Universally

The bus rules say that when data or addresses are being • Low cost
• Low cost accepted
• Plug&Play
• Large Portfolio
sent, the DATA wire is only allowed to be changed in • Large portfolio
voltage (so, '1', '0') when the voltage on the clock line is • Cost effective

LOW. The 'start' and 'stop' special messages BREAK • Limited • Complex • Powerful master • No Plug&Play
required
• Limited speed
functionality HW
that rule, and that is how they are recognized as special. • Point to Point
• Automotive
oriented • No Plug&Play • No “fixed”
SW - Specific standard
• Limited
drivers required
portfolio
• Expensive

How are the connected devices firmware

recognized? DesignCon 2003 TecForum I2C Bus Overview 27

• Master device ‘polls’ used a specific unique identification or Slide 27

“addresses” that the designer has included in the system
• Devices with Master capability can identify themselves to
other specific Master devices and advise their own specific
address and functionality
– Allows designers to build ‘plug and play’ systems
– Bus speed can be different for each device, only a maximum limit
• Only two devices exchange data during one ‘conversation’
DesignCon 2003 TecForum I2C Bus Overview
26
Most Philips CAN devices are not plug & play. That is
because for MOST chips the system needs to be fixed
and nothing can be added later. That is because an
added chip is EXPECTED to take part in EVERY data
conversation but will not know the clock speed and
cannot synchronize. That means it falsely reports a bus
timing error on every message and crashes the system.
Philips has special transceivers that allow them listen to

the bus without taking part in the conversations. This

Slide 26
Any device with the ability to initiate messages is
called a ‘master’. It might know exactly what other
chips are connected, in which case it simply addresses
the one it wants, or there might be optional chips and it
then checks what’s there by sending each address and
seeing whether it gets any response (acknowledge).
An example might be a telephone with a micro in it. In
some models, there could be EEPROM to guarantee
memory data, in some models there might be an LCD
display using an I2C driver. There can be software
written to cover all possibilities. If the micro finds a
display then it drives it, otherwise the program is
arranged to skip that software code. I2C is the simplest
of the buses in this presentation. Only two chips are
involved in any one communication - the Master that
initiates the signals and the one Slave that responded
when addressed.
special feature allows them to synchronize their clocks
and THEN actively join in the conversations. So, from
Philips, it becomes POSSIBLE to do some minor
plug/play on a CAN system.
USB/SPI/MicroWire and mostly UARTS are all just
'one point to one point' data transfer bus systems. USB
then uses multiplexing of the data path and forwarding
of messages to service multiple devices.
Only CAN and I2C use SOFTWARE addressing to
determine the participants in a transfer of data between
two (I2C) or more (CAN) chips all connected to the
same bus wires. I2C is the best bus for low speed
maintenance and control applications where devices
may have to be added or removed from the system.

12
 AN10216-01 I2C Manual
I2C Theory Of Operation • Compatible with a number of processors with
integrated I2C ports (micro 8,16,32 bits) in 8048,
I2C Introduction 80C51 or 6800 and 68xxx architectures
• I2 C bus = Inter-IC bus • Easily emulated in software by any microcontroller
• Bus developed by Philips in the 80’s • Available from an important number of component
• Simple bi-directional 2-wire bus: manufacturers
– serial data (SDA)
– serial clock (SCL)
• Has become a worldwide industry standard and used by all
major IC manufacturers
I2C Hardware architecture
• Multi-master capable bus with arbitration feature
• Master-Slave communication; Two-device only communication Pull-up resistors
Typical value 2 kΩ to 10 kΩ
• Each IC on the bus is identified by its own address code
• The slave can be a:
– receiver-only device
– transmitter with the capability to both receive and send data

DesignCon 2003 TecForum I2C Bus Overview 29

SCL Open Drain structure (or
Open Collector) for both
SCL and SDA
Slide 29
10 pF Max

The I2C bus is a very easy bus to understand and use.

Slides 29 and 30 give a good explanation of bus
specifics and the different speeds. Many people have DesignCon 2003 TecForum I2C Bus Overview 31

asked where rise time is measured and the specification

stipulates it’s between 30% and 70% of VDD. This Slide 31
becomes important when buffers ‘distort’ the rising
edges on the bus. By keeping any waveform distortions I2C Bus Terminology
below 30% of VDD, that portion of the rising edge will • Transmitter - the device that sends data to the bus.
not be counted as part of the formal rise time. A transmitter can either be a device that puts data
on the bus of its own accord (a ‘master-
I2C by the numbers transmitter’), or in response to a request from data
Standard-Mode Fast-Mode High-Speed-
Mode
from another devices (a ‘slave-transmitter’).
Bit Rate
0 to 100 0 to 400
0 to 0 to • Receiver - the device that receives data from the
(kbits/s) 1700 3400
Max Cap Load
400 400 400 100
bus.
(pF)
Rise time • Master - the component that initializes a transfer,
1000 300 160 80
(ns)
Spike Filtered
generates the clock signal, and terminates the
N/A 50 10
(ns) transfer. A master can be either a transmitter or a
Address Bits 7 and 10 7 and 10 7 and 10
Rise Time receiver.
VDD • Slave - the device addressed by the master. A slave
VIH 0.7xVDD
can be either receiver or transmitter.
• Multi-master - the ability for more than one
VIL 0.3xVDD master to co-exist on the bus at the same time
VOL 0.4 V @ 3 mA Sink Current
GND
without collision or data loss.
DesignCon 2003 TecForum I2C Bus Overview 30 • Arbitration - the prearranged procedure that
authorizes only one master at a time to take control
Slide 30 of the bus.
• Synchronization - the prearranged procedure that
2
I C is a low to medium speed serial bus with an synchronizes the clock signals provided by two or
impressive list of features: more masters.
• Resistant to glitches and noise • SDA - data signal line (Serial DAta)
• Supported by a large and diverse range of • SCL - clock signal line (Serial CLock)
peripheral devices
• A well-known robust protocol
• A long track record in the field
• A respectable communication distance which can
be extended to longer distances with bus extenders

13
 AN10216-01 I2C Manual
START/STOP conditions
• Data on SDA must be stable when SCL is High
• Exceptions are the START and STOP conditions
S P
DesignCon 2003 TecForum I2C Bus Overview
Slide 32
START and STOP Conditions
Within the procedure of the I2C bus, unique situations
arise which are defined as START (S) and STOP (P)
conditions.
START: A HIGH to LOW transition on the SDA line
while SCL is HIGH
STOP: A LOW to HIGH transition on the SDA line
while SCL is HIGH
The master always generates START and STOP
conditions. The bus is considered to be busy after the
START condition. The bus is considered to be free
again a certain time after the STOP condition. The bus
stays busy if a repeated START (Sr) is generated
instead of a STOP condition. In this respect, the
START (S) and repeated START (Sr) conditions are
functionally identical. The S symbol will be used as a
generic term to represent both the START and repeated
START conditions, unless Sr is particularly relevant.
Detection of START and STOP conditions by devices
connected to the bus is easy if they incorporate the
necessary interfacing hardware. However,
microcontrollers with no such interface have to sample
the SDA line at least twice per clock period to sense the
transition.
I2C Address, Basics
µcon- µcon-
troller
I/O A/D
D/A
LCD RTC
troller II
SCL
SDA
A0
1010 0 1 1 A1
EEPROM
A2
1010A2A1A0R/W
New devices or
functions can be
Fixed Hardware easily ‘clipped on to
Selectable an existing bus!
• Each device is addressed individually by software
• Unique address per device: fully fixed or with a programmable part
through hardware pin(s).
• Programmable pins mean that several same devices can share the
same bus
• Address allocation coordinated by the I2C-bus committee
• 112 different types of devices max with the 7-bit format (others reserved)
32 DesignCon 2003 TecForum I2C Bus Overview 33
Slide 33
HARDWARE CONFIGURATION
Slide 33 shows the hardware configuration of the I2C
bus. The ‘bus’ wires are named SDA (serial data) and
SCL (serial clock). These two bus wires have the same
configuration. They are pulled-up to the logic ‘high’
level by resistors connected to a single positive supply,
usually +3.3 V or +5 V but designers are now moving
to +2.5 V and towards 1.8 V in the near future.
All the connected devices have open-collector (open-
drain for CMOS - both terms mean only the lower
transistor is included) driver stages that can transmit
data by pulling the bus low, and high impedance sense
amplifiers that monitor the bus voltage to receive data.
Unless devices are communicating by turning on the
lower transistor to pull the bus low, both bus lines
remain ‘high’. To initiate communication a chip pulls
the SDA line low. It then has the responsibility to drive
the SCL line with clock pulses, until it has finished, and
is called the bus ‘master’.
BUS COMMUNICATION
Communication is established and 8-bit bytes are
exchanged, each one being acknowledged using a 9th
data bit generated by the receiving party, until the data
transfer is complete. The bus is made free for use by
other ICs when the ‘master’ releases the SDA line
during a time when SCL is high. Apart from the two
special exceptions of start and stop, no device is
allowed to change the state of the SDA bus line unless
the SCL line is low.
If two masters try to start a communication at the same
time, arbitration is performed to determine a “winner”
(the master that keeps control of the bus and continue
the transmission) and a “loser” (the master that must
abort its transmission). The two masters can even
generate a few cycles of the clock and data that
‘match’, but eventually one will output a ‘low’ when
the other tries for a ‘high’. The ‘low’ wins, so the
14
 AN10216-01 I2C Manual
‘loser’ device withdraws and waits until the bus is freed master releases SDA line to accomplish the
again. Acknowledge phase. If the other device is connected to
the bus, and has decoded and recognized its ‘address’, it
There is no minimum clock speed; in fact any device will acknowledge by pulling the SDA line low. The
that has problems to ‘keep up the pace’ is allowed to responding chip is called the bus ‘slave’.
‘complain’ by holding the clock line low. Because the
device generating the clock is also monitoring the
voltage on the SCL bus, it immediately ‘knows’ there is I2C Read and Write Operations (1)
a problem and has to wait until the device releases the • Write to a Slave device
SCL line. < n data bytes >
Master
SCL Slave

S slaveaddress
S slave addressW WA Adata data
A A data
data A P transmitter receiver
A P
SDA

For full details of the bus capabilities refer to Philips “0” = Write Each byte is acknowledged by the slave device

Semiconductors Specification document ‘The I2C bus The master is a “MASTER - TRANSMITTER”:
–it transmits both Clock and Data during the all communication
specification’ or ‘The I2C bus from theory to practice’ • Read from a Slave device
book by Paret and Fenger published by John Wiley & < n data bytes > SCL

receiver
Sons. transmitter
S slave address R A data A data A P

SDA

“1” = Read Each byte is acknowledged by the master device (except the last
one, just before the STOP condition)
The I2C specification and other useful application The master is a “MASTER TRANSMITTER then MASTER - RECEIVER”:
information can be found on Philips Semiconductors – it transmits Clock all the time
– it sends slave address data and then becomes a receiver
web site at
DesignCon 2003 TecForum I2C Bus Overview
http://www.semiconductors.philips.com/i2c/ 35

Slide 35
I2C Address, 7-bit and 10-bit formats
• The 1st byte after START determines the Slave to be addressed Terminology for Bus Transfer
• Some exceptions to the rule:
• F (FREE) - the bus is free; the data line SDA and
– “General Call” address: all devices are addressed : 0000 000 + R/W = 0
– 10-bit slave addressing : 1111 0XX + R/W = X
the SCL clock are both in the high state.
•7-bit addressing
• S (START) or SR (Repeated START) - data
transfer begins with a start condition (not a start
S X X X X X X X R/W A DATA
bit). The level of the SDA data line changes from
The 7 bits
Only one device will acknowledge high to low, while the SCL clock line remains high.
• 10-bit addressing When this occurs, the bus is ‘busy’.
S 1 1 1 1 0 X X R/W A1 X X X X X X X X A2 DATA • C (CHANGE) - while the SCL clock line is low,
XX = the 2 MSBs The 8 remaining the data bit to be transferred can be applied to the
More than one device can bits Only one device will SDA data line by a transmitter. During this time,
acknowledge acknowledge
DesignCon 2003 TecForum I2C Bus Overview 34
SDA may change its state, as along as the SCL line
remains low.
• D (DATA) - a high or low bit of information on the
Slide 34
SDA data line is valid during the high level of the
SCL clock line. This level must be maintained
Slide 34 shows the I2C address scheme. Any I2C device
stable during the entire time that the clock remains
can be attached to the common I2C bus and they talk
high to avoid misinterpretation as a Start or Stop
with each other, passing information back and forth.
condition.
Each device has a unique 7-bit or 10-bit I2C address.
For 7-bit devices, typically the first four bits are fixed, • P (STOP) - data transfer is terminated by a stop
the next three bits are set by hardware address pins (A0, condition, (not a stop bit). This occurs when the
A1, and A2) that allow the user to modify the I2C level on the SDA data line passes from the low
address allowing up to eight of the same devices to state to the high state, while the SCL clock line
operate on the I2C bus. These pins are held high to VCC, remains high. When the data transfer has been
sometimes through a resistor, or held low to GND. terminated, the bus is free once again.

The last bit of the initial byte indicates if the master is

going to send (write) or receive (read) data from the
slave. Each transmission sequence must begin with the
start condition and end with the stop condition.
On the 8th clock pulse, SDA is set ‘high’ if data is
going to be read from the other device, or ‘low’ if data
is going to be sent (write). During its 9th clock, the

15
 AN10216-01 I2C Manual

I2C Read and Write Operations (2) Slide 38 shows how multiple masters can synchronize
• Combined Write and Read their clocks, for example during arbitration. When bus
< n data bytes > < m data bytes > capacitance affects the bus rise or fall times the master
S slave
S
A P
slaveaddress
addressW WA Adata data
A A data
data A SrSr slave address R A data A data A P
will also adjust its timing in a similar way.
“0” = Write Each byte is “1” = Read Each byte is
acknowledged acknowledged
by the slave device by the master device
(except the last one, just
before the STOP
I2C Protocol - Arbitration
• Combined Read and Write condition)
< n data bytes > < m data bytes >
• Two or more masters may generate a START condition at the same time
S slave address R A data A data A S
Sr slave
P addressW WA AdatadataA
slave address A data
data A P
• Arbitration is done on SDA while SCL is HIGH - Slaves are not involved
A P

“1” = Read Each byte is “0” = Write Each byte is

acknowledged acknowledged Master 1 loses arbitration
DATA1 ≠SDA
by the master device by the slave device
(except the last one, just
before the Re-START
condition)
DesignCon 2003 TecForum I2C Bus Overview 36

Slide 36

Slide 36 shows a combined read and write operation. Start

command
“1” “0” “0” “1” “0” “1”

DesignCon 2003 TecForum I2C Bus Overview 39

Acknowledge; Clock Stretching

• Acknowledge Slide 39
Done on the 9th clock pulse and is mandatory
Æ Transmitter releases the SDA line
Æ Receiver pulls down the SDA line (SCL must be HIGH) If there are two masters on the same bus, there are
Æ Transfer is aborted if no acknowledge arbitration procedures applied if both try to take control
No acknowledge
of the bus at the same time. When two chips try to start
Acknowledge
communication at the same time they may even
generate a few cycles of the clock and data that
‘match’, but eventually one will output a ‘low’ when
the other tries for a ‘high’. The ‘low’ wins, so the
• Clock Stretching ‘loser’ device withdraws and waits until the bus is freed
- Slave device can hold the CLOCK line LOW when performing
other functions
again. Once a master (e.g., microcontroller) has control,
- Master can slow down the clock to accommodate slow slaves no other master can take control until the first master
DesignCon 2003 TecForum I2C Bus Overview 37
sends a stop condition and places the bus in an idle
state.
Slide 37

Slide 37 shows how the Acknowledge phase is done What do I need to drive the I2C bus?
and how slave devices can stretch the clock signal.
Most Philips slave devices do not control the clock line. Slave 1 Slave 2 Slave 3 Slave 4

Master

I2C BUS

I2C Protocol - Clock Synchronization There are 3 basic ways to drive the I2C bus:

Vdd 1) With a Microcontroller with on-chip I2C Interface

Master 1 Master 2 Bit oriented - CPU is interrupted after every bit transmission
(Example: 87LPC76x)
Byte oriented - CPU can be interrupted after every byte transmission
CLK 1 CLK 2 (Example: 87C552)
SCL
2) With ANY microcontroller: 'Bit Banging’
The I2C protocol can be emulated bit by bit via any bi-directional open drain port

3) With a microcontroller in conjunction with bus controller like the

PCF8584 or PCA9564 parallel to I2C bus interface IC
1 4 DesignCon 2003 TecForum I2C Bus Overview 40

2 3

Slide 40
• LOW period determined by the longest clock LOW period
• HIGH period determined by shortest clock HIGH period
Slide 40 shows there are multiple ways to control I2C
DesignCon 2003 TecForum I2C Bus Overview 38
slaves.

Slide 38

16
 AN10216-01 I2C Manual
Pull-up Resistor calculation
DC Approach - Static Load
Worst Case scenario: maximum current load that the output transistor can
handle Æ 3 mA . This gives us the minimum pull-up resistor value
Vdd min - 0.4 V
R= With Vdd = 5V (min 4.5 V), Rmin = 1.3 kΩ
3 mA
AC Approach - Dynamic load
• maximum value of the rise time:
– 1µs for Standard-mode (100 kHz)
– 0.3 µs for Fast-mode (400 kHz)
• Dynamic load is defined by:
– device output capacitances V(t) = VDD (1-e -t /RC )
(number of devices) Rising time defined between
30% and 70%
– trace, wiring
Trise = 0.847.RC
DesignCon 2003 TecForum I2C Bus Overview
Slide 41
Slide 41 shows the typical resistor values needed for
proper operation. C is the total capacitance on either
SDA or SCL bus wire, with R as its pull-up resistor.
I2C Designer Benefits
• Functional blocks on the block diagram correspond
with the actual ICs; designs proceed rapidly from
block diagram to final schematic.
• No need to design bus interfaces because the I2C
bus interface is already integrated on-chip.
• Integrated addressing and data-transfer protocol
allow systems to be completely software-defined.
• The same IC types can often be used in many
different applications.
• Design-time reduces as designers quickly become
familiar with the frequently used functional blocks
represented by I2C bus compatible ICs.
• ICs can be added to or removed from a system
without affecting any other circuits on the bus.
• Fault diagnosis and debugging are simple;
malfunctions can be immediately traced.
• Assembling a library of reusable software modules
can reduce software development time.
I2C Manufacturers Benefits
• The simple 2-wire serial I2C bus minimizes
interconnections so ICs have fewer pins and there
are not so many PCB tracks; result - smaller and
less expensive PCBs
• The completely integrated I2C bus protocol
eliminates the need for address decoders and other
‘glue logic’
• The multi-master capability of the I2C bus allows
rapid testing/alignment of end-user equipment via
external connections to an assembly-line
• Increases system design flexibility by allowing
simple construction of equipment variants and easy
upgrading to keep design up-to-date
• The I2C bus is a de facto world standard that is
implemented in over 1000 different ICs (Philips
has > 400) and licensed to more than 70 companies
I2C Bus recovery
• Typical case is when masters fails when doing a read operation in a slave
• SDA line is then non usable anymore because of the “Slave-Transmitter”
mode.
• Methods to recover the SDA line are:
– Reset the slave device (assuming the device has a Reset pin)
– Use a bus recovery sequence to leave the “Slave-Transmitter” mode
• Bus recovery sequence is done as following:
1 - Send 9 clock pulses on SCL line
2 - Ask the master to keep SDA High until the “Slave-Transmitter” releases
the SDA line to perform the ACK operation
41
3 - Keeping SDA High during the ACK means that the “Master-Receiver”
does not acknowledge the previous byte receive
4 - The “Slave-Transmitter” then goes in an idle state
5 - The master then sends a STOP command initializing completely the
bus
DesignCon 2003 TecForum I2C Bus Overview 42
Slide 42
Slide 42 shows how a hung bus could be recovered.
The bus can become hung for several reasons, e.g.….
1. Incorrect power-up and/or reset procedure for
ICs
2. Power to a chip is interrupted – brown-outs etc
3. Noise on the wiring causes false clock or data
signals
I2C Protocol Summary
START
STOP
HIGH to LOW transition on SDA while SCL is HIGH
LOW to HIGH transition on SDA while SCL is HIGH
DATA 8-bit word, MSB first (Address, Control, Data)
- must be stable when SCL is HIGH
- can change only when SCL is LOW
- number of bytes transmitted is unrestricted
ACKNOWLEDGE - done on each 9th clock pulse during the HIGH period
- the transmitter releases the bus - SDA HIGH
- the receiver pulls DOWN the bus line - SDA LOW
CLOCK - Generated by the master(s)
- Maxim um speed specified but NO minimum speed
- A receiver can hold SCL LOW when performing
another function (transmitter in a Wait state)
ARBITRATION
- A master can slow down the clock for slow devices
- Master can start a transfer only if the bus is free
- Several masters can start a transfer at the same time
- Arbitration is done on SDA line
- Master that lost the arbitration must stop sending data
DesignCon 2003 TecForum I2C Bus Overview 43
Slide 43
Slide 43 provides a summary of the I2C protocol.
17
 AN10216-01 I2C Manual

I2C Summary - Advantages For example, in an application where 4 identical I2C

EEPROMs are used (EE1, EE2, EE3 and EE4), a four
• Simple Hardware standard
channel PCA9546 can be used. The master is plugged
• Simple protocol standard
• Easy to add / remove functions or devices (hardware and software)
to the main upstream bus while the 4 EEPROMs are
• Easy to upgrade applications
plugged to the 4 downstream channels (CH1, CH2,
• Simpler PCB: Only 2 traces required to communicate between devices
CH3 and CH4). If the master needs to perform an
• Very convenient for monitoring applications
operation on EE3, it will have to:
• Fast enough for all “Human Interfaces” applications
- Connect the upstream channel to CH3
– Displays, Switches, Keyboards
- Simply communicate with EE3.
– Control, Alarm systems
• Large number of different I2C devices in the semiconductors business EE1, EE2 and EE4 are electrically removed from the
• Well known and robust bus main I2C bus as long as CH3 is selected. Some of the
I2C multiplexers offer an Interrupt feature, allowing
DesignCon 2003 TecForum I2C Bus Overview 44
collection of the different downstream Interrupts
(generated by the downstream devices). An Interrupt
Slide 44 output provides the information (transition from High
to Low) to the master every time one or more Interrupt
Slide 44 summarizes the advantages of the I2C bus. is generated (transition from High to Low) by any of
the downstream devices.
Overcoming Previous Limitations

Address Conflicts I2C Multiplexers: Address Deconflict

How to solve I2C address conflicts? I2C EEPROM

1
I2C EEPROM
2

• I2C protocol limitation: when a device does not have its I2C address
programmable (fixed), only one same device can be plugged in the same MASTER
bus
Same I2C devices with same address

Î An I2 C multiplexer can be used to get rid of this limitation

I2C EEPROM I2C EEPROM
• It allows to split dynamically the main I2C in several sub-branches in order to 1 2
talk to one device at a time
• It is programmable through I2C so no additional pins are required for control I2C MULTIPLEXER
• More than one multiplexer can be plugged in the same I2C bus MASTER
The multiplexer allows to address 1 device
• Products then the other one
# of Channels Standard w/Interrupt Logic
DesignCon 2003 TecForum I2C Bus Overview 48
2 PCA9540 PCA9542/43
4 PCA9546 PCA9544/45
8 PCA9548
DesignCon 2003 TecForum I2C Bus Overview 47
Slide 48

Slide 47 The SCL/SDA upstream channel fans out to multiple

A 7 or 10-bit address that is unique to each device
identifies an I2C device.
This address can be:
• Partly fixed, part programmable (allowing to have
more than one of the same device on the same bus)
• Fully fixed allowing to have only one single same
device on the device.
If more than one same “non programmable” device
(fully fixed address) is required in a specific
application, it is then necessary to temporarily remove
the non-addressed device(s) from the bus when talking
with the targeted device. I2C multiplexers allow to
dynamically split the main I2C bus into 2, 4 or 8 sub-
I2C buses. Each sub-bus (downstream channel) can be
connected to the main bus (upstream channel) by a
simple 2-byte I2C command.
SCx/SDx channels that are selected by the
programmable control register. The I²C command is
sent via the main I²C bus and is used to select or
deselect the downstream channels.
The Multiplexers can select none or only one SCx/SDx
channels at a time since they were designed primarily
for address conflict resolution such as when multiple
devices with the same I2C address need to be attached
to the same I2C bus and you can only talk to one of the
devices at a time.
These devices are used in video projectors and server
applications. Other applications include:
• Address conflict resolution (e.g., SPD EEPROMs
on DIMMs).
• I2C sub-branch isolation

18
 AN10216-01 I2C Manual

• I2C bus level shifting (e.g., each individual
SCx/SDx channel can be operated at 1.8 V, 2.5 V,
3.3 V or 5.0 V if the device is powered at 2.5 V).
Interrupt logic inputs for each channel and a combined
output are included on every multiplexer and provide a
flag to the master for system monitoring. These devices
do not isolate the capacitive loading on either side of
the device so the designer must take into account all
trace and device capacitance on both sides of the device
and on any active channels. Pull up resistors must be
used on all channels
Capacitive Loading > 400 pF (isolation)
Multiplexers allow dynamic splitting of the overloaded
I2C bus into several sub-branches with a total capacitive
load smaller than the specified 400 pF. Note that this
method does not allow the master to access all the buses
at the same time. Only part of the bus will be accessible
at a time.
Multiplexers allow bus splitting but do not have a
buffering capability. Buffers and repeaters allow
increasing the total capacitive load beyond the 400 pF
without splitting the bus in several branches. If a
PCA9515 is used, the bus can be loaded up to 800 pF
with 400 pF on each side of the device.

How to go beyond I2C max cap load?

Practical case: Multi-card application
• I2C protocol limitation: the maximum capacitive load in a bus is 400 pF. If the
load is higher AC parameters will be violated.
• The following example shows how to build an application where:
Î An I2C multiplexer can be used to get rid of this limitation – Four identical control cards are used (same devices, same I2Caddress)
– Devices in each card are controlled through I2C
• It allows to split dynamically the main I2C in several sub-branches in order to – Each card monitors and controls some digital information
divide the bus capacitive load – Digital information is:
• It is programmable through I2C so no additional pins are required for control 1) Interrupt signals (Alarm monitoring)
• More than one multiplexer can be plugged in the same I2C bus 2) Reset signals (device initialization, Alarm Reset)
• LIMITATION: All the sub-branches cannot be addressed at the same time – Each card generates an Interrupt when one (or more) device generates
an Interrupt (Alarm condition detected)
• Products: – The master can handle only one Interrupt signal for all the application
# of Channels Standard w/Interrupt Logic
2 PCA9540 PCA9542/43
4 PCA9546 PCA9544/45
8 PCA9548
DesignCon 2003 TecForum I2C Bus Overview 51
DesignCon 2003 TecForum I2C Bus Overview 49

Slide 49 Slide 51

The I2C specification limits the maximum capacitive In this application, 4 identical cards are used. Identical
load in the bus to 400 pF. In applications where a means that the same devices are used, and that the I2C
higher capacitive load is required, 2 types of devices devices on each card have the same address. Each card
can be used: monitors and controls some specific signal and those
• I2C multiplexers and switches signals are controlled/monitored through the I2C bus by
• I2C buffers and repeaters using a PCA9554 type device.

In this application, each card monitors some alarm

I2C Multiplexers: Capacitive load split system’s sub system and controls some LEDs for visual
status. Each alarm, when triggered, generates an
500 pF Interrupt that is sent to the master for processing.
MASTER
PCA9554 collects the Interrupt signals and sends a
I2C bus “Card General Interrupt” to the master. When the
master processes the alarm, it sends a Reset signal to
200 pF
I2C bus 2
200 pF the corresponding alarm to clear it. Master receives
I2C bus 3 only an Interrupt signal, which is a combination of all
300 pF I2C MULTIPLEXER
300 pF
the Interrupt signals in the cards. Since the cards are
MASTER identical, it is then necessary to deconflict the different
I2C bus 1
100 pF addresses and isolate the cards that are not accessed.
The multiplexer splits the bus in two downstream 200
pF busses + 100 pF upstream PCA9544 in this application has 2 functions:
DesignCon 2003 TecForum I2C Bus Overview 50 • Deconflict the I2C addresses by creating 4 sub I2C
busses that can be isolated
Slide 50 • Collect the Interrupt from each card and propagate
a “General Interrupt” to the master

19
 Application Report
SLOA101 - August 2002

Introduction to the Controller Area Network (CAN)

Steve Corrigan HPL

ABSTRACT

A controller area network (CAN) is ideally suited to the many high-level industrial protocols
embracing CAN and ISO 11898 as their physical layer. Its cost, performance, and
upgradeability provide for tremendous flexibility in system design. This paper presents a brief
introduction to the CAN operating principles, the implementation of a basic CAN bus using
Texas Instrument’s CAN transceivers and DSPs, and a discussion of the robust error
detection and fault confinement mechanisms. Some of the properties of CAN, especially
relating to the electrical layer and features of transceiver products, are then discussed at a
tutorial level.

Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 The CAN Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Standard CAN or Extended CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 The Bit Fields of Standard CAN and Extended CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 Standard CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.2 Extended CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 A CAN Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Message Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2.1 The Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2.2 The Remote Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.3 The Error Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.4 The Overload Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Error Checking and Fault Confinement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 The CAN Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 CAN Transceiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.2 High Short-Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.3 High ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.4 Wide Common-Mode Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.5 Common-Mode Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.6 High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.7 Controlled Driver Output Transition Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.8 Low Current Standby and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.9 Thermal Shutdown Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.10 Glitch Free Power Up and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Trademarks are the property of their respective owners.

1
SLOA101

5.1.11 Unpowered Node Does Not Disturb the Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 The Relationship Between Bus Length and Signaling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7 Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

List of Figures
1 The Layered ISO 11898 Standard Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Standard CAN: 11-Bit Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Extended CAN: 29-Bit Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 The Inverted Logic of a CAN Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Arbitration on a CAN Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6 Details of an Electronic Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 CAN Dominant and Recessive Bus States of the SN65HVD230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8 CAN Bus Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9 CAN Test Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10 3.3-V CAN Transceiver Power Savings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
11 Common-Mode Noise Coupled onto 4 Twisted-Pair Bus Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

List of Tables
1 CAN Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Maximum Signaling Rates for Various Cable Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2 Introduction to the Controller Area Network (CAN)

 SLOA101

1 Introduction
The CAN bus was developed by BOSCH1 as a multi-master, message broadcast system that
specifies a maximum signaling rate of 1M bit per second (bps). Unlike a traditional network such
as USB or Ethernet, CAN does not send large blocks of data point-to-point from node A to node
B under the supervision of a central bus master. In a CAN network many short messages like
temperature or RPM are broadcast to the entire network, which allows for data consistency in
every node of the system.
This application report explains the CAN message format, message identifiers, and bit-wise
arbitration—a major benefit of the CAN signaling scheme. CAN bus implementation is examined
and typical waveforms are presented.

2 The CAN Standard

CAN is an International Standardization Organization (ISO) defined serial communications bus
originally developed for the automotive industry to replace the complex wiring harness with a
two-wire bus. The specification calls for signaling rates up to 1 Mbps, high immunity to electrical
interference, and an ability to self-diagnose and repair data errors. These features have led to
CAN’s popularity in a variety of industries including automotive, marine, medical, manufacturing,
and aerospace.
The CAN communications protocol, ISO 11898, describes how information is passed between
devices on a network, and conforms to the Open Systems Interconnection (OSI) model that is
defined in terms of layers. Actual communication between devices connected by the physical
medium is defined by the physical layer of the model. The ISO 11898 architecture defines the
lowest two layers of the seven layer OSI/ISO model as the data-link layer and physical layer in
Figure 1.
DSP
Application Layer or
Controller

Logic Link Control

Data-Link
Embedded
Layer CAN Controller,
Medium Access Control CAN
Controller Embedded or Separate
Physical Signaling
Physical
Layer Physical Medium Attchment
Electrical Specifications:
CAN Transceivers, Connectors,
Medium Dependant Interface Transceiver Cable

CAN Bus-Line
ISO 11898 Specification Implementation

Figure 1. The Layered ISO 11898 Standard Architecture

1 Robert Bosch GmbH, www.bosch.com

Introduction to the Controller Area Network (CAN) 3

SLOA101

In Figure 1, the application layer establishes the communication link to an upper-level

application specific protocol such as the vendor independent CANopen protocol. This protocol is
supported by the international users and manufacturers group, CAN in Automation (CiA).
Additional CAN information is located at the CiA website, can-cia.de. There are many similar
emerging protocols dedicated to particular applications like industrial automation or aviation.
Examples of industry-standard CAN-based protocols are KVASER’s CAN Kingdom,
Allen-Bradley’s DeviceNet and Honeywell’s Smart Distributed System (SDS).

3 Standard CAN or Extended CAN

The CAN communication protocol is a carrier-sense multiple-access protocol with collision
detection and arbitration on message priority (CSMA/CD+AMP). CSMA means that each node
on a bus must wait for a prescribed period of inactivity before attempting to send a message.
CD+AMP means that collisions are resolved through a bit-wise arbitration, based upon a
preprogrammed priority of each message in the identifier field of a message. The higher priority
identifier always wins bus access.
The first version of the CAN standards listed in Table 1, ISO 11519 (Low-Speed CAN) is for
applications up to 125 kbps with a standard 11-bit identifier. The second version, ISO 11898
(1993), also with 11-bit identifiers provides for signaling rates from 125 kbps to 1 Mbps while the
more recent ISO 11898 amendment (1995) introduces the extended 29-bit identifier. The ISO
11898 11-bit version is often referred to as Standard CAN Version 2.0A, while the ISO 11898
amendment is referred to as Extended CAN Version 2.0B. The Standard CAN 11-bit identifier
field in Figure 2 provides for 211, or 2048 different message identifiers, while the Extended CAN
29-bit identifier in Figure 3 provides for 229, or 537 million identifiers.

Table 1. CAN Versions

NOMENCLATURE STANDARD MAX. SIGNALING RATE IDENTIFIER
Low–Speed CAN ISO 11519 125 kbps 11-bit
CAN 2.0A ISO 11898:1993 1 Mbps 11-bit
CAN 2.0B ISO 11898:1995 1 Mbps 29-bit

3.1 The Bit Fields of Standard CAN and Extended CAN

3.1.1 Standard CAN

S R I E I
O 11-Bit Identifier T D r0 DLC 0. . .8 Bytes Data CRC ACK O F
F R E F S

Figure 2. Standard CAN: 11-Bit Identifier

The meaning of the bit fields of Figure 2 are:

• SOF—The single dominant start of frame (SOF) bit marks the start of a message, and is
used to synchronize the nodes on a bus after being idle.
• Identifier—The Standard CAN 11-bit identifier establishes the priority of the message. The
lower the binary value, the higher its priority.

4 Introduction to the Controller Area Network (CAN)

 SLOA101

• RTR—The single remote transmission request (RTR) bit is dominant when information is
required from another node. All nodes receive the request, but the identifier determines the
specified node. The responding data is also received by all nodes and used by any node
interested. In this way all data being used in a system is uniform.
• IDE—A dominant single identifier extension (IDE) bit means that a standard CAN identifier
with no extension is being transmitted.
• r0—Reserved bit (for possible use by future standard amendment).
• DLC—The 4-bit data length code (DLC) contains the number of bytes of data being
transmitted.
• Data—Up to 64 bits of application data may be transmitted.
• CRC—The 16-bit (15 bits plus delimiter) cyclic redundancy check (CRC) contains the
checksum (number of bits transmitted) of the preceding application data for error detection.
• ACK—Every node receiving an accurate message overwrites this recessive bit in the original
message with a dominate bit, indicating an error-free message has been sent. Should a
receiving node detect an error and leave this bit recessive, it discards the message and the
sending node repeats the message after rearbitration. In this way each node acknowledges
(ACK) the integrity of its data. ACK is 2 bits, one is the acknowledgement bit and the second
is a delimiter.
• EOF—This end-of-frame (EOF) 7-bit field marks the end of a CAN frame (message) and
disables bit–stuffing, indicating a stuffing error when dominant. When 5 bits of the same logic
level occur in succession during normal operation, a bit of the opposite logic level is stuffed
into the data.
• IFS—This 7-bit inter-frame space (IFS) contains the amount of time required by the
controller to move a correctly received frame to its proper position in a message buffer area.

3.1.2 Extended CAN

S S I R E I
O 11-Bit Identifier R D 18-Bit Identifier T r1 r0 DLC 0. . .8 Bytes Data CRC ACK O F
F R E R F S

Figure 3. Extended CAN: 29-Bit Identifier

As shown in Figure 3, the Extended CAN message is the same as the Standard message with
the addition of:
• SRR—The substitute remote request (SRR) bit replaces the RTR bit in the standard
message location as a placeholder in the extended format.
• IDE—A recessive bit in the identifier extension (IDE) indicates that there are more identifier
bits to follow. The 18-bit extension follows IDE.
• r1—Following the RTR and r0 bits, an additional reserve bit has been included ahead of the
DLC bit.

Introduction to the Controller Area Network (CAN) 5

SLOA101

4 A CAN Message

4.1 Arbitration
A fundamental CAN characteristic shown in Figure 4 is the opposite logic state between the bus,
and the driver input and receiver output. Normally a logic high is associated with a one, and a
logic low is associated with a zero—but not so on a CAN bus. This is why it is desirable to have
the driver input and receiver output pins of a CAN transceiver passively pulled high internally, as
in the SN65HVD230. In the absence of any input, the device automatically defaults to a
recessive bus state on all input and output pins.
V(CANH)
CANH
D = 101
V(CANL)
CANL

1 0 1
R = 101 Recessive Dominant Recessive

Figure 4. The Inverted Logic of a CAN Bus

Bus access is event-driven and takes place randomly. If two nodes try to occupy the bus
simultaneously, access is implemented with a nondestructive, bit-wise arbitration.
Nondestructive means that the node winning arbitration just continues on with the message,
without the message being destroyed or corrupted by another node.
The allocation of priority to messages in the identifier is a feature of CAN that makes it
particularly attractive for use within a real-time control environment. The lower the binary
message identifier number, the higher its priority. An identifier consisting entirely of zeros is the
highest priority message on a network since it holds the bus dominant the longest. Therefore, if
two nodes begin to transmit simultaneously, the node that sends a zero (dominant) while the
other nodes send a one (recessive) gets control of the CAN bus and goes on to complete its
message. A dominant bit always overwrites a recessive bit on a CAN bus.
Note that a node constantly monitors its own transmission. This is the reason for the transceiver
configuration of Figure 4 in which the CANH and CANL output pins of the driver are internally
tied to the receiver’s input. The propagation delay of a signal in the internal loop from the driver
input to the receiver output is typically used as a qualitative measure of a CAN transceiver. This
propagation delay is referred to as the loop time (tLOOP in a TI data sheet), but takes on varied
nomenclature from vendor to vendor.
Figure 5 displays the arbitration process. Since the nodes continuously monitor their own
transmissions, when the node B recessive bit is overwritten by node C’s higher priority dominant
bit, B detects that the bus state does not match the bit that it transmitted. Therefore, node B
halts transmission while node C continues on with its message. Another attempt to transmit the
message is made by node B once the bus is released by node C. This functionality is part of the
ISO 11898 physical signaling layer, which means that it is contained entirely within the CAN
controller and is completely transparent to a CAN user.

6 Introduction to the Controller Area Network (CAN)

 SLOA101

C Wins B Wins
Arbitration Arbitration

Node C
Transmits

Node B
Transmits

CAN Bus

Figure 5. Arbitration on a CAN Bus

The allocation of message priority is up to a system designer, but industry groups mutually agree
upon the significance of certain messages. For example, a manufacturer of motor drives may
specify that message 0010 is a winding current feedback signal from a motor on a CAN network
and that 0011 is the tachometer speed. Since 0010 has the lowest binary identifier, messages
relating to current values always have a higher priority on the bus than those concerned with
tachometer readings.
In the case of DeviceNetTM, devices from many manufacturers such as proximity switches and
temperature sensors can be incorporated into the same system. Since the messages generated
by DeviceNet sensors have been predefined by their professional association, the Open
DeviceNet Vendors Association (ODVA), a certain message always relates to the specific type of
sensor such as temperature, regardless of the actual manufacturer.

4.2 Message Types

There are four different message types, or frames (Figures 2 and 3) that can be transmitted on a
CAN bus: the data frame, the remote frame, the error frame, and the overload frame. A
message is considered to be error free when the last bit of the ending EOF field of a message is
received in the error–free recessive state. A dominant bit in the EOF field causes the transmitter
to repeat a transmission.

4.2.1 The Data Frame

The data frame is the most common message type, and is made up by the arbitration field, the
data field, the CRC field, and the acknowledgement field. The arbitration field determines the
priority of a message when two or more nodes are contending for the bus. The arbitration field
contains an 11-bit identifier for CAN 2.0A in Figure 2 and the RTR bit, which is dominant for data
frames. For CAN 2.0B in Figure 3 it contains the 29-bit identifier and the RTR bit. Next is the
data field which contains zero to eight bytes of data, and the CRC field which contains the 16-bit
checksum used for error detection. Lastly, there is the acknowledgement field. Any CAN
controller that is able to correctly receive a message sends a dominant ACK bit that overwrites
the transmitted recessive bit at the end of correct message transmission. The transmitter checks
for the presence of the dominant ACK bit and retransmits the message if no acknowledge is
detected.

Introduction to the Controller Area Network (CAN) 7

SLOA101

4.2.2 The Remote Frame

The intended purpose of the remote frame is to solicit the transmission of data from another
node. The remote frame is similar to the data frame, with two important differences. First, this
type of message is explicitly marked as a remote frame by a recessive RTR bit in the arbitration
field, and secondly, there is no data.

4.2.3 The Error Frame

The error frame is a special message that violates the formatting rules of a CAN message. It is
transmitted when a node detects an error in a message, and causes all other nodes in the
network to send an error frame as well. The original transmitter then automatically retransmits
the message. There is an elaborate system of error counters in the CAN controller which
ensures that a node cannot tie up a bus by repeatedly transmitting error frames.

4.2.4 The Overload Frame

The overload frame is mentioned here for completeness. It is similar to the error frame with
regard to the format, and it is transmitted by a node that becomes too busy. It is primarily used to
provide for an extra delay between messages.

4.3 Error Checking and Fault Confinement

The robustness of CAN may be attributed in part to its abundant error checking procedures. The
CAN protocol incorporates five methods of error checking: three at the message level and two at
the bit level. If a message fails with any one of these error detection methods, it is not accepted
and an error frame is generated from the receiving nodes, causing the transmitting node to
resend the message until it is received correctly. However, if a faulty node hangs up a bus by
continuously repeating an error, its transmit capability is removed by its controller after an error
limit is reached.

At the message level are the CRC and the ACK slots displayed in Figures 2 and 3. The 16-bit
CRC contains the checksum of the preceding application data for error detection with a 15-bit
checksum and 1-bit delimiter. The ACK field is two bits long and consists of the acknowledge bit
and an acknowledge delimiter bit. Finally, at the message level there is a form check. This check
looks for fields in the message which must always be recessive bits. If a dominant bit is
detected, an error is generated. The bits checked are the SOF, EOF, ACK delimiter, and the
CRC delimiter bits.

At the bit level each bit transmitted is monitored by the transmitter of the message. If a data bit
(not arbitration bit) is written onto the bus and its opposite is read, an error is generated. The
only exceptions to this are with the message identifier field which is used for arbitration, and the
acknowledge slot which requires a recessive bit to be overwritten by a dominant bit. The final
method of error detection is with the bit stuffing rule where after five consecutive bits of the same
logic level, if the next bit is not a compliment, an error is generated. Stuffing ensures rising
edges available for on-going synchronization of the network, and that a stream of recessive bits
are not mistaken for an error frame, or the seven-bit interframe space that signifies the end of a
message. Stuffed bits are removed by a receiving node’s controller before the data is forwarded
to the application.

8 Introduction to the Controller Area Network (CAN)

 SLOA101

With this logic, an active error frame consists of six dominant bits—violating the bit stuffing rule.
This is interpreted as an error by all of the CAN nodes which then generate their own error
frame. This means that an error frame can be from the original six bits to twelve bits long with all
the replies. This error frame is then followed by a delimiter field of eight recessive bits and a bus
idle period before the corrupted message is retransmitted. It is important to note that the
retransmitted message still has to contend for arbitration on the bus.

5 The CAN Bus

The data link and physical signaling layers of Figure 1, which are normally transparent to a
system operator, are included in any controller that implements the CAN protocol, such as Texas
Instruments’ TMS320LF2407 3.3-V DSP with integrated CAN controller. Connection to the
physical medium is then implemented through a line transceiver such as TI’s SN65HVD230
3.3-V CAN transceiver to form what the ISO–11898 standard refers to as an electronic control
unit (ECU) in Figure 6.

Electronic Control Unit (ECU)

TMS320LF2407A

CAN–Controller

CANTX/IOPC6 CANRX/IOPC7

D R
SN65HVD230

CANH CANL

CAN Bus–Line

Figure 6. Details of an Electronic Control Unit

Signaling is differential which is where CAN derives its robust noise immunity and fault
tolerance. Balanced differential signaling reduces noise coupling and allows for high signaling
rates over twisted-pair cable. Balanced means that the current flowing in each signal line is
equal but opposite in direction, resulting in a field-canceling effect that is a key to low noise
emissions. The use of balanced differential receivers and twisted-pair cabling enhance the
common-mode rejection and high noise immunity of a CAN bus.
The two signal lines of the bus, CANH and CANL, in the quiescent recessive state, are passively
biased to ≈ 2.5 V. The dominant state on the bus takes CANH ≈ 1 V higher to ≈ 3.5 V, and takes
CANL ≈ 1 V lower to ≈ 1.5 V creating a typical 2-V differential signal as displayed in Figure 7.

Introduction to the Controller Area Network (CAN) 9

 Introduction to AMBA AXI4 102202
Issue 01

1 Overview
This guide introduces the main features of Advanced Microcontroller Bus Architecture (AMBA) AXI4,
highlighting the differences from the previous version AXI3. The guide explains the key concepts and
details that help you implement the AXI4 protocol.

In this guide, we describe:

• What AMBA is.
• Why AMBA is so popular in modern SoC design.
• The concepts of transfers and transactions, which underpin how AMBA operates.
• The different channel signals and the functionality that they provide.
• Exclusive access transfers, which allow multiple masters to access the same slave at the same
time.
• The rules and conditions that the AMBA protocol dictates.
• The key attributes and support for common elements like mixed endian structures.

At the end of this guide, you can Check your knowledge.

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2 What is AMBA, and why use it?

The Arm Advanced Microcontroller Bus Architecture, or AMBA, is an open-standard, on-chip
interconnect specification for the connection and management of functional blocks in system-on-a-
chip (SoC) designs.

Essentially, AMBA protocols define how functional blocks communicate with each other.

The following diagram shows an example of an SoC design. This SoC has several functional blocks that
use AMBA protocols like AXI4 and AXI3 to communicate with each other:

2.1 Where is AMBA used?

AMBA simplifies the development of designs with multiple processors and large numbers of
controllers and peripherals. However, the scope of AMBA has increased over time, going far beyond
just microcontroller devices.

Today, AMBA is widely used in a range of ASIC and SoC parts. These parts include applications
processors that are used in devices like IoT subsystems, smartphones, and networking SoCs.

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2.2 Why use AMBA?

AMBA provides several benefits:
• Efficient IP reuse
IP reuse is an essential component in reducing SoC development costs and timescales. AMBA
specifications provide the interface standard that enables IP reuse. Therefore, thousands of SoCs,
and IP products, are using AMBA interfaces.
• Flexibility
AMBA offers the flexibility to work with a range of SoCs. IP reuse requires a common standard
while supporting a wide variety of SoCs with different power, performance, and area
requirements. Arm offers a range of interface specifications that are optimized for these different
requirements.
• Compatibility
A standard interface specification, like AMBA, allows compatibility between IP components from
different design teams or vendors.
• Support
AMBA is well supported. It is widely implemented and supported throughout the semiconductor
industry, including support from third-party IP products and tools.
Bus interface standards like AMBA, are differentiated through the performance that they enable. The
two main characteristics of bus interface performance are:
• Bandwidth
The rate at which data can be driven across the interface. In a synchronous system, the maximum
bandwidth is limited by the product of the clock speed and the width of the data bus.
• Latency
The delay between the initiation and completion of a transaction. In a burst-based system, the
latency figure often refers to the completion of the first transfer rather than the entire burst.
The efficiency of your interface depends on the extent to which it achieves the maximum bandwidth
with zero latency.

2.3 How has AMBA evolved?

AMBA has evolved over the years to meet the demands of processors and new technologies, as
shown in the following diagram:

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AMBA1 AMBA2 AMBA3 AMBA4 AMBA5

CHI

ACE

ACE-Lite

AXI3 AXI4

AXI-Lite

AXI4-Stream

ATB

AHB AHB-Lite AHB5

ASB

APB APB 2 APB 3 APB 4

1996 1999 2003 2010 2011 2014 2016

2.3.1 AMBA 1
Arm introduced AMBA in the late 1990s. The first AMBA buses were the Advanced System Bus (ASB)
and the Advanced Peripheral Bus (APB). ASB has been superseded by more recent protocols, while
APB is still widely used today.

APB is designed for low-bandwidth control accesses, for example, register interfaces on system
peripherals. This bus has a simple address and data phase and a low complexity signal list.

2.3.2 AMBA 2
In 1999, AMBA 2 added the AMBA High-performance Bus (AHB), which is a single clock-edge
protocol. A simple transaction on the AHB consists of an address phase and a subsequent data phase.
Access to the target device is controlled through a MUX, admitting access to one master at a time.
AHB is pipelined for performance, while APB is not pipelined for design simplicity.

2.3.3 AMBA 3
In 2003, Arm introduced the third generation, AMBA 3, which includes ATB and AHB-Lite.

Advanced Trace Bus (ATB), is part of the CoreSight on-chip debug and trace solution.

AHB-Lite is a subset of AHB. This subset simplifies the design for a bus with a single master.

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Introduction to AMBA AXI4 102202
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Advanced eXtensible Interface (AXI), the third generation of AMBA interface defined in the AMBA 3
specification, is targeted at high performance, high clock frequency system designs. AXI includes
features that make it suitable for high-speed submicrometer interconnect.

2.3.4 AMBA 4
In 2010, the AMBA 4 specifications were introduced, starting with AMBA 4 AXI4 and then AMBA 4
AXI Coherency Extensions (ACE) in 2011.

ACE extends AXI with additional signaling introducing system-wide coherency. This system-wide
coherency allows multiple processors to share memory and enables technology like big.LITTLE
processing. At the same time, the ACE-Lite protocol enables one-way coherency. One-way coherency
enables a network interface to read from the caches of a fully coherent ACE processor.

The AXI4-Stream protocol is designed for unidirectional data transfers from master to slave with
reduced signal routing, which is ideal for implementation in FPGAs.

2.3.5 AMBA 5
In 2014, the AMBA 5 Coherent Hub Interface (CHI) specification was introduced, with a redesigned
high-speed transport layer and features designed to reduce congestion. There have been several
editions of the CHI protocol, and each new version adds new features.

In 2016, the AHB-Lite protocol was updated to AHB5, to complement the Armv8-M architecture, and
extend the TrustZone security foundation from the processor to the system.

In 2019, the AMBA Adaptive Traffic Profiles (ATP) was introduced. ATP complements the existing
AMBA protocols and is used for modeling high-level memory access behavior in a concise, simple, and
portable way.

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3 AXI protocol overview

AXI is an interface specification that defines the interface of IP blocks, rather than the interconnect
itself.

The following diagram shows how AXI is used to interface an interconnect component:

AXI
Master

AXI
Slave
AXI
Interconnect
component
AXI
Master

AXI
Slave

In AX3 and AXI4, there are only two AXI interface types, master and slave. These interface types are
symmetrical. All AXI connections are between master interfaces and slave interfaces.

AXI interconnect interfaces contain the same signals, which makes integration of different IP
relatively simple. The previous diagram shows how AXI connections join master and slave interfaces.
The direct connection gives maximum bandwidth between the master and slave components with no
extra logic. And with AXI, there is only a single protocol to validate.

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3.1 AXI in a multi-master system

The following diagram shows a simplified example of an SoC system, which is composed of masters,
slaves, and the interconnect that links them all:

Master 1 Master 2

Inter-connection a rchitecture

Slave 1
Completer Slave 2 Slave 3 Slave 4

AXI Protocol
Master interface

Slave interface

An Arm processor is an example of a master, and a simple example of a slave is a memory controller.

The AXI protocol defines the signals and timing of the point-to-point connections between masters
and slaves.

The AXI protocol is a point-to-point specification, not a bus specification. Therefore, it describes only
the signals and timing between interfaces.

The previous diagram shows that each AXI master interface is connected to a single AXI slave
interface. Where multiple masters and slaves are involved, an interconnect fabric is required. This
interconnect fabric also implements slave and master interfaces, where the AXI protocol is
implemented.

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The following diagram shows that the interconnect is a complex element that requires its own AXI
master and slave interfaces to communicate with external function blocks:

The following diagram shows an example of an SoC with various processors and function blocks:

The previous diagram shows all the connections where AXI is used. You can see that AXI3 and AXI4
are used within the same SoC, which is common practice. In such cases, the interconnect performs the
protocol conversion between the different AXI interfaces.

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3.2 AXI channels

The AXI specification describes a point-to-point protocol between two interfaces: a master and a
slave.

The following diagram shows the five main channels that each AXI interface uses for communication:

Write Address ( AW)

Write Data (W)

Write Response (B)

Master Slave

Read Address (AR)

Read Data (R)

Write operations use the following channels:

• The master sends an address on the Write Address (AW) channel and transfers data on the Write
Data (W) channel to the slave.

• The slave writes the received data to the specified address. Once the slave has completed the
write operation, it responds with a message to the master on the Write Response (B) channel.

Read operations use the following channels:

• The master sends the address it wants to read on the Read Address (AR) channel.
• The slave sends the data from the requested address to the master on the Read Data (R) channel.

The slave can also return an error message on the Read Data (R) channel. An error occurs if, for
example, the address is not valid, or the data is corrupted, or the access does not have the right
security permission.

Each channel is unidirectional, so a separate Write Response channel is needed to pass responses
back to the master. However, there is no need for a Read Response channel, because a read
response is passed as part of the Read Data channel.

Using separate address and data channels for read and write transfers helps to maximize the
bandwidth of the interface. There is no timing relationship between the groups of read and write
channels. This means that a read sequence can happen at the same time as a write sequence.

Each of these five channels contains several signals, and all these signals in each channel have the
prefix as follows:

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• AW for signals on the Write Address channel

• AR for signals on the Read Address channel
• W for signals on the Write Data channel
• R for signals on the Read Data channel
• B for signals on the Write Response channel

B stands for buffered, because the response from the slave happens after all writes have completed.

3.3 Main AXI features

The AXI protocol has several key features that are designed to improve bandwidth and latency of data
transfers and transactions, as you can see here:

Independent read and write channels

AXI supports two different sets of channels, one for write operations, and one for read operations.
Having two independent sets of channel helps to improve the bandwidth performances of the
interfaces. This is because read and write operations can happen at the same time.

Multiple outstanding addresses

AXI allows for multiple outstanding addresses. This means that a master can issue transactions
without waiting for earlier transactions to complete. This can improve system performance
because it enables parallel processing of transactions.

No strict timing relationship between address and data operations

With AXI, there is no strict timing relationship between the address and data operations. This
means that, for example, a master could issue a write address on the Write Address channel, but
there is no time requirement for when the master has to provide the corresponding data to write
on the Write Data channel.

Support for unaligned data transfers

For any burst that is made up of data transfers wider than one byte, the first bytes accessed can
be unaligned with the natural address boundary. For example, a 32-bit data packet that starts at a
byte address of 0x1002 is not aligned to the natural 32-bit address boundary.

Out-of-order transaction completion

Out-of-order transaction completion is possible with AXI. The AXI protocol includes transaction
identifiers, and there is no restriction on the completion of transactions with different ID values.

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This means that a single physical port can support out-of-order transactions by acting as several
logical ports, each of which handles its transactions in order.

Burst transactions based on start address

AXI masters only issue the starting address for the first transfer. For any following transfers, the
slave will calculate the next transfer address based on the burst type.

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4 Channel transfers and transactions

This section explains the handshake principle for AXI channels, and shows how the handshake is the
underpinning mechanism for all read and write transactions.

4.1 Channel handshake

The AXI4 protocol defines five different channels, as described in AXI channels. All of these channels
share the same handshake mechanism that is based on the VALID and READY signals, as shown in the
following diagram:

Valid

Destination
Source

Ready

The VALID signal goes from the source to the destination, and READY goes from the destination to
the source.

Whether the source or destination is a master or slave depends on which channel is being used. For
example, the master is a source for the Read Address channel, but a destination for the Read Data
channel.

The source uses the VALID signal to indicate when valid information is available. The VALID signal
must remain asserted, meaning set to high, until the destination accepts the information. Signals that
remain asserted in this way are called sticky signals.

The destination indicates when it can accept information using the READY signal. The READY signal
goes from the channel destination to the channel source.

This mechanism is not an asynchronous handshake, and requires the rising edge of the clock for the
handshake to complete.

4.2 Differences between transfers and transactions

When designing interconnect fabric, you must know the capabilities of the masters and slaves that are
being connected. Knowing this information lets you include sufficient buffering, tracking, and decode
logic to support the various data transfer ordering possibilities that allow performance improvements
in faster devices.

Using standard terminology makes understanding the interactions between connected components
easier. AXI makes a distinction between transfers and transactions:

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• A transfer is a single exchange of information, with one VALID and READY handshake. The
following diagram shows a transfer:

• A transaction is an entire burst of transfers, containing an address transfer, one or more data
transfers, and, for write sequences, a response transfer. The following diagram shows a
transaction:

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4.3 Channel transfer examples

This section examines some examples of possible handshakes between source and destination. It
shows several possible combinations of VALID and READY sequences that conform to the AXI
protocol specifications.

In the first example, shown in the following diagram, we have a clock signal, followed by an
information bus, and then the VALID and READY signals:

This example has the following sequence of events:

1. In clock cycle 2, the VALID signal is asserted, indicating that the data on the information channel is
valid.
2. In clock cycle 3, the following clock cycle, the READY signal is asserted.
3. The handshake completes on the rising edge of clock cycle 4, because both READY and VALID
signals are asserted.

The following diagram shows another example:

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This example has the following sequence of events:

1. In clock cycle 1, the READY signal is asserted.
2. The VALID signal is not asserted until clock cycle 3.
3. The handshake completes on the rising edge of clock cycle 4, when both VALID and READY are
asserted.

The final example shows both VALID and READY signals being asserted during the clock cycle 3, as
seen in the following diagram:

Again, the handshake completes on the rising edge of clock cycle 4, when both VALID and READY are
asserted.

In all three examples, information is passed down the channel when READY and VALID are asserted
on the rising edge of the clock signal.

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Read and write handshakes must adhere to the following rules:

• A source cannot wait for READY to be asserted before asserting VALID.
• A destination can wait for VALID to be asserted before asserting READY.

These rules mean that READY can be asserted before or after VALID, or even at the same time.

4.4 Write transaction: single data item

This section describes the process of a write transaction for a single data item, and the different
channels that are used to complete the transaction.

This write transaction involves the following channels:

• Write Address (AW)
• Write (W)
• Write Response (B)
First, there is a handshake on the Write Address (AW) channel, as shown in the following diagram:

Clock c ycle 1 2 3 4 n n+1 n+2 n+3

ACLK
AW channel

AWADDR Address
AWVALID
AWREADY

WDATA
W channel

WVALID

WREADY

WLAST

BRESP
B channel

BVALID

BREADY

This handshake is where the master communicates the address of the write to the slave. The
handshake has the following sequence of events:
1. The master puts the address on AWADDR and asserts AWVALID in clock cycle 2.
2. The slave asserts AWREADY in clock cycle 3 to indicate its ability to receive the address value.
3. The handshake completes on the rising edge of clock cycle 4.

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Introduction to AMBA AXI4 102202
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After this first handshake, the master transfers the data to the slave on the Write (W) channel, as
shown in the following diagram:

Clock c ycle 1 2 3 4 n n+1 n+2 n+3

ACLK
AW channel

AWADDR Address
AWVALID
AWREADY

WDATA Data
W channel

WVALID

WREADY

WLAST

BRESP
B channel

BVALID

BREADY

The data transfer has the following sequence of events:

1. The slave is waiting for data with WREADY set to high in clock cycle n.
2. The master puts the data on the WDATA bus and asserts WVALID in clock cycle n+2.
3. The handshake completes on the rising edge of clock cycle n+3

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Introduction to AMBA AXI4 102202
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Finally, the slave uses the Write Response (B) channel, to confirm that the write transaction has
completed once all WDATA has been received. This response is shown in the following diagram:

Clock c ycle 1 2 3 4 n n+1 n+2 n+3

ACLK
AW channel

AWADDR Address
AWVALID
AWREADY

WDATA Data
W channel

WVALID

WREADY

WLAST

BRESP Okay
B channel

BVALID

BREADY

The write response has the following sequence of events:

1. The master asserts BREADY.
2. The slave drives BRESP to indicate success or failure of the write transaction, and asserts
BVALID.
The handshake completes on the rising edge of clock cycle n+3.

4.5 Write transaction: multiple data items

AXI is a burst-based protocol, which means that it is possible to transfer multiple data in a single
transaction. We can transfer a single address on the AW channel to transfer multiple data, with
associated burst width and length information.

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The following diagram shows an example of a multiple data transfer:

Clock c ycle 1 2 3 4 5 6 7 8 9 10 11 12

ACLK
AW channel

AWADDR Address
AWVALID
AWREADY

WDATA Data Data Data

W channel

WVALID

WREADY

WLAST

BRESP Okay
B channel

BVALID

BREADY

In this case, the AW channel indicates a sequence of three transfers, and on the W channel, we see
three data transfers.

The master drives the WLAST high to indicate the final WDATA. This means that the slave can either
count the data transfers or just monitor WLAST.

Once all WDATA transfers are received, the slave gives a single BRESP value on the B channel. One
single BRESP covers the entire burst. If the slave decides that any of the transfers contain an error, it
must wait until the entire burst has completed before it informs the master that an error occurred.

4.6 Read transaction: single data item

This section looks in detail at the process of a read transaction for a single data item, and the different
channels used to complete the transaction.

This write transaction involves the following channels:

• Read Address (AR)
• Read (R)

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First, there is a handshake on the Read Address (AR) channel, as shown in the following diagram:

Clock c ycle 1 2 3 4 5 n n+1 n+2 n+3

ACLK

ARADDR Address
AR channel

ARVALID
ARREADY

RDATA
R channel

RVALID

RREADY

RLAST

RRESP

The handshake has the following sequence of events:

1. In clock cycle 2, the master communicates the address of the read to the slave on ARADDR and
asserts ARVALID.
2. In clock cycle 3, the slave asserts ARREADY to indicate that it is ready to receive the address
value.
The handshake completes on the rising edge of clock cycle 4.
Next, on the Read (R) channel, the slave transfers the data to the master. The following diagram
shows the data transfer process:

Clock c ycle 1 2 3 4 5 n n+1 n+2 n+3

ACLK

ARADDR Address
AR channel

ARVALID
ARREADY

RDATA Data
R channel

RVALID

RREADY

RLAST

RRESP Okay

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Introduction to AMBA AXI4 102202
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The data transfer handshake has the following sequence of events:

1. In clock cycle n, the master indicates that it is waiting to receive the data by asserting RREADY.
2. The slave retrieves the data and places it on RDATA in clock cycle n+2. In this case, because this is
a single data transaction, the slave also sets the RLAST signal to high.
At the same time, the slave uses RRESP to indicate the success or failure of the read transaction
to the master, and asserts RVALID.
3. Because RREADY is already asserted by the master, the handshake completes on the rising edge
of clock cycle n+3.

4.7 Read transaction: multiple data items

The AXI protocol also allows a read burst of multiple data transfer in the same transaction. This is
similar to the write burst that is described in Write transaction: multiple data items.

The following diagram shows an example of a burst read transfer:

ACLK

ARADDR Address
AR channel

ARVALID
ARREADY

RDATA Data Data Data

R channel

RVALID

RREADY

RLAST

RRESP Okay Okay Okay

In this example, we transfer a single address on the AR channel to transfer multiple data items, with
associated burst width and length information.

Here, the AR channel indicates a sequence of three transfers, therefore on the R channel, we see
three data transfers from the slave to the master.

On the R channel, the slave transfers the data to the master. In this example, the master is waiting for
data as shown by RREADY set to high. The slave drives valid RDATA and asserts RVALID for each
transfer.

One difference between a read transaction and a write transaction is that for a read transaction there
is an RRESP response for every transfer in the transaction. This is because, in the write transaction,
the slave has to send the response as a separate transfer on the B channel. In the read transaction, the
slave uses the same channel to send the data back to the master and to indicate the status of the read
operation.

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Introduction to AMBA AXI4 102202
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If an error is indicated for any of the transfers in the transaction, the full indicated length of the
transaction must still be completed. There is no such thing as early burst termination.

4.8 Active transactions

Active transactions are also known as outstanding transactions.

An active read transaction is a transaction for which the read address has been transferred, but the
last read data has not yet been transferred at the current point in time.

With reads, the data must come after the address, so there is a simple reference point for when the
transaction starts. This is shown in the following diagram:

For write transactions, the data can come after the address, but leading write data is also allowed. The
start of a write transaction can therefore be either of the following:
• The transfer of the write address
• The transfer of leading write information

Therefore, an active write transaction is a transaction for which the write address or leading write
data has been transferred, but the write response has not yet been transferred.

The following diagram shows an active write transaction where the write address has been
transferred, but the write response has not yet been transferred:

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The following diagram shows an active write transaction where the leading write data has been
transferred, but the write response has not yet been transferred:

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Introduction to AMBA AXI4 102202
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5 Channel signals
This section introduces the main AXI signals and attributes, and explains how they are used to
improve system performance.

The AXI protocol defines five channels: three for write signals, and two for read signals.

5.1 Write channel signals

The channels used for a write transaction are:
• Write Address
• Write Data
• Write Response

The following table shows the Write Address channel signals:

Write Address (AW) channel signals AXI version
AWVALID AXI3 and AXI4
AWREADY AXI3 and AXI4
AWADDR[31:0] AXI3 and AXI4
AWSIZE[2:0] AXI3 and AXI4
AWBURST[1:0] AXI3 and AXI4
AWCACHE[3:0] AXI3 and AXI4
AWPROT[2:0] AXI3 and AXI4
AWID[x:0] AXI3 and AXI4
AWLEN[3:0] AXI3 only
AWLEN[7:0] AXI4 only
AWLOCK[1:0] AXI3 only
AWLOCK AXI4 only
AWQOS[3:0] AXI4 only
AWREGION[3:0] AXI4 only
AWUSER[x:0] AXI4 only

The following table shows the Write Data channel signals:

Write Data (W) channel signals AXI version
WVALID AXI3 and AXI4
WREADY AXI3 and AXI4
WLAST AXI3 and AXI4
WDATA[x:0] AXI3 and AXI4
WSTRB[x:0] AXI3 and AXI4
WID[x:0] AXI3 only
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Write Data (W) channel signals AXI version

WUSER[x:0] AXI4 only

The following table shows the Write Response channel signals:

Write Response (B) channel signals AXI version
BVALID AXI3 and AXI4
BREADY AXI3 and AXI4
BRESP[1:0] AXI3 and AXI4
BID[x:0] AXI3 and AXI4
BUSER[x:0] AXI4 only

All the signals in each channel have the same prefix:

• AW for the Write Address channel
• W for the Write Data channel
• B for the Write Response channel

There are some differences between the AXI3 protocol and the AXI4 protocol for the write channels:
• For the write address channel, the AWLEN signal is wider for the AXI4 protocol. Therefore, AXI4
is able to generate longer bursts than AXI3.
• AXI4 reduces the AWLOCK signal to a single bit to only accommodate exclusive transfers
because locked transfers are not supported.
• AXI4 adds the AWQOS signal to the AW channel. This signal supports the concept of quality of
service (QoS) in the AXI4 protocol.
• AXI4 adds the AWREGION signal to the AW channel. This signal supports slave regions which
allow for multiple logical interfaces from a single physical slave interface.
• AXI4 removes the WID signal from the W channel. This is because write data reordering is no
longer allowed.
• AXI4 adds user-defined signals to each channel.

5.2 Read channel signals

The channels used for a read transaction are:
• Read Address
• Read Data

The following table shows the Read Address channel signals:

Read Address (AR) channel signals AXI version
ARVALID AXI3 and AXI4
AREADY AXI3 and AXI4
ARADDR[31:0] AXI3 and AXI4

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Read Address (AR) channel signals AXI version

ARSIZE[2:0] AXI3 and AXI4
ARBURST[1:0] AXI3 and AXI4
ARCACHE[3:0] AXI3 and AXI4
ARPROT[2:0} AXI3 and AXI4
ARID[x:0] AXI3 and AXI4
ARLEN[3:0] AXI3 only
ARLEN[7:0] AXI4 only
ARLOCK[1:0] AXI3 only
ARLOCK AXI4 only
ARQOS[3:0] AXI4 only
ARREGION[3:0] AXI4 only
ARUSER[x:0] AXI4 only

The following table shows the Read Data channel signals:

Read Data (R) channel signals AXI version
RVALID AXI3 and AXI4
READY AXI3 and AXI4
RLAST AXI3 and AXI4
RDATA[x:0] AXI3 and AXI4
RRESP[1:0] AXI3 and AXI4
RID[x:0] AXI3 and AXI4
RUSER[x:0] AXI4 only

All the signals in each channel have the same prefix:

• AR for the Read Address channel
• R for the Read Data channel

There are some differences between the AXI3 protocol and the AXI4 protocol for the read channels:
• For the AXI4 protocol, the read address length signal ARLEN is wider. Therefore, AXI4 is able to
generate longer read bursts than AXI3.
• AXI4 reduces the ARLOCK signal to a single bit to only accommodate exclusive transfers because
locked transfers are not supported.
• As with the write channel signals, the concepts of quality of service and slave regions apply to
read transactions. These use the ARQOS and ARREGION signals in the AR channel.
• AXI4 adds user-defined signals to the two read channels.

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5.3 Data size, length, and burst type

Each read and write transaction has attributes that specify the data length, size, and the burst signal
attributes for that transaction.

In the following list of attributes, x stands for write and read, so they apply to both the Write Address
channel and the Read Address channel:
• AxLEN describes the length of the transaction in the number of transfers.
o For AXI3, AxLEN[3:0] has 4 bits, which specifies a range of 1-16 transfers in a transaction.
o For AXI4, AxLEN[7:0] has 8 bits, which specifies a range of 1-256 data transfers in a
transaction.
• AxSize[2:0] describes the maximum number of bytes to transfer in each data transfer. Three bits
of encoding indicate 1, 2, 4, 8, 16, 32, 64, or 128 bytes per transfer.
• AxBURST[1:0] describes the burst type of the transaction: fixed, incrementing, or wrapping.

The following table shows the different properties of these burst types:
Value Burst type Usage notes Length Alignment
(number of transfers)
0x00 FIXED Reads the same address repeatedly. 1-16 Fixed byte lanes only
Useful for FIFOs. defined by start address
and size.
0x01 INCR Incrementing burst. AXI3: 1-16 Unaligned transfers are
The slave increments the address for AXI4: 1-256 supported.
each transfer in the burst from the
address for the previous transfer.
The incremental value depends on the
size of the transfer, as defined by the
AxSIZE attribute.
Useful for block transfers.
0x10 WRAP Wrapping burst. 2, 4, 8, or 16 The start address must
Similar to an incrementing burst, be aligned to the
except that if an upper address limit is transfer size.
reached, the address wraps around to a
lower address.
Commonly used for cache line
accesses.
0x11 RESERVED Not for use. - -

5.4 Protection level support

AXI provides access permissions signals, AWPROT and ARPROT, that can protect against illegal
transactions downstream in the system. For example, if a transaction does not have the correct level
of protection, a memory controller could refuse read or write access by using these signals.

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Clock).
• I2C supports various data rates as per versions from 100 Kbps, 400 Kbps, 1 Mbps to 3.4 Mbps
• It is synchronous communication like SPI and unlike UART. Hence there is common clock signal between
masters and slaves.
• It uses start and stop bits and ACK bit for every 8 bits of data transfer.
The figure-3 depicts UART interface between master and slave devices. Also refer difference between I2C
vs I2S >> .

Tabular difference between UART, SPI and I2C

Let us compare UART vs SPI vs I2C and summarize difference between UART, SPI and I2C in tabular
format.

Features UART SPI I2C

Full Form Universal Serial Peripheral Interface Inter-Integrated Circuit

Asynchronous
Receiver/Transmitter

Interface
Diagram

Pin TxD: Transmit Data SCLK: Serial Clock SDA: Serial Data
Designations RxD: Receive Data MOSI: Master Output, Slave SCL: Serial Clock
Input
MISO: Master Input, Slave
Output
SS: Slave Select

Data rate As this is is Maximum data rate limit is I2C supports 100 kbps, 400
asynchronous not specified in SPI kbps, 3.4 Mbps. Some variants
communication, data interface. Usually supports also supports 10 Kbps and 1
rate between two about 10 Mbps to 20 Mbps Mbps.
devices wanting to
communicate should
be set to equal
value. Maximum
data rate supported
is about 230 Kbps to
460kbps.

Distance Lower about 50 feet highest Higher

Type of Asynchronous Synchronous Synchronous

communication

Number of Not Application One One or more than One

masters

Clock No Common Clock There is one common serial There is common clock signal
signal is used. Both clock signal between master between multiple masters and
the devices will use and slave devices. multiple slaves.
there independent
clocks.

Hardware lesser less more

Hardware lesser less
complexity
Protocol For 8 bits of data Each company or
one start bit and one manufacturers have got their
stop bit is used. own specific protocols to
communicate with
peripherals. Hence one
needs to read datasheet to
know read/write protocol for
SPI communication to be
established. For example we
would like SPI
communication between
microcontroller and EPROM.
Here one need to go
through read/write
operational diagram in the
EPROM data sheet.
Software As this is one to one Slave select lines are used
addressing connection between to address any particular
two devices, slave connected with the
addressing is not master. There will be 'n'
needed. slave select lines on master
device for 'n' slaves.
Advantages • It is simple •It is simple protocol and
communication and hence so not require
most popular which processing overheads.
is available due to •Supports full duplex
UART support in communication.
almost all the •Due to separate use of CS
devices with 9 pin lines, same kind of multiple
connector. It is also chips can be used in the
referred as RS232 circuit design.
interface. •SPI uses push-pull and
hence higher data rates and
longer ranges are possible.
•SPI uses less power
compare to I2C
Disadvantages • They are suitable • As number of slave
for communication increases, number of CS
between only two lines increases, this results
devices. in hardware complexity as
• It supports fixed number of pins required will
data rate agreed increase.
upon between • To add a device in SPI
devices initially requires one to add extra
before CS line and changes in
communication software for particular
otherwise data will device addressing is
be garbled. concerned.
•Master and slave
relationship can not be
changed as usually done in
I2C interface.
more
It uses start and stop bits. It
uses ACK bit for each 8 bits of
data which indicates whether
data has been received or not.
Figure depicts the data
communication protocol.
There will be multiple slaves
and multiple masters and all
masters can communicate with
all the slaves. Upto 27 slave
devices can be
connected/addressed in the
I2C interface circuit.
•Due to open collector design,
limited slew rates can be
achieved.
•More than one masters can
be used in the electronic circuit
design.
•Needs fewer i.e. only 2 wires
for communication.
•I2C addressing is simple
which does not require any CS
lines used in SPI and it is easy
to add extra devices on the
bus.
•It uses open collector bus
concept. Hence there is bus
voltage flexibity on the
interface bus.
•Uses flow control.
•Increases complexity of the
circuit when number of slaves
and masters increases.
•I2C interface is half duplex.
•Requires software stack to
control the protocol and hence
it needs some processing
overheads on
microcontroller/microprocessor.
 •No flow control available in
SPI.

Reference RS232 Interface>> SPI Interface>> I2C vs I2S Interface>>

what is difference between

difference between UART vs SPI vs I2C
Difference between 100Base-T1 and 1000Base-T1
CAN vs TTCAN
CAN vs TTP
RS232 vs RS422 vs RS485 interface
LIN vs CAN vs FlexRay vs MOST
Difference between MOST25,MOST50,MOST150

RF and Wireless Terminologies

SATELLITE RF Antenna Avionics Wireless LiFi vs WiFi MiFi vs WiFi BPSK vs QPSK
BJT vs FET PDH vs SDH CS vs PS MS vs PS

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Last Updated on May 23, 2021 by Amlendra

In this article, I have tried to collect I2C Interview questions which can ask by your
Interviewer. I have already written an article on I2C protocol if you have not seen
this article, you should read this article before starting this Q&A.

What is I2C communication?

I2C is a serial communication protocol. It provides good support to the slow
devices, for example, EEPROM, ADC, I2C LCD, and RTC etc. It is not only used with
the single board but also used with the other external components which have
connected with boards through the cables.

I2C is basically a two-wire communication protocol. It uses only two wire for
communication. In which one wire is used for the data (SDA) and other wire is used
for the clock (SCL).

In I2C, both buses are bidirectional, which means master able to send and receive
the data from the slave. The clock bus is controlled by the master but in some
situations slave is also able to suppress the clock signal, but we will discuss it later.

Additionally, an I2C bus is used in the various control architecture, for example,
SMBus (System Management Bus), PMBus (Power Management Bus), IPMI
(Intelligent Platform Management Interface) etc.

 
What does I2C stand for?
Inter-Integrated Circuit

How many wires are required for I2C communication?

In I2C only two buses are required for the communication, the serial data bus
(SDA) and serial clock bus (SCL).

I2C is half­duplex or full­duplex?

half-duplex

I2C is Synchronous or Asynchronous Communication?

I2C is Synchronous Communication

Explain the physical layer of the I2C protocol

I2C is pure master and slave communication protocol, it can be the multi-master
or multi-slave but we generally see a single master in I2C communication. In I2C
only two-wire are used for communication, one is data bus (SDA) and the second
one is the clock bus (CLK).

All slave and master are connected with same data and clock bus, here important
thing is to remember these buses are connected to each other using the WIRE-
AND con몭guration which is done by to putting both pins is open drain. The wire-
AND con몭guration allows in I2C to connect multiple nodes to the bus without any
short circuits from signal contention.
The open-drain allows the master and slave to drive the line low and release to
high impedance state. So In that situation, when master and slave release the bus,
need a pull resistor to pull the line high. The value of the pull-up resistor is very
important as per the perspective of the design of the I2C system because the
incorrect value of the pull-up resistor can lead to signal loss.

Note: We know that I2c communication protocol supports multiple masters and
multiple slaves, but most system designs include only one master.

If you want to learn STM32 from scratch, you should follow this course “Mastering
Microcontroller with Embedded Driver Development“. The course contains video
lectures of 18.5-hours length covering all topics like, Microcontroller & Peripheral
Driver Development for STM32 GPIO, I2C, SPI, USART using Embedded C.

Enroll In Course
 
Explain the operation and frame of I2C protocol
I2C is a  chip to chip communication protocol. In I2C, communication is always
started by the master. When the master wants to communicate with slave then he
asserts a start bit followed by the slave address with read/write bit.

After asserting the start bit, all slave comes in the attentive mode. If the
transmitted address match with any of the slave on the bus then an
ACKNOWLEDGEMENT (ACK) bit is sent by the slave to the master.

After getting the ACK bit, master starts the communication. If there is no slave
whose address match with the transmitted address then master received a NOT-
ACKNOWLEDGEMENT (NACK) bit, in that situation either master assert the stop bit
to stop the communication or assert a repeated start bit on the line for new
communication.

When we send or receive the bytes in i2c, we always get a NACK bit or ACK bit
after each byte of the data is transferred during the communication.

In I2C, one bit is always transmitted on every clock. A byte which is transmitted in
I2C could be an address of the device, the address of register or data which is
written to or read from the slave.

In I2C, SDA line is always stable during the high clock phase except for the start
condition, stop condition and repeated start condition. The SDA line only changes
their state during the low clock phase.

See the below image,

Start Bit: Start the communication

Stop bit: Stop communication.

What is START bit and STOP bit?

Start Condition:

The default state of SDA and SCL line is high. A master asserts the start condition
on the line to start the communication. A high to low transition of the SDA line
while the SCL line is high called the START condition. The START condition is
always asserted by the master. The I2C bus is considered busy after the assertion
of the START bit.
Stop Condition:

The STOP condition is asserted by the master to stop the communication. A Low
to high transition of SDA line while the SCL line is high called the STOP condition.
The STOP condition is always asserted by the master. The I2C bus is considered
free after the assertion of the STOP bit.
Note: A START and STOP condition always asserted by the master.

Note: You can also see, Embedded c interview questions

What is the repeated start condition?

The repeated start condition similar to the START condition but both are di몭erent
from each other. The repeated start is asserted by the master before the stop
condition (When the bus is not in an idle state).

A Repeated Start condition is asserted by the master when he does not want to
lose their control from the bus. The repeated start is bene몭cial for the master
when it wants to start a new communication without asserting the stop condition.

Note: Repeated start is bene몭cial when more than one master connected with the
I2c Bus.
 

What is the standard bus speed in I2C?

There are following speed mode in I2C

                      MODE                          SPEED

                      Standard-mode                       100 kbit/s

                        Fast-mode                       400 kbit/s

                     Fast-mode Plus                       1 Mbit/s

                     High-speed mode                       3.4 Mbit/s

What is the limiting factor as to how many devices can

go on the I²C bus?
It depends on the total capacitance.

Who sends the start bit?

In I2C master sends the start bit.

What is the maximum bus length of the I2C bus?

It depends on the bus-load (capacitance) and the speed. Basically I2C is not
designed for long-distance. It is limited to a few meters. For fast mode, and
resistor pullup, capacitance should be less than 200pF, according to
“UM10204.pdf” NXP document. So If your wire is 20pF/25cm and you have another
80pF of stray and input capacitance, you’re limited to 1.5m of cable length. But it is
only a rough assumption. It can vary in real scenarios.

How many kinds of addressing structures are there in

I2C?
Right now two addressing support by I2C, 7-bit, and 10 -bit.

Is it possible to have multiple masters in I2C?

Yes I2C support multiple master and multiple slaves.

What is a bus arbitration?

The arbitration is required in the case of a multi-master, where more than one
master is tried to communicate with a slave simultaneously. In I2C arbitration is
achieved by the SDA line.

For Example,
Suppose two masters in the I2C bus is tried to communicate with a slave
simultaneously then they will assert a start condition on the bus. The SCL clock of
the I2c bus would be already synchronized by the wired and logic.
In the above case, everything will be good till the state of SDA line will same what
is the masters driving on the bus. If any master sees that the state of SDA line
di몭ers, what is it driving then they will exit from the communication and lose their
arbitration.

Note: Master which is losing their arbitration will wait till the bus become free.

What is I2C clock stretching?

In I2c, communication can be paused by the clock stretching to holding the SCL
line low and it cannot continue until the SCL line released high again.
In I2C, slave able to receive a byte of data on the fast rate but sometimes slave
takes more time in processing the received bytes in that situation slave pull the
SCL line to pause the transaction and after the processing of the received bytes, it
again released the SCL line high again to resume the communication.

The clock stretching is the way in which slave drive the SCL line but it is the fact,
most of the slave does not drive the SCL line

Note: In the I2c communication protocol, most of the I2C slave devices do not use
the clock stretching feature, but every master should support the clock stretching.

 
What is I2C clock synchronization?
Unlike Rs232, I2c is synchronous communication, in which the clock is always
generated by the master and this clock is shared by both master and slave. In the
case of multi-master, all master generate their own SCL clock, hence it is
necessary that the clock of all master should be synchronized. In the i2C, this
clock synchronization is done by wired and logic.

For a better understanding, I am taking an example, where two masters try to

communicate with a slave. In that situation, both masters generate their own
clock, master M1 generate clk1 and master M2 generate clk2 and clock which
observed on the bus is SCL.

The SCL clock would be the Anding (clk1 & clk2) of clk1 and clk2 and most
interesting thing is that highest logic 1 of SCL line de몭nes by the CLK which has
lowest logic 1.
When must data be stable for a correct I²C bus
transaction?
When the clock is high

Is Hot swapping possible in I2C protocol?

Yes, hot swapping is possible in I2C.

Can devices be added and removed while the system

is running in I2C?
Yes because Hot swapping is possible in I2C protocol.

Which is better to use I2C or SPI?

Each communication protocol has own advantage and disadvantage. You can not
say blindly which one is better SPI and I2C. SPI has its own bene몭ts and I2C has its
own bene몭ts. We select the protocol as per the project requirement. You can
check the article to SPI vs I2C for more detail.

What is the application of the I2C protocol?

It is connected with serial RAM, LCD, EEPROM, and its use within the television
sets.
 

If a slave is servicing an internal interrupt, what will it

do to avoid losing data?
The slave will stretch the clock until the interrupt servicing is complete.

Can we monitor the I2C bus?

Yes, we can. There are many analyzers available, you can check this analyzer
“Siglent SDS1104X-E “.

Advantages of I2C communication?

There is a lot of advantage of I2C protocol which makes the user helpless to use
the I2C protocol in many applications.

It is the synchronous communication protocol, so there is no need of a precise

oscillator for the master and slave.
It requires only two-wire, one wire for the data (SDA) and other wire for the clock
(SCL).
It provides the exibility to the user to select the transmission rate as per the
requirements.
In I2C bus, each device on the bus is independently addressable.
It follows the master and slave relationships.
It has the capability to handle multiple masters and multiple slaves on the I2C Bus.
I2C has some important features like arbitration, clock synchronization, and clock
stretching.
I2C provides ACK/NACK (acknowledgment/ Not-acknowledgement) features
that provide help in error handling.

 
What are the limitations of I2C interface?
Half-duplex communication, so data is transmitted only in one direction (because
of the single data bus) at a time.
Since the bus is shared by many devices, debugging an I2C bus (detecting which
device is misbehaving) for issues is pretty dif cult.
The I2C bus is shared by multiple slave devices if anyone of these slaves
misbehaves (pull either SCL or SDA low for an inde nite time) the bus will be
stalled. No further communication will take place.
I2C uses resistive pull-up for its bus. Limiting the bus speed.
Bus speed is directly dependent on the bus capacitance, meaning longer I2C bus
traces will limit the bus speed.

What is the difference between SPI and I2C (I2C vs

SPI)?
You can see this article, Di몭erence between I2c and SPI

Questions for you:

What is locking(or waiting) and unlocking the I2c protocol? How you could design
the unlocking I2c protocol for your system.
I2C is Edge Triggering or Level Triggering?
Is in I2c two slaves have the same address?
How will the master indicate that it is either address/data? How will it intimate to
the slave that it is going to either read/write?
What is the voltage level for 0 and 1 in I2C?
How could a slave send the data to the Master in I2C while the master is
communicating with another slave?

Recommended Post
Understanding of I2C protocol.
SPI vs I2C protocol.
EEPROM Interfacing with PIC Microcontroller – I2C Based.
RTC DS1307 Interfacing  with PIC Microcontroller.
Interfacing EEPROM with 8051 Microcontroller – I2C Based.
Q) What does SPI stand for?

serial peripheral interface.  SPI is developed by Motorola.

Q) SPI is serial or parallel communication?

SPI is serial communication. By serially send and receive data in the same line.

Q) What is the SPI communication protocol?

The serial peripheral interface is four wire-based full-duplex communication

protocol these wire generally known as MOSI (master out slave in), MISO (master
in slave out), SCL (a serial clock which produces by the master) and SS (slave
select line which use to select speci몭c slave during the communication).

SPI follows the master and slave architecture and communication is always
started by the master. SPI is a synchronous communication protocol because the
clock is shared by the master and slave.

SPI is supported only multi-slave does not support multi-master and slaves are
selected by the slave select signal. In SPI during the communication data is
shifted out from the master and shifted into the slave vice- versa through the shift
register.

Q) How many wires are required for SPI communication?

The serial peripheral interface is four wire-based protocol these wire generally
known as MOSI (master out slave in), MISO (master in slave out), SCL (serial clock
which produces by the master) and SS (slave select line which use to select
speci몭c slave during the communication).
 

Q) What are the 4 logic signals speci몭ed by the SPI bus?

The SPI bus speci몭es four logic signals:

SCLK: Serial Clock (It is produced by the master to start the communication)

MOSI: Master Out, Slave In (This line is used to carry data from the master to the
slave)

MISO: Master in, Slave out (This line is used to carry the data from the slave to the
master)

SS: Slave Select (This line is used to select the slave in case of the multi-slave
communication)

Q) Is it possible to have multiple masters in SPI?

No, SPI has only a single master.

Q) Is it possible to have multiple slaves in SPI?

Yes, SPI supports multiple slaves.

Q) What is the role of the shift register in Master and Slave devices in
SPI?

In SPI, shift register are used. Here data is transferring to the slave using the MOSI
bus and at the same time receiving the dummy data from the MISO bus and vice
versa. Every writes there is dummy read and every read there is dummy write.
 

Q) Does SPI slave acknowledge the receipt of data?

Nope, SPI doesn’t give any ACK like I2C.

Q) SPI has a higher throughput than I2C – True / False? 

SPI is faster than I2C.

Q) Is SPI support duplex communication?

Yes.

Q) Why use SPI?

Unlike the serial com port, SPI is the synchronous communication protocol. In SPI
master and slave both shared the same clock and clock is produced by the
master. In the case of asynchronous serial communication, every byte consists of a
start and stop bits which create extra overhead on communication.

Another disadvantage of serial com port communication is that it needs to

maintain clock frequency of the transmitter and receiver ( both not shared the
clock). If the frequency of the transmitter and receiver does not match then the
receiver will not receive the data transmitted by the transmitter.

Q) SPI is Synchronous or Asynchronous Communication?

SPI is Synchronous Communication.

 

Q) Does start-stop bit support by SPI?

No.

Q) Does pullup register require in SPI?

No.

Q) Does bus arbitration support by SPI?

No.

Q) Does the clock stretching support by SPI?

No.

Q) What is the di몭erence between SPI and I2C (I2C vs SPI)?

You can see this article, Di몭erence between I2c and SPI

Q) What are the advantages of the SPI communication protocol?

There is no start and stop bits, so the data can be streamed continuously without
interruption.
It supports full-duplex.
No need for precision oscillators in slave devices as it uses a master’s clock.
 No complicated slave addressing system like I2C.
Higher data transfer rate than I2C (almost twice as fast).
Separate MISO and MOSI lines, so data can be sent and received at the same time.
Simple software implementation.

Q) What are the disadvantages of the SPI communication protocol?

If there is more than one slave in communication then the wiring will be complex.
Uses four wires (I2C and UARTs use two).
No acknowledgment that the data has been successfully received (I2C has this).
No form of error checking like the parity bit in UART.
It only allows for a single master.

Below I am mentioning some unsolved SPI interview Questions for you. If you
know the answer, then please write in comment box or email me directly. Your
e몭ort will be helpful to others.

Q) Can devices be added and removed while the system is running (Hot swapping) in I2C
and SPI?

Q) Is it better to use I2C or SPI for data communication between a microprocessor and
DSP?

Q) How to set SPI bus speed in the master device?

Q) What will happens if two SPI slaves same time communicate with Master (two Cs pins
are high)?

Q) Is it better to use I2C or SPI for data communication from ADC?

Q) How to set SPI bus speed in the master device?

Q) Does SPI need a baud rate?

Q) What happens when mode fault is enabled in SPI (Serial Peripheral Interface)?