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Fyp Final Report Libre 1
Fyp Final Report Libre 1
INTERNAL ADVISOR
DR. IMRAN TASADDUQ
EXTERNAL ADVISOR
ENGR. MUSTAFA IMRAN
JUNE 2008
HARDWARE IMPLEMENTATION OF OFDM TRANSMITTER AND RECEIVER
USING FPGA
BY
JUNE 2008
ACKNOWLEDGEMENT
First of all we would like to thank Almighty Allah. Its only because of the blessings of Allah
We take this special occasion to thank our parents. We dedicated this work to our parents.
We really have to express our collective gratitude towards our internal advisor Dr. Imran
Tasadduq for all his help, invaluable guidance, critics and generous support throughout our
final year project. We really appreciate the way he mentored us throughout our brief
We also like to thank our external advisor Mr. Mustafa Imran for his enlightening
Special acknowledgements to Ms. Samreen Amir and Mr. Wasif Shams. Their interest in
this project was very beneficial and helped design many vital parts of the project.
Finally, we would like to thank DIGITEK Engineering for providing us with ModelSim 6.1e
and the ip cores of Viterbi decoder and Reed Solomon decoder that made the difficult task
June 2008
ii
TABLE OF CONTENTS
Page
ACKNOWLEDGEMENT ii
TABLE OF CONTENTS iii
LIST OF TABLES vi
LIST OF FIGURES vii
ABSTRACT ix
CHAPTER 1: INTRODUCTION 1
1.1 Introduction 1
1.2 Digital communication system architecture 1
1.3 Orthogonal Frequency Division Multiplexing 2
1.4 A Typical OFDM system 3
1.4.1 Scrambler / Descrambler 4
1.4.2 Reed Solomon Encoder / Decoder 5
1.4.3 Convolutional Encoder / Decoder 5
1.4.4 Interleaver / De-interleaver 6
1.4.5 Constellation Mapper / De-mapper 6
1.4.6 FFT / IFFT 6
1.4.7 Cyclic Prefix Adder / Remover 7
1.5 Field Programmable Gate Array 7
1.6 Project Objective 8
1.7 Project Specifications 8
1.7.1 Transmitter Specifications 10
1.7.2 Receiver Specifications 11
1.8 Project design flow 11
1.9 Project scope 12
iii
2.1.1 History of OFDM 13
2.2 The OFDM system 15
2.3 Advantages and disadvantages of OFDM 16
2.4 Applications of OFDM 17
2.5 Verilog Hardware description Language 17
2.6 Synthesis process in Verilog HDL 18
3.1 Introduction 20
3.2 OFDM system hardware architecture 20
3.3 The Transmitter 22
3.4 FIFO 24
3.5 Scrambler 24
3.5.1 Design of Scrambler 25
3.6 Reed Solomon Encoder 27
3.6.1 Description of the Reed Solomon code 27
3.6.2 Galois field arithmetic 29
3.6.3 Encoder design 32
3.7 Convolutional Encoder 35
3.7.1 Encoder design 36
3.8 Interleaver 38
3.8.1 Interleaver design 39
3.9 Constellation mapper 44
3.9.1 Design of Constellation mapper 44
3.10 Inverse Fast Fourier Transform 46
2
3.10.1 Radix-2 algorithm 47
3.10.2 IFFT design 49
3.11 Cyclic Prefix Adder 52
3.11.1 Design of Cyclic Prefix Adder 52
iv
4.3 Cyclic Prefix Remover 56
4.4 Fast Fourier Transform 57
4.5 Constellation De-mapper 57
4.5.1 Design of Constellation De-mapper 58
4.6 De-interleaver 59
4.7 Viterbi Decoder 61
4.8 Reed Solomon Decoder 61
4.9 De-scrambler 62
4.9.1 De-scrambler design 62
5.1 Introduction 64
5.2 Simulation of OFDM Transmitter 64
5.2.1 Scrambler 64
5.2.2 Reed Solomon Encoder 65
5.2.3 Convolutional Encoder 65
5.2.4 Interleaver 66
5.2.5 Constellation mapper 66
5.2.6 IFFT 66
5.2.7 Cyclic Prefix Adder 67
5.3 Synthesis of OFDM Transmitter 68
5.4 Simulation of OFDM Receiver 68
5.4.1 Constellation De-Mapper 68
5.4.2 De-Interleaver 69
5.4.3 De-Scrambler 69
5.5 Synthesis of OFDM Receiver 69
REFERENCES 71
v
LIST OF TABLES
Page
vi
LIST OF FIGURES
Page
vii
3.22 Architecture of 64-point-22 FFT 53
3.23 bf2i and bf2ii radix 2 butterflies 51
3.24 Top level architecture of cyclic prefix adder 53
4.1 I/O diagram of the OFDM receiver 54
4.2 Complete Architecture of the proposed OFDM system (receiver 56
highlighted)
4.3 FFT 59
4.4 QPSK constellation diagram 60
4.5 I/O diagram of constellation demapper 60
4.6 Verilog code showing the logic behind implementation of 61
constellation demapper
4.7 De-scrambler I/O diagram 64
4.8 De-scrambler logic diagram 65
5.1 Scrambler simulation results 66
5.2 Solomon Encoder simulation results 67
5.3 Simulation Waveform of the Convolutional Encoder 68
5.4 Constellation Mapper simulation results 68
5.5 IFFT simulation results 69
5.6 Cyclic Prefix Adder simulation result 69
viii
HARDWARE IMPLEMENTATION OF OFDM TRANSMITTER AND RECEIVER
USING FPGA
ABSTRACT
It provides high bandwidth efficiency because the carriers are orthogonal to each other and
multiple carriers share the data among themselves. The main advantage of this
environment. The main objective of this project is to design and implement a baseband
OFDM transmitter and receiver. The implementation has been carried out in hardware using
Field Programmable Gate Array (FPGA). Both the transmitter and the receiver are
implemented on a single FPGA board with the channel being a wired one. The FPGA board
used is Altera’s Cyclone III starter board which contains 24,600 logic elements. The
designing has been done in Verilog HDL. Modelsim 6.1e has been used to simulate the
design. Input to the system is given using computer’s serial port. NI Labview has been used
to do the serial port interfacing. The output of the transmitter has been compared with the
output of MATLAB for the same OFDM system modeled in MATLAB. The data obtained at
the output of the transmitter is fed to the PC using serial port and is converted to complex
numbers because MATLAB gives output in the form of complex numbers. Although error
correction schemes have been employed in the transmitter and the receiver but as the
channel is a wired one, and hence there is no ISI or other channel impairments, therefore
errors don’t occur. Therefore, only the proper operation of the OFDM system has been
aimed to achieve.
ix
Chapter 1 Introduction
CHAPTER 1
INTRODUCTION
1.1 INTRODUCTION
Demand for broadband access is increasing at a quick rate, and at the same time, is not
limited to areas that already have an existing high quality infrastructure. For instance,
developing countries and rural areas may not have the existing telecom infrastructure or
the existing connections, typically over copper, to meet the requirements of Digital
Subscriber Line (DSL) technology. Furthermore, it is expected that users will require
more bandwidth on the move. While current technologies can meet this bandwidth
demand, the useful range is limited. This limitation opens up opportunities for
transmission of information in digital form from one point to another point as shown in
Figure 1.1.
Source of Received
Information Information
Channel Receiver
Transmitter
1
Chapter 1 Introduction
The three basic elements in a communication system are transmitter, channel and
receiver. The source of information is the messages that are to be transmitted to the
other end in the receiver. A transmitter can consist of source encoder, channel coder
through which the resources are conserved. A channel coder may include error
detection and correction code. A modulation process then converts the base band signal
During transmission, the signal experiences impairment which attenuates the signals
amplitude and distort signals phase. Also, the signals transmitting through a channel
At the receiving end, the reversed order of the steps taken in the transmitter is
performed. Ideally, the same information must be decoded at the receiving end.
technique that has been recognized as an excellent method for high speed bi-directional
tightly together, reducing the required bandwidth but keeping the modulated signals
OFDM is similar to FDM but much more spectrally efficient by spacing the sub-channels
much closer together (until they are actually overlapping)[1]. This is done by finding
frequencies that are orthogonal, which means that they are perpendicular in a
without interfering with it. In Figure 1.2 the effect of this is seen, as the required
bandwidth is greatly reduced by removing guard bands (which are present in FDM) and
2
Chapter 1 Introduction
Figure 1.3 shows a detailed OFDM communications system. Each block is briefly
defined below:
3
Chapter 1 Introduction
"
Data bits are given to the transmitter as inputs. These bits pass through a scrambler that
randomizes the bit sequence. This is done in order to make the input sequence more
4
Chapter 1 Introduction
disperse so that the dependence of input signal’s power spectrum on the actual
At the receiver end descrambling is the last step. De-scrambler simply recovers original
The scrambled bits are then fed to the Reed Solomon Encoder which is a part of
technique. Input data is over-sampled and parity symbols are calculated which are then
appended with original data [3]. In this way redundant bits are added to the actual
message which provides immunity against severe channel conditions. A Reed Solomon
n = 2m − 1 1.1
k = 2 m − 1 − 2t 1.2
Here m is the number of bits per symbol, k is the number of input data symbols (to be
encoded), n is the total number of symbols (data + parity) in the RS codeword and t is
the maximum number of data symbols that can be corrected. At the receiver Reed
Reed Solomon error-coded bits are further coded by Convolutional encoder. This coder
adds redundant bits as well. In this type of coding technique each m bit symbol is
transformed into an n bit symbol; m/n is known as the code rate. This transformation of
m bit symbol into n bit symbol depends upon the last k data symbols, therefore k is
5
Chapter 1 Introduction
Viterbi algorithm is used to decode convolutionaly encoded bits at the receiver side.
Viterbi decoding algorithm is most suitable for Convolutional codes with k 10.
Interleaving is done to protect the data from burst errors during transmission.
Conceptually, the in-coming bit stream is re-arranged so that adjacent bits are no more
adjacent to each other. The data is broken into blocks and the bits within a block are re-
arranged [5]. Talking in terms of OFDM, the bits within an OFDM symbol are re-
arranged in such a fashion so that adjacent bits are placed on non-adjacent sub-carriers.
As far as De-Interleaving is concerned, it again rearranges the bits into original form
during reception.
The Constellation Mapper basically maps the incoming (interleaved) bits onto different
QAM etc.) for different sub-carriers. The De-Mapper simply extracts bits from the
This is the most important block in the OFDM communication system. It is IFFT that
basically gives OFDM its orthogonality [1]. The IFFT transform a spectrum (amplitude
and phase of each component) into a time domain signal. It converts a number of
complex data points into the same number of points in time domain. Similarly, FFT at the
receiver side performs the reverse task i.e. conversion from time domain back to
frequency domain.
6
Chapter 1 Introduction
OFDM symbols, a cyclic guard interval is introduced. The guard period is specified in
terms of the fraction of the number of samples that make up an OFDM symbol. The
cyclic prefix contains a copy of the end of the forthcoming symbol. Addition of cyclic
prefix results in circular convolution between the transmitted signal and the channel
response, therefore received signal is only a scaled version of transmitted signal (in
frequency domain), hence distortions due to severe channel conditions are eliminated
[6]. Removal of cyclic prefix is then done at the receiver end and the cyclic prefix–free
By modern standards, a logic circuit with 20000 gates is common. In order to implement
large circuits, it is convenient to use a type of chip that has a large logic capacity. A field-
implementation of relatively large logic circuits [6]. FPGA is different from other logic
technologies like CPLD and SPLD because FPGA does not contain AND or OR planes.
An FPGA contains 3 main types of resources: logic blocks, I/O blocks for connecting to
the pins of the package, and interconnection wires and switches. The logic blocks are
horizontal and vertical routing channels between rows and columns of logic blocks [7].
The routing channels contain wires and programmable switches that allow the logic
circuits of more than a few hundred thousands equivalent gates in size [7]. Equivalent
7
Chapter 1 Introduction
gates is a way to quantify a circuit’s size by assuming that the circuit is to be built using
only simple logic gate and then estimating how many of these gates are needed.
The objective of this project is to carry out an efficient implementation of the OFDM
system (i.e. transmitter and receiver) using “Field Programmable Gate Array (FPGA)”.
FPGA has been chosen as the target platform because OFDM has large arithmetic
Digital Signal Processor (DSP) [7]. However, the highly pipelined nature of much of the
The complete OFDM system, comprising of the transmitter and the receiver, has been
8
Chapter 1 Introduction
• FPGA board: Altera Cyclone III starter board (24,600 logic elements)
• HSMC to Santa Cruz daughter card (from TERASIC) for serial port
communication
• Quartus II used to map the design to targeted device (Altera Cyclone III).
Top level architecture of the proposed OFDM system is shown in Figure 1.4.
etc.
PC
RS 232
Interface
CYCLONE III
FPGA
BOARD
9
Chapter 1 Introduction
Figure 1.5 shows a top-level block diagram of the OFDM transmitter. Single-Clock
operation speaks itself for the synchronous operation of the system. The Reset input
must be asserted for atleast one clock cycle for the system to reset. Output of the
transmitter is fed to the host PC via the serial port and also to the OFDM receiver.
' %
#$#
#$#
& '
10
Chapter 1 Introduction
In figure 1.6 a top level block diagram of the receiver is shown. Its specifications are
same as that of the transmitter. Here the recovered (demodulated data would be fed to
'
#$#
& '
• Determining the basic operation of each block and creating the appropriate logic
• Input is given to the system through the PC’s RS232 and hardware is tested
11
Chapter 1 Introduction
Creating logic
for each block
I/O Integration
of the blocks
RTL Description of
design functionality
in Verilog
Simulation
Synthesis
Hardware
Testing
Factors such as data rate, allowable bit rate of the input, code rate of the Forward Error
correction stage and noise immunity can well define the scope of this project. These
12
Chapter 2 Literature Survey
CHAPTER TWO
LITERATURE SURVEY
such as asymmetric digital subscriber lines (ADSL), it is referred as discrete multi tone
(DMT). In OFDM, each carrier is orthogonal to all other carriers. However, this condition
is not always maintained in DMT [8]. OFDM is an optimal version of multi carrier
transmission schemes.
Although OFDM has become widely used only recently, the concept dates back some
40 years. Following table cites some landmark dates in the history of OFDM.
Year Event
13
Chapter 2 Literature Survey
2002
The IEEE 802.16 committee releases an
OFDM-based standard for wireless
broadband access for metropolitan area
networks under revision 802.16a.
2003
The IEEE 802.11 committee releases the
802.11g standard for operation in the
2.4GHz band.
2003
The multi-band OFDM standard for ultra
wideband is developed, showing OFDM’s
usefulness in low-SNR systems.
14
Chapter 2 Literature Survey
The use of Frequency Division Multiplexing (FDM) goes back over a long period of time,
where more than one low rate signal, such as telegraph, was carried over a relatively
wide bandwidth channel using a separate carrier frequency for each signal [1]. To
facilitate separation of the signals at the receiver, the carrier frequencies were spaced
sufficiently far apart so that the signal spectra did not overlap. Empty spectral regions
between the signals assured that they could be separated with readily realizable filters.
A detailed explanation of the OFDM system was given in the previous chapter, in which
computational requirements, therefore, Fast Fourier Transform (FFT) was utilized. For
an N point discrete Fourier Transform the required number of computations is N2, but
that for FFT is Nlog (N), which is much lesser than DFT. In this way the problem of
bandwidth inefficiency due to the placement of guard bands between sub-channels was
solved and a new technique “Orthogonal Frequency Division Multiplexing” came into
being.
As OFDM is a multi-carrier modulation technique, therefore, the input data is split and
mapped onto different sub-carriers. Each carrier is modulated using one of the single-
The OFDM system successfully avoids any inter-channel interference (ICI) because the
carriers are kept orthogonal. In addition, a cyclic prefix (CP) is added before the start of
15
Chapter 2 Literature Survey
(ISI), provided that the delay spread in the channel is less than the guard period [17].
This guard period is specified in terms of the fraction of the number of samples that
make up a symbol.
Another advantage of OFDM is its resilience to Multipath, which is the effect of multiple
reflected signals hitting the receiver. This results in interference and frequency-selective
fading which OFDM is able to overcome by utilizing its parallel, slower bandwidth nature.
This makes OFDM ideal to handle the harsh conditions of the mobile wireless
environment.
The introduction of cyclic prefix made OFDM system resistant to time dispersion [18].
OFDM symbol rate is low since a data stream is divided into several parallel streams
before transmission. This make the fading is slow enough for the channel to be
Cyclic prefix is a crucial feature of OFDM used to combat the inter-symbol interference
which the signal is propagated [1]. The basic idea is to replicate part of the OFDM time-
domain waveform from the back to the front to create a guard period. The duration of the
guard period should be longer than the worst-case delay spread of the target multi-path
environment. The use of a cyclic prefix instead of a plain guard interval, simplifies the
In wire system, OFDM system can offer an efficient bit loading technique [1]. It enables a
system to allocate different number of bits to different sub channels based on their
One of the major disadvantages of OFDM is its requirement for high peak-to average-
power ratio (PAPR) [6]. This put high demand on linearity in amplifiers.
16
Chapter 2 Literature Survey
Second, the synchronization error can destroy the orthogonality and cause interference.
Phase noise error and Doppler shift can cause degradation to OFDM system [1]. A lot of
suitable technology to meet the demands of wireless data traffic. This has made it not
only ideal for such new technologies like WiMAX and Wi-Fi but also currently one of the
prime technologies being considered for use in future fourth generation (4G) networks.
Now, OFDM has been adopted as the new European digital audio broadcasting (DAB)
(ADSL) and high bit-rate digital subscriber line (HDSL) systems. It has been proposed
for power line communications systems as well due to its resilience to dispersive
channel and narrow band interference. It has been employed in WiMAX a well.
Verilog HDL is one of the two most common Hardware Description Languages (HDL)
HDL allows the design to be simulated earlier in the design cycle in order to correct
technology-independent, easy to design and debug, and are usually more readable than
(i) Algorithmic level (much like c code with if, case and loop statements).
(ii) Register transfer level (RTL uses registers connected by Boolean equations).
17
Chapter 2 Literature Survey
(iv) Switch level (the switches are MOS transistors inside gates).
The language also defines constructs that can be used to control the input and output of
simulation.
More recently Verilog is used as an input for synthesis programs which will generate a
gate-level description (a netlist) for the circuit. Some Verilog constructs are not
synthesizable. Also the way the code is written will greatly affect the size and speed of
* " (
" *
) *
+ ( *
) * % (
% (
A synthesis program may generate an RTL net list, which consists of register-transfer
18
Chapter 2 Literature Survey
wires. All these are performed by RTL module builder. This builder is to build or acquire
from a library predefined components, each of the required RTL blocks in the user-
The above synthesis process may produce an unoptimized gate level net list. A logic
optimizer can use the produced net list and the constraint specified to produce an
optimized gate level net list. This net list can be programmed directly into a FPGA chip.
19
Chapter 3 Transmitter Design and Implementation
CHAPTER 3
3.1 INTRODUCTION
The proposed OFDM system consists of an OFDM baseband transmitter and an OFDM
baseband receiver. This chapter gives details on the complete architecture of the
proposed design and elaborates further on the design and implementation of the
The transmitter gets its input from the serial port of the host PC. An input stream is sent
as input to the transmitter that modulates the incoming stream by splitting it and putting it
onto separate sub-carriers (64 in our case). The modulated data after passing through
various blocks is given as input to the receiver and also sent back to the host PC (via
Implementation of the proposed system has been done on Altera’s Cyclone III starter
board. This board does not have a serial port therefore we used an HSMC to Santa Cruz
daughter card (from TERASIC). This daughter card contains an Altera standard HSMC
connector and a serial port. The HSMC connector plugs into the HSMC connector
present on the Cyclone III board, thereby providing an RS232 physical connection to the
FPGA board.
An RS232 receiving module takes the serial stream and extracts the 8 bit payload by
removing the start and stop bits. Figure 3.1 shows the format of data stream in serial
Stop D7 D6 D5 D4 D3 D2 D1 D0 Start
Figure 3.1 Serial communication format (8 bit data + start bit + stop bit)
20
Chapter 3 Transmitter Design and Implementation
The 1-byte data from the RS232 receiver is stored in a FIFO register. Data from the
FIFO is given (bit by bit) to the transmitter module. Figure 3.2 depicts the hardware
PLL FIFO
HSMC TO
SANTA CRUZ
CONNECTOR
RS232
Receiver
Scrambler
High Speed Mezzanine Connector
Input RS Encoder
RS232 port
OFDM Transmitter
Conv. Encoder
Interface
Control Unit
Output
Interleaver
Constellation mapper
IFFT
Cyclic Prefix
RS232 Transmitter
highlighted)
21
Chapter 3 Transmitter Design and Implementation
We can see that the modulated output from the transmitter is fed into another FIFO, and
then taken out into the RS232 transmitter (byte by byte) that prepares the data for serial
transmission over the RS232 interface by adding start and stop bits. The baud rate on
There is a 50 MHz on-board clock source which in conjunction with the PLL core
(provided with the Quartus II software) can be used to produce any clock frequency. The
Figure 3.3 shows an I/O view of the proposed system and Table 3.1 gives a description
in_data
clock out_dat
OFDM system
arst_n
Signal
Type Width Description
name
in_data Input 1 Data input to the OFDM system
clock Input 1 Clock signal (via 50 MHz on-board clock)
arst_n input 1 Asynchronous reset (asserted at negative edge)
out_data Output 1 Demodulated output data
Figure 3.2 shows the various building blocks of the transmitter. The control unit
synchronizes the operation all the blocks in order to avoid any timing mismatches. Each
22
Chapter 3 Transmitter Design and Implementation
As mentioned above, the transmitter gets its input from the FIFO register one bit per
clock cycle. This implies that the input to the transmitter is I bit wide. It is only when the
FIFO is full that the transmitter starts extracting data from it. Similarly when the FIFO
gets empty the transmitter stops taking data from it. Therefore, the transmitter makes
use of certain control and status signals provided by the FIFO to determine when to ask
the FIFO for data and when to stop taking input data.
In a similar fashion, the output of the transmitter is also stored in a FIFO register. In
order for this FIFO to determine when to start storing output data from the transmitter,
the transmitter provides a status signal that tells this FIFO that data is present on the
output lines.
Figure 3.4 shows the I/O diagram for the transmitter and Table 3.2 gives the description
in_data
clock out_dat
arst_n readreq
Transmitter
wrfull
start_output
readempty
Signal
Type Width Description
Name
in_data Input 1 Input data to the transmitter
23
Chapter 3 Transmitter Design and Implementation
edge)
FIFO status signals - asserted when FIFO is
wrfull Input 1
full
FIFO status signal – asserted when FIFO is
readempty Input 1
empty
out_data Output 48 Modulated data coming out of the transmitter
FIFO control signal – requests data from FIFO
readreq Output 1 (transmitter asserts this signal when the FIFO
is full)
Asserted when there is data present on the
start_output Output 1
out_data lines
3.4 FIFO
First In First Out is a popular data structure (also known as queue) that is used for
buffering in order to provide flow control. We obtained the FIFO from Altera’s
FIFOs of any width and depth with various options of control and status signals. Using
technology specific modules allows for quick prototyping of the design. Hence all we had
design.
Now the following sections describe the various building blocks of the OFDM transmitter
as shown in Figure 3.2. The functions of these blocks and their role in the OFDM system
were briefly discussed in Chapter 1, therefore here the hardware implementation details
3.5 SCRAMBLER
a signal’s power spectrum upon the actual transmitted data and making it more disperse
concentrated in a narrow frequency band, it can interfere with adjacent channels [14].
24
Chapter 3 Transmitter Design and Implementation
Figure 3.1 shows the input/output parameters of the Scrambler. Input bus is 1 bit wide
and arst_n is the asynchronous reset input. A negative edge on the arst_n input resets
the Scrambler. A bit is latched in at the positive edge of the clock. See Table 3.3 for a
In
arst_n
enable
Signal
Type Width Description
Name
in Input 1 Input data to the transmitter
Scramblers can be implemented using a Linear Feedback Shift Register (LFSR) [9]. An
adders (i.e. XOR gates). Feedback is taken from two or more memory elements, which
are XOR-ed and fed back to the first stage (memory element) of the LFSR. In the
proposed design, a standard 7 bit scrambler has been used to randomize the incoming
bits. An initial seed value is stored in the LFSR when arst_n is asserted; this value may
25
Chapter 3 Transmitter Design and Implementation
be any random bit string except for all zeroes or all ones. If the initial seed contains all
zeroes or all ones then the LFSR is locked in a state where every output value is same
out
, 6 5 4 3 2 1 0
in
Figure 3.2 shows the basic construction of the scrambler. A feedback output, which is
actually the modulo-2 added result of the contents of memory elements 4 and 7, is XOR-
ed with the input and the result is designated as output and it is also shifted into the first
stage. These memory elements are actually flip-flops (D-flip flops are used here); with
the output of each flip flop acting as the input for the next flip flop.
Figure 3.3 shows, in detail, the circuit diagram of the scrambler. We can see that the
reset (arst_n) is asserted on the negative edge, this is shown by the bubble at the reset
26
Chapter 3 Transmitter Design and Implementation
out
D Q D Q D Q D Q D Q D Q D Q
clock
arst_n
in
Reed Solomon forward error correcting codes have become commonplace in modern
Solomon, then working at MIT Lincoln Labs [21], it was many years before technology
Versions of Reed Solomon codes are now used in error correction systems found just
Voyager)
Reed Solomon codes work by adding extra information (redundancy) to the original
data. The encoded data can then be stored or transmitted. When the encoded data is
27
Chapter 3 Transmitter Design and Implementation
recovered it may have errors introduced, for instance by scratches on the CD,
imperfections on a hard disk surface or radio frequency interference with mobile phone
reception. The added redundancy allows a decoder (with certain restrictions) to detect
which parts of the received data are corrupted, and correct them [22]. The number of
errors the code can correct depends on the amount of redundancy added.
RS codes are a systematic linear block code. It is a block code because the code is put
together by splitting the original message into fixed length blocks. Each block is further
sub divided into m-bit symbols [22]. Each symbol is a fixed width, usually 3 to 8 bits
The linear nature of the codes ensures that in practice every possible m-bit word is a
valid symbol. For instance with an 4-bit code all possible 4 bit words are valid for
encoding, and you don't have to worry about what data you are transmitting. Systematic
means that the encoded data consists of the original data with the extra 'parity' symbols
appended to it [22].
n = 2m − 1 3.1
k = 2 m − 1 − 2t 3.2
(n − k )
t= 3.3
2
where m is the number of bits per symbol, k is the number of input data symbols (to be
encoded), n is the total number of symbols (data + parity) in the RS codeword and t is
the maximum number of data symbols that can be corrected. The difference n-k (usually
called 2t) is the number of parity symbols that have been appended to make the
encoded block.
In the proposed design n=15 and k=9 represented by RS (15, 9). It gives m=4 and t=3.
Therefore, each symbol is 4 bits wide and a maximum of 3 symbols can be corrected in
28
Chapter 3 Transmitter Design and Implementation
the decoder. Figure 3.4 graphically represents an n symbol code showing the parity and
data portions.
n symbols
The power of Reed Solomon codes lies in being able to just as easily correct a
corrupted symbol with a single bit error as it can correct a symbol with all its bits in
error. This makes RS codes particularly suitable for correcting burst errors. Usually the
upto 12 bits could be corrupted affecting at most 3 symbols, and the original message
However it does mean that RS codes are relatively sensitive to evenly spaced errors.
Reed Solomon codes are based on finite fields, often called Galois fields. Rather than
look at all the numbers that can be obtained from some given initial collection by using
collection is called a field. Some fields, like the set of integers, are infinite.
Galois fields have the useful property that any operation on an element of the field will
always result in another element of the field [23]. The field is also finite, so it can be
traditional mathematics, results in a value out of the field gets mapped back in to the
29
Chapter 3 Transmitter Design and Implementation
Galois arithmetic has very little to do with counting things, 2+2 is not necessarily 4. For
ease of handling the Galois field elements are often called by their binary equivalent,
but this can be misleading. There are many Galois fields, and part of the RS
more difficult, (as always) but can be done using purely combinational logic.
An RS code with 4 bit symbols will use a Galois field GF (24), consisting of 16 symbols.
Thus every possible 4 bit value is in the field. The order in which the symbols appear
depends on the primitive polynomial [23]. This polynomial is used in a simple iterative
algorithm to generate each element of the field. Different polynomials will generate
different fields. The primitive polynomial used in the proposed design for GF (24) is,
P( X ) = 1 + X + X 4 3.4
The elements of the Galois field GF (24) are generated by using this primitive
polynomial. The symbol is used to give the power representation of each element.
30
Chapter 3 Transmitter Design and Implementation
13
1011
14
1001
These values are calculated by substituting for X in the primitive polynomial such that,
α 4 = 1+α 3.5
4 5
This will give the value of , and for the value of we write,
α 5 = α 4α 3.6
α 5 = (1 + α )α 3.7
α5 = α +α 2 3.8
The final parameter that is used to generate RS codes is the generator polynomial [23].
G ( X ) = ( X + α )( X + α 2 )( X + α 3 )( X + α 4 )......( X + α 2t ) 3.9
For our case (i.e. RS (15, 9) and 2t=6) the generator polynomial turns out to be,
G ( X ) = α 6 + α 9 X + α 6 X 2 + α 4 X 3 + α 14 X 4 + α 10 X 5 + X 6 3.10
Given n, k, the symbol width m, the Galois field primitive polynomial P and the
31
Chapter 3 Transmitter Design and Implementation
Since the code is systematic, the whole of the block can be read into the encoder, and
then output the other side without alteration. Once the kth data symbol has been read
in, the parity symbol calculation is finished, and the parity symbols can be output to give
The idea of the parity words is to create a long polynomial (n coefficients long – it
contains the message and the parity) which can be divided exactly by the RS generator
polynomial. That way, at the decoder the received message block can be divided by the
RS generator polynomial. If the remainder of the division is zero, then no errors are
another is not conceptually easy, but if you follow the mathematics in some of the
The encoder acts to divide the polynomial represented by the k message symbols D(x)
Figure 3.5 (on next page) depicts the top level architecture of the proposed Reed
Solomon Encoder. This is a bit-serial Reed Solomon Encoder which means that its
input bus is one bit wide. One bit is latched per positive edge of the clock. Having 4 bits
per symbol makes it clear that 4 clock cycles are required to input a symbol. arst_n is
Signal
Type Width Description
Name
32
Chapter 3 Transmitter Design and Implementation
The encoder contains the following three building blocks (as shown in Figure 3.5):
• Shift Registers
clock
arst_n
Shift Registers
in_data
out
This block contains 2t shift registers each m bits wide. Therefore, for our case there
would be 6 shift registers each 4 bits wide. One of these six registers has parallel
Figure 3.6 is a detailed architecture of Reed Solomon Encoder. It is seen that the reset
and clock signals are not shown. We can see the six shift registers. The output of each
register becomes the shift input of the next register stage. An exception is Reg5; its
output is XORed with the input data bit and then ANDed with the compliment of
redundancy interval bit (red), and then this output of the AND gate becomes the shift
input for Reg4. Outputs of these registers act as inputs for the Galois Field block
described next.
33
Chapter 3 Transmitter Design and Implementation
-
MUX
. out
)
in_data
Redundancy
red interval controller red
The Galois Field Adder and Multiplier block performs all the Galois Field arithmetic
functions. Figure 3.7 depicts the internal architecture of the GF multiplier and adder.
It works as follows: R0 to R5 are basically register outputs that are shifted out into the
GF circuit (as shown in figure 3.6). This circuit basically multiplies contents of each
register with a constant multiplier which is established by connections to the XOR gates.
For instance, R1 is connected to 2nd and 4th XOR gates so R1 is multiplied by 0101
9
which is and is also a coefficient of the generator polynomial. In this way every
after these multiplications the products are added. This process takes four clock cycles
and in the fourth cycle the result is loaded into R5 as shown in figure 3.6.
34
Chapter 3 Transmitter Design and Implementation
.
-
#
$
/
0
D3 D2 D1 D0
Figure 3.6 shows how the Redundancy interval controller is connected to the main
circuit. For the first 36 clock cycles (9x4) the redundancy signal (given the name red in
figure 3.6) is low and data bits go into the circuit and through the multiplexer as well.
But after that the red signal goes high allowing the parity bits to pass through the
multiplexer. Redundancy is the name given to the interval during which data bits are not
allowed to get into the circuit and parity bits are brought out. To achieve this, a 6-bit
counter is employed. Using this counter a high output is obtained when the counter
communication systems. The purpose of forward error correction (FEC) is to improve the
data being transmitted through the channel [4]. The process of adding this redundant
information is known as channel coding [4]. Convolutional codes operate on serial data,
one or a few bits at a time. There are a variety of useful Convolutional, and a variety of
35
Chapter 3 Transmitter Design and Implementation
algorithms for decoding the received coded information sequences to recover the
original data.
Convolutional codes are usually described using two parameters: the code rate and the
constraint length. The code rate, m/n, is expressed as a ratio of the number of bits into
the Convolutional encoder (m) to the number of channel symbols output by the
Convolutional encoder (n) in a given encoder cycle. The constraint length parameter, K,
denotes the "length" of the Convolutional encoder, i.e. how many k-bit stages are
available to feed the combinatorial logic that produces the output symbols. Convolutional
codes are often used to improve the performance of digital radio, mobile phones, and
satellite links.
In the proposed design a Convolutional encoder with a code rate of ½ has been chosen
i.e. m=1 and n=2. A constraint length of 7 is kept because it is standard and its decoding
Figure 3.8 shows the I/O parameters of the Convolutional Encoder. Input bus is 1 bit
wide and arst_n is the asynchronous reset input. A negative edge on the arst_n input
resets the encoder. A bit is latched in at the positive edge of the clock. For every input
bit there is a two bit wide output designated by even and odd. Table 3.6 gives
in even
enable
clock Convolutional
Encoder odd
arst_n
36
Chapter 3 Transmitter Design and Implementation
Signal
Type Width Description
Name
“Algorithmic State Machine” [16]. However, a shift register gives an easy to implement
For the configuration of m=1, n=2 and k (constraint length) =7, Figure 3.9 shows how the
Initially all zeroes are stored in the register. When the first input bit arrives it is shifted
into the register from left and the 2 bit output appears on the lines designated as even
and odd.
6 5 4 3 2 1 0
in
odd even
37
Chapter 3 Transmitter Design and Implementation
The even output is generated by adding the contents of 1st, 0, 3rd, 4th and 6th stages of
the shift register, whereas the odd output is generated by adding the 5th, 0, 3rd, 4th and
6th stages of the register. This addition is modulo-2 addition carried out through XOR
gates (modulo-2 addition is basically a XOR operation). Just like the Scrambler the
3.8 INTERLEAVER
transmission against burst errors. These errors overwrite a lot of bits in a row, but
Conceptually, the in-coming bit stream is re-arranged so that adjacent bits are no more
adjacent to each other. Actually the data is broken into blocks and the bits within a block
are re-arranged. In the proposed design, a block consists of 64 symbols (128 bits).
elements (usually RAMs) are used. In the first RAM the incoming block of bits is stored
in sequential order. This data from the first RAM is read out randomly (using an
algorithm) so that the bits are re-arranged and stored in the second RAM and then read
out.
As mentioned above that the incoming bit stream is broken into blocks, when
interleaving in the OFDM system the block size should be equal to the size of an OFDM
38
Chapter 3 Transmitter Design and Implementation
symbol. Since there are 64 sub-carriers and each sub-carrier is modulated using QPSK,
therefore in one OFDM symbol there would be 128 bits. Hence, the job of the interleaver
As discussed above, the function that the interleaver has to perform is to read 128 bits,
re-arrange them and read them out. This can be accomplished by using RAMs for
temporarily storing the bits and then the bits can be read out from the RAMs in the
desired order. Remember that the block before the interleaver is the Convolutional
Encoder that gives an output of two bits. Therefore the input bus of the interleaver
in
2
arst_n
Address ROM
enable
39
Chapter 3 Transmitter Design and Implementation
Signal
Type Width Description
Name
Note that the input and output buses are two bits wide. The three building blocks of the
interleaver are:
• Block Memory
• Controller
• Address ROM
The block memory contains the memory elements necessary to store the incoming block
of data. There are a total of four memory elements; each is a 64x1 RAM. Four RAMs are
used in order to achieve pipelined operation. Two of these RAMs are used for writing a
block while another block is being read out from the other two RAMs. In this way the
RAMs are alternately switched between reading and writing modes. Hence, reading and
writing is done simultaneously without any latency. The configuration of each of these
RAMs is such that two bits are written at a time in two memory locations and one bit is
read at a time. Recall that input to the interleaver is two bit wide, therefore that takes
care of it. Two memories each 64x1 is used instead of a single memory 128x1 because
While writing a block of data (i.e. 128 bits), 16 bits are alternately written into the 64x1
RAMs. That is to say that first 16 bits are written to the first RAM, next 16 to the second
RAM, next 16 again to the first RAM and so on. This is done in order to keep the two bits
40
Chapter 3 Transmitter Design and Implementation
The job of the controller is to guide the incoming block of data to the correct memory
blocks, to switch the RAMs between reading and writing modes, and to switch between
the two RAMs for 16 alternate bits in writing mode. This is done by using counters.
The address ROM is basically a 64x6 ROM that stores read addresses for the RAMs.
Note that a single ROM is enough for the four RAMs. This is because only two RAMs at
a time are in the read mode and the two bits that are read out of the two RAMs are in the
same memory locations as per the design. Each location of the ROM is 6 bits wide
Figure 3.13 shows the circuit diagram of interleaver. Counter1 and Counter2 provide for
the write addresses for the four RAMs 1A, 2A, 1B and 2B. Counter C is a 3-bit counter
that controls switching between either RAM 1A and RAM 2A or RAM 1B and RAM 2B
depending upon which RAMs are in write mode. Counter1 and Counter2 are 5-bit
counters after every 8th count control switches to either Counter1 or Counter2; this is
controlled by Counter C. The SYNC signal decides which RAMs must write and which
should read. When SYNC is 0 RAM 1A and RAM 2A are in write mode and RAM 1B and
For the first data block SYNC remains 0 and therefore the block is written to RAM 1A
and RAM 2A. When the last bit of the block is written SYNC goes high and RAM 1A and
RAM 2A go in read mode, whereas RAM 1B and RAM 2B go in write mode and the next
block is written to these blocks. At the same time the previous is read out of RAMs 1A
Contents of the Address Rom are shown in Table. Note that the output of ROM is
41
Chapter 3 Transmitter Design and Implementation
45
-
1 1
1 1
- -&
2 2
31 1
31 1
1 1
1 1
#
# #&
2 2
31 1 31 1
42
Chapter 3 Transmitter Design and Implementation
13 19
14 35
15 51
16 4
17 20
18 36
19 52
20 5
21 21
22 37
23 53
24 6
25 22
26 38
27 54
28 7
29 23
30 39
31 55
32 8
33 24
34 40
35 56
36 9
37 25
38 41
39 57
40 10
41 26
42 42
43 58
44 11
45 27
46 43
47 59
48 12
49 28
50 44
51 60
52 13
53 29
54 45
55 61
56 14
57 30
58 46
59 62
60 15
61 31
62 47
63 63
43
Chapter 3 Transmitter Design and Implementation
Constellation Mapper maps the incoming bits onto separate sub-carriers. In the
proposed design there are 64 sub-carriers and each of them is modulated using QPSK,
therefore the function of Constellation Mapper would be to map every two bits on a
Figure 3.14 shows the constellation diagram of QPSK. Mapping of bits on constellation
points is done in accordance with gray code so that adjacent constellation points may
have just one bit different. Table 3.3 shows the data bits and the corresponding
constellation points.
The block before Constellation Mapper is the Interleaver which gives an output of two
bits per clock cycle. Therefore, two bits are mapped to a constellation point every clock
cycle.
A ROM is used to store the constellation points. Each constellation point is represented
by 48 bits in binary. In these 48 bits, the most significant 24 bits represent the real part
44
Chapter 3 Transmitter Design and Implementation
and the least significant 24 bits represent the imaginary part. In both the real and
imaginary parts the most significant 8 bits are the integer part and the least significant 16
bits represent the fractional part. 2’s complement notation has been used to represent
The incoming input bits (2 bits) act as address for the ROM. Table 3.4 shows the ROM
contents at each address location. Each of these values in the ROM is a constellation
point corresponding to the data bits which here act as addresses for the ROM.
Input
#
Clock % 6/ /78
Output
/7
Figure 3.15 shows the circuit of a constellation Mapper. It contains nothing but a ROM.
Note that the input is two bits wide and the output is 48 bits wide. For a description of the
Signal
Type Width Description
Name
45
Chapter 3 Transmitter Design and Implementation
computational requirements, therefore, Fast Fourier Transform (FFT) was utilized. For
but that for FFT/IFFT is Nlog (N), which is much lesser than DFT.
The FFT/IFFT operates on finite sequences. Waveforms which are analog in nature
must be sampled at discrete points before the FFT/IFFT algorithm can be applied.
The Discrete Fourier Transform (DFT) operates on sample time domain signal which is
N −1
X (k ) = x(n)e − j 2πk / N 3.11
n =0
X(k) represents the DFT frequency output at the k-the spectral point where k ranges
from 0 to N-1. The quantity N represents the number of sample points in the DFT data
frame. The quantity x(n) represents the nth time sample, where n also ranges from 0 to
The corresponding inverse discrete Fourier transform (IDFT) of the sequence X(k) gives
46
Chapter 3 Transmitter Design and Implementation
N −1
1
x ( n) = X (k )e j 2πk / N 3.12
N k =0
N −1
X (k ) = x(n)W Nnk 3.13
n=0
This quantity is called Twiddle Factor. It is the sine and cosine basis function written in
Examination of the first equation reveals that the computation of each point of DFT
requires the following: (N-1) complex multiplication, (N-1) complex addition (first term in
sum involves ej0 = 1). Thus, to compute N points in DFT require N(N-1) complex
because the multiplication function requires a relatively large amount of processing time
even using computer. Thus, many methods for reducing the number of multiplications
When the number of data points N in the FFT/IFFT is a power of 4 (i.e., N = 4v), we can,
of course, always use a radix-2 algorithm for the computation. However, for this case, it
47
Chapter 3 Transmitter Design and Implementation
In the decimation-in-frequency algorithm, the outputs or the frequency domain points are
N −1 − j 2πk / N
1
X (k ) = x ( n)e 3.15
N k =0
As an example we consider N=16. We split or decimate the N-point input sequence into
get X(k), X(k+N/4), X(k+N/2) and X(k+3N/4). This process is called decimation in
frequency. This decimation continues until each DFT becomes a 4 point DFT. Each 4
point DFT is known as a butterfly when we represent it graphically. Figure 3.16 shows a
Since in the proposed design there are 64 sub-carriers so the input to FFT would be 64
For a 4n point FFT n stages are required and N/4 4 point DFTs per stage. Therefore in
our case there would be 3 stages (64 = 43) and 16 4 point DFTs per stage or we can say
48
Chapter 3 Transmitter Design and Implementation
inputs to the FFT are given in the actual order [25]. In this way we get the output in a re-
arranged order.
In the proposed design radix-22 DIT FFT algorithm is targeted because its butterfly is
simple like that of radix 2 and no. of complex multiplications are less like radix 4. Figure
In the radix-22 algorithm, a radix-4 butterfly is created using two radix-2 butterflies. The
benefit of using the radix 2 algorithm is the ease of controlling the butterfly due to its
From here on whenever I mention FFT, it will ll incorporate both IFFT and FFT. Basically
there are two ways to implement FFT in hardware, one is using pipelined architecture
and the other is using memory-based architecture. The former requires less hardware
resources and hence occupies less area, but requires greater number of clock cycles.
On the other hand in the memory-based architecture more hardware resources are
required but it takes less number of clock cycles. In the proposed design pipelined
architecture has been chosen in order to make the FFT design area efficient.
Additionally, fixed point FFT implementation has been carried out to avoid any overflows
49
Chapter 3 Transmitter Design and Implementation
Figure 3.18 shows the I/O diagram of IFFT and description of the I/O parameters is
clock
arst_n
realoutput
enable IFFT
imgoutput
realinput
imginput
Signal
Type Width Description
Name
arst_n Input 1 Asynchronous reset (negative edged)
clock Input 1 Positive edged clock
When high data is present on the realinput and
enable Input 1
imginput lines
realinput Input 24 Real part of the input complex number
Imginput Input 24 Imaginary part of the input complex number
Realoutput Output 24 Real part of the output complex number
Imgoutput Output 24 Imaginary part of the output complex number
Complex data is fed in one data-point per clock cycle. The enable signal is asserted the
Figure A.2 is a block diagram of a 64-point Radix-22 fixed-point FFT example. The
module consists of six radix-2 butterflies, shift registers associated with each butterfly,
two complex multipliers, two twiddle factor generators, and a controller that provides the
control signals. The feedback shift registers vary in length from 1 to 32-bits, and are
labeled accordingly.
50
Chapter 3 Transmitter Design and Implementation
Controller
Each group of two butterflies, consisting of a bf2i and a bf2ii, together emulate a radix-4
butterfly. Figure 3.19 shows the internals of each and how they are connected together.
[25]. The FFT Radix-2 butterfly must have two inputs in order to produce the next FFT
intermediate value, but the data in our scenario is available only in a serial mode. The
51
Chapter 3 Transmitter Design and Implementation
SDF mechanism provides a solution where the first input is delayed until the second
input is presented, after which the calculation can proceed. Both the bf2i and bf2ii
modules accomplish this by multiplexing the first input to a shift register of sufficient
length so that that data-point is present at the butterfly input when the second data-point
appears. A counter provides the control signals for these multiplexers, which are internal
The counter additionally provides signals to the bf2ii for switching the adder operations,
and swapping the real and complex input wires. These mechanisms effect a
In order to avoid overflow, the data set is scaled down as it propagates through the
pipeline. The FFT operation consists of a long series of summations, and thus either the
floating-point), or the numerical data must be scaled down. Since the module is fixed
Cyclic prefix is basically a replica of a fractional portion of the end of an OFDM symbol
interference that can occur due to Multipath. Cyclic prefix is effective only if its duration
The architecture of cyclic prefix adder simply consists of an address ROM that stores
addresses, a RAM to store incoming data in sequential order and a counter that
provides read addresses to the RAM. Figure 3.20 shows the top-level architecture of the
cyclic prefix adder. Refer to Table 3.7 for the description of I/O signals.
52
Chapter 3 Transmitter Design and Implementation
in
arst_n
enable
Address counter
Signal
Type Width Description
Name
arst_n Input 1 Asynchronous reset (negative edged)
clock Input 1 Positive edged clock
When high data is present on the realinput and
enable Input 1
imginput lines
In Input 48 Input complex number
Out Output 48 Output complex number
In the proposed design, the last eight symbols (complex numbers) of the OFDM symbol
are replicated at the beginning of the symbol, therefore a total of 72 (64 + 8) symbols are
actually transmitted.
53
Chapter 4 Receiver Design and Implementation
CHAPTER 4
4.1 INTRODUCTION
This chapter gives detailed description about the implementation of the receiver part of
the project. The receiver has been implemented on the same Cyclone III board. It
consumes about 5600 out of the 24,600 logic elements present in the board.
The OFDM receiving unit receives its input directly from the transmitter whenever its
output is available. The receiver follows an exact reverse procedure of which was
followed in the transmitter. It receives the complex (modulated) output points and
performs demodulation and recovers the original bits sent to the transmitter.
I/O diagram of the receiver is shown in Figure 4.2. We can see that there are no control
or status signals to or from a FIFO; the reason is that the modulated data, from the
transmitter, is directly fed to the receiver as input. Description of the shown signals is
in_data
clock out_dat
OFDM Receiver
arst_n
start_output
enable
54
Chapter 4 Receiver Design and Implementation
Signal
Type Width Description
Name
in_data Input 48 Input data to the receiver
Figure 3.2 shows the hardware architecture of the complete OFDM system highlighting
the receiver part this time. The various blocks that constitute the receiver are shown.
The receiver, just like the transmitter, operates at a clock frequency of 20 MHz provided
Now the rest of the chapter is dedicated to the detailed description and design of the
55
Chapter 4 Receiver Design and Implementation
PLL FIFO
HSMC TO
SANTA CRUZ
CONNECTOR
RS232
Receiver
OFDM
High Speed Mezzanine Connector Transmitter
Input
RS232 port
FFT
Control Unit
Constellation demapper
Interleaver
Viterbi decoder
OFDM Receiver
RS decoder
FIFO
Descrambler
RS232 Transmitter
Figure 4.2 Complete Architecture of the proposed OFDM system (receiver highlighted)
The cyclic prefix was added at the transmitting end in order to avoid inter-symbol
interference, therefore during reception it must be eliminated for any further processing
of the received signal. This is done by simply skipping the first eight sub-carriers in the
56
Chapter 4 Receiver Design and Implementation
received OFDM symbol. In hardware this is implemented in the control unit. The control
unit only enables the next block (FFT) when the first eight bits of the received OFDM
Details on FFT/IFFT algorithm and hardware implementation were given in the previous
chapter. The only difference being that if it was given for IFFT (although FFT was
same, only the difference is that the divider is removed and the real and imaginary parts
at the input are swapped i.e. real becomes imaginary and imaginary becomes real.
Same goes for the output i.e. real and imaginary parts at the output are swapped as
imginput imgoutput
realinput realoutput
The function of the constellation demapper is to map the QPSK symbols (complex
numbers) coming from the output of FFT to the data points shown in the constellation
diagram shown in Figure 3.4. Basically it is the inverse procedure of what was done in
57
Chapter 4 Receiver Design and Implementation
The mapping of data points to QPSK symbols (as done in the transmitter) is shown in
Table 4.3.
Therefore, basically the incoming constellation points are mapped onto the data points
as shown in Table 3.4. Figure 4.5 shows the I/O diagram of the constellation demapper
clock
arst_n out
Constellation
Demapper
in
58
Chapter 4 Receiver Design and Implementation
Signal
Type Width Description
Name
Instead of going into the hardware architecture, the design is shown using the Verilog
code. A simple switch-case structure is used to construct the design. The code is shown
below:
always @(in)
begin
case ({in[47], in[23]})
2'b00: tmp_out = 2'b00;
2'b01: tmp_out = 2'b10;
2'b10: tmp_out = 2'b01;
2'b11: tmp_out = 2'b11;
default: tmp_out = 2'b00;
endcase
end
Figure 4.6 Verilog code showing the logic behind implementation of constellation
demapper
4.6 DE-INTERLEAVER
In the previous chapter interleaving was defined as a process in which bits, within a
block of 128 bits, are re-arranged in order to avoid burst errors. De-interleaving performs
the inverse task. It re-arranges the interleaved bits into their original order.
Recall the row-column method of interleaving discussed in the previous chapter. De-
interleaving is done the same way, the difference being that the number of rows and the
59
Chapter 4 Receiver Design and Implementation
interleaving on a block of 16 bits using a matrix with 8 rows and 2 columns, then the
interleaved pattern can be de-interleaved using a matrix with 2 rows and 8 columns.
Hence the only difference in the hardware architectures of interleaver and de-interleaver
is the contents of the address ROM, which actually provides the read addresses to the
RAM that stores the data to be de-interleaved. Table 4.4 shows the new contents of the
60
Chapter 4 Receiver Design and Implementation
36 36
37 44
38 52
39 60
40 5
41 13
42 21
43 29
44 37
45 45
46 53
47 61
48 6
49 14
50 22
51 30
52 38
53 46
54 54
55 62
56 7
57 15
58 23
59 31
60 39
61 47
62 55
63 63
The Viterbi Decoder decodes Convolutional codes. We have used the Altera’s Viterbi
Decoder IP core in our design. Altera’s Viterbi IP core is a parameterized IP core that is
synthesizable and allows for parallel as well as hybrid implementation of the Viterbi
decoder.
The Reed Solomon decoder decodes the codes generated by the Reed Solomon
Encoder. For the implementation of the Reed Solomon Decoder we have again used
61
Chapter 4 Receiver Design and Implementation
4.9 DESCRAMBLER
Figure 3.1 shows the input/output parameters of the Descrambler. A bit is latched in at
the positive edge of the clock. See Table 4.5 for a description of the signals.
In
arst_n
enable
Signal
Type Width Description
Name
in Input 1 Input data to the Descrambler
Figure 4.8 shows the Descrambler. Note that the structure is quite same.
62
Chapter 4 Receiver Design and Implementation
6 5 4 3 2 1 0
in
, ,
out
63
Chapter 5 Simulation, Synthesis and Results
CHAPTER 5
5.1 INTRODUCTION
This chapter discusses the simulation results obtained from the ModelSim with random
input samples and also the important synthesis results obtained from Quartus II. The
accuracy of the output has been compared to the output from MATLAB simulation. The
result is divided into 2 different sections, for OFDM Transmitter and OFDM Receiver.
The output from each of the modules is shown and followed by the overall output.
5.2.1 SCRAMBLER
To verify proper functioning of the Scrambler was initially fed with a seed value of
1110101 and the following input bit stream was given to the Scrambler:
in: 0110101000
out: 1101110001
After a dry run of the scrambler using high-level modelling in Verilog it was verified that
64
Chapter 5 Simulation, Synthesis and Results
In order to check the proper functioning of Reed Solomon Encoder a test bench was
written in Verilog. The input given to the encoder through the test bench was a string of
in: 555555555H
It is well known in the art that if all the input symbols to a Reed Solomon encoder are
identical, then the parity symbols will all be identical as well and will be equal to the input
out: 555555555555555H
Other input combinations were also given and desired results were achieved that
After simulation of the above shown Verilog code the following waveform was
generated. It can be seen that first of all a low pulse was given to the arst_n (reset) input
in order to initialize the shift register with all zeroes. Next the following bit stream was
in: 1011101
out: 11010001011100
65
Chapter 5 Simulation, Synthesis and Results
For a 7 bit input a 14 bit output is generated. Figure 14 shows the resultant waveforms
after the simulation of the Convolutional Encoder. Once again this circuit was taken
through a dry run using high level modeling in Verilog and the results were verified.
5.2.4 INTERLEAVER
The waveform for the interleaver goes upto 128 clock cycles. Therefore, it is not shown
here. For an input block of data containing alternate 1s and 0s the output was
out: 0000000011111111000000001111111100000000………….so on
Following wave form shows that when an input of 10 was given to the Constellation
out: 00b504ff4afch
5.2.6 IFFT
The IFFT was tested by giving the following 64 complex data points,
66
Chapter 5 Simulation, Synthesis and Results
47'h000011100101
47'h000011100101
Note that the first eight outputs are actually the last eight inputs and the rest of the
output points are same as the inputs. The following waveform shows the same
67
Chapter 5 Simulation, Synthesis and Results
Table 5.1 shows some important synthesis results for each module of the OFDM
transmitter.
The Cyclic Prefix Remover simply removes the cyclic portion added at the transmitting
end, and the simulation of the next block FFT is similar to IFFT so it is not shown. In
addition to these blocks the simulations of Viterbi Decoder and Reed Solomon Decoder
are also not shown because their ip cores are used in the project. Simulation results for
and
00 and 01
68
Chapter 5 Simulation, Synthesis and Results
As shown in Figure 5.7. The results are in accordance with table 3.4
5.4.2 DE-INTERLEAVER
Just like the interleaver the simulation waveform of de-interleaver extends to 128 cycles
5.4.3 DE-SCRAMBLER
b111111111000000000
b110111111111000010
which is shown in figure 5.8. The output has been verified using MATLAB (using
69
Chapter 5 Simulation, Synthesis and Results
70
References
REFERENCES
[7] Aseem Pandey, Shyam Ratan Agrawalla & Shrikant Manivannan, “VLSI
Implementation of OFDM”, Wipro Technologies, September 2002.
[14] Lattice Semiconductor white paper, “Implementing WiMAX OFDM Timing and
Frequency Offset Estimation in Lattice FPGAs,” 2005.
71
References
[15] Doelz, M.L., Heald E.T. and Martin D.L. "Binary Data Transmission Techniques
for Linear Systems." Proc. I.R.E., 45: 656-661, May 1957.
[20] Michael D. Ciletti, Advanced Digital Design with the Verilog HD Xilinx Design Series.
Prentice Hall, 2002.
72
Appendix A RTL code in Verilog for OFDM Transmitter
APPENDIX A
//**********************************************
// OFDM System - OFDM Transmitter and
// Receiver
//**********************************************
module OFDMSystem (
input in,
input clock,
input arst_n,
output TxD,
output start_output
);
//******************************************
//PLL
//******************************************
PLL pll(
clock,
clock1,
clock2
);
//*****************************************
//FIFO
//*****************************************
73
Appendix A RTL code in Verilog for OFDM Transmitter
fifo input_data_fifo (
in_data,
clock1,
readreq,
clock2,
RxD_data_ready,
out_fifo,
readempty,
readfull,
wrempty,
wrfull
);
//***************************************
// OFDM Transmitter module
//***************************************
OFDM_transmitter transmitter (
clock1,
arst_n,
out_fifo,
out_data,
wrfull,
readreq,
readempty,
start_output
);
//****************************************
// RS-232 Asyncronous Receiver
//****************************************
async_receiver SerialReceiver(
clock2,
arst_n,
in,
RxD_data_ready,
in_data,
idle
);
//****************************************
// RS-232 Asyncronous Transmitter
//****************************************
async_transmitter serialtrans(
clock2,
arst_n,
start_trans,
q,
TxD,
TxD_busy
);
//*******************************************
// FIFO for storing transmitter's output
//*******************************************
74
Appendix A RTL code in Verilog for OFDM Transmitter
trans_out_fifo fifo(
{out_data,16'd0},
clock2,
(start_serialtrans & ~TxD_busy & !start_trans),
clock1,
start_output,
q,
rdempty1,
rdfull1,
rdusedw,
wrempty1,
wrfull1,
wrusedw
);
//*********************************************************
//*********************************************************
//*********************************************************
endmodule
//*****************************************
75
Appendix A RTL code in Verilog for OFDM Transmitter
module OFDM_transmitter (
input clock,
input arst_n,
input in_data,
output [47:0] out_data,
input wrfull,
output readreq,
input readempty,
output start_output
);
//************************************
//Control Unit
//************************************
ControlUnit controlunit (
clock,
arst_n,
wrfull,
readempty,
readreq,
controlword
);
//*************************************
//Scrambler
//*************************************
Scrambler scrambler (
clock,
arst_n,
controlword[6],
in_data,
scrambler_out
);
//***************************************
//Reed Solomon [RS (15,9)] encoder
//***************************************
ReedSolomon_Encoder rs_enc (
clock,
scrambler_out,
controlword[5],
76
Appendix A RTL code in Verilog for OFDM Transmitter
arst_n,
rs_out
);
//***************************************
//Convolution Encoder (k=7, m=1, n=2)
//***************************************
convolution conv_enc (
clock,
arst_n,
rs_out,
controlword[4],
even_conv,
odd_conv
);
//***********************************
//Interleaver
//***********************************
Interleaver interleaver (
clock,
arst_n,
{odd_conv, even_conv},
controlword[3],
interleaver_out
);
//****************************************
//Constellation Mapper (QPSK)
//****************************************
const_mapper constmapper (
clock,
arst_n,
interleaver_out,
constmap_out
);
//******************************************
//IFFT (64-point)
//******************************************
ifft IFFT (
clock,
arst_n,
controlword[2],
constmap_out[47:24],
constmap_out[23:0],
ifft_out[47:24],
ifft_out[23:0]
);
//*******************************************
//Cyclic Prefix Adder (1/8)
//*******************************************
77
Appendix A RTL code in Verilog for OFDM Transmitter
cyclic_prefix CyclicPrefixAdder (
clock,
arst_n,
controlword[1],
ifft_out,
cyclic_out
);
//*******************************************
//End of blocks
//*******************************************
endmodule
//***************************************
// Control Unit
//***************************************
module ControlUnit (
input clock,
input arst_n,
input readfull,
input readempty,
output reg readreq,
output reg [6:0]controlword
);
//*************************************
//Control signal for Scrambler
//*************************************
78
Appendix A RTL code in Verilog for OFDM Transmitter
//****************************************
//Control signal for Reed Solomon Encoder
//****************************************
//*****************************************
//Control signal for convolutional encoder
//*****************************************
79
Appendix A RTL code in Verilog for OFDM Transmitter
end
//**************************************
//Control signal for the Interleaver
//**************************************
//***********************************
//Control signal for ifft
//***********************************
80
Appendix A RTL code in Verilog for OFDM Transmitter
else if(temp)
counter_en_ifft <= counter_en_ifft + 8'd1;
end
//***************************************
//Control signal for cyclic prefix
//***************************************
//****************************************
//Output control signal
//****************************************
81
Appendix A RTL code in Verilog for OFDM Transmitter
//******************************
//Read request
//******************************
endmodule
//********************************************
//Scrambler module
//********************************************
module Scrambler (
input clock, //positive edged clock signal
input arst_n, //Asynchronous negitive edged reset
input enable,
input in, //Input to the Scrambler
output out //Output of the Scrambler
);
wire actual_in;
//********************************************
//This always block shifts the LFSR register
//one position towards right and shifts the
//input XORed with the feedback in the left
//most position of LFSR. If arst_n is asserted
//then seed value is fed to the LFSR
//*********************************************
82
Appendix A RTL code in Verilog for OFDM Transmitter
endmodule
//**********************************************
// Bit-Serial RS(15,9) Encoder
//**********************************************
module ReedSolomon_Encoder (
input clock,
input in_data,
input enable,
input arst_n,
output reg out
);
GF_multiply_sum multiply_sum (
clock,
(~(count_out[0] & count_out[1])) & arst_n,
{(R5out ^ (in_data & ~red)) & ~red,
83
Appendix A RTL code in Verilog for OFDM Transmitter
Reg4[0],
Reg3[0],
Reg2[0],
Reg1[0],
Reg0[0]},
enable,
GF_out
);
COUNTER_2_BIT counter2bit (
clock,
arst_n,
enable,
count_out
);
Redundancy redundancy (
clock,
arst_n,
enable,
red,
clearA
);
s_reg_par_load_4 Reg5 (
~(count_out[0] & count_out[1]),
GF_out,
1'b0,
clock,
reset,
enable,
R5out
);
MUX_2_1 mux (
(in_data & ~red),
(R5out ^ (in_data & ~red)),
red,
out_data
);
84
Appendix A RTL code in Verilog for OFDM Transmitter
else if(!enable)
Reg3 <= 4'b0000;
end
end
endmodule
//*****************************************
//Convolutional Encoder module
//*****************************************
module convolution(
input clock,
input arst_n,
input in,
input enable,
output even,
output odd
);
85
Appendix A RTL code in Verilog for OFDM Transmitter
endmodule
//*****************************************
//Interleaver: Performs Interleaving within
//a block of 128 bits
//*****************************************
module Interleaver (
input clock,
input arst_n,
input [1:0] in,
input enable,
output [1:0] out
);
wire sig;
wire out1A, out2A, out1B, out2B;
wire [1:0] out1;
wire [1:0] out2;
wire [5:0] rd_address;
86
Appendix A RTL code in Verilog for OFDM Transmitter
sync_dpram_64x1_rrwrou RAM1A (
clock,
reg_in1,
rd_address,
Counter1,
!en1 & !SYNC,
out1A
);
sync_dpram_64x1_rrwrou RAM2A (
clock,
reg_in1,
rd_address,
Counter2,
en1 & !SYNC,
out2A
);
sync_dpram_64x1_rrwrou RAM1B (
clock,
reg_in1,
rd_address,
Counter1,
!en1 & SYNC,
out1B
);
sync_dpram_64x1_rrwrou RAM2B (
clock,
reg_in1,
rd_address,
Counter2,
en1 & SYNC,
out2B
);
ROM_64_6 ROM (
add_counter,
clock,
rd_address
);
87
Appendix A RTL code in Verilog for OFDM Transmitter
88
Appendix A RTL code in Verilog for OFDM Transmitter
endmodule
//******************************************
//Constellation Mapper - Maps bits onto QPSK
//Symbols
//******************************************
module const_mapper (
input clock,
input arst_n,
input [1:0] in,
output [47:0] data_out
);
ROM_48_4 ROM (
in,
clock,
data_out
);
89
Appendix A RTL code in Verilog for OFDM Transmitter
endmodule
//************************************
//ifft
//************************************
module ifft (
input clock,
input arst_n,
input enable,
input [23:0] realinput,
input [23:0] imginput,
output [23:0] realoutput,
output [23:0] imgoutput
);
fft_processor fft (
clock,
arst_n,
enable,
swappedrealin,
swappedimgin,
out1[47:24],
out1[23:0]
);
//**************************************
//Instantiation of the dividers
//**************************************
divider_ifft divider1 (
clock,
7'd64,
temprealoutput,
realoutput,
rem1
);
divider_ifft divider2 (
clock,
7'd64,
tempimgoutput,
imgoutput,
rem2
);
90
Appendix A RTL code in Verilog for OFDM Transmitter
endmodule
//*****************************************
// Addition of cyclic prefic
//*****************************************
module cyclic_prefix (
input clock,
input arst_n,
input enable,
input [47:0] in,
output [47:0] out
);
ROM_64x6_cyclicprefix rdaddROM (
wraddcounter,
clock,
wradd
);
//Instantiation of RAMs
RAM_64x48 RAM1 (
~arst_n,
clock,
temp_in1,
1'b1,
rdadd,
wradd,
~sync,
out1
);
RAM_64x48 RAM2 (
~arst_n,
clock,
temp_in1,
1'b1,
rdadd,
wradd,
sync,
91
Appendix A RTL code in Verilog for OFDM Transmitter
out2
);
//Always blocks
92
Appendix A RTL code in Verilog for OFDM Transmitter
if(!arst_n)
enable1 <= 1'b0;
else
enable1 <= enable;
end
endmodule
//*************************************
// RS-232 RX module
//*************************************
module async_receiver (
input clk,
input arst_n,
input RxD,
output reg RxD_data_ready,
output reg [7:0] RxD_data,
output RxD_idle
);
93
Appendix A RTL code in Verilog for OFDM Transmitter
if(RxD_cnt_inv==2'b00)
RxD_bit_inv <= 1'b0;
else if(RxD_cnt_inv==2'b11)
RxD_bit_inv <= 1'b1;
end
end
94
Appendix A RTL code in Verilog for OFDM Transmitter
95
Appendix A RTL code in Verilog for OFDM Transmitter
end
endmodule
96
Appendix B
APPENDIX B
//********************************************
// OFDM Receiver module
//********************************************
module OFDM_receiver (
input clock,
input arst_n,
input enable,
input [47:0] in_data,
output out_data
);
//*******************************************
// Control Unit
//*******************************************
Receiver_control_unit control_unit (
clock,
arst_n,
enable,
controlword
);
//*******************************************
// Fast Fourier Trasnform
//*******************************************
fft_processor fft (
clock,
arst_n,
controlword[5],
in_data[47:24],
in_data[23:0],
fft_output[47:24],
fft_output[23:0]
);
//*******************************************
97
Appendix B
// Constellation De-Mapper
//*******************************************
const_demapper constellation_demapper (
clock,
arst_n,
fft_output,
demap_output
);
//*******************************************
// De-interleaver
//*******************************************
DeInterleaver interleaver (
clock,
arst_n,
demap_output,
controlword[4],
deinterleaver_output
);
//*******************************************
// Viterbi Decoder
//*******************************************
viterbi viterbidecoder (
.clk(clock),
.decbit(decbit),
.eras_sym(eras_sym),
.normalizations(normalizations),
.reset(~arst_n),
.rr(deinterleaver_output),
.sink_rdy(sink_rdy),
.sink_val(sink_val),
.source_rdy(source_rdy),
.source_val(source_val)
);
//******************************************
// Reed-Solomon Decoder
//******************************************
rsdec rsdecoder (
.bypass(1'b0),
.clk(clock),
.decfail(decfail),
.num_err_sym(num_err_sym),
.reset(~arst_n),
.rsin(rsin),
.rsout(rsout),
.sink_ena(rs_sink_ena),
.sink_eop(rs_sink_eop),
.sink_sop(rs_sink_sop),
.sink_val(rs_sink_val),
.source_ena(rs_source_ena),
.source_eop(rs_source_eop),
.source_sop(rs_source_sop),
.source_val(rs_source_val)
);
98
Appendix B
//*****************************************
// Descrambler
//*****************************************
Descrambler descrambler(
clock,
arst_n,
enable,
in,
out
);
endmodule
//********************************************
//Module - Descrambler
//********************************************
module Descrambler (
input clock,
input arst_n,
input enable,
input in,
output reg out
);
endmodule
99