DESIGN AND DEVELOPMENT OF FPGA BASED DIGITAL TTL

TRIGGER GENERATOR FOR IUAC-DLS

Ashish Sharma#, B.K. Sahu, IUAC, New Delhi, India

Abstract is based around Altera’s Cyclone V Hard SoC (System on

The high power RF system of IUAC-DLS comprising Chip) based FPGA (Field Programmable Gate Array)
of a 25 MW, S-band, 5 cell klystron, a solid state IGBT development board, which is expanded to use its SoC
switch based pulse modulator, WR284 waveguide capabilities in the form of HPS-FPGA bridge [5] to
assembly and a 2.6 cell RF gun is currently under enable remote control of the device. Following sections of
installation and commissioning stage. There is a the paper describes the design details and the performance
requirement of multiple trigger signals for generation of results. Remote control mechanism is also briefly
synchronized high power RF pulse output from the explained.
Klystron-Modulator to accelerate the electron beam inside
the RF cavity. The trigger signals are required to be in the
range from 0.1 to ~35 μs width with repetition frequency
in the range of 0.5 Hz till 50 Hz with a typical
requirement at 6.25 Hz which is the designated repetition
rate of IUAC-DLS at different delays. A system has been
developed using Altera’s Cyclone V Hard SoC (HPS)
based FPGA which is capable of driving load in the range
of 50 Ω to 1 MΩ at TTL levels. It is made with generic
approach to enhance the design for including more
channels in future expansions. At present, a 4-channel
design has been implemented. Synchronism to reference
input of Master Oscillator (MO) is also provided. Front
panel controls are used to individually control each
channel’s pulse delay and width. Least rise time of 18 ns Figure 1: Layout of DLS High Power RF System
with a jitter of < 24 ns on falling edge and < 500 ps on
rising edge is achieved. 50 ns pulse is achievable with an DESIGN
error of <30 ns. FPGA-HPS bridge is studied for remote
control of the device. Buffering of EXTernal Reference Signal
An EXT reference signal from 1 MHz to 50 MHz, 3.3
INTRODUCTION Vpp (max) is read into a General Purpose Input Output
High-Power RF source for IUAC-DLS consists of a (GPIO) pin of FPGA and is used as drive input (D) to a
Toshiba make Klystron and Scandinova make Pulse positive-edge triggered D-flip flop implemented in VHDL
Modulator [1-2]. In order to operate the high power inside the FPGA as shown in Fig. 2(a). A 50 MHz on
source in pulsed mode, 3 synchronized trigger signals for board crystal oscillator serves as the clock for triggering
the generation of pulsed RF as shown in Fig. 1. Trigger the flip-flop. The resultant Q output of D flip-flop is
signal T1 has to be Zero delay with ~ 9-10 μs width fed to further used as the main clock for whole program
RF Driver Amplifier, signal T2 is delayed by 3.1 μs and assembly.
exits till 32.5 μs fed to the Pulse Modulator, while the Equal Precision Frequency Counter
signal T3 is delayed by 6 μs and exists till 10 μs owing to
The main aim of frequency measurement in this Trigger
the 4 μs RF window as prescribed by IUAC-DLS RF
Generator is to ensure that any frequency in the range 1-
requirement [1,3]. The usage and setting of signals
50 MHz can be used as EXT reference. It helps in
necessitates that all the channels of Trigger Generator
derivation of minimum Time (for width and delay) and
should be able to have a minimum resolution of 0.1 μs or
minimum Frequency resolution which are adjustable
better with possibility to adjust their delay and width
using front panel shaft encoder knobs. For a 10 MHz
individually.
reference signal, a 0.1 μs time and 0.1 Hz frequency
All the Trigger signals need to be repeated at variable
resolution is achieved.
frequencies at various cycles of RF conditioning and
The equal precision frequency measurement is most
operation which range from 0.5 Hz till 50 Hz with a
accurate frequency counter technique [4] wherein a gate
typical requirement at 6.25 Hz which is the designated
pulse that is synchronized to the signal being measured,
repetition rate of DLS [3]. So, the repetition rate must be
and is exactly an integer multiple of the measured signal
at least adjustable by 0.25 Hz.
period is used. Within this synchronized gate pulse,
The 4-Channel TTL compatible Trigger Generator is
number of pulses of the system clock signal and the
designed and tested with high-power RF system. Design
___________________________________________
#
ashish.sharma@iuac.res.in
measured signal are counted simultaneously. Then the and system clock signal frequencies. In the above
frequency of the measured signal is derived as below. expressions, T and fs are known beforehand, while Nx and
N N (1) Ns are computed using VHDL program as shown in Fig.
T x  s
fx fs 2(a). As the gate time is an integer multiple of the
Or, Nx (2) measured signal period, this eliminates any period error of
fx  fs the measured signal, as the buffered signal is fed into
Ns
frequency counter module. Prior buffering of the
Where T is the synchronized gate pulse ON time, Nx
measured signal may still cause some phase error rather
and Ns are the number of pulses of measured signal and
than frequency error. The timing diagram of equal
system clock signal respectively; that are counted
precision measurement is shown in Fig. 2(b).
simultaneously with the T seconds of ON time of the
synchronized gate pulse. fx and fs are the measured signal
Frequency Counter
meas_clk sys_clk Standard Clock Signal, fs
sync_gate
ref_clk
Counter 1 t
ENA
sys_clk meas_clk Measured Signal, fx

t
freq_val
RESET Counter 2 pre_gate T Gate pulse sync with fs
ENA
t

Clock sync_gate Gate pulse sync with fx

Divider pre_gate
(1 Hz) t

Nx Counted pulses in fx

Ns Counted pulses in fs
Vcc = 3V3
R B0 t
Pulse Gen. CH 0

R Pulse Gen. CH 1
B1 Counter (b)
ENA
Counter Pulse Gen. CH 2
R B2 ENA =5V
Pulse Gen. RL = 1 MΩ
Counter CH 3 5V 5V
ENA
R B3 Counter
GND ENA 0V 0V
74128
1×4 width 0 Delay Generator
SE0 DeMux width 1 RL
BC337
Encoder width 2
Read 2.5 V
width 3 4-Channels 3.3 V
0V
WIDTH, DELAY, FREQUENCY RL = 50 Ω
1×4 0V
DeMux delay 1
SE1
(c) (d)
20 × 4 LCD

Encoder delay 2
Read ASCII Code Binary-to-BCD
delay 3
Converter Converter
SE2 Encoder Frequency
Read

(a) (e)

Figure 2: Complete Logic diagram of Trigger Generator (a), Equal Precision Frequency Measurement (b), 50Ω driver
circuit (c), Finished PCB design (d), Front Panel of 2U×19” box with LCD, buttons, encoders and BNC Output
connectors (e).
channel A always leads channel B in case of forward
De-Multiplexing and Interfacing of Encoders movement or clockwise movement thereby counting in
In order to accept user’s input setting for pulse positive direction whereas, upon anti-clockwise
frequency in Hz, pulse width in μs, and pulse delay in μs, movement channel B pulses lead channel A.
three knobs are provided on the front panel of the Trigger
Generator assembly as per Fig 2(e). These knobs are used Logic implementation of Delay, Width, Period
for all the channels in 1-to-4 de-multiplexed fashion. The Each event in time domain is counted with respect to
selection of width and delay for each channel is achieved the EXT reference signal. For an EXT reference signal of
by reading the state all the 4 push buttons mounted on the typically 10 MHz, in order to produce 10 Hz repetition
front panel. Mutual exclusion is maintained among rate, the counter needs to count 10 MHz/ 10 Hz i.e. 10 6
selection of any one of all the buttons at a particular pulses. It is simply implemented by a comparator and a
instant of time. A RESET button is also provided to zero counter.
all existing settings.
The knobs are mechanical shaft encoders fed with 5V Logic implementation of Pulse Generation
supply, which upon rotary movement of the shaft produce For every rising edge of the EXT Reference Signal, a
quadrature pulses in 2 channels which can then be easily tick is counted in the pulse logic implementation. A
counted inside the VHDL code. Since encoders with counter counts this event and checks it first with the delay
mechanical sensors require switch debouncing, a noise value set for the particular channel from the respective
filter is used to avoid false pulsing and decoding as shown knob. Once counter reaches the delay count value, the
in Fig. 2(a). The pulses received from the encoder in corresponding channel output is put logic ‘1’ or ‘High’
i.e. set to 3.3V. It remains as high until the counter value ps. Sub-microsecond time adjustments are easily possible
reaches the point of (delay + width) count from with error of around 30 ns due to fall time limitation from
beginning. After that channel output voltage is pulled to BC337.
logic ‘0’ or ‘Low’. The cycle is repeated after count
corresponding to Frequency is met.
50Ω - 1MΩ Driving circuit
As most of the devices offer 50 Ω termination or load
which leads to increased current requirements. This
current cannot be provided by the normal GPIO pins of
the FPGA which are rated for around 20 mA current
(a) (b)
source. In order to facilitate driving a 50 Ω termination,
an additional circuitry has been added. Here, a simple Figure 3: Outputs at 50Ω load. TB = 1μs, 2V/div (a), at 1
inverting amplifier circuit is built around BC337 (NPN MΩ load. TB = 2μs, 5V/div (b)
transistor) which can offer high collector current of the
order of 800 mA (DC), high bandwidth of ~ 210 MHz
followed by a TTL IC 74128 (Quad 2-Input NOR 50 Ω
line driver) as shown in Fig. 2 (c). Outputs are thus rated
as 5V/1MΩ and 2.5V/50Ω.
Complete Circuit Assembly and PCB
The design is based around Altera’s Cyclone V-SoC
FPGA board whose GPIO pins are read into main PCB
through two 40-pin FRC cables as shown in Fig. 2(d). All (a) (b)
the buttons, shaft encoder knobs and LCD are controlled
by GPIO pins of FPGA and mounted on the front panel of Figure 4: Rise Time (a), Fall-time Jitter (b) measurements
a 2U×19” rack-mountable box as shown in Fig. 2(e). 3.3V
EXT reference signal and the 4-channel pulse output CONCLUSION
signals are also read into and taken from GPIO pins. The This Trigger Generator with achieved time related
4-channel output signals drive the base of four BC337 parameters like rise time, jitter etc. are found tolerable for
transistors which are wired up in common emitter present requirement and is tested during conditioning
configuration and resulting into inverse pulse voltage process of RF system. In future it is planned to be used in
output. Each of the inverse output of transistor circuit is the operation of high power RF system of DLS with
next fed to inputs of quad 2-input NOR gate IC 74128 variable pulse delay, width and rep. rate. Remote control
which acts as 50 Ω line driver. of device will be helpful during that phase.
Remote Control
32-bit Lightweight HPS-FPGA bridge is used for ACKNOWLEDGEMENTS
Cyclone V HPS to communicate with FPGA via Avalon Authors would like to thank Dr. K. Singh for
AXI bus [5]. A Qsys model of system is developed where suggesting the technique for this development and Dr. S.
all the delay, width and frequency parameters are Ghosh for providing opportunity to work on the project.
modelled as PIOs/32 bit registers and memory mapped to Support from Prof. A.C. Pandey, Director, IUAC is also
variables in VHDL code running under FPGA fabric. A well appreciated.
Remote ON/OFF button state is used to switch between
local and remote control. All the variables are written REFERENCES
using a C program stored in the ARM Cortex 9 HPS and
[1] B.K. Sahu et al., Proceedings of InPAC 2019.
used to communicate between HPS and FPGA.
[2] A.Sharma et al., Technical Report, IUAC/TR/AS/
Ref-22/2018-19.
RESULTS AND DISCUSSIONS [3] S.Ghosh et al., NIM-B, 402(2017)358-36356.
The system has been tested with High Power RF [4] Y.Y. Fang et al., SciRes, 4(2012), 696-700.
system in the configuration shown in Fig. 1 and its [5] Cyclone V HPS Technical Reference Manual, http
performance was found to be satisfactory. All trigger s://www.intel.com/content/dam/www/programmable/
requirements were 50Ω, TTL. Figures below shows the us/en/pdfs/literature/hb/cyclone-v/cv_54005.pdf
actual outputs of trigger generator captured on a 200 MHz
DSO, with 10 MHz EXT reference. Outputs with 50Ω
load are cleaner in comparison to 1MΩ where ringing can
be seen. Rise time of 18 ns is achieved while falling edge
jitter is found to be ~24 ns and rising edge jitter is ~500