B.

Tech Internship/Major Project Document Preperation Rules

1. Page selection Portrait A4 page
2. Margins left 1.3 inch, right ,top and bottom 1 inch
3. Header: “Project Title” must be top Right of the Page , times new roman, italic , 0.5 inches
From top edge of the page.
4. Footer: “Dept. of ECE, UCET, MGU, Nalgonda.” must be bottom Left of the Page , times
new roman, italic , 0.5 inches From bottom edge of the page.
5. Total Document Must be Justified Alignment, All the fonts must be in times new roman only
6. Chapter title bold , times new roman,font size 16, must be Capitalize Each Word, center align
Example: 1. Introduction
7. Sub Chapter bold , times new roman,font size 14, must be Capitalize Each Word
Example: 1.1. Sub Chapter Name
8. Sub Sub Chapter bold , times new roman, font size 12, must be Capitalize Each Word
Example: 1.1.1. Sub Sub Chapter Name
9. Each paragraph is must start with one Tab Space , Justified Alignment, Line Spacing 1.5
between The lines
10. No Spacing Between One Paragraph to other paragraph
11. Do not kept unwanted gaps between paragraphs and any part of the documents also.
12. Figure : Must be center align , Figure name bottom of the figure , Bold , Italic, Font Size 12
and continue the chapter number
Example: Fig. 1.1. Write Figure Name Here
Example: Fig. 2.5. Write Figure Name Here
13. Tables : Must be center align , Table name bottom of the figure , Bold , Italic, Font Size 12
and continue the chapter number
Example: Table 1.1. Write Table Name Here
Example: Table 2.5. Write Table Name Here
14. In the Chapter 1. Introduction kept the following sub chapters
1.1. Motivation
1.2. Problem Statement
1.3. Contributions
1.4. Thesis Organization
For details see annexure I
15. In Chapter 2 Literature Survey See Annexure II
16. Every chapter is must end with “summery”(write what you understand after reading this
chapter in your own words)
17. For contents, Front Pages See Annexure III
18. For Title Page , Certificates See Annexure IV
19. Start page sequence (Title page, Certificate, Acknowledgment, Declaraton, Abstract,
contents, List of Figures, List of tables, Abbreviations) next chapters,
20. Page numbers bottom of the page, for starting pages give roman numbers in lower case
 Annexure I
1. Introduction
Moore’s law, which states that the “number of transistors that can be place inexpensively
on an integrated circuit will double approximately every two years,” has often been subject to the
following criticism: while it boldly states the blessing of technology scaling, it fails to expose its
bane. A direct consequence of Moore’s law is that the “power density of the integrated circuit
increases exponentially with every technology generation”. History is witness to the fact that this
was not a benign outcome. This implicit trend has arguably brought about some of the most
important changes in electronic and computer designs. Since the 1970s, most popular electronics
manufacturing technologies used bipolar and NMOS transistors. However, bipolar and NMOS
transistors consume energy even in a stable combinatorial state, and consequently, by 1980s, the
power density of bipolar designs was considered too high to be sustainable. IBM and Cray
started developing liquid, and nitrogen cooling solutions for high-performance computing
systems.
The 1990s saw an inevitable switch to a slower, but lower-power CMOS technology.
CMOS transistors consume lower power largely because, to a first order of approximation,
power is dissipated only when they switch states, and not when the state is steady. Now, in the
late 2000s, we are witnessing a paradigm shift in computing: the shift to multi-core computing.
The power density has once again increased so much that there is little option but to keep the
hardware simple, and transfer complexity to higher layers of the system design abstraction,
including software layers.
The need for low power design is motivated by several factors, such as the emergence of
portable systems, thermal considerations, reliability issues, and, finally, environmental concerns.
The demand for portable computers is increasing every year and is projected to increase in the
future [1].
Moreover, large current levels on metal interconnections lead to electro migration,which
may cause electrical shorts between lines [3]. Along with electro migration, there are many
reliability and signal integrity issues in integrated circuits due to excessive power consumption.
Furthermore, of the total power consumed by office equipment, about 80% is consumed by
computing equipment and mostly when that equipment is not in use [1].Efficient low power
design techniques are required to avoid these problems. Reducing a circuit’s average power
consumption typically improves the circuit’s reliability. This leads to a reduction in cooling
requirements, which in turn reduces the packaging and cooling costs. Thus, effective low power
design methods are of supreme importance.
1.1 Motivation
Power and delay optimization in VLSI circuit design can be performed at several level of
abstraction namely high-level and architectural level synthesis, logic level synthesis, and
physical level. The optimization can be done on each level subject to the degree of actual
realization of the circuit at that level [3].
Conventional very large scale integrated circuit (VLSI) systems rely on System on a Chip
(SoC) to achieve higher performance and receive more diversified architectures. As the chip
function becomes more diversified and complex, and clock frequency and total number of
transistors decrease gradually, total leakage power becomes more severe. Design of low power
circuits, therefore, becomes very important to reduce power consumption of the chip becomes a
big issue and research focus at present. Because the SoC clock circuit and storage circuit are the
main cause of power loss, design of a lower power storage element becomes a critical factor to
reduce total power consumption of SoC.
Flip-Flop (FF) is an important and widely used storage element, especially on mobile
devises such as notebook computers, personal digital assistants (PDAs) and cell phones. Hence,
design of flip-flop plays a big role to meet such a requirement for providing a higher
performance at a lower power. In SoC applications clock system (including clock distribution
networks and storage elements) consumes power about 20% to 45% of total system. In the clock
system the number of transistors and power consumption mostly are taken by the flip-flops. Thus
reducing the power consumption of the flip-flop can greatly improve total power performance.
In the conventional design of PTFF the generated pulse is maintained at the same width
and intensity. However, the flip-flop used on high order system circuits does not maintain a
constant triggered operation, but always in a standby state. Since the pulse clock of PTFF is
maintained at the same width and intensity, extra power loss incurs. While PTFF can improve
some drawbacks of the conventional flip-flop as previously discussed, at present there are no
design and research reports that have announced regard changing circuit pulse width and
intensity according to input data of flip-flop.
 At present on research of the flip-flop, pulse-triggered flip-flop (PTFF) has been
successfully used on many high performance and/or low power processors. For instance, on
Intel's Pentium processor chips more than 90% of the flip-flop adopts PTFF architecture. Besides
improving system performance, it also reduces power consumption and can resolve incurred
cooling and chip packaging issues.

1.2 Problem Statement

Power consumption and timing delays are the two important design parameters in high
speed VLSI systems. In many digital very large scale integration (VLSI) designs, the clock
system that includes clock distribution network and flip-flops. Flip flop is one of the most power
consumption components. It accounts for 30% to 60% of the total system power, where 90% of
which is consumed by the flip-flops and the last branches of the clock distribution network that is
driving the flip-flop [13], as clock frequency increases, the latency of the flip-flop or latch will
play an even greater role in the overall cycle time. A Flip-Flop that synchronizes the state
changes during a clock pulse transition is the edge-triggered flip-flop. When the clock pulse
input exceeds a specific threshold level, the inputs are locked out and the flip-flop is not affected
by further changes in the inputs until the clock pulse returns to 0 and another pulse occurs. As
the clock frequency increase, pulse-triggered flip-flop tends to be popular as compared to
conventional master-slave flip-flops. Because they employ time borrowing across cycle
boundaries which results in zero or negative setup time. Moreover, the number of transistors we
used in the pulse-triggered flip-flop is less than the number we used in the conventional master-
slave flip-flops, so the simple structure of the pulse-triggered flip-flop leads to a better power
efficiency.
In recent years, there has been an increasing demand for high-speed digital circuits at low
power consumption. Because the clock frequency is determined by system specifications, the
clock signal is constantly active, it makes timing components (latches and flip-flops) the most
power consuming components in the VLSI system.
Pulse triggered flip flops are two types implicit and explicit type. Implicit type pulse
triggered flip flops have in-built Latch and pulse generator. There is no need of external pulse
generation, but in explicit pulse triggered flip flops has separate latch and pulse generation logic.
Implicit pulse generation is often considered to be more power efficient than explicit pulse
generation. This is because the former merely controls the discharging path while the latter needs
to physically generate a pulse train. Implicit-type designs, however, face a lengthened
discharging path in latch design. The transistors of pulse generation logic are often enlarged to
assure that the generated pulses are sufficiently wide to trigger the data capturing of the latch.
Explicit-type P-FF designs face a similar pulse width control issue, but the problem is further
complicated in the presence of a large capacitive load, e.g., when one pulse generator is shared
among several latches.
1.3 Contributions
In this report, present two low power pulse triggered flip flops,(i)Design of Low power
pulse triggered flip flop using self-driven pass transistor logic (ii) Design of Low Power Pulsed
Flip Flop Using Sleep Transistor Scheme.The main contributions of this report are as follows:
(i) Low power pulse triggered flip-flop using self-driven pass transistor logic:
A low power implicit type pulse triggered flip-flop using self-driven pass transistor logic
is presented. The pulse generation logic comprising of two transistor AND gate is used in the
critical path of the design for improved speed and reduced complexity. The pass transistor logic
driven by generated clock pulse is used directly to drive the output of the flip-flop. The
Transistors of the pulse generation logic benefit from significant size reductions and the overall
layout area is even slightly reduced. This gives improved power and power–delay–product
performances against other PTFF designs. As a result, transistor sizes in delay inverter and pulse-
generation circuit can be reduced for power saving.
(ii) Design of Low Power Pulse Triggered Flip Flop Using Sleep Transistor Scheme:
The low power pulse triggered flip flop design using sleep transistor scheme has two
logics they are leakage feedback scheme and leakage feed forward scheme. The proposed
leakage feedback scheme (LFB-PTFF) consists of two PMOS transistors MP1 and MP2 in pull-
up network and two NMOS transistors MN1 and MN2 in the pull-down network. The “sleep”
control signal is given to the input of MP1 and its complement is given to the input of MN1. The
complemented output of the flip-flop is fed back to the inputs of MP2 and MN2. Transistors
MP1 and MN1 are sleep transistors and MP2 and MN2 are helper sleep transistors. During sleep
mode, both the sleep transistors are turned ‘off’, and any one of the two helper sleep transistors
are turned ‘on’. This makes the output Q to be driven to any of the appropriate virtual rail
(virtual Vdd or virtual gnd).
1.4 Thesis Organization
This thesis is focused on the applicability of pulse triggered flip-flops in low power and
low voltage applications. Chapter 2 describes the literature review of the pulse triggered flip
flops. Chapter 3 first describes the power consumption in CMOS logic circuits and power
reducing techniques in CMOS circuits, and also gives the description about conventional pulse
triggered flip flop designs which is having two types implicit and explicit type pulse triggered
flip flops. Chapter 4describes a brief introduction on pass transistor logic for both N type
MOSFET and P type MOSFET and then this provides the complete analysis of two proposed
PTFF designs they are, Low Power Pulse Triggered Flip Flop with Self-Driven Pass Transistor
Logic and Design of Low Power Pulse Triggered Flip Flop Design Using Sleep Transistor
Scheme. Chapter 5 summarizes the simulation results of various pulse triggered flip flop designs.
Finally, conclusions are discussed in chapter 6.

Annexure II
 2. Literature Survey
Flip-Flops are extremely important circuit elements in all synchronous VLSI circuits.
They are not only responsible for the correct timing, functionality and performance of the chip,
but the clock distribution networks consume a significant portion of the total power of the circuit.
It is estimated that the power consumption of the clock system, which consists of clock
distribution networks and storage elements, is as high as 20%–45% of the total system power
[13]. Comparing to different elements in the VLSI circuits, flip-flops are the primary source of
the power consumption in synchronous system. Moreover, flip-flops have a large impact on
circuit speed. The performance of the Flip-Flop is an important element to determine the
performance of the whole circuit. For example, the Clock-to-Q delay, Setup time and Hold time,
all these parameters of the flip-flops can affect the performance of the whole circuit. Therefore,
the studies on Flip-Flop become more and more in recent years.
Circuits become slower when the supply voltage is low and the threshold voltage is high.
Power dissipation becomes greater when the supply voltage is high and the threshold voltage is
low. So there is compromise between circuit speed and power dissipation. Lowering the supply
voltage and the threshold voltage enables high speed and low power operation.
Pulse-triggered flip flops (PTFF) have been considered a popular alternative to the conventional
master–slave-based FF in the applications of high-speed operations [14]–[17]. Besides the speed
advantage, its circuit simplicity is also beneficial to lowering the power consumption of the clock
tree system. A PTFF consists of a pulse generator for generating strobe signals and a latch for
data storage. Since triggering pulses generated on the transition edges of the clock signal are very
narrow in pulse width, the latch acts like an edge-triggered FF. The circuit complexity of a PTFF
is simplified since only one latch, as opposed to two used in conventional master–slave
configuration, is needed. P-FFs also allow time borrowing across clock cycle boundaries and
feature a zero or even negative setup time. PTFFs are thus less sensitive to clock jitter. Despite
these advantages, pulse generation circuitry requires delicate pulse width control in the face of
process variation and the configuration of pulse clock distribution network [16].Pulse triggered
flip flops are classified into two categories, implicittype pulse triggered flip flops, explicit type
pulse triggered flip flops.
 J.Tschanzet.al[18], proposed an implicit type pulsed data closed to output (ip-DCO) flip
flop consisting of an implicit type pulse generator based on AND logic and a semi-dynamic
structured latch design. Two practical problems arise in this design. First, during the positive
edge of the clock, nMOS transistors N2 and N3 are turned on. If data remains high, internal node
X will be discharged on every positive edge of the clock. This leads to a large switching power.
The other problem is that node X controls two large MOS transistors (P2 and N5). The large
capacitive load at node X causes speed and power performance degradation.

J.Tschanzet al.[18], proposed an explicit type pulsed data closed to output (ep-DCO)
PTFF which is considered as one of the fastest flip-flops in its semi-dynamic structure. But it
consumes significant amount of power due to its charging and discharging of internal node X for
every clock cycle. This produces glitches in the output which leads to increase in switching
power consumption and system malfunctioning due to noise problems.

S.H.Rasoulietal.[23], proposed an improved PTFF design, named modified hybrid latch

flip-flop (MHLFF), by employing a static-structured latch. This design eliminates the
discharging problem at internal node X. However, it encounters a longer D-to-Q delay during ‘0’
to ‘1’ transition because internal node X is not pre-discharged. To enhance the discharging
capability, larger NMOS transistors are required. Another disadvantage of this design is that
node X becomes floating when output Q and data D both equal to ‘1’.

Mahmoodiet al.[24],proposed sense amplifier energy recovery flip flop dynamic flip-flop
with precharge and evaluate phases of operation. In [5], this flip-flop is used to operate with a
low-voltage-swing clock. We use this flip-flop to operate with an energy recovery clock. When
the clock voltage exceeds the threshold voltage of the clock transistor (MN1), evaluation occurs.
At the onset of evaluation, the difference between the differential data inputs (D and DB) results
in an initial small voltage difference between SET and RESET nodes.

Mahmoodietal. [24], proposed differential conditional-capturing energy recovery

(DCCER) flip-flop. Similar to a dynamic flip-flop, the DCCER flip-flop operates in a precharge
and evaluates fashion. However, instead of using the clock for precharging, small pull-up pMOS
transistors (MP1 and MP2) are used for charging the precharge nodes (SET and RESET). The
DCCER flip-flop uses a NAND-based set/reset latch for the storage mechanism.
 Mahmoodiet al.[24], also proposed a single-ended conditional capturing energy recovery
(SCCER) flip-flop. SCCER is a single-ended version of the DCCER flip-flop. The transistor
MN3, controlled by the output QB, provides conditional capturing. The right-hand side
evaluation path is static and does not require conditional capturing. Placing MN3 above MN4 in
the stack reduces the charge sharing.

Yin-Tsung Hwang et al. [34] proposed a low power pulse triggered flip flop with
conditional pulse enhancement scheme. This flip flop has two logics the pulse generation control
logic, an AND function, is removed from the critical path to facilitate a faster discharge
operation. A simple two-transistor AND gate design is used to reduce the circuit complexity.
Second, a conditional pulse-enhancement technique is devised to speed up the discharge along
the critical path only when needed.

Peiyi Zhaoet al. [21]proposed a clock-gating in the conditional capture technique result in
redundant power consumed by the gate controlling the delivery of the delayed clock to the flip-
flop. As a result, conditional precharge technique outperformed the conditional capture technique
in reducing the flip-flop EDP [16]. But the conditional precharge technique has been applied
only to ip-FF, and it is difficult to use a double-edge triggering mechanism for these flip-flops, as
it will require a lot of transistors. A new technique, conditional discharge technique, is proposed
in this paper for both implicit and explicit pulse-triggered flip-flops without the problems
associated with the conditional capture technique.

Peiyi Zhaoet al.[21]alsoproposed a conditional discharge flip-flop (CDFF),the flip-flop is

made up of two stages. Stage one is responsible for capturing the LOW-to-HIGH transition. If
the input D is HIGH in the sampling window, the internal node X is discharged, assuming (Q,
Qb) that were initially (LOW, HIGH) for the dischargepath to be enabled. As a result, the output
node will be charged to HIGH through P2 in the second stage. Stage 2 captures the HIGH-to-
LOW input transition. If the input D was LOW during the sampling period, then the first stage is
disabled, and node X retains its precharge state. Whereas, node Y will be HIGH, and the
discharge path in the second stage will be enabled in the sampling period, allowing the output
node to discharge and to correctly capture the input data.
 Chen Kong Tehetal. [22]proposed conditional data mapping flip-flops (CDMFFs), which
reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant
internal transitions. We present two CDMFFs, having differential and single-ended structures,
respectively, and compare them to the state-of-the-art flip-flops. The results indicate that both
CDMFFs have the best power-delay product in their groups, respectively.

Peiyi Zhao, Jason McNeely etal. [25] proposed a clocked-pair-shared flip-flop, in the
clocked-pair-shared flip-flop; clocked pair (N3, N4) is shared by first and second stage. An
always on pMOS, P1, is used to charge the internal node X rather than using the two clocked
precharging transistors (P1, P2) in CDMFF. Comparing with CDMFF, a total of three clocked
transistors are reduced, such that the clock load seen by the clock driver is decreased, resulting in
an efficient design. Further the transistor N7 in the clocked inverter in CDMFF is removed.
CPSFF uses four clocked transistors rather than seven clocked transistors in CDMFF, resulting in
approximately 40% reduction in number of clocked transistors.

Ying-Haw Shuetal.[26] proposed an XNOR-based double-edge-triggered flip-flop (DET-

FF), XNOR-based approaches is difficult to reach the speed demand due to the delay of the
XNOR-based clock generator. This paper proposes a new designed DET-FF based on an
alternative XNOR gate. By utilizing the sensitivity to the driving capacity of the previous stage,
we use this simplified XNOR gate as a pulse-generator. A modified transparent latch following
the pulse-generator acts as an XNOR-based DET-FF.

Hiroshi Kawaguchi etal. [13]proposed a reduced clock swing flip flop, which is
composed of a reduced swing clock driver and a special flip-flop which embodies the leak
current cutoff mechanism. The RCSFF is composed of a true single-phase master-latch and a
cross-coupled NAND slave-latch. The master-latch is a current-latch-type sense-amplifier. The
salient feature of the RCSFF is that it can accept a reduced voltage swing due to the single-phase
nature of the flip-flop.

Annexure III
 Acknowledgement
The satisfaction that accompanies the successful completion of the task would be put
incomplete without the mention of the people who made it possible, whose constant guidance
and encouragement crown all the efforts with success.
We wish to express our deep sense of gratitude to GUIDE NAME Assistant Professor &
Project Guide, Department of Electronics & Communication Engineering, University College of
Engineering and Technology, for his able guidance and useful suggestions, which helped us in
completing the project work, in time.
We would like to thank NAME, Project coordinator, Department of Electronics &
Communication Engineering, University College of Engineering and Technology, for his expert
guidance and encouragement at various levels of my Project.
We are particularly thankful to NAME, Head of Department of Electronics and
Communication Engineering for his guidance, intense support and encouragement, which helped
us to mould our project into a successful one.
We would like to thank Principal NAME for her expert guidance and encouragement at
various levels of our Project.
We show our gratitude to our honorable Registrar Prof. M. Yadagiri, for having
provided all the facilities and support.
We avail this opportunity to express our deep sense of gratitude to our honorable Vice.
Chancellor Prof. Khaja Althaf Hussain, congenial atmosphere to complete this project
successfully.
We also thank all the staff members of Electronics and Communication Engineering
department for their valuable support and generous advice. Finally thanks to all our friends and
family members for their continuous support and enthusiastic help.

Student name (Roll No)

Student name (Roll No)
 Declaration

We hereby declare that this major project report titled “Project Title” is a genuine
project work carried out by us in B. Tech (Electronics and Communication Engineering)
degree course of Mahatma Gandhi University, Nalgonda and has not been submitted to any
other course or university for the award of degree.

Signature of the students

Student name
Student name
 Abstract
Flip-flops are critical timing elements in digital circuits which have a large impact on
circuit speed and power consumption. The performance of the flip-flop is important to determine
the performance of the whole synchronous circuit. In recent years, there has been an increasing
demand for high-speed digital circuits at low power consumption. Pulse-triggered flip-flops
employ time borrowing across cycle boundaries which results in zero or negative setup time.
Pulse generator provides a narrow pulse width to the latching stage during which the flip-flop is
in the transparent mode. By reducing this pulse width, the setup time and hold time of the flip-
flop are reduced.The pulse generation logic comprising of two transistor AND gate is used in the
critical path of the design for improved speed and reduced complexity. In this project, two pulse
triggered flip flops are proposed, namely pulse triggered flip-flop with sleep transistor scheme
and pulse triggered flip-flop with self-driven pass transistor logic. Firstly, thepass transistor is
self-driven by generated clock pulse is used directly to drive the output of the flip-flop. This pass
transistor provides extra driving to node Q during 0-1 data transition and discharging node Q
during 1-0 data transitions. Next, the sleep transistor scheme has two pairs of sleep transistors to
operate the flip flop in sleep mode and active mode. This sleep transistor scheme reduces the
leakage power of flip flop.As compared to the conventional pulse triggered flip-flop, the
proposed designs features best speed, power and power-delay-product performance. The
proposed techniques are implemented using HSPICE CMOS 90nm technology. The average
power consumption of self-driven pass transistor logic is reduced by 12.75% and that of the sleep
transistor scheme can be reduced by 7.18% as compared with conventional IP-DCO. Also, the
sleep transistor scheme reduces the average leakage power by 25.22% as compared with
conditional pulse enhancement scheme (CPE-PTFF). The result of the simulation demonstrates
that the proposed pulse triggered flip flop has the improved design performance.
 Contents

Chapter Name Page. No

Acknowledgement i
Declaration ii
Abstract iii
Table of Contents iv
List of Figures v
List of Tables vi
Abbreviations vii
1. Introduction 1
1.1. Motivation 2
1.2. Problem Statement 3
1.3. Contributions 4
1.4. Thesis Organization 5
2. Literature Survey 6
3. Conventional Pulse Triggered Flip Flop Designs 10
3.1. Dynamic Switching Power Consumption 10
3.2. Leakage Power Consumption 13
3.2.1. Sub Threshold Leakage Current 13
3.2.2. Short-Channel Effects 14
3.2.3. Drain-Induced Barrier Lowering 15
3.2.4. Body Effect 15
3.2.5. Temperature Effect 16
3.2.6. Characterization of Sub Threshold Leakage Current 16
3.3. Short-Circuit Power Consumption 17
3.4. Static DC Power Consumption 18
3.5. Power Reduction Techniques 19
3.5.1. Techniques for Reducing Dynamic Power 20
3.5.2. Gate Sizing 21
3.5.3. Voltage and Frequency Scaling 22
 3.5.4. Design Time Voltage and Frequency Setting 23
3.5.5. Static Voltage and Frequency Scaling 23
3.5.6. Dynamic Voltage and Frequency Scaling 24
3.5.7. Voltage Scaling and Reduced Voltage Swing 24
3.6. Techniques for Reducing Short Circuit Power 25
3.7. Techniques for Reducing Leakage Power 25
3.7.1. Multiple Supply Voltage 25
3.7.2. Multiple Threshold Voltage 26
3.7.3. Transistor Stacking 28
3.7.4. Power Gating 29
3.8. Basic Latch Designs 31
3.9. Conventional Pulse Triggered Flip Flop Designs 33
3.9.1. Implicit Type Pulsed Data Closed to Output Flip Flop 34
3.9.2. Modified Hybrid Latch Flip Flop 35
3.9.3. Energy Recovery Clocked Flip-Flops 36
3.9.4. Low Power Pulse Triggered Flip-Flop with Conditional Pulse
Enhancement Scheme 40
3.9.5. Explicit Type Pulsed Data Closed to Output Flip Flop 43
4. Proposed Pulse Triggered Flip-Flop Designs 45
4.1. Pass Transistor Logic for MOSFETs 45
4.1.1. N-FET Pass Transistor Logic 45
4.1.2. P-FET Pass Transistor Logic 49
4.2. Proposed PTFF Design with Self Driven Pass Transistor Logic 52
4.3. Design of Low Power Pulsed Flip Flop Using Sleep Transistor Scheme 54
4.3.1. Leakage Feedback Scheme (LFB-PTFF) 54
4.3.2. Leakage Feed forward Scheme (LFF-PTFF) 55
5. Results and Discussions 57
6. Conclusions and Future Scope 66
References 67
List of Papers Published Based on the Thesis 70
CURRICULUM VITAE 71
 List of Figures

Figure Title Page. No

3.1 CMOS Circuit with Standard Power Supply and Ground Voltages 11
3.2 The Depletion Regions of a Short-Channel NMOS Transistor 15
3.3 The Short-Circuit Current Produced by Two Cascaded Inverters 18
3.4 Static DC Current Due To the Direct Interfacing 19
3.5 Leakage Increases Exponentially with Temperature 20
3.6 Fundamental Techniques to Reduce Dynamic Power 21
3.7 The Slack in the Circuit. (A) Multiple Supply-Voltage Pipeline Stage
(B) Level Converter Latch 26
3.8 Multiple Threshold Voltage 𝑉𝑡 without the Overhead of Level Converters 27
3.9 The Transistors in a Low-Leakage State 28
3.10 (a) ActiveMode in “On” State (b) Idle Mode in “Off” State 30
3.11 NOR-Based SR Latch Operation 31
3.12 SR Latch Using NOR Gates 32
3.13 Simplified Circuit for SR Latch 32
3.14 D-Latch Logic Diagram 32
3.15 CMOS D-Latch 33
3.16 Implicit Type Pulsed Data Closed to Output Flip Flop (IP-DCO) 35
3.17 Modified Hybrid Latch Flip Flop (MHLLF) 35
3.18 SAER Flip-Flop 37
3.19 SDER Flip-Flop 37
3.20 DCCERFlip-Flop 38
3.21 SCCER Flip-Flop 39
3.22 Pulse Triggered Flip Flop with Conditional Pulse Enhancement Scheme 41
3.23 Explicit Type Pulsed Data Closed To Output Flip-Flop (EP-DCO) 44
4.1 Basic NFET Pass Transistor 45
4.2 (A) Logic 1 Input (B) Logic 0 Input 46
4.3 Pulse Transmission through an NFET 48
4.4 Output Capacitance Contributions 48
4.5 PFET Pass Transistor 49
4.6 (A) Logic 0 And (B) Logic 1 Inputs 50
4.7 Pulse Response of a PFET 52
4.8 Low Power PTFF with Self-Driven Pass Transistor Logic 53
4.9 NOR Based Reset Circuit 53
4.10 4-Bit Ring Counter 54
4.11 PTFF Using Sleep Transistor Based Leakage Feedback Scheme 55
4.12 PTFF Using Sleep Transistor Based Leakage Feed Forward Scheme 55
5.1 Simulation Test Bench Mode 57
5.2 Simulation Wave Form of IP-DCO 58
5.3 Simulation Wave Form of MHLFF 58
5.4 Simulation Wave Form of SCCER 59
5.5 Simulation Wave Form of PTFF with Conditional Pulse Enhancement 59
5.6 Simulation Wave Form of Proposed PTFF with Self Driven Logic 60
5.7 Simulation Wave Form of Proposed Leakage Feedback Scheme 60
5.8 Comparison of Delay, Average Power and PDP for Self-Driven Logic 62
5.9 Comparison of Data Switching Activities for Self-Driven Logic 62
5.10 Comparison of Delay, Average Power and PDP For
Sleep Transistor Scheme 64
5.11 Comparison of Data Switching Activities for Sleep Transistor Scheme 64
 List of Tables

Table Title Page. No

4.1 Truth Table of Proposed PTFF with Sleep Transistor Scheme 56

5.1 Performance Metrics Comparisons of Various PTFF Designs 61
5.2 Switching Activity vs. Average Power of Conventional FF With
Self-Driven Logic 61
5.3 Performance Metrics Comparisons of Various PTFF with
Sleep Transistor Scheme 63
5.4 Switching Activity vs. Average Power of Conventional PTFF with
Sleep Transistor Scheme 63
5.5 Leakage Power Comparison of various PTFF in standby mode (nW) 64
 Abbreviations

CMOS Complementary Metal Oxide Semi-Conductor Transistor

MOSFET Metal Oxide Semi-Conductor Field Effect Transistor
NiMH Nickel-Metal Hydride
Ni-Cd Nickel-Cadmium
VLSI Very Large Scale Integrated Circuit
SOC System on a Chip
PTFF Pulse Triggered Flip Flop
IP-DCO Implicit Type Pulsed Data Closed To Output Flip Flop
MHLFF Modified Hybrid Latch Flip Flop
𝑃𝐷𝐶 Static DC PowerConsumption
SCE Short-Channel Effects
DIBL Drain-Induced Barrier Lowering
VDD Supply Voltage
BTBT Band To Band Tunneling
CL Load Capacitance
VTH Threshold Voltage
SR-LATCH Set Reset Latch
FPTG Four-Phase Transmission-Gate Flip-Flop
TGFF Transmission-Gate Flip-Flop
SAER Sense Amplifier Energy Recovery Flip Flop
SDER Semi Dynamic Energy Recovery Flip Flop
DCCER Dynamic Conditional Capture Energy Recovery Flip Flop

Annexure IV
Type Your Project Title Here Same Font and Colours No
Changes Just Type Name Roll No. Etc……

A Internship/Major project Report Submitted to

Mahatma Gandhi University, Nalgonda

In partial fulfillment of the requirements

for the award of the degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING

By

NAME
(ROLL NO)

Under the guidance of

GUIDE NAME
Designation
Department of Electronics and Communication Engineering

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

UNIVERSITY COLLEGE OF ENGINEERING & TECHNOLOGY
Nalgonda - 508001

2018
 UNIVERSITY COLLEGE OF ENGINEERING & TECHNOLOGY

Nalgonda – 508001, Telangana

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE

Certified that this is a bonafide record of the Internship work entitled, "Project
Title", done by Student Name (Roll No), Student Name (Roll No), Student Name
(Roll No), Student Name (Roll No), Submitted to the faculty of Electronics and
Communication Engineering, in partial fulfillment of the requirements for the Degree
of Bachelor of Technology in Electronics and Communication Engineering from
Mahatma Gandhi University, Nalgonda during the year 2017-2018.

Project Guide: Head of the Department:

Guide Name Guide Name
Assistant Professor(c), Assistant Professor(c),
Dept. of Electronics and Communication Dept. of Electronics and Communication
Engineering,
University College of Engineering and Engineering,
Technology , Nalgonda
University College of Engineering and
Technology , Nalgonda
Viva-Voce held on……………………………………………
SIGNATURE OF THE EXTERNAL EXAMINER
1.
2.