EXPERIMENT-2

AIM: Design and simulation of half and full subtractor using various modelling.

TOOLS USED: Xilinx ISE 14.7

1)HALF SUBTRATORss
METHODOLOGY: A half subtractor is a circuit which subtract two bit binary and gives
the result for the difference and borrow. Whenever first bit is low and second bit is high borrow
generated ,difference high is generated when bits are in alternative form.

Fig 1.1 half sub using XOR and AND gates.

TRUTH TABLE:
Inputs Outputs

a b diff bor

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Table1.1 : truth table for half subtractor

APPLICATIONS:
a) It is mainly used in ALU for two bit binary subtraction .

VERILOGCODE:
1)Gate level modelling
module hs(
input a,
input b,
output diff,
output bor
);

xor fordiff(diff,a,b);
and forbor(bor,~a,b);
endmodule
b) data flow level modelling
module hs(
input a,
input b,
output diff,
output bor
);
assign diff=a^b;
assign bor=~a&b;
endmodule
c) behavioral modelling
module hs(
input a,
 input b,
output reg diff,
output reg bor
);
always@(a or b)
begin
case({a,b})
2'b00:begin diff=0; bor=0;end
2'b01:begin diff=1; bor=1;end
2'b10:begin diff=1; bor=0;end
2'b11:begin diff=0; bor=0;end
endcase
end
endmodule

TEST BENCH CODE:

`timescale 1ps / 1ps
module test_hs;

// Inputs
reg a;
reg b;

// Outputs
wire diff;
wire bor;

// Instantiate the Unit Under Test (UUT)

hs uut (
 .a(a),
.b(b),
.diff(diff),
.bor(bor)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

#5 a = 0;
b = 1;
#5 a = 1;
b = 0;
#5 a = 1;
b = 1;

end
endmodule
RTL SCHEMATICS:
1.RTL schematics using gate and data flow modelling.

Fig1.2 block schematics using gate and data level modelling

Fig1.3 RTL schematics showing inner component.

2.RTL schematics using behavioral modelling

Fig1.4 RTL schematics using behavioral modelling

OUTPUT WAVEFORM:

Fig1.5 output waveform of half subtractor for different input combinations

B)FULL SUBTRACTOR:
METHODOLOGY: A full adder circuit is two bit binary subtractor with the borrow of
previous subtraction , difference is obtained by XOR of all the inputs. Design is shown how the
circuit can constructed using XOR, AND and OR gates.

Fig1.6 full subtrator using XOR and AND gates.

TRUTH TABLE:
Inputs Output
a b c diff bor
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 1
1 1 1 1 1

Table1.2 truth table of full subtractor.

APPLICATIONS: a) it is used in the alu of microprocessors and computers .
VERILOG CODE:
a)gate level modelling
module fs(
input a,
input b,
input c,
output diff,
output bor
);
wire t1,t2,t3;
xor a1(t1,a,b);
xor a2(diff,t1,c);
and b1(t2,~a,b);
and b2(t3,~t1,c);
or forborrow(bor,t2,t3);

endmodule
b)data flow level modelling
module fs(
input a,
input b,
input c, //c is input borrow
output diff,
output bor
);
wire t1,t2,t3;
assign t1=a^b;
assign diff=t1^c;
assign t2=~a&b;
assign t3=~t1&c;
assign bor=t2|t3;
endmodule */
c)behavioral level modelling
module fs(
input a,
input b,
input c, //c is input borrow
output reg diff,
output reg bor
);

always@(a or b or c)
begin
case({a,b,c})
3'b000:begin diff=0; bor=0; end
3'b001:begin diff=1; bor=1; end
3'b010:begin diff=1; bor=1; end
3'b011:begin diff=0; bor=1; end
3'b100:begin diff=1; bor=0; end
3'b101:begin diff=0; bor=0; end
3'b110:begin diff=0; bor=0; end
3'b111:begin diff=1; bor=1; end
endcase
end
 endmodule

TESTBENCH CODE:
`timescale 1ps / 1ps
module fs_test;

// Inputs
reg a;
reg b;
reg c;

// Outputs
wire diff;
wire bor;

// Instantiate the Unit Under Test (UUT)

fs uut (
.a(a),
.b(b),
.c(c),
.diff(diff),
.bor(bor)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
 // Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#5 a = 0;
b = 0;
c = 1;
#5 a = 0;
b = 1;
c = 0;
#5 a = 0;
b = 1;
c = 1;
#5 a = 1;
b = 0;
c = 0;
#5 a = 1;
b = 0;
c = 1;
#5 a = 1;
b = 1;
c = 0;
#5 a = 1;
b = 1;
c = 1;
end
endmodule
RTL SCHEMATICS:
1)RTL schematics using gate and data flow level modelling.

Fig1.7block representation of RTL schematics gate and data flow level.

2)RTL schematics showing inner component of full adder

Fig1.8 RTL schematics showing inner component of full adder

3)RTL schematics of behavioral modelling

Fig1.9 RTL schematics of behavioral modelling

OUTPUT WAVEFORM:

Fig1.10 output waveform of full subtractor for different combination of inputs

RESULT:
In this experiment half and full subtractor were implemented using various modelling technique.
The simulation were observed using Xilinxs 14.7 and found to correct and in accordance with
design.
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