library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity "Letrero is"

Port (CLOCK 50MHZ : in STD_LOGIC;
COL : out STD_LOGIC_VECTOR (4 downto 0);
FIL : out STD_LOGIC_VECTOR (6 downto 0));
end Letrero

architecture Behavioral of Letrero is

signal Xclk : STD_LOGIC;
signal Xclk_letras : STD_LOGIC;
signal Xq : STD_LOGIC_VECTOR (2 downto 0);
signal Xq : STD_LOGIC_VECTOR (4 downto 0);
signal XSL : STD_LOGIC_VECTOR (5 downto 0);

component Divisor
Port ( CLK 50Mhz : in STD_LOGIC;
CLK1khz : out STD_LOGIC);
end component;

component Cont
Port ( Clk : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (2 downto 0);
end component;

component anillo
Port ( Entrada : in STD_LOGIC_VECTOR (2 downto 0);
salida : out STD_LOGIC_VECTOR (4 downto 0));
end component;

component Memoria
Port ( Selector_Letra: in STD_LOGIC_VECTOR (5 downto 0);
Direccion : in STD_LOGIC_VECTOR (4 downto 0);
Datos : out STD_LOGIC_VECTOR (2 downto 0));
end component;

component Cont_Letras
Port ( CLK_Letras in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (5 downto 0));
end component;

component Reloj_letras
Port ( CLK50Hmz : in STD_LOGIC;
CLL1hz : out STD_LOGIC);
end component;

begin
step1: Divisor port map (CLOCK50MHZ, Xclk);
step2: Cont port map (Xclk, Xq);
step3: anillo port map (Xq, Xcol);
step4: Memoria port map (XSL, Xcol, FIL);
step5: Reloj_letras port map (CLOCK50MHZ, Xclk_Letras);
step6: Cont_Letras port map (Xclk_letras, XSL);

COL <= Xcol;

end Behavioral;

entity anillo is
Port ( Entrada : in STD_LOGIC_VECTOR (2 downto 0);
Salida : out STD_LOGIC_VECTOR (4 downto 0);
end anillo;

architecture Behavioral of anillo is

begin
process(Entrada)
begin

case ENTRADA is
when "000" => Salida <= "01111";
when "001" => Salida <= "10111";
when "010" => Salida <= "11011";
when "011" => Salida <= "11101";
when "100" => Salida <= "11110";
when others => Salida <= "00000";
end case;

end process;
end Behavioral;

architecture Behavioral of Memoria is

signal s0, s1, s2, s3, s4, s5: STD_LOGIC_VECTOR (6 downto 0);
begin
process (Selector_Letra,Direccion)
begin
if Selector_letra = "00000" then

s0 <= "0000000";
s1 <= "1111111";
s2 <= "0001000";
s3 <= "0010100";
s4 <= "0100010";
s5 <= "1000001";

case Direction is -- Letra H

when "11110" => Datos <= s1;
when "11101" => Datos <= s0;
when "11011" => Datos <= s0;
when "10111" => Datos <= s0;
when "01111" => Datos <= s0;
when others => Datos <= "0000000";
end case;

elsif Selector_letra = "00100" then

s0 <= "0000000";
s1 <= "1111111";
s2 <= "0001000";
s3 <= "0010100";
s4 <= "0100010";
s5 <= "1000001";

case Direccion is -- Letra H

when "11110" => Datos <= s5;
 when "11101" => Datos <= s4;
when "11011" => Datos <= s3;
when "10111" => Datos <= s2;
when "01111" => Datos <= s1;
when others => Datos <= "0000000";
end case;

NET "CLOCK50MHZ" LOC = "B8";

NET "COL(0)" LOC = "A3"; //1

NET "COL(1)" LOC = "B9"; //2
NET "COL(2)" LOC = "B8"; //3
NET "COL(3)" LOC = "C6"; //4
NET "COL(4)" LOC = "A10"; //5

NET "FIL(0)" LOC = "B6"; //A

NET "FIL(1)" LOC = "B2"; //B
NET "FIL(2)" LOC = "C13"; //C
NET "FIL(3)" LOC = "A13"; //D
NET "FIL(4)" LOC = "C12"; //E
NET "FIL(5)" LOC = "C9"; //F
NET "FIL(6)" LOC = "A9"; //G