DEPpart 2

R.
Lauwereins Imec 2001
Course contents
Digital design Combinatorial circuits: without status Sequential circuits: with status FSMD design: hardwired processors Language based HW design: VHDL
Digital design Combinatorial circuits Sequential circuits FSMD design
VHDL
2/1
R.Lauwereins Imec 2001
Design of Combinatorial Circuits

Minimization of Boolean functions Technology mapping Correct timing behavior Basic RTL building blocks (Adder, ALU, MUX, )
VHDL
2/2

Minimization of Boolean functions
Karnaugh map Minimization with the Karnaugh map Dont care conditions Quine-McCluskey
VHDL
Technology mapping Correct timing behavior Basic RTL building blocks (Adder, ALU, MUX, )
2/3

VHDL
2/4
Karnaugh map
Motivation:
Assume: F=xyz+xyz Cost = Delay
(fan-in)complete circuit = (2)+(3)+(3)+(2) = 10
Assume: relative gate delay NAND or NOR or NOT = 0.6 + fan-in * 0.4
VHDL
Delay = (gate-delay)critical path = 1 + (1.8+1) + (1.4+1) = 6.2

x y z
F=xyz+xyz
2/5
Karnaugh map
Motivation:
F=xyz+xyz =xy(z+z) =xy The value of z hence does not matter Cost = Delay
(fan-in)complete circuit = (1+2) = 3 i.o. 10
VHDL
Assume: relative gate delay NAND or NOR or NOT = 0.6 + fan-in * 0.4 Delay = (gate-delay)critical path = 1 + (1.4+1) = 3.4 i.o. 6.2
x y z F
2/6
Karnaugh map
Minimization via manipulation of Boolean expressions is clumsy: no method exists to select the theorems such that we are sure to obtain the minimum cost Is it possible to see in the truth table which input value does not matter?
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F 0 0 0 0 1 1 0 0 xyz xyz -
VHDL
We indeed see easily that the value of F equals 1 for x=1 and y=0 irrespective of the value of z We however see this easily only for z, since only for z the lines z=0 and z=1 for equal x and y are consecutive
2/7
Karnaugh map
A Karnaugh map contains the same information as a truth table (each square is a minterm), but neighboring squares differ only in the value of 1 variable!!
x 0 x 1 x z x yz y 00 01 11 10 x y 0 xy xy 1 xy xy 0 1
VHDL
xy (z does not matter) xz (y does not matter) xz (y does not matter)
0 xyz xyz xyz xyz

x
2/8
1 xyz xyz
xyz
xyz
Karnaugh map
x 0 1 x y 0 1 0 1
m0
m1
m0
m2
m1
m3
z x yz 0 x 1
VHDL
y
00 01 11 10
0
4
1
5
3
7
2
6
2/9
Karnaugh map
Fill out from truth table w xy zw z 00 0 1 4 0 12 0 8 1 01 1 0 5 1 13 1 9 0 11 3 0 7 1 15 1 11 0 10 2 0 6 0 14 0 10 1
x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 y 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 z 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
w 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 F F 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1
00
01 y 11
VHDL
x
10
2/10
Karnaugh map
Minimize F=xyzw+xyzw+xyzw+xyzw+xyzw+xyzw+xyzw
w xy
zw
z
00 01 11 10
00
1
0 0 1
0
1 1 0
0
1 1 0
0
0 0 1 F= yw +xyw +yzw
VHDL
01
y 11 x 10
2/11
Karnaugh map
Implement F=xyzw+xyzw+xyzw+xyzw+xyzw+xyzw+xyzw x y z w Cost = = Delay = = 4*(1) + 7*(4) + 1*(7) 39 1 + (2.2+1) + (3.4+1) 8.6
VHDL
2/12
Karnaugh map
Implement F=yw+xyw+yzw x y z w
VHDL
Cost
= = Delay = =
3*(1) + {1*(2)+2*(3)} + 1*(3) 14 i.p.v. 39 1 + (1.8+1) + (1.8+1) 6.6 i.p.v. 8.6
2/13
Karnaugh map
v w zw xy 00 y 01 z 00 01 11 0 4 1 5 3 7 10 2 6 14 10 10 18 22 30 26 z xy 19 17 16 00 23 21 20 01 31 29 28 11 27 25 24 10 y 11 01 00 w
VHDL
11
12 13 15 8 9 11
10
F(v,x,y,z,w) Differs from course book

2/14
Karnaugh map
Differs from course book w zw xy 00 z 00 01 11 0 4 1 5 3 7 10 2 6 10 18 22 z xy 19 17 16 00 23 21 20 01 x y 11 01 00 v w
01
y x 11 10
12 13 15 14
8 9 11 10
30 31 29 28 11
26 27 25 24 10
VHDL
F=(u,v,x,y,z,w) x 10 11 01 40 41 43 44 45 47 36 37 39 42 46 38 58 62 54 59 57 56 10 63 61 60 11 55 53 52 01 x
2/15
00
32 33 35 34
50 51 49 48 00

VHDL
2/16
Minimization with the Karnaugh map

Truth table or canonical form Create the Karnaugh map
Determine all prime implicants
VHDL
Determine all essential prime implicants
Search for minimal coverage

2/17

F=xyz+wz+xyz+wy F=xyz+ F=xyz+wz+ F=xyz+wz+xyz+wy wz+xyz+wy xyz+wy z Step 1: Create Karnaugh map
y
1 x w 1 1 1 1 1 1 1 1 1
VHDL
Rule: - Take product term per product term and indicate where in the Karnaugh map it equals 1
2/18

Step 2: Determine all prime implicants z wxz xyz wy yz wz wxy
y
1 x w 1 1 1 1 1 1 1 1 1
VHDL
Rule: - Analyze each 1-minterm - Determine the largest sub-cube(s) that contain(s) the minterm and add them to the list of prime implicants (without adding an already listed sub-cube)
2/19

Step 3: Determine all essential prime implicants z wxz xyz wy yz wz wxy
y
1 x w 1 1 1 1 1 1 1 1 1
VHDL
Rule: - Search for 1-minterms that are only contained in 1 prime implicant - Indicate this prime implicant as
2/20
essential

Step 4: Search minimal coverage z y 1 x w 1 1 1 1 1 1 1 1 1 wxz xyz wy yz wz wxy 1 2 0 1
Fmin=xyz+wy+wz
VHDL
Rule: - Goal: search for the smallest set of (as big as possible) prime implicants that contain all 1-minterms - Take all essential prime implicants as initial list - Repeatedly add a prime implicant to the list that contains the largest number of not yet covered 1-minterms. When there are two that contain the same number of not yet covered 1-minterms, make a random choice.
2/21
Such a strategy is known as Greedy strategy: at each decision point, take the best choice without looking to future implications - This does not always lead to a global optimum

Original: F=xyz+wy+xyz+wz
wxyz
Minimal Fmin=xyz+wy+wz
wxyz
VHDL
Cost=4*1+2*3+2*2+1*4=18 Delay
2/22
Cost Delay
=(1)+(.6+3*.4+1) +(.6+4*.4+1)=7
=4*1+1*3+2*2+1*3=14 =22% cheaper =(1)+(.6+3*.4+1) +(.6+3*.4+1)=6.6 =6% faster

Example 2: F(v,w,x,y,z)
v 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1
v 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 w 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1
VHDL
2/23

Realisation as sum of 1-minterms: F=(6,7,10,11,14,15,21,23,25,27,29,31)
v w x y z
VHDL
Cost=(5*1)+(12*(5+1))+(1*(12+1))=90 Delay=(.6+1*.4)+(.6+5*.4+1)+(.6+12*.4+1)=11
2/24

Minimisation Step 1: Create Karnaugh map
z y v z
0
x w 0 0 0
0
0 0 0
0
1 1 1
0
1 1 1
0
0 0 0
0
1 1 1
0
1 1 1
0
0 0 0
VHDL
2/25

Minimisation Step 2: determine all prime implicants
z y v z
0
x w 0 0 0
0
0 0 0
0
1 1 1
0
1 1 1
0
0 0 0
0
1 1 1
0
1 1 1
0
0 0 0
VHDL
2/26

Minimisation Step 3: Determine all essential prime implicants
z y v z
0
x w 0 0 0
0
0 0 0
0
1 1 1
0
1 1 1
0
0 0 0
0
1 1 1
0
1 1 1
0
0 0 0
VHDL
Is already the minimum coverage F1min2=vxy+vwy+vxz+vwz

2/27

Realisation of F1min2=vxy+vwy+vxz+vwz
v w x y z
VHDL
Cost=1+(4*(3+1))+(1*(4+1))=22 (76% cheaper) Delay=(.6+1*.4)+(.6+3*.4+1)+(.6+4*.4+1)=7 (34% faster)
2/28

Realisation in more than two layers F =vxy+vwy+vxz+vwz =vy(x+w)+vz(x+w) =(x+w)(vy+vz)
v w x y z Cost =(1*1)+(5*(2+1))=16 (82% cheaper) Delay =(.6+1*.4)+(.6+2*.4+1) +(.6+2*.4+1)+(.6+2*.4+1) =8.2 (25% faster)
VHDL
2/29

Dual minimisation Step 1: Create the Karnaugh map
z y v z
0
x w 0 0 0
0
0 0 0
0
1 1 1
0
1 1 1
0
0 0 0
0
1 1 1
0
1 1 1
0
0 0 0
VHDL
2/30

Dual minimisation Step 2: Determine all prime implicants
z y v z
0
x w 0 0 0
0
0 0 0
0
1 1 1
0
1 1 1
0
0 0 0
0
1 1 1
0
1 1 1
0
0 0 0
VHDL
2/31

Dual minimisation Step 3: Determine all essential prime implicants
z y v z
0
x w 0 0 0
0
0 0 0
0
1 1 1
0
1 1 1
0
0 0 0
0
1 1 1
0
1 1 1
0
0 0 0
VHDL
2/32
Is already the minimum coverage F0min2=(v+y)(w+x)(v+z)

Realisation of F0min2=(v+y)(w+x)(v+z)
v w x y z
VHDL
Cost=(1*1)+(3*(2+1))+(1*(3+1))=14 (84% cheaper) Delay=(.6+1*.4)+(.6+2*.4+1)+(.6+3*.4+1)=6.2 (44% faster)
2/33

Summary
Realisation Sum of 1-minterms Minimal AND-OR 3-layers Minimal OR-AND Cost 90 22 16 14 Rel. cost 100% 24% 18% 16% Delay 11 7 8.2 6.2 Rel. delay 100% 64% 75% 56%
Area/time trade-off Well see that, depending on the technology mapping, we will eventually obtain for an ASIC realisation: OR-AND-INV Cost = 11 (Rel. cost=12%) Delay = 4 (Rel. delay=36%) NOR Cost = 10 (Rel. cost=11%) Delay = 4.2 (Rel. delay=38%)
VHDL
2/34

VHDL
2/35
Dont care conditions

Incompletely specified Boolean function
x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 w 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a 1 0 1 1 0 1 1 1 1 1 x x x x x x b 1 1 1 1 1 0 0 1 1 1 x x x x x x c 1 1 0 1 1 1 1 1 1 1 x x x x x x d 1 0 1 1 0 1 1 0 1 1 x x x x x x e 1 0 1 0 0 0 1 0 1 0 x x x x x x f 1 0 0 0 1 1 1 0 1 1 x x x x x x g 0 0 1 1 1 1 1 0 1 1 x x x x x x
BCD7-segment a f e d g b c
VHDL
2/36

Step 1: Create Karnaugh maps
w a z
1 0 1 1 0 1 1 1
w b z
1 1 1 1 1 0 1 0 x x x x 1 1 x x
w c z
1 1 1 0 1 1 1 1 x x x x 1 1 x x
w d z
1 0 1 1 0 1 0 1 x x x x 1 1 x x
x x x x 1 1 x x
e
1 0 0 1
f
1 0 0 0 1 1 0 1
g
0 0 1 1 1 1 0 1
VHDL
y x
0 0 0 1
x x x x
1 0 x x
x x x x
1 1 x x
x x x x
1 1 x x
2/37

Step 2: determine all prime implicants
w a z
1 0 1 1 0 1 1 1
w b z
1 1 1 1 1 0 1 0 x x x x 1 1 x x
w c z
1 1 1 0 1 1 1 1 x x x x 1 1 x x
w d z
1 0 1 1 0 1 0 1 x x x x 1 1 x x
x x x x 1 1 x x
e
1 0 0 1
f
1 0 0 0 1 1 0 1
g
0 0 1 1 1 1 0 1
VHDL
y x
0 0 0 1
x x x x
1 0 x x
x x x x
1 1 x x
x x x x
1 1 x x
2/38

Step 3: Determine all essential prime implicants
w a z
1 0 1 1 0 1 1 1
w b z
1 1 1 1 1 0 1 0
w c z
1 1 1 0 1 1 1 1
w d z
1 0 1 1 0 1 0 1
x x x x
1 1 x x Complete coverage
x x x x
x x x x
x x x x
VHDL
e
1 0 0 1
f
1 0 0 0
1 1 0 1 x x x x 1 1 x x Complete coverage
g
0 0 1 1
1 1 0 1 x x x x 1 1 x x Incomplete coverage
y x
0 0 0 1 x x x x 1 0 x x Complete coverage
2/39

Step 4: Determine minimum coverage
g
0 0 1 1 1 1 0 1 x x x x 1 1 x x
VHDL
Selection of the cube that realises the remaining minterm: - Select all cubes that realise the minterm and are already essential for another function; in this case, both are already essential - Select that cube that appears in the smallest number of other functions to keep the fan-out as low as possible
2/40

Note down the standard form
w a z
1 0 1 1 0 1 1 1
yw z yw x
x x x x
1 1 x x
VHDL
a=yw+z+yw+x
2/41

w b z
1 1 1 1 1 0 1 0
x x x x
1 1 x x
yw z yw x y zw zw
VHDL
a=yw+z+yw+x b=y+zw+zw
2/42

w c z
1 1 1 0 1 1 1 1
x x x x
1 1 x x
VHDL
yw z yw x y zw zw z w y
a=yw+z+yw+x b=y+zw+zw c=z+w+y
2/43

w d z
1 0 1 1 0 1 0 1
x x x x
1 1 x x
VHDL
a=yw+z+yw+x b=y+zw+zw c=z+w+y d=yw+yz+yzw+zw+x
yw z yw x y zw zw z w y yz yzw zw
2/44

yw z yw x y zw zw z w y yz yzw zw
e
1 0 0 1
y x
0 0 0 1
x x x x
1 0 x x
VHDL
a=yw+z+yw+x b=y+zw+zw c=z+w+y d=yw+yz+yzw+zw+x e=yw+zw

2/45

yw z yw x y zw zw z w y yz yzw zw yz yw
f
1 0 0 0 1 1 0 1
x x x x
1 1 x x
VHDL
a=yw+z+yw+x b=y+zw+zw c=z+w+y d=yw+yz+yzw+zw+x e=yw+zw f=zw+yz+yw+x

2/46

yw z yw x y zw zw z w y yz yzw zw yz yw
g
0 0 1 1 1 1 0 1
x x x x
1 1 x x
VHDL
2/47
a=yw+z+yw+x b=y+zw+zw c=z+w+y d=yw+yz+yzw+zw+x e=yw+zw f=zw+yz+yw+x g=yz+yz+yw+x

xyzw
VHDL
a
2/48

Cost when realising as (1-minterms):
a: 4*1+8*(4+1)+1*(8+1)=53 b: 4*1+8*(4+1)+1*(8+1)=53 c: 4*1+9*(4+1)+1*(9+1)=59 d: 4*1+7*(4+1)+1*(7+1)=47 e: 4*1+4*(4+1)+1*(4+1)=29 f: 4*1+6*(4+1)+1*(6+1)=41 g: 4*1+7*(4+1)+1*(7+1)=47
329 (100%)
VHDL
Cost for minimal 2-layer-implementation

Invertors: 4*1=4 AND-gates: 8*(2+1)+1*(3+1)=28 OR-gates: 1*(2+1)+2*(3+1)+3*(4+1) +1*(5+1)=32
64 (19%)
2/49

Delay when realising as (1-minterms):
Critical path=c (9-input OR) c: (1)+(.6+4*.4+1)+(.6+9*.4+1)=9.4 (100%)
Delay for minimal 2-layer-implementation

Critical path=d (3-input AND & 5-input OR) d: (1)+(.6+3*.4+1)+(.6+5*.4+1)=7.4 (79%)
VHDL
2/50

VHDL
2/51
Quine-McCluskey
Method with Karnaugh map
OK for human minimisation : visually oriented no guarantee for optimum solution
Computer method
Quine-McCluskey table oriented leads to optimum solution is the basis of all CAD circuit design tools hardly doable by hand
VHDL
2/52

Minimization of Boolean functions Technology mapping
Gate arrays: NAND, NOR Custom library: AOI, OAI, PLA FPGA
VHDL
Correct timing behavior Basic RTL building blocks (Adder, ALU, MUX, )
2/53

VHDL
2/54
Technology Mapping: Gate Arrays

Properties of the methodology followed:
When minimizing 1-minterms: INV-AND-OR When minimizing 0-maxterms: INV-OR-AND Any function can be realized in two layers of logic with this methodology The fan-in of the gates can become arbitrary large
Properties of gate arrays:

They only contain m-input NAND or m-input NOR gates
VHDL
Technology mapping is:

Translating a circuit consisting of INV-AND-OR to one with only m-input NAND Dual: INV-OR-AND m-input NOR
2/55

Design flow:
Decomposition Replace each n-input AND (OR) by a few m-input ANDs (ORs), with m<n Replace each AND and OR by NAND or NOR
Conversion
VHDL
Optimisation
Eliminate double inversions
Retiming
Try to make all input-output delays equal
2/56

Conversion rules (based on the laws of De Morgan):
(xy) = (x + y)
(x+y) = (xy)
VHDL
Optimisation rule:
(x) = x
2/57

Conversion rules in practice:
VHDL
The realisation with only NAND or only NOR is faster: we save an invertor per gate!
2/58

Realisation of an invertor:
VHDL
2/59

Decomposition:
VHDL
2/60

Retiming (delay optimisation): try to make the delay from each input to the output equal Example:
AND-OR implementation obtained from Karnaugh minimisation
VHDL
2/61

Example (first possible decomposition in 3-input NAND):
VHDL
Delay = (.6+3x.4)+(1)+(.6+3x.4)+ (.6+3x.4)+(1)+(.6+3x.4) = 9.2

2/62

Example (second possible decomposition in 3-input NAND):
VHDL
Delay = (.6+3x.4)+(1)+(.6+3x.4)+ (.6+3x.4) = 6.4 (70%)

2/63

VHDL
2/64
Technology Mapping: Custom Library

ASICs have AOI en OAI: small and fast! For small functions (not in course book): Realise the inverse function with AND-OR or OR-AND Example: realise again following function: F=(6,7,10,11,14,15,21,23,25,27,29,31)
Realisation as sum of 1-minterms: cost = 90; delay = 11 Minimal realisation as OR-AND: cost = 14 (16%); delay = 6.2 (56%)
VHDL
2/65

F=(6,7,10,11,14,15,21,23,25,27,29,31)
v z
F= (0,1,2,3,4,5,8,9,12,13,16,17,18,19,20, 22,24,26,28,30)
z
F y v w x y z
1 x
w 1 1 1
1
1 1 1
1
0 0 0
1
0 0 0
1
1 1 1
1
0 0 0
1
0 0 0
1
1 1 1
VHDL
F F Cost=(5*1)+6=11 (12%) Delay=1+(.6+6*.4)=4 (36%)

F
2/66

For large functions:
Realise as AND-OR or OR-AND
Transform to NAND or NOR
Determine critical path Replace repeatedly 2 layers of gates on critical path by AOI/OAI Replace repeatedly 2 layers of gates off critical path by AOI/OAI
VHDL
2/67

F=wz+z(w+y)
Replace 2 gates on critical path by AOI Transform Determine Replace Analyze Realise with the 2 gates to the other AND NAND critical on and path critical and OR path NOR path by AOI (2e possibility)
y w z
VHDL
Cost=11 Cost=10 Cost=9 Cost=14 Cost=? (64%) (79%) (71%) Delay=? (53%) Delay=5.2 Delay=5.6 Delay=3.8 Delay=7.2 (72%) (78%)
2/68

VHDL
2/69
Technology Mapping: PLA

PLA is an AND-plane with large fan-in followed by an OR-plane with large fan-in Technology mapping: realisation as ANDOR, without the necessity for decomposition
VHDL
2/70

VHDL
2/71
Technology Mapping: FPGA

CLB is 2 functions of 4 variables or 1 function of 5 variables Technology mapping is similar as for custom design but i.o. AOI/OAI we search for sub-circuits of 4 or 5 variables, first on the critical path, next on the other paths For FPGAs technology mapping is done by automatic tools (see next slide); when prototype: no hand optimalisation, when final product: hand optimalisation beneficial. Also for ASICs automatic tools exist, hand optimalisation is beneficial BCD7-segment: create 7 truth tables i.f.o. 4 variables: the rest is done by the tools
VHDL
2/72
Technology mapping: FPGA
VHDL
Technology mapping
2/73

Minimization of Boolean functions Technology mapping Correct timing behavior Basic RTL building blocks (Adder, ALU, MUX, )
VHDL
2/74
Correct timing behavior: Hazard-free design

z y 1 x 1 1 0 x y z y a b F Static 1-hazard 1 1 2 x y z 3 4 5 y a F b 6
VHDL
2/75

The hazard condition causes an unwanted glitch!
Static 1-hazard: the output had to stay 1 but became briefly 0

Cause: different delay in two paths
Solution: see next slide
VHDL
2/76

z y 1 x 1 1 0 x y z y a 1 1 2 x y z 3 4 5 y b c 6 a F
VHDL
b
c
2/77

Dynamic hazard: the output had to switch (eg. from 1 to 0) but switched several times (bvb. 1 0 1 0) Cause: different delay in multiple paths Example: see next slide
VHDL
2/78

x x x a F
0 x x x a F
VHDL
Statically equivalent to: x

2/79

Hazards are hard to detect by hand: importance of simulation
The danger for hazards increases when rise times and fall times are not equal
Are hazards a problem?
For synchronous circuits, they are not
Unless they control the clock of a memory element For asynchronous circuits, they always are a problem This is why asynchronous design is heavily demotivated for FPGAs (the delay of the different paths is only known after APRAutomatic Placement and Routing)
VHDL
2/80

Minimization of Boolean functions Technology mapping Correct timing behavior Basic RTL building blocks
Ripple-carry adders Carry-look-ahead adders Adder/subtractors Multipliers Logic units Arithmetic-logic units Decoders Selectors Buses Priority encoders Magnitude comparators Shifters and rotators
VHDL
2/81

VHDL
2/82
Ripple-carry adders
Half adder
xi 0 0 1 1 yi 0 1 0 1 ci+1 0 0 0 1 si 0 1 1 0
ci+1 0
yi 0 1
si 0
yi 1 0
xi
xi
VHDL
xi
yi
ci+1
xi
yi
HA
ci+1
2/83
si
si
1 CLB
Ripple-carry adders
Full adder
xi 0 0 0 0 1 1 1 1 yi 0 0 1 1 0 0 1 1 ci 0 1 0 1 0 1 0 1 ci+1 0 0 0 1 0 1 1 1 si 0 1 1 0 1 0 0 1
yi ci+1 1 ci 1 1 1 ci 1 xi si
yi xi 1 1 1
VHDL
xi yi ci
1 CLB
2/84
ci+1
si
Ripple-carry adders
Full adder: alternative implementation
xi 0 0 0 0 1 1 1 1 yi 0 0 1 1 0 0 1 1 ci 0 1 0 1 0 1 0 1 ci+1 0 0 0 1 0 1 1 1 si 0 1 1 0 1 0 0 1
yi ci+1 1 ci xi yi ci 1 1 1 ci 1 xi si
yi xi 1 1 1
VHDL
1 gate less, larger delay from xi&yi to ci+1, same delay from ci to ci+1 xi yi ci+1 FA si ci ci+1 si
2/85
Ripple-carry adders
4-bit ripple-carry adder
x3 c4 FA s3 y3 c3 x2 FA s2 y2 c2 x1 FA s1 y1 c1 x0 FA s0 y0 c0=0
VHDL
Critical path: x0 or y0 to c4: 1 XOR + 4 AND + 4 OR
In principal 1 CLB per bit Because of special circuitry (dedicated carry chain): 1 CLB per 2 bits
2/86

VHDL
2/87
Carry-look-ahead adders
Ripple-carry adder is slow because the critical path x0 to cn+1 is long Speed-up is possible by computing for example c4 directly (in principle in 2 layers of logic) from c0, x0x3 en y0y3. Hence the name Carry-look-ahead How is this done? See exercises and course book
xii+3 yii+3
VHDL
ci+4
4-bit CLA
ci
2/88
sii+3

VHDL
2/89
Adder-subtractors
X Y S
S 0 1 Function X+Y X-Y=X+Y*=X+Y+1 Note Addition Subtraction
Cout
Adder/ subtractor F
x3 S
y3
x2
y2
x1
y1
x0
y0
VHDL
c4
FA
c3
FA
c2
FA
c1
FA
c0
f3
overflow
f2
f1
f0
2/90
Only for 2-complement!!!

VHDL
2/91
Multipliers
A 1-bit by 1-bit multiplier: C=BA
b0
b0 0 0 1 1 a0 0 1 0 1 c0=a0.b0 0 0 0 1
a0
a0b0
VHDL
A 1-bit by 1-bit multiplier is hence an AND gate

a0 b0
c0
2/92
Multipliers
A 2-bit by 2-bit multiplier: C=BA
a0 a1 b0 b1 b1
b1
a1 a0b1 a1b1 c3 c2 a1b0 c1
b0
a0 a0b0 c0
b0
VHDL
HA c3 c2
HA c1 c0
Each of these terms is a 1-bit by 1-bit multiplier: AND

2/93
Multipliers
A 4-bit by 3-bit multiplier: cost=O(n2)
a0 a1 b0 0 b3 b3 b2 b1 b2 b1 b0
4-bit adder cout s3 a2 b3 b2 b1
s2
s1
s0
VHDL
b0
cout c6
4-bit adder s3 s2 c5 c4
s1 c3
s0 c2 c1 c0
2/94

VHDL
2/95
Logic units
Goal: implement a unit that can realise all 16 Boolean functions of 2 bits The unit has two inputs X and Y and 4 select bits S3S2S1S0 that select the wanted function The coding of the select bits is identical to the function number in the table of possible Boolean functions
VHDL
2/96
Logic units
1-minterms m3 m2 m2+m3 m1 m1+m3 m1+m2 m1+m2+m3 m0 m0+m3 m0+m2 m0+m2+m3 m0+m1 m0+m1+m3 m0+m1+m2 m0+m1+m2+m3 Function value for x,y 00 01 10 11 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Expression F0=0 F1=xy F2=xy F3=x F4=xy F5=y F6=xy+xy F7=x+y F8=(x+y) F9=xy+xy F10=y F11=x+y F12=x F13=x+y F14=(xy) F15=1
VHDL
2/97
Logic units
xi yi
S0 S1 S2 S3
xi
yi
S0..3
LU
VHDL
fi fi
2/98

VHDL
2/99
Arithmetic-logic units
Goal: build a unit that realises 4 arithmetic operations (addition, subtraction, increment and decrement) and 4 logic operations (AND, OR, INV, identity) Realisation principle: use an adder in front of which we place a modifier circuit (Arithmetic-Logic Extender) This principle has already been applied for the 2-complement adder/subtractor: this was an adder in front of which we placed an exor circuit to allow for subtraction
VHDL
2/100
a4 b4 a3 b3 a2 b2 a1 b1 a0 b0
VHDL
FA Cout f4
FA
FA
FA
FA
f3
f2
f1
f0
S selects the function to be executed: 0=addition, 1=subtraction

2/101
a4 b4 a3 b3 a2 b2 a1 b1 a0 b0
S01
M
ALE ALE ALE ALE X FA Cout f4 f3 f2 f1 f0 FA FA FA FA ALE Y
VHDL
M selects the type of operation: 0=logic, 1=arithmetic S0 and S1 select the operation
2/102
M M S S M 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 1 1 1 S S S 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 Function Function Function Complement Complement Complement AND AND Identity OR Decrement Decrement Add Subtract Subtract Increment F F X Y F X Y X Y A A A 0 A A 0 A 0 A AAND AND ANDB B B A A AAND AND ANDB B A 00 A A A A 00 A A OR OR B B A AOR ORB B 00 A-1 A-1 A A all all11 A+B A+B A A B B A-B A-B A A B B A+1 A all 0 C C C 00 0 0 0 0 00 00 00 00 00 11 1
VHDL
2/103
M 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Function Complement AND Identity OR Decrement Add Subtract Increment F A A AND B A A OR B A-1 A+B A-B A+1 X A A AND B A A OR B A A A A Y 0 0 0 0 all 1 B B all 0 C0 0 0 0 0 0 0 1 1
VHDL
c0
S0
S1
M S1
1 1 c0
2/104
VHDL
X 1
S0
S1
S1
M S0
a b S0 S1 M
bi
ai
2/105
1 1 1 1 1 1 1 1 1 1 1 1 1 1 X
VHDL
S0
S1 1
S1
M S0 1 1 1 1 1
a b S0 S1 M
bi
ai
2/106
a4 b4 a3 b3 a2 b2 a1 b1 a0 b0
S01
M
ALE ALE ALE ALE X FA Cout f4 f3 f2 f1 f0 FA FA FA FA ALE Y
VHDL
2/107

VHDL
2/108
Decoders
E 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 C3 0 0 0 0 0 0 0 1 C2 0 0 0 0 0 0 1 0 C1 0 0 0 0 0 1 0 0 C0 0 0 0 0 1 0 0 0
E A1 A0
C3
C2
C1
C0
VHDL
A1..0 E Decoder 2 CLB
C3..0
2/109
Decoders
A3..2 E Decoder
A1..0 E Decoder E
A1..0 Decoder E
A1..0 Decoder E
A1..0 Decoder
VHDL
C15..12
C11..8
C7..4
C3..0
2/110

VHDL
2/111
Selectors
S1 0 0 1 1 S0 0 1 0 1 Y D0 D1 D2 D3
D3
D2
D1
D0 S1 S0
VHDL
D3..0
In principle: 2-to-1 MUX is 1/2 CLB Due to special provisions: 4-to-1 MUX is 1 CLB
S1..0
4-to-1 MUX Y
2/112
Selectors
D3 D2 D1 D0
S1 0 0 1 1 S0 0 1 0 1 Y D0 D1 D2 D3
Decoder
S1 S0
Y Alternative implementation
VHDL
2/113
Selectors
D15..12 S1..0 S1..0 D11..8 S1..0 D7..4 S1..0 D3..0
4-to-1 selector
4-to-1 selector
4-to-1 selector
4-to-1 selector
VHDL
S3..2
4-to-1 selector Y
2/114

VHDL
2/115
Buses
Problem with high fan-in MUX:
fan-in OR gate too big all inputs have to be routed to 1 central location: substantial routing delay and difficult routing
Solution: bus with tristate drivers

D3 D2 D1 D0 S1 S0
E 0 1 Y Z D
VHDL
Decoder
2/116
Buses
In an FPGA (lab session) a limited number of tristate buffers is foreseen, connected to horizontal long lines. It is possible to indicate for a certain signal that we prefer to map it to a long line. Note that a Boolean signal already can have 4 different values:
0: the logical signal 0 1: the logical signal 1 x: dont care Z: high-impedant
VHDL
Simulations will allow to visualize each of the 4 different values

2/117

VHDL
2/118
Priority encoders
D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 Any 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Any
0 D2 D3 A1
D0
D1
D0
D1
0 0 0 0
VHDL
D2
D3 D0 D1
A0
1 1 D2 D3 1 1 1 1 1 1 1 1
2/119
Priority encoders
Any
D3 D0 D2 0 D3 A1 D0 D1 D0 D1
0 0 0 0
VHDL
Any A1
D3..0
A0
D2
D3 D0 D1
Any
A0 Priority encoder A1..0 1 1/2 CLB D2 D3
1 1 1 1 1 1 1 1 1 1
2/120
Priority encoders
D15..12 D11..8 D7..4 D3..0
Priority encoder
Priority encoder
Priority encoder
Priority encoder
VHDL
Any
Priority encoder
4-to-1 MUX
4-to-1 MUX
A3..2
2/121
A1
A0

VHDL
2/122
Magnitude comparators
x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 y1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 x x0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 y y0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 G G (X>Y) (X>Y) 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 L L (X<Y) (X<Y) 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
y0
x0 1
y1
x1
1 1 1 1 1 y0
x0
VHDL
y1
x1
1 1 1 1 1 1
2/123
G x1 x0 y1 y0 y0 x0 1 y1
x1
1 1 1 1 1 y0
L G Xi Yi Gi+1 Li+1 Gi Li 1 CLB L
x0
VHDL
y1
x1
1 1 1 1 1 1
Comp
2/124
x7 y7 G L x6 y6 x5 y5 x4 y4 x3 y3 x2 y2
x1 y1 x0 y0
Comp Comp Comp Comp Comp Comp Comp
x7 y7
Comp
x6 y6
x5 y5
Comp
x4 y4
x3 y3
Comp
x2 y2
x1 y1 x0 y0 Comp
VHDL
Comp
Comp
Comp G
2/125
Simpler circuits are used for comparison with constants!!
X X x7 x6 X is 8 bits y y=1 when X>=64 y y=1 when X=0 x0 y y=1 when X is even y y=1 when X=255 y y=1 when X<192 x7 x6
VHDL
2/126

VHDL
2/127
Shifters and rotators

Shifter:
An input word is shifted m positions to the left or to the right m bits disappear at one side m bits are created at the other side For an arithmetic shift (word = 2-complement)
VHDL
For a left shift m zeros are shifted in from the right For a right shift m times the MSB is shifted in from the left (for 2complement)
For a logic shift
It is possible to indicate which value is shifted in

2/128
m bit left shift is multiplication with 2m m bit right shift is division by 2m

Rotator:
An input word is shifted m positions to the left or to the right The bits that drop-off at one side, are shifted back in at the other side
VHDL
2/129

S2: 0=no shift,1=shift S1: 0=left,1=right S0: 0=shift,1=rotate d0 d1 d2 d3 S2 S1 S0 L-in R-in M M
VHDL
4-to-1 MUX y3
4-to-1 MUX y2
4-to-1 MUX y1
4-to-1 MUX y0
2/130

8-bit barrel left rotator
S0
VHDL
S1
S2
2/131

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R.

Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Design of Combinatorial Circuits

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Design of Combinatorial Circuits

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Design of Combinatorial Circuits

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

(fan-in)complete circuit = (2)+(3)+(3)+(2) = 10

Delay = (gate-delay)critical path = 1 + (1.8+1) + (1.4+1) = 6.2

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

(fan-in)complete circuit = (1+2) = 3 i.o. 10

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

xy (z does not matter) xz (y does not matter) xz (y does not matter)

0 xyz xyz xyz xyz

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

3*(1) + {1*(2)+2*(3)} + 1*(3) 14 i.p.v. 39 1 + (1.8+1) + (1.8+1) 6.6 i.p.v. 8.6

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

F(v,x,y,z,w) Differs from course book

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Design of Combinatorial Circuits

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Minimization with the Karnaugh map

Digital design Combinatorial circuits Sequential circuits FSMD design

Determine all prime implicants

Determine all essential prime implicants

Search for minimal coverage

R.Lauwereins Imec 2001

Minimization with the Karnaugh map

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Minimization with the Karnaugh map

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Minimization with the Karnaugh map

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

Minimization with the Karnaugh map

Digital design Combinatorial circuits Sequential circuits FSMD design

R.Lauwereins Imec 2001

3(1) + {1(2)+2(3)} + 1(3) 14 i.p.v. 39 1 + (1.8+1) + (1.8+1) 6.6 i.p.v. 8.6

=41+13+22+13=14 =22% cheaper =(1)+(.6+3.4+1) +(.6+3.4+1)=6.6 =6% faster

Cost=1+(4(3+1))+(1(4+1))=22 (76% cheaper) Delay=(.6+1.4)+(.6+3.4+1)+(.6+4*.4+1)=7 (34% faster)

Cost=(11)+(3(2+1))+(1(3+1))=14 (84% cheaper) Delay=(.6+1.4)+(.6+2.4+1)+(.6+3.4+1)=6.2 (44% faster)