CADSTAR SI Verify Self Teach

Zuken SI Verify with CADSTAR Self-Teach Tutorial
SI Verify with CADSTAR

Self-Teach Tutorial
Copyright © Zuken Ltd 2005-2007 All Rights Reserved. Unauthorized copying or distribution prohibited.
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Introduction-1
Introduction
This is a set of lessons complete with design data that guide you through the key features of SI Verify, in seven
chapters:
1. Design Flow, including:
• Set up your CADSTAR design for SI Verify.

• Run SI Verify when you have an existing design or when you want to perform design-independent what-if
analysis.
2. Scenario Editor, including:
• Create and save design scenarios for what-if analysis.

• Extract equivalent transmission line circuits from placed or routed designs.
3. Configuration Editor, including:
• Define configurations to represent track and board layer cross-sections.

• Use the field solver to analyze configurations and use the results in your scenarios.
4. Simulation, including:
• Get simulated waveforms.
• Interpret simulated results.

5. Simulation Library, including:
• Import IBIS models or create your own.

• Manage model libraries.
6. Constraint Manager, including:
• Understanding the Tree View and spreadsheet.
• Viewing net topology.

• Mapping parts and component instances to simulation models.
7. Importing and Using Electrical Board Descriptions, including:
• Importing an Electrical Board Description (EBD) to model boards attached via connectors.
• Simulating including the effects of attached boards.
The design files you need to complete the lessons for each chapter are stored under separate folder names for each as
follows: ch1_des_flow, ch2_se, ch3_ce, ch4_scs, ch5_similib, ch6_cm and ch7_mb. Please install the training data as
described in Installing the Training Data.
Before you start work on each new chapter of the training, please close all applications. When you have closed the
applications it is a good idea to run the utility Sweeper which is available in the start menu with the other CADSTAR
programs; this clears any server processes that are still active
Introduction-2
Installing the Training Data

Please install the training data using the self-extracting executable SIVerifySelfTeach.exe. You will be asked where you
would like to save your files; please specify a unique new folder.
Main Changes since Previous Version

If you are updating from the previous SI Verify version, you can learn about the most important changes by completing
training exercises in the parts of the training manual referenced below.
• Simulate the effect of backdrilling vias, which can be used to improve signal integrity. Please see Simulate
Backdrilled Vias in Chapter 4.
• Display differential impedance results in additional places to work more efficiently. Please see Display
Differential Impedance Results in Chapter 4.
• Measure at pulses other than the first to allow simulated lines to settle before measurement. Please see
Extended Waveform and Pin/Die Measurements in Chapter 4.
• Use relative offsets in Configuration Editor to input configurations more naturally. Please see Solve Coupled
Transmission Lines in Chapter 3.
• Display the result of subtracting one waveform from another to isolate noise. Please see Subtract Waveforms
in Chapter 4.
• Change the colors used in waveform display. You can use this feature in any exercise where you display
waveforms by changing Color Set in the General tab of the [View]-[Diagram Options] dialog in the simulation
window. Chapter 4 contains several simulation exercises.
• Export simulation library data for items selected in Constraint Manager to preserve the model set used for
analysis in specific cases. Please see Export Simulation Library Data in Chapter 6.
• Simulate including test land capacitance. Please see Extract Test Land Capacitance in Chapter 2.
• Use IBIS Series Switch models in Scenarios. Please see IBIS Series Switch Models in Chapter 5.
• Simulate including effects of mutual inductance. Please see Mutual inductance in Chapter 4.
Introduction-3
Chapter 1 Design Flow

This chapter covers how to set up a CADSTAR design for use with SI Verify, including how to set important attributes.
When you use SI Verify to analyze and simulate your design, you also need to manage simulation models; there is a
separate chapter on the Simulation Library that describes this process in detail.
In this chapter as in all other lessons, please use the standard CADSTAR setup and library locations as they were in the
initial installation. No special extra setup is required. Some of the training designs include local simulation libraries
(project libraries) that are part of the design data.

Please use only the data in ch1_des_flow for the lessons in this chapter. The correct file to open is not selected by
default.
Design Flow-1
SI Verify Design Data Structure

Before proceeding with the lessons, it is important to know the locations where design data is stored. The primary data
file for SI Verify is the .ctf file which holds important design data and settings.
The chart below shows the main directory structure for SI Verify files which are created in addition to any CADSTAR
data. SI Verify data is stored in the hotstage directory. The stem of the design data directory name (<job>) is used for
the other design files. SI Verify has its own physical design files, stored in the pcb directory, The main design files are
the floorplanning file .fif, and the router file .rif which is stored in a router subdirectory. The .prk file is a control file. It is
important not to delete the .prk file, otherwise the design will not load into SI Verify.
Files are automatically placed in this directory structure when you invoke SI Verify or export P.R.Editor XR HS/SI Verify
files from CADSTAR.
<job>
hotstage data
<job>.ctf
pcb
router
<job>.fif
<job>.rif
<job>.prk
Design
Data
<job> adviser
Important
internal
files
hpe
Important
internal
files
The ctf, rif and fif files are the main data files for SI Verify, but the adviser and hpe directories contain important data that
you should not disturb
Design Flow-2
Load
Create and Load SI Verify Design Data
Lesson: Check the layer stack settings and run the field solver
Purpose
Understand how to set a layer stack to obtain correct results in SI Verify.
SI Verify can perform very fast calculations using a table of field solver results containing impedance, capacitance,
inductance and crosstalk coupling values. You run the field solver from CADSTAR before you export the design to SI
Verify. You need to run the Field Solver before you use the simulator or any simulation-based functions.
A correctly-described layer stack is essential to obtain correct results when you are analyzing a physical design. Please
note that you will only get highly-approximate results for boards that do not contain at least one continuous ground or
power plane. For details of how these approximations are determined, please see the user manual.
Steps
1. Start the Design Editor and open hs_tra_routed.pcb.
Note: Please remember to use the data in the ch1_des_flow folder for this exercise.
2. Invoke the Layers dialog using [Settings]-[Layers…].
3. In the Show Layers of Type area of the dialog, tick Electrical, Powerplane and Construction only to obtain the
result shown below.
Design Flow-3
Note: The layers are ordered from top to bottom. In this case there are eleven significant layers: four electrical layers, a
VCC plane and a Ground plane where each layer is separated from the next by a dielectric (normally laminate or
prepreg) layer
Note: Since L1 is an electrical (signal) layer, the tracking is assumed to embed into prepreg-type dielectric material prior
to curing. The direction of embedding is specified by the Embedding setting. Above means the track embeds into the
material above this layer; in this case there is no dielectric layer above, so the track is considered to embed into the air
above the to surface of the board. No impedance results can be obtained for any layer that is not embedded. The
thickness is the finished thickness of the tracking. As a guide, one ounce copper yields a thickness of 0.0356mm
(0.0014 inches). The diagram below illustrates the layer stack used in this design,
L1 (Above)
Dielectric_1-2
Dielectric_2-3 L2 (Above)
VCC_+3.3V (Not embedded)
Dielectric_3-4
GND (Not embedded)

Dielectric_4-5 L5 (Below)
Dielectric_5-6
L6 (Below)
Electrical layers always embed into dielectrics or air. Power and ground planes do not embed as they are modeled as
continuous conductor sheets
Note: For electrical layers only, not power or ground planes or dielectric layers, it is possible to select Reference Plane
(power and ground planes are automatically considered to be reference planes). The field solver does not normally
consider partial power planes, where some signal layer areas are flooded with copper. If you make a layer a Reference
Plane, then calculations for other layers will consider it to behave like a ground plane, which has a major effect on field
solver results. You should set Reference Plane on any electrical layers that are or later will be substantially filled with
power or ground copper.
Design Flow-4
4. Consider layer Dielectric_1-2. Since this is a dielectric layer, not only must the thickness be correct, but the
material must be correctly described. This layer uses a material which also has the name Dielectric_1-2,
although there is no requirement for these two names to be the same.
5. Close all open dialogs and select [Settings]-[Materials]. Double-click on the material Dielectric_1-2 so that its
details are displayed as shown below. This material has a relative permittivity of 4.5, which is fairly typical for
FR4 material. Note: You should check the relative permittivity (also called Dielectric Constant) of the materials
you are using with your board manufacturer.
It is essential to specify correct material details so that the field solver will yield correct results
6. Close the Material Details dialog by clicking Cancel.
7. Invoke the Field Solver menu using [Tools]-[Field Solver].
The field solver is the same one that is used with the EMC Adviser and the method used to run it is the same
8. Click on the Parameters… button in this menu.
Design Flow-5
This dialog allows you to provide useful extra input to the Field Solver
9. Check that Standard Track Width and Standard Min Spacing are set to your minimum track width and track
spacing for the current board. Note: Please do not change these values for this example, but if you need to
enter different values in other designs, select the parameter and click on the Value… button to obtain the dialog
for doing so. Please note that values are always expressed in millimeters.
10. Click on Close in this dialog.
11. Click on OK in the Field Solver dialog to run the field solver. On completion, you will see a transcript generated
by the field solver similar to the example below. You normally do not need to examine this text except to check
that no problem was indicated, so you can close this dialog.

The field solver generates the files <job>.mle, <job>.mls, <job>.mli and <job>.mlt. These are internal files that
you should not use directly.
Design Flow-6
The field solver is also a module of the EMC Adviser and generates an Adviser-style transcript
0.
Design Flow-7
Lesson: Set net classes
Purpose
If you associate nets with net classes in CADSTAR then you will be able to navigate by net class in the Tree View of SI
Verify.
Steps
1. Select [Settings]-[Assignments…] and click on the Net Classes tab. You will obtain a display like the one
below. Notice that one net class, _hsl_by_rifout has been defined.
Net classes provide a way of constraining groups of nets. In this dialog, Rise Time, Voltage Amplitude and Via Delay
have no significance for SI Verify. Source Pin Order can affect the order of connections assumed for unrouted nets as a
legacy method for SI Verify. It is best, however, to set net_topology to "ordered", set pin_source to identify source pins
as shown in Table 1 and set pin orders as described later in this chapter to control pin connection order (this method
also works for P.R.Editor XR 5000 HS). The EMC Adviser uses the original settings and does not recognize pin_source.
2. Cancel the Assignments dialog.

3. Find net CLK_Zuken using [Edit]-[Find…], selecting the By Net tab. The net will be highlighted as shown.
Design Flow-8
4. Close the Find dialog and click the Item Properties ( ) icon on the toolbar.
5. Click the Net… button in the Item Properties dialog to obtain the display shown below, observing that this net
has been associated with net class _hsl_by_rifout. Net sign19 is also associated with this net class.
In this design the net class is already set on CLK_zuken (and one other net)
6. Cancel the Item Properties dialog.

0.
Design Flow-9
Lesson: Setting net topology
Purpose
Net topology is the order of the connections in a net, and is controlled by setting pin_order and pin_branch attributes. SI
Verify does not constrain the routed topology, but the topology settings affect its behavior when dealing with unrouted
nets, because these nets can be analyzed and simulated according to automatically-estimated route lengths.
Constraints can only be checked against results in SI Verify on nets where the topology has been specified. SI
Verify allows you to visualize topology settings on unrouted nets, as you will see in Chapter 6 Constraint Manager, but
only if you have defined the topology. P.R Editor XR 2000/5000 HS can route according to topology constraints. You can
set net topology using the pin_order, pin_branch and net_topology attributes. This training course does not contain
an exhaustive treatment of how to construct net topology but the basic method for setting topology is as shown in a to c
below. Please do not perform items a to b as part of the training. The steps for the next lesson start after the heading
“Steps”.
(a) Set the pin attribute pin_order on each pin to the position of the pin in the routing order. The same
number on two pins on the same branch indicates that either pin can be routed to first. It is best to use
numeric values starting at 1.
pin_source=TRUE Net attribute net_topology = ordered
1
3
2 2 2
VTT
swappable pins
ref_voltage=0.9V
Design Flow-10
(b) Set pin attribute pin_branch to a number representing the routing branch a pin is on. If the routing is
not branched there is no need to set this attribute.
Net attribute net_topology = ordered

pin_source=TRUE
2,1 3,1
2,2 3,2
Note: You can create a differential pair using the net attribute net_diff_pair on two nets with the same number and
types of pins (not covered by a lesson). The net_diff_pair attribute takes an identical value on the two nets that
represents the name of the differential pair, for example “diffpair1”. If you specify that two nets form a differential pair,
that setting will be reflected in SI Verify; you will see the pair you defined under Differential Pairs in the Tree View.
Defining differential pairs makes differential simulation easier in SI Verify.
Net attribute net_topology = ordered

pin_source=TRUE
VTT
net_diff_pair=name
12 3
5
5
12 3 4
pin_source=TRUE 4 VTT
Steps
1. Use [Settings]-[Attribute Names] to check that pin attributes pin_order and pin_branch are available. If they
are not, then add them.
2. Select net A12 using Find.. as before.
3. Use [Actions]-[Edit Attributes…] to set pin_order as shown below, then click OK. There is more about net
Design Flow-11
topology in Chapter 6 Constraint Manager.
This topology represents a daisy chain where routing begins at U18-71 and the remaining pins are in a chain with
swappable pin order
Swappable pin order
U18-71
U7-32 U11-30 U17-24
This is the routing order that will be assumed in analysis if the net is un-routed. SI Verify will assume the best physical
order of the three swappable pins
0.
Design Flow-12
Lesson: Setting attributes that affect SI Verify
Purpose
You can create constraints by setting attributes within CADSTAR. Some of these constraints affect routing in P.R.Editor
XR 2000/5000 HS; in SI Verify they will appear as read-only constraints in the Constraint Manager and you will be able
to check performance against those constraints.
Please note: When setting attribute values please make sure you do not enter carriage return or newline
characters, as these can prevent the attributes from having their desired effect.
The set of attributes we are concerned with is shown in the table below. The attributes that you set in CADSTAR are
shown in the left hand column and the derived SI Verify constraints or attributes in the second column.
CADSTAR Attribute SI Verify Constraint or Comments

Attribute (attributes
shown in brackets)
cond_thickness (cond_thickness) These values are only used if you have a
diel_thickness (diel_thickness) layer stack that has consecutive
diel_constant (diel_constant) conducting layers with no intervening
dielectric layers (not a recommended mode
of operation). In this case, dielectrics of
thickness diel_thickness and relative
permittivity (dielectric constant)
diel_constant are inserted automatically for
the purposes of the field solver, so that
parameters such as characteristic
impedance can be calculated. Conductors
are assumed to have thickness
cond_thickness if their defined thickness is
zero or negative.
Examples:
diel_constant=4.7
diel_thickness = 0.254mm
cond_thickness=0.0254mm
These attributes are set at the board level.
net_topology (net_topology) Set to "ordered" for high-speed nets
net_max_delay Max Delay Will be converted to Electrical Net
net_min_delay Min Delay constraints in SI Verify.
Examples:
net_max_length Max Length
net_max_delay = “500ps”
net_min_length Min Length net_min_length = “50mm”
net_max_stub Stub Length net_max_stub = “10mm”
net_max_xtalk Max Crosstalk net_max_xtalk = “100”
Note: mV assumed
These attributes are set at the net level.
char_Z Min Zo, Max Zo Minimum and maximum characteristic
Z_tol Z_tol impedance are set around a center value
with a percentage plus and minus
tolerance specified by Z_tol.
Example:
char_Z = “50”
note: Ohm assumed
Z_tol = 10%
Char_Z is set at the net level and Z_tol at
the board level.
Design Flow-13
pin_delay_grp Skew Group Used to specify maximum skew

pin_length_grp Skew Group (differences in length and delay) within the
same net or between different nets.
Example:
pin_delay_grp = “fred:5”
The maximum difference in the delay to
each pin of the group fred from any defined
source (define using pin_source) is 5
picoseconds.
Example:
pin_length_grp = “addr:25mm”
The maximum difference in routing path
length to each pin of the group addr from
any defined source is 25mm.
These constraints will only be transferred
to SI Verify if there is one and only one pin
defined as a source using the pin_source
attribute on any one logical net.
These attributes are set at the pin level.
pin_source (pin_source) A value of TRUE on this pin-level attribute
indicates that the pin should be treated as
a source.
pin_min_delay Pin pair Min Delay, Max In SI Verify, a pin pair constraint within an
pin_max_delay Delay, Min Length or electrical net is created between each
Max Length constraint. source identified by the pin_source
pin_min_length attribute and the pin with one of these
pin_max_length attributes set.
Example:
pin_min_delay = “120ps”
ref_voltage (please (ref_voltage) plus It is essential to set this attribute on all
ignore the similarly- treatment as a power fixed-voltage nets before using the field
named voltage attribute net solver or transferring the design to SI
for the training) Verify. The value is expressed in mV.
Example:
ref_voltage = 5000.0mV
Table 1: Important SI Verify Attributes
* Please note that the CADSTAR SI attribute SI_Part is not used by SI Verify.
Design Flow-14
Steps
1. Use [Settings]-[Attribute Names] to invoke the User Attributes dialog and make sure that all of the attribute
names listed in Table 1 are present in the design. Add any that are not using [Settings]-[Attribute Names].
2. Close the User Attributes dialog.

3. Check the values of board-level attributes cond_thickness, diel_thickness, diel_constant and z_tol; select
each of them (or the board outline) as shown in the screenshot below and click the Item Properties icon ( ).
Note: The field solver will use these values as defaults in the circumstances listed in Table 1.
You can see the board-level attribute values above the board outline
4. Select [Actions]-[Edit Attributes…].

5. Choose By Net in the Edit Attributes dialog and click Choose Nets…
Click
6. Select net –RAS- and click OK.

7. Set pin order using [Actions]-[Edit Attributes] as shown so that you can check results against constraints.
8. Set net_max_stub to 25mm, net_max_length to 100mm, net_min_length to 50mm, net_max_xtalk to
Design Flow-15
100mV and char_Z to 50 on net -RAS-.

9. Now check the skew (difference in length) constraints that have been set up within a group of nets. Select all the
nets A00 to A07 inclusive. Check the following: Attribute pin_source is set to TRUE on all of the U18 pins in the
bus as shown below. On every U11 pin the attribute pin_length_grp should be set to to addr:25mm to
constrain the maximum difference in length between the nets.
SI Verify will create skew groups of pin pairs starting at the pins with pin_source=TRUE and ending at the pins with the
pin_length_grp attribute values. For the nets in view in this screenshot, the pin pairs will be U18 pin 186 to U11 pin 47,
U18 pin 189 to U11 pin 46 and U18 pin 84 to U11 pin 44.
10. Select the power nets GND, VCC_+1.8V, VCC_+3.3V and VCC_+5V then use [Actions]-[Edit Attributes] to
observe the values set for the ref_voltage attribute.

11. Select net -CS0- and check that pin_source is set to TRUE on pin U18-3 and pin_min_length and
pin_max_length are set to 20mm and 50mm respectively on pin U13-36.
12. Start SI Verify directly from CADSTAR using [Tools]-[SI Verify…] and wait for SI Verify to launch fully.
13. Click on the design level + symbol, then the design version level + symbol as shown below to open the tree view
for the design.
Design Flow-16
Click
Click
Open the top design level, then the design version level to see the tree view for your design
14. Select [Tools]-[Options] in SI Verify and click on the General tab.

15. Set Delay Mode is to Length if it is not already set to this value and OK the dialog.
Note: SI Verify can either work with lengths or delays but not both simultaneously.
Check the results of your settings in the Constraint Manager of SI Verify as follows.
16. Click on the Power Nets ( ) icon in the tree view on the left hand side, noticing that nets
GND, VCC_+1.8V, VCC_+3.3V and VCC_+5V are listed as power nets.
17. Click on electrical net -RAS- ( ) in the tree view and select the Delay tab in the spreadsheet on
the right hand side. Observe that Min Length and Max Length constraints have been set on this electrical net.
18. Click on the Crosstalk tab and see that the Max crosstalk constraint has been set.
19. Click on the Misc tab, observing that the Stub length constraint has been set.
20. Click on the Impedance tab, then double click on ( ) to reveal the logical net below. Select the
logical net ( ) and observe that Min Zo and Max Zo have been set to 45 and 55 Ohm
respectively; this is 5Ω (10 percent) below and above the char_Z value you set in CADSTAR. The tolerance
was set by the board level attribute Z_tol.
Design Flow-17
Impedance constraints are set at the logical net level
21. Select electrical net -CS0- and open the pin pairs ( ) below the electrical net in the tree
view. Select the pin pair U18-3 – U13-36 and click on the Delay tab. Check that Min Length and Max Length
are set to 20 (mm) and 50 (mm) respectively.
22. Select the Skew Groups icon in the tree view as shown below and check that the skew group is composed of
pin pairs all of which are from U18 to U11. Check that the skew constraint is 25mm as you set in CADSTAR.
The pin pairs have been created between the pins that have pin_source attribute = TRUE and the pins that
have pin_length_grp attribute = addr:25mm in CADSTAR.
The pin_length_grp and pin_source attributes have been converted to a Skew Group
23. Use [File]-[Save] in SI Verify to save your design, then [File]-[Exit].

24. When asked whether you want to rebuild SI Verify results into layout, click Yes. Click Close in the SI Verify
Interface popup that informs you that ‘net_max_stub’ is now an attribute of any item. Do not close CADSTAR
Design Editor.
0.
Design Flow-18
Lesson: Run CADSTAR and SI Verify independently
Purpose
To use CADSTAR and SI Verify independently on the same design.

You can use SI Verify with designs where components are placed or placed and routed; where nets are not routed,
estimates are used automatically. Once you have generated SI Verify data files from CADSTAR, as you did in the
previous lesson, you can run SI Verify independently from the Start menu. The advantage of working this way is that you
can cross-probe nets and other design items between the two applications.
In the previous lesson, you invoked SI Verify directly from CADSTAR, but you can also generate SI Verify files without
running SI Verify, then invoke SI Verify independently. To work this way (not covered by a lesson) you use [File]-[File
Export…] in CADSTAR.
When you cross-probe from CADSTAR to SI Verify, logical nets are selected in SI Verify. When you cross-probe
electrical nets from SI Verify, all logical nets that make up electrical nets are selected, including any nets connected via
series passive components as illustrated below.
Please note that all electrical nets will contain just one logical net until you have modeled the passive components in
your design in the Simulation Library.
U1 R1 U2
Logical net 2
Logical
net 1 R2
Logical
net 3 C1
An electrical net comprising three logical nets; connections to ground and power do not count as extra logical nets
Steps
1. Start SI Verify from the Start menu, selecting file hs_tra_routed.rif in the hs_tra_routed\pcb\router folder.
2. Single-click on some nets in CADSTAR, observing that they are cross-probed to logical nets in SI Verify.
Design Flow-19
Click
3. Select some electrical nets in SI Verify, observing that they are cross-probed into appropriate logical nets in
CADSTAR when you click the telephone ( ) symbol on the toolbar.

4. Select [Tools]-[Options] in CADSTAR and click on the Cross Probing tab. The Cross Probing Features
Enabled area allows you to control cross-probing between CADSTAR and SI Verify. The options available are
self-explanatory, but please note that if you are making large selections, performance will be affected if cross-
probing is continuously enabled.
The Cross Probing Features Enabled area controls cross-probing with SI Verify
5. Close all open applications.
Note: When you create the data files for SI Verify and start it directly from CADSTAR in a single operation using [Tools]-
[SI Verify…], cross-probing is not available.
0.
Design Flow-20
Chapter 2 Scenario Editor

The Scenario Editor allows you to perform sophisticated what-if analysis. You can create pure scenarios in which you
enter experimental circuits yourself, or you can extract equivalent circuits from your physical design, adding any extra
circuit elements you wish to model before simulating. You can save these scenarios for future reference, keeping an
audit trail of your design assumptions.
Please use only the data in ch2_se for the lessons in this chapter. The correct file to open is not selected by
default.
Please Note: Some dialogs in SI Verify, such as the [Tools]-[Options] dialog in the Constraint Manager, need to be
closed (if they have been opened) before other operations can be performed.
Scenario Editor-1
What--if Analysis
Perform What
Lesson: Explore topologies using the Scenario Editor
Purpose
To decide what net topologies are appropriate for different types of signal without pre-existing design data. The Scenario
Editor is a tool for editing and simulating proposed topologies. In this lesson, SI Verify is used directly from CADSTAR,
whereas in the previous lesson in Chapter 1 Design Flow we exported data then invoked SI Verify separately.
Steps
1. Invoke the CADSTAR Design Editor from the Start menu.

2. Use [File]-[New] to create a new empty PCB design, selecting Self Teach in the PCB Design tab of the New
dialog, and saving your new design as Whatif in the ch2_se folder in the Self Teach area.
3. Click on the Shape Defaults ( ) tool on the toolbar, check the Board button and click OK.
This setting means we will create a board outline
4. Click on the Add Rectangle ( ) tool then draw a rectangle to represent the board outline. The precise
Scenario Editor-2
dimensions are not important as we will not use this as the actual board outline.
5. Use [Tools]-[SI Verify…] to transfer the design to SI Verify and click OK in the confirmation dialog. When you
are asked whether you wish to run the field solver, answer YES. Your empty PCB design will be transferred to SI
Verify. You can now use SI Verify to explore design scenarios independently of any PCB design. SI Verify will
start, with a display like the one shown below.
CADSTAR SI Verify shows the empty design called “Whatif” in the Tree View in the left-hand pane
6. Click the + key next to Whatif in the tree view in the left hand pane. The tree view will expand to the next level.
7. Select in the left pane then create a new scenario called using [Edit]-[New]-[Scenario].
8. In the Create Scenario window, confirm that the option is Empty, and click Finish. The Name window that
appears next will display the default scenario name Scenario1; you can enter a different scenario name if you
prefer. Click OK to finish creating the scenario.
Click
Click
You are creating a new scenario sheet, so the sheet is Empty.
9. Select your new scenario in the Tree View as shown below and start the Scenario Editor by clicking on its icon
in the toolbar.
Scenario Editor-3
Click
Click
The initially-empty scenario is opened in the Scenario Editor
10. Add a Driver ( ) and 4 Receivers ( ) using [Add]-[Symbol] as shown below.
Click
Click
Adding buffer symbols to the scenario
11. Click [Right mouse button]-[Command Cancel], or push [Enter] or [Esc] on the keyboard.
Scenario Editor-4
12. In turn, select standard topologies, Star ( ), Remote Star ( ) Daisy ( ) and H-Tree ( ),
observing the effect of each setting.
The topology settings, from left to right, are Star (star point at the near end), Remote Star (star point at the far end),
Daisy Chain (pins connected in a chain starting at the driver) and H-Tree (balanced delay from driver to each receiver)
Scenario Editor-5
13. Select a transmission line in the Scenario Editor, then use [Edit]-[Nominal Values] ( ) to obtain the dialog
for editing nominal values on a transmission line. The default nominal values that you see here can be set in the
Options dialog in the Constraint Manager. Confirm that the values are Length 100mm, Velocity 0.15mm/ps
and Impedance 50 Ohm.
Click
The transmission line values that will be used for simulation are shown in the Nominal Values dialog
14. Close the Nominal Values dialog by clicking [OK].

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Scenario Editor-6
Lesson: Simulate Standard Topologies
Purpose
Check the signal waveform for different topology settings. In a Daisy topology, the pins are arranged in a chain. Short
track stubs are allowed when connecting to receiver pins.
Steps
1. Click the Daisy ( ) icon in the Scenario Editor.
2. Click the Simulate （）icon.
There is quite a large difference in the signal arrival times
3. Click the Data tab in the simulation view. You can see which buffer models have been used for each symbol – in
this case default models.
Scenario Editor-7
Default simulation models are being used for these pins
Note: In a Remote Star topology there is a branch point near the receivers.
4. Change the topology to Remote Star （）and Simulate（）.
The Remote Star topology gives lower skew
5. Change the topology to H-Tree ( ) and Simulate （）.
Scenario Editor-8
Clock distribution can be balanced using an H-Tree
6. The H-Tree topology balances the delay to each receiver while permitting receivers to be placed some distance
apart.
7. Change the topology to Star ( ) and Simulate （）.
The Star topology gives a slower rising edge
8. Click [File]-[Apply] followed by [File]-[Close] in Scenario Editor.

9. Create a new, empty scenario with name Scenario2 and open it in the Scenario Editor in the same way as you
created and opened Scenario1.
10. Add a Driver ( ), a Receiver ( ) and a transmission line ( ) using the Add Symbol ( ) dialog.
Scenario Editor-9
11. Make point ( ) to point ( ) connections to connect the symbols as shown.
Connect the symbols so that the transmission line is between the driver and receiver
12. Choose the Driver, and select [Edit]]-[Model Information]] (Alternatively, double-click the driver symbol).
13. Change the tab from Component to Pin.
14. Click Select Model ( ) to invoke the Model Selection dialog.
You can select a buffer model from the set defined in the simulation library
15. Choose simulation model LVC_040_S0_out.

16. Click [OK] in the Model Selection dialog. You will see the assigned model change in the Model Information
dialog.
17. Click [OK] on the Model Information dialog.
Scenario Editor-10
The assigned model is shown in the dialog
18. Similarly, assign model LVC_000_S0_in to the receiver.
The receiver model is assigned to the input pin
19. Click the Simulate ( ) Icon.
Scenario Editor-11
The waveform shows some ringing
20. Close the simulation window using [File]-[Close].
Do not close Scenario2.

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Scenario Editor-12
Lesson: Use voltage symbols in Scenario Editor
Purpose
Use symbols in the Scenario Editor to represent connections to fixed D.C. voltages
Steps
1. Select [Add]-[Symbol] on the menu bar of Scenario Editor.
2. Click the Resistor ( ) icon.

3. Click OK in the Component dialog, noticing that the default resistor value is 50 Ohm.
4. Place the resistor near the receiver.
5. Click the Signal Reference ( ) Icon.

6. Move the mouse cursor to the Scenario Editor canvas and press the ‘r’ key twice to rotate the component.
7. Put the Signal Reference (fixed voltage) symbol below the resistor.
Placing the resistor and fixed voltage symbols
8. Double Click on the Signal Reference (fixed voltage) symbol (alternatively, press [RMB]-[Signal Reference]).
9. Click the Edit List… button in the Signal Reference List dialog.
Scenario Editor-13
This dialog displays the list of signal names and their associated voltages. In this case, none have previously been
defined
10. Add ‘GND’ in the Signal Name column and ‘0’ in the Voltage column.
The defined signal and voltage definition can be used in multiple signal reference symbols
11. Click OK in the Add or Edit Signal Reference dialog.
12. Click on GND and then OK.
Clicking on the Signal Name selects its name and voltage value
13. Connect the signal reference, resistor and receiver.
Scenario Editor-14
The resistor and signal reference for a termination to ground
14. Click the Simulate ( ) Icon.
The waveform is much smoother because the signal is terminated
15. Click [File]-[Close] in the Scenario Editor. There is no need to save your scenario.
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Scenario Editor-15
Check Sensitivity to Crosstalk
Lesson: Crosstalk Simulation
Purpose
Simulate crosstalk considering signal timing and coupling.
Steps
1. Create a new Scenario with name xtalk.
2. Select your new scenario and click the Scenario Editor icon.
Click
Click
Create new scenario with name xtalk and open it in the Scenario Editor
3. Enter topology as shown. The Scenario Editor can tidy the diagram for you. Add and connect the correct
symbols, then use [Edit]-[Tidy] to redraw the diagram in a neat manner.
Scenario Editor-16
4. Click one of the transmission lines in the Scenario Editor.

5. Click the other transmission line with the CTRL key held down.
6. Press [RMB] and select Coupled on the menu that appears.
7. Double-click on one of the transmission lines. The other coupled lines will be selected automatically and the
Nominal Values dialog will appear.
8. Click the button in the Nominal Values dialog.

9. Click OK in the Edit Configuration dialog and click OK in the dialog that pops up.
Note: This dialog informs you that a new configuration will be created, and the Configuration Editor will appear after
you click OK. You can edit track cross sections in the Configuration Editor. (Please see the Configuration Editor
chapter for details).
An RLGC (resistance, inductance, conductance, capacitance) matrix is calculated by a field solver when you click
Solve.
Static characteristic impedance and velocity (assuming other conductors are grounded) are calculated and shown in the
Configuration Editor automatically.
10. Click the Solve button.
You can model transmission line configurations in Configuration Editor
11. Click OK in the Configuration Editor. The RLGC matrix that was created by the field solver will be automatically
applied to the transmission lines.

12. Select [Tools]-[Display Options] in the Scenario Editor; the Options dialog will appear.
13. Click on the Items tab. In this tab you can select from a list of colors for each item.
14. Change the display color of Coupled Transmission Lines to purple (or another color of your choosing) as
Scenario Editor-17
shown below and click OK.
This dialog controls display colors in the Scenario Editor
15. Observe that the transmission line parameters have been annotated to the coupled transmission lines in the
Scenario Editor as shown below.
Configuration Editor has calculated the transmission line parameters
16. Click the Simulate ( ) Icon in the Scenario Editor.

17. Select IC1-1 in the tree view of the Simulation Control window.
18. Press [RMB] and select Stimulus.
19. Change Periodic to Constant low in the Stimulus dialog.
Scenario Editor-18
Changing one of the stimuli to a constant low will isolate crosstalk coupled from the other line
20. Click OK in the Stimulus dialog
21. Simulate again, this time by pressing the Simulate ( ) icon in the simulation window, and observe the
crosstalk on the Enet to which you assigned a constant-level stimulus.
Simulate with a constant level stimulus on one of the nets
22. Close the simulation window.

23. In Scenario Editor, [File]-[Apply] to save the scenario xtalk then close the Scenario Editor.
24. Save the design from the Constraint Manager, then Exit from Constraint Manager. When asked if you want to
rebuild results into Design Editor, answer No.
25. Exit from Design Editor.

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Note: It is possible to reopen this design in SI Verify and continue work on the saved data at a later time.
Scenario Editor-19
Create a Scenario from PCB Data
Lesson: Create a scenario from PCB data
Purpose
When you have a physical PCB with data that is either placed, or placed and routed, you can extract scenarios based
on the physical design data; an electrical equivalent circuit is created automatically. You can modify the scenario and
add other components in the same way as in any other scenarios, so it is possible, for instance, to model the effect of
proposed terminations or attached measuring instruments.
Steps
1. Select SI Verify from the Start menu.
2. Browse to hs_tra_routed\pcb\router in the Open High Speed Design dialog and open file hs_tra_routed.rif.
3. Select electrical net CLK_zuken and click the Scenario Editor icon ( ), [Edit]-[New]-[Scenario] or [Right
Mouse Button]-[New]-[Scenario].
4. Name the new scenario “CLK_zuken_routed”.
5. Click OK. The topology and transmission line parameters will be extracted automatically from the physical layout.
The scenario is the equivalent circuit of the physical layout of the selected Enet. The scenario for physical data is
created automatically in the same way as for a design with schematic data only, but takes the physical placement and
routing into account. Notice that the layer from which each transmission line was extracted is identified in the diagram.
6. Close the Scenario Editor ([File]-[Close]).

7. Exit the Constraint Manager ([File]-[Exit]) without saving.
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Scenario Editor-20
Simulate with Enhanced Via Models
Two types of via model can be used: Simple Via Models that include only capacitance, and Enhanced (Complex) Via
Models that include capacitance, inductance and resistance.
Lesson: Simulate a Scenario with User-Entered Via Models and a Physical Design
Purpose
You can create Complex via models based on the real design layer stack. Equivalent circuits for simulation are created
automatically. A PI model comprising a resistor, an inductor and two capacitors, as shown below, is created for each
layer transition.
R L
C1 C2
Steps
2. Browse to ViaPhysical\pcb\router in the Open High Speed Design dialog and open file ViaPhysical.rif.
3. Click [Edit]-[New]-[Scenario], choosing to create an Empty scenario.
4. Select your new scenario in the Tree View and click the Scenario Editor ( ) icon to open it in Scenario
Editor.
5. Click [Add]-[Symbol] in Scenario Editor.
6. Select the Complex Via ( ) symbol in the Add Symbol dialog. A Via dialog will appear.
7. Click in the Value cell in the Via Start Layer row to obtain the Select Layer dialog.
8. Select layer L1 and click OK in the Select Layers dialog.
9. Similarly, click in the Value cell in the Via End Layer row to obtain the Select Layer dialog and select layer L2.
10. Click OK in the Via dialog.
11. Choose a central position on the Scenario Editor’s canvas and place the via symbol by clicking [LMB].
Scenario Editor-21
12. Click [MMB] to stop adding via symbols.

13. Double-click on your new via symbol to obtain the Via Model Information dialog.
14. In the Via Model Information dialog, enter values as follows: C1(pF) = C2(pF) = 0.25, R(mOhm)=0.2, l(nH)=1,
remembering to use the Enter (Carriage Return) key to terminate each value entered.
15. Click OK in the Via Model Information dialog.

16. Add a driver symbol, a receiver symbol and two transmission line symbols as shown in the following diagram.
Do not connect them together yet.
17. Double-click on the driver symbol (IC1) to obtain the Model Information dialog.
18. Click on the Pin tab in the Model Information dialog.

19. Click Select Model… to obtain the Model Selection dialog.
Note: If the Model Selection dialog does not appear, please check that all Constraint Manager sub-dialogs have been
closed.
20. Select model HighSpeed_out and click OK.

Note: This is a special, very fast, linear model created for training purposes only.
21. Click OK in the Model Information dialog.
22. Double-click on the receiver symbol (IC2) to obtain the Model Information dialog.
23. Click on the Pin tab in the Model Information dialog.
24. Click Select Model… to obtain the Model Selection dialog.

25. Select model HighSpeed_in and click OK.
26. Click OK in the Model Information dialog.
27. Connect the driver and receiver to their transmission lines and finally connect from transmission line on the left
(TL1) to the via as shown in the following illustration. The Select Layer dialog appears when you click on the
via; when this happens, select layer L1 and click [OK].
Scenario Editor-22
Click
Click
28. Similarly, connect the other transmission line (TL2) to the via, this time selecting layer L2.
29. Using the same method you used earlier, add and connect a driver, receiver and two transmission lines of the
same type, but omit the via, as shown in the following illustration.
30. Click [File]-[Apply] in Scenario Editor to save your scenario.
31. Click the Simulate ( ) icon in Scenario Editor and wait for the simulation to complete.
32. In the simulation window, select the two receiver pins in the left pane and zoom in closely to the top of the
Scenario Editor-23
waveform as shown.
Note: Notice the difference between the two waveforms. The signal that passes through the via shows a
discontinuity caused when the leading edge of the signal encounters it.
Discontinuity
caused by via
33. Close the simulation window and Scenario Editor. Do not close Constraint Manager.
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Scenario Editor-24
Lesson: Extract Complex Via Models from a Physical Design
Purpose
Complex via models can be automatically extracted from the physical design. Equivalent circuits for simulation are
created. A PI model comprising a resistor, an inductor and two capacitors, as shown below, is created for each layer
transition.
R L
C1 C2
Steps
Note: Constraint Manager should still be running, with design ViaPhysical loaded, to start this lesson.
1. Click [Tools]-[Options] and select the General tab in the Options dialog. Notice that Enhanced Via Modeling
is enabled, so that you can use complex via models instead of just capacitive via models.
2. Close the [Tools]-[Options] dialog.
3. Select Enet ADDRESS:ADD[0] in the Tree View of Constraint Manager.
4. Click the Scenario Editor ( ) icon and open a scenario based on this Enet in Scenario Editor.
5. Double-click on the leftmost via ( ) symbol in Scenario Editor to open the Via Model Information dialog.
6. Select the Connections tab in the Via Model Information dialog.
Note: This dialog shows the names of connected transmission lines and the layers on which they are routed.
Scenario Editor-25
7. Select the Via Parameters tab in the Via Model Information dialog.
Note: This dialog shows the PI model element values that have been derived from physical layout.
8. Exit from all open applications.
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Scenario Editor-26
Extract Test Land Capacitance

Lesson: Extract Test Land Capacitance for Simulation
Capacitance between single-layer test lands and ground/power planes is calculated automatically using the
field solver.
Test Land
on Surface
Layer
Dielectric
CTESTLAND Material
(e.g. FR-4)
Ground or
Power Plane
Purpose
Extract the capacitance of a test land and use it in simulation.
Steps
2. Browse to test_points\pcb\router in the Open High Speed Design dialog and open file test_points.rif.
3. In Constraint Manager, select Enet SIGN7 and click the Scenario Editor ( ) icon, accepting the default
scenario name. Capacitance is calculated for the surface test land, in this case approximately 0.2pF.
Note: Test land capacitance calculations ignore capacitance between the test land and other items except for power
and ground planes. Some fringing effects are also approximated.
Scenario Editor-27
Test Land Capacitance
4. Click the Simulate ( ) icon in Scenario Editor to simulate the net including the effect of the test land
capacitance.
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Scenario Editor-28
Chapter 3 Configuration Editor

The Configuration Editor is for editing track cross-sections. You can define configurations containing one or more tracks
and solve your arrangements with a field solver to yield important signal integrity parameters including characteristic
impedance and propagation velocity. You can automatically include your results in scenarios to model single or coupled
transmission lines. The Configuration Editor is an editor for track configurations with a graphic display. A track
configuration is a cross-sectional view of one or more tracks. You can extract track configurations automatically from a
PCB design, or define your own. You can find the line parameters of the tracks, including characteristic impedance and
propagation velocity, using a built-in field solver, and use your results when simulating.
Two field solvers are used in SI Verify:
• 4_x field solver: The 4_x field solver is the default. It is used for all purposes except solution of trapezoidal
traces from the Configuration Editor.
• Fem (Finite Element) field solver: Much lower speed (order 4_x times 100, solution time increases roughly
according to the square of the number of conductors).. This is the only solver that can be used for trapezoidal
traces. If you define trapezoidal traces the finite element solver will automatically be used. In the finite element
solver, the entire cross-section is meshed to improve the accuracy of a lossy solution.
Please use only the data in ch3_ce for the lessons in this chapter. The correct file to open is not selected by
default.
Configuration Editor-1
Define and Solve Uncoupled Track Configurations

Lesson: Calculate the characteristic impedance and propagation velocity of a transmission line
Purpose
Determine transmission line characteristics for simulation.
Steps
2. Browse to ce_tra\pcb\router in the Open High Speed Design dialog and open file ce_tra.rif.
3. Select Scenario1 ( ) and invoke the Scenario Editor ( ).
Click
Click
These scenarios were created and saved in an initially-empty design
4. Double-click the transmission line to invoke the Nominal Values dialog.

(You can also do this by selecting the transmission line and clicking the Nominal Values ( ) Icon.)
Double-Click
Double-clicking the transmission line invokes the Nominal Values dialog
5. Click the Edit Config. ( ) button.
The length, velocity and impedance can be edited in this dialog
6. Click OK ( ) in the Edit Configuration window.
The Configuration Editor is for editing track cross-sections
7. Click the Dielectrics tab.
The Dielectrics tab is for editing, adding and deleting dielectric layers such as prepreg
8. Press RMB with the cursor over the Name column heading and select [Add Dielectric on Top].
Adding a new dielectric above the conductor

9. Click the Conductors tab
10. Click the and buttons next to Conductor Position. You will see the conductor embedding change.
Finish by returning the conductor to its original position.

11. Set conductor thickness 0.035 and conductor width 0.1.
The conductor thickness affects field solver results
12. Change the thickness of each dielectric layer to 0.2 as shown below.
There are now two dielectrics, each of thickness 0.2mm
13. Turn on the Top Plane check box to turn the configuration into a stripline.
14. Turn off the Top Plane check box. Click the button and select the Conductors tab in the Edit
Materials dialog; the lists of conductor materials are displayed. You can add, delete or edit materials using this
dialog.
When adding a material, please ensure the correct tab is selected, in this case Conductors
15. Click the Cancel button in the Edit Materials dialog.

16. Select the Conductors tab in the Configuration Editor.
17. Click the Material column, then click the selector button ( ) in the column
18. Click Aluminium
19. Click the Solve ( ) button; characteristic impedance and velocity are calculated.
These results show the impedance and velocity with other conductors (if any) grounded
20. Click the Extended Results… button.
You can see RLGC (resistance, inductance, conductance and capacitance) values in this dialog.
When there is just one conductor in the matrix, there is just one value for each item
21. Click OK in the Extended Results dialog.

22. Save this setting to a template by clicking the Save ( ) button and specifying the name “Sample”.
23. Click OK.
Saving the template makes it re-usable when you have the same number of conductors
24. Click OK in the Configuration Editor Window; the impedance and velocity calculated by the field solver are back-
annotated to the transmission line in Scenario Editor.
The calculated transmission line values are back-annotated to the scenario
25. Select [File]-[Close] in the Scenario Editor, choosing not to apply your edits.
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Solve Coupled Transmission Lines

Lesson: Edit the configuration for a coupled transmission line
Track configurations represent configurations of tracks with respect to dielectrics and reference (power and ground)
planes. The same configuration may occur more than once in a board layer stack: for instance, in a completely
symmetrical board with central power and ground planes and a signal layer each side of those planes, configurations on
the top board layer will be identical to configurations on the bottom layer.
You can extract these configurations from physical design data, or create your own configurations to represent proposed
arrangements. You can solve configurations with the field solver and use them in simulation.
The illustration below is a configuration for two coupled conductors above a reference plane.
Purpose
Solve to find the coupling between transmission lines for simulation.
Steps
1. Select the Scenario named “xtalk” in Constraint Manager.

2. Click the Scenario Editor Icon ( ) in Constraint Manager.
3. Double Click one of the transmission lines in the Scenario Editor.
Double-Click
The transmission lines are coupled, so selecting one also selects the other
4. A Nominal Values dialog will appear; click [Edit Config] in that dialog.
5. An Edit Configuration dialog will appear; click OK in that dialog.
6. Add a dielectric as you did in the previous lesson, setting all dielectric thicknesses to 0.2 if this value is not
already set.
7. Click the Conductors tab.

8. Set the offset and width of TL1 to 0.2 and 0.1 respectively.
9. Set both offset and width of TL2 to 0.1.
10. Set the thickness of both TL1 and TL2 to 0.017.
11. Select TL1 and twice click the button next to Conductor Position so that this conductor is on the surface as
shown in the next illustration.
Offsetting the conductors to model crosstalk on adjacent board layers
12. Click Offset for TL1 and enter 0.35
13. Click Solve to obtain field solver results for coupled conductors on adjacent board layers, noticing the higher
characteristic impedance on the conductor that is on the outer surface.
14. Close Configuration Editor and Scenario Editor. Do not close Constraint Manager.
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Trapezoidal Configurations and Lossy Simulation

Trapezoidal Traces
It can be shown by measurement that a trapezoidal shape models a PCB trace more closely than a rectangle. This effect
becomes more pronounced as the traces become narrower. You can model tracks as trapezoids when solving from the
Configuration Editor.
Nominal Trace Width (1 ounce Width of Surface Embedded into Width at Laminate Surface
copper, FR4 laminate with internal Prepreg
trace embedded into prepreg)
0.005” (0.127mm) 0.00421” (0.104mm) 0.005” (0.127mm)
0.004” (0.107mm) 0.00354” (0.090mm) 0.00424” (0.108mm)
This table shows the nearest trapezoidal approximation to track shape measured from hardware
This is the real cross-section of a 0.005” (0.127mm) nominal internal trace as shown in the preceding table, showing how
the cross-section differs from that of a rectangle. Notice the curved walls of the trace that are better approximated using
a trapezoidal rather than rectangular shape
Lesson: Create and solve a single-conductor lossy trapezoidal line
Purpose
Model the true track cross-section more closely, appreciating the differences in results.
Steps
1. Select scenario TC01_Single_Microstrip in the Tree View of Constraint Manager and click the Scenario Editor
( ) icon on the toolbar.

2. Double-click on transmission line (*TL1) in Scenario Editor and click [Edit Config…].
3. Click No when asked if you want to create a new configuration for just this line. The transmission line will be
opened in the Configuration Editor as shown.
4. Edit the Width field to value 0.127mm.
Note: We will model a 0.127mm (0.005”) internal trace for which the fabricated dimensions were shown earlier in this
chapter, to see the difference between the impedance calculated for a rectangle and the impedance calculated for a
trapezoid.
5. Click the Dielectrics tab.

6. With the cursor over the Name column header on the left, click [RMB]-[Add Dielectric on Top].
7. Click Solve to solve this configuration with the 4_x field solver to obtain a result similar to that shown in the
following illustration.
8. Click on the Type value, which is initially set to Rectangle, and select new value Trapezoid. Do not edit any
other values yet.
Note: You may have to click the field in the Type column more than once to see the available choices.
9. Click Solve again. This time you will get a popup warning in a Confirm dialog as shown. Click Yes in this
Confirm dialog and wait for the solution to complete. Notice that the characteristic impedance result has
changed by about 1Ω, reflecting the use of a different solution algorithm.
Note: The Fem (Finite Element) solver is now used automatically because your trace is defined as a trapezoid, even
though the shape is still a rectangle.
10. Edit Width2 in the Conductors tab to value 0.104mm to create a trapezoidal track then click Solve, again
answering Yes in the Confirm dialog.
Note: The impedance will increase. The trace width where it contacts the laminate is still 0.127mm as before, but now
the top of the trace that is embedded into prepreg is only 0.104mm, so the coupling to the ground plane from the edges
of the trace is slightly reduced.
11. Click OK to apply the field solution to your scenario.

12. In Scenario Editor, double-click on the driver IC1 to obtain the Model Information dialog.
13. Select the Pin tab in the Model Information dialog then click Select Model... to obtain the Model Selection
dialog.
14. Choose the fast rise time model LVT_040_S0_out in the Model Selection dialog and click OK then Click OK in
the Model Information dialog.
15. In Scenario Editor, double-click on transmission line TL1 to obtain the Nominal Values dialog.
16. Change Length to 1000 (mm), hitting Carriage Return (Enter Key) after entering the value, so that line loss will
be more obvious in simulation.
17. Click OK in the Nominal Values dialog.
18. Click [Add]-[Symbol…] to obtain the Add Symbol dialog then click on the resistor symbol to obtain the
Component dialog. enter a value of 62, hitting Carriage Return (Enter Key) after entering the value, then click OK.
19. Drag the resistor symbol, using the R key to rotate it then connect it as shown in the following illustration.
20. Add a Voltage ( ) symbol from the Add Symbol dialog, rotating and connecting it as shown in the following
illustration.
Note: Use ESC or [RMB]-[Command Cancel] to stop adding symbols.
21. Double-Click on the voltage symbol to obtain the Signal Reference List dialog then click Edit List…to obtain
the Add or Edit Signal References dialog.
22. Add a signal called “GND” with Voltage (V) of 0.0, hitting Carriage Return (<Enter> Key) after entering each
value.
23. OK this dialog then select the new signal in the Signal Reference List dialog and click OK in that dialog to
annotate the signal and voltage into the Scenario Editor.
24. Click the Simulate ( ) icon on the toolbar in Scenario Editor to confirm that you can simulate with a lossy,
trapezoidal field solution.
Receiver
showing line
Driver
loss
These results include both DC and frequency-dependent loss
25. [File]-[Close] the simulation window then [File]-[Close] Scenario Editor without applying. Do not exit from
Constraint Manager.
Note: If you later solve the same track cross-section (configuration) with the same field solver, the result will be quickly
retrieved from the cache instead of being re-solved. This function is independent of whether you save the scenario or an
edited copy of the design.
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Lesson: Create and solve a coupled lossy trapezoidal line
Purpose
Understand how trapezoidal geometries affect field solver results for coupled lines.
Steps
1. Select scenario TC06_Parallel_Stripline in the Tree View of Constraint Manager and click the Scenario Editor
( ) icon on the toolbar.

2. Double-click on either of the two transmission lines in Scenario Editor and click [Edit Config…]. Click No when
asked if you want to create a new configuration for just this line. You will see parallel rectangular conductors in
the Configuration Editor as shown in the following illustration.
3. Change Type to Trapezoid for both conductors and edit the dimensions and positions as shown in the following
illustration, then click Solve, answering Yes in the Confirm dialog. You should obtain results and extended
results similar to those shown.
4. Now assign trapezoidal shapes as shown in the following illustration. The example represents 0.127mm (0.005”)
internal traces. Solve again, noticing that both the single-ended and extended modal results have changed. The
results differ more than for the single-conductor case since the trace-to-trace coupling is affected.
Note: The results for characteristic impedance and velocity shown in the main Configuration Editor dialog are the results
with the conductor in question switching and the other conductor grounded. In the Extended Results, the Even Mode
results are for the condition where the other conductor is switching in the same direction (both High->Low or both Low-
>High) and the Odd Mode results are for the case where the other conductor is switching in the opposite direction. If
your coupled lines form a differential pair, the Differential Impedance (double the Odd Mode value) is reported in
Extended Results.
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Chapter 4 Simulation
You can simulate the following items:
• Scenarios that we saw in Chapter 2 Scenario Editor.

• Routed items in your physical design.
• Placed but un-routed items in your design based on their net topology.
This means you can comprehensively explore the effects of your actual placement and routing and proposed design
constraints.
Please use only the data in ch4_scs for the lessons in this chapter. The correct file to open is not selected by
default.
Simulation-1
Control the Simulation Window
Lesson: Start simulation
Purpose
Launch SI Verify and simulate an electrical net.
Steps
1. Open the design dr_res_rcv in SI Verify, selecting ch4_scs\dr_res_rcv\pcb\router\dr_res_rcv.rif
2. Select under
3. Click the Simulate Uncoupled Icon ( ) in the Constraint manager.
This example is a driver and receiver connected via a series resistor

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Simulation-2
Lesson: Hide and show waveforms
Purpose
Select whether or not waveforms should be displayed for individual device pins and for pins as well as chip die.
Steps
1. Select in the Simulation window.

2. Press [RMB]-[Hide Waves]. Doing this removes the pin waveform for each IC from the waveform view. Each IC
waveform is then shown only as it would be inside the device, at the die.
3. Select and hide it.
4. Select
5. Press [RMB]-[Show Waves].
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Simulation-3
Lesson: Show the Test Load waveform
Purpose
The Test Load waveform is the simulated waveform when a nominal load is being driven rather than the actual load in
the design. These nominal loads can be defined in IBIS models imported into the simulation library, or in the simulation
library itself. Load conditions normally appear in component databooks, but these are not necessarily identical to the
loads in IBIS models or in the simulation library. Delays can be measured relative the response with the Test Load so
that the additional effect of the PCB layout can be checked; this is the method used for reporting flight time.
Steps
1. Click the Diagram Options Icon ( ).

2. Select the General tab in the Diagram Options dialog.
3. Turn on the Testload Pin check box.
4. Click OK.
5. Click of
6. Click in the tree view.
7. Click in the Simulation Control Window and select black.

8. Similarly, select U2 pin 3 and assign the color blue.
9. Click U1 pin 2 with the CTRL key held down.
10. Click the Zoom Frame icon ( ), framing around the rising edge of the waveform.
The Test Load waveform (bold black) shows the response at the driver pin with a nominal load. The receiver waveform
(bold blue) shows the response at the receiver with the actual load.
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Simulation-4
Lesson: Take interactive waveform measurements (Flight time)
Purpose
Measure voltages and timing in the simulation window.
Steps
1. Select [Measure]-[Rising Edge]-[Flighttime]. Results are displayed for Shortest, Typical, Longest and
Settled. Maxima, typical and minima are analyzed based on threshold levels, but not on manufacturing or
device model variations. These values have the following meanings:
t (shortest)
t (typical)
t (longest)
• Shortest is measured from V_OmDR on the test waveform to the maximum guaranteed LOW input threshold
V_ILmax. This is the first point at the input when the signal could be interpreted as a HIGH. Please note that
where there is no defined test waveform, the unloaded waveform (the response with no load) is used in its
place for delay measurements. You can choose to display the unloaded waveform using the [View]-[Diagram
Options] dialog.
• Typical is measured from V_OmDR on the test waveform to the threshold V_ImDR. Since these are the two
general measurement points, this value represents the typical extra delay caused by interconnect.
• Longest is measured from V_OmDR on the test waveform to the input threshold V_IHmin. Since V_IHmin is
the guaranteed input high level, this value represents the latest point at which the signal could be interpreted as
a HIGH.
• Settled is measured from V_OmDR on the test waveform to the time at which the high input threshold
V_IHmin is crossed for the final time. This value is useful for data signals that are strobed by a clock signal,
because the signal must be settled by the start of the setup time.
Simulation-5
2. Un-select Pin Testload (L->H) and select instead Pin Testload (H->L) using CTRL+Click in both cases so that
U2-3 remains selected.
3. Zoom in to the falling edges of the waveforms by clicking the Zoom Frame icon ( ) on the toolbar and
selecting the area to display with the LMB.
4. Select [Measure]-[Falling Edge]-[Flighttime]. Results are displayed for Shortest, Typical, Longest and
Settled in a similar way as for the rising edge. The results are as follows:
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t (shortest)
t (typical)
t (longest)
Longest and settled flight times are identical as there are no multiple threshold crossings in this waveform
• Shortest is measured from V_OmDF on the test waveform to the minimum guaranteed HIGH input threshold
V_IHmin. This is the first point at the input when the signal could be interpreted as a LOW.
• Typical is measured from V_OmDF on the test waveform to the threshold V_ImDF. Since these are the two
general measurement points, this value represents the typical extra delay caused by interconnect.
• Longest is measured from V_OmDF on the test waveform to the input threshold V_ILmax. Since V_ILmax is
the guaranteed input low level, this value represents the latest point at which the signal could be interpreted as
a LOW.
• Settled is measured from V_OmDF on the test waveform to the time at which the low input threshold V_ILmax
is crossed for the final time.
Simulation-6
Lesson: Take interactive waveform measurements (DC Level)
Purpose
Measure DC voltages in the simulation window.
Steps
1. In Constraint Manager, select under .
2. Click the Simulate Uncoupled icon ( ) in the Constraint manager.

3. Select U2-5 in the simulation window.
4. Select [Measure]-[Extrema]. Results will appear in the Simulation Measurements pane, as shown below.
The results appear in the Simulation Measurements pane. The extrema are the highest and lowest voltage together with
the time points at which they were measured.
5. Select [Measure]-[Topline]. The result is the high level obtained after the rising edge signal has settled.
6. Select [Measure]-[Baseline]. The result is the low level obtained after the falling edge signal has settled.
7. Select [Measure]-[Risetime]. You will see the 20 percent to 80 percent rise time.
8. Select [Measure]-[Falltime]. You will see the 80 percent to 20 percent fall time.
9. Select [Edit]-[Delete All Measurements]. Measurement displays are deleted.
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Simulation-7
Lesson: Take interactive waveform measurements (Edge)
Purpose
Measure Overshoot, Undershoot, Slope, Settling time and Monotonicity in the simulation window.
Steps
1. Select [View]-[Diagram Options] and check both DC High and DC Low in the General tab, then click OK.
2. Select [Measure]-[Rising Edge]-[1st/Max Overshoot] to obtain the result shown in the picture below. The
overshoot is the voltage difference between the DC High level and the maximum voltage reached on the leading
rising edge of the signal.
The overshoot is measured relative to the DC high level
3. Select [Measure]-[Falling Edge]-[1st/Max Overshoot]. The overshoot is the voltage difference between the
DC Low level and the most negative voltage reached on the first falling edge of the signal.
4. Also try [Measure]-[Rising Edge]-[1st/Max Undershoot] and [Measure]-[Falling Edge]-[1st/Max
Undershoot]. Study and understand the diagram below.
Simulation-8
Overshoot and undershoot can be measured on both the rising and falling edge
5. Select [Measure]-[Rising Edge]-[Settling Time]. The result is the time the signal takes to settle within 10
percent of the settled high logic state.

6. Select [Measure]-[Falling Edge]-[Settling Time]. The result is the time the signal takes to settle within 10
percent of the settled low logic state.

7. Select [Measure]-[Rising Edge]-[Monotonicity]. The Simulation Measurements pane shows that the flank is
monotonic; this means that the leading edge of the signal always goes from low to high and never temporarily
changes direction during the 20% to 80% part of the transition.
Vtop
(80%)
Monotonic Non-monotonic
Vbase
(20%)
If a change of direction occurs in the Vbase to Vtop region, false switching could occur.
8. Select [Measure]-[Falling Edge]-[Monotonicity]. The Simulation Measurements pane shows that the flank is
monotonic; the measurement works in the same way as for the rising edge.
9. Select [Measure]-[Rising Edge]-[Slope]. The result is the time delay between when the voltage first crosses
the threshold VimDR and when it last leaves the threshold VIHmin. Since this is the difference between the
general measurement threshold voltage and the minimum guaranteed input high voltage, it is the difference
between the most likely and guaranteed switching points.
10. Select [Measure]-[Falling Edge]-[Slope]. The result has a similar meaning to the rising edge slope, except that
Simulation-9
the thresholds are VimDF and VILmax.

Note: Do not close the simulation window
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Simulation-10
Lesson: Use FFT (Fast Fourier Transform) Results
Purpose
Fast Fourier Transforms analyze the amplitude of current, voltage and impedance as different frequencies, producing
results similar to those of a spectrum analyzer. The FFT results can be used to determine critical frequencies for
important signals.
Steps
1. Select pin U1-6 in the Simulation Control window.
2. Select [RMB]-[Stimulus…].
3. Double Click 50MHz.
4. Click OK in the Stimulus dialog.
Double-
Click
5. Simulate the scenario using the ( ) icon on the toolbar in the Waveform Control window.
6. Click the FFT tab.

7. Select U2-5. Since the stimulus is a 50MHz signal, you will see a peak in the FFT at that frequency.
Simulation-11
Peak at 50MHz
There is a peak at the fundamental frequency of the stimulus

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Simulation-12
Lesson: Export simulation results
Purpose
Export waveforms in a form compatible with widely-available spreadsheet software. The data is exported as XML, and
can be filtered to produce CSV.
Steps
1. In the simulation window, select the Waveform tab then select [File]-[Export]. You will obtain the dialog shown
below.
Filters are provided: to yield CSV files for each electrical net, pin or die waveform
2. Tick the Keep XML File box.

3. Select XMLCSV_enet.py
4. Click the button.

5. Click the Browse button and select a folder of your choice in which you want to save the data (the desktop is
OK for this purpose).

6. Click OK in the Export dialog.
7. Browse the measurements_lesson folder that was created in the last step then open subfolder Sim1.
8. Open the .csv file Measurements_lesson.enet.csv in your spreadsheet application.
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Simulation-13
Use Parameter Sweep
Lesson: Parameter sweep for a resistor
Parameter sweep lets you see the effect of variations in passive component values or transmission line parameters, for
instance you can check the overshoot for different values of resistor.
Purpose
Select a series termination resistor value and find the line length when overshoot starts to become a problem.
Steps
1. In Constraint Manager, select under

2. Click the Simulate Uncoupled icon ( ) in the Constraint manager.
3. Select U1-2
4. Select [RMB]-[Stimulus…].
5. Make the following settings if they are not present already:
• Bit Pattern Periodic

• Duty Cycle 50%
• Initial Delay 0ns

• Frequency 10.0MHz
6. If the initial logic level of the Data waveform is high, click Invert so that it becomes low.
Simulation-14
8. Click the Simulate icon ( ) in the simulation Window.

9. Click in the tree view.
10. Click the parameter sweep icon ( ).
11. Click
12. Enter 0 for Minimum.
13. Enter 100 for Maximum.
14. Enter 21 for Variation.
15. Click
16. Click
17. Wait for the parameter sweep to complete.
st
18. Click and select 1 Overshoot - Rising Edge to obtain a result similar to
that shown in the picture below. Overshoot is minimized at about 50Ω, but of course you could decide to tolerate
some overshoot to obtain greater drive strength.
Simulation-15
The plot shows how the first overshoot changes with series resistor value
19. Click the tab.
20. Select R1 in the list.
21. Press the RMB.

22. Select Change Value…
23. Enter 51 in the Parameter Edit dialog and click OK.
24. Click the Simulate icon ( ). You will see that undershoot and overshoot are very small with this resistor value.
25. Close the simulation window using [File]-[Close].
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Simulation-16
Lesson: Parameter sweep for Transmission line
Purpose
Select a Transmission line and find the line length when overshoot starts to become a problem.
Steps
1. Select under
2. Click the Scenario Editor icon ( )

3. Select transmission line TL1 using the LMB in the Scenario Editor.
4. Click the Simulate icon ( ) in the Scenario Editor.

5. Select [Simulation]-[Parameter Sweep] and select TL1 if it is not already selected.
6. Click Next.
7. Configure the transmission line sweep as shown in the following picture.
The transmission line is swept from zero to 300mm in 31 steps
8. Click Next. A dialog will appear to show each of the transmission line lengths to be evaluated.
9. Click Start Sweep.
st
10. When the simulation has completed, select 1 Overshoot – Rising Edge. You will see a parameter sweep
result as in the picture below.
Simulation-17
Overshoot begins to rise after about 30mm transmission line length
11. Select [File]-[Exit] in the Simulation Control window.
12. Select [File]-[Close] in the Scenario Editor.

13. Select [File]-[Exit] in the Constraint Manager.
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Simulation-18
Interactive Simulation
Lesson: Interactive Simulation
Purpose
Simulate an electrical net.
Steps
1. Open the design hs_tra_routed in SI Verify, selecting ch4_scs\hs_tra_routed\pcb\router\hs_tra_routed.rif
2. Select under the branch.
3. Click the Simulate Uncoupled icon ( ) in Constraint manager.
The simulation considers the real routing, or, if only placement exists, creates transmission lines equal to the
pin-to-pin Manhattan lengths.
Simulation-19
4. Close the simulation window.
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Simulation-20
Batch Simulation
Lesson: Check the settings for batch simulation
Purpose
Select the simulation type.
Steps
1. Select [Tools]-[Options] on the menu bar of the Constraint Manager.
2. In the General tab, change the Delay Mode to Time if it is in any other mode.
3. Click the Simulation tab.
4. Change the Signal Integrity mode to Simulation in the Update area if it is in any other mode.
5. Observe the settings in the Update area that affect the behavior of Update Selected (calculated and simulated
results returned to the Constraint Manager).
• Checking Crosstalk means crosstalk will be included in spreadsheet updates. You should not select this option
unnecessarily since spreadsheet update becomes considerably slower.
• Checking Same Bus means that for bus nets, crosstalk from other nets in the same bus will be considered to
contribute to crosstalk.
• Checking Signal Integrity means that spreadsheet results other than crosstalk will be returned to the
spreadsheet when you select items and use Update Selected.
• Checking Calculation means that formulae will be used together with information generated by the field solver
to obtain results. This is the fastest method, but less accurate than simulation. Only transmission delays are
calculated in this mode, with no consideration of threshold crossings, and results are absolute rather than
relative to test load response.
6. Click on Export…
7. Select the csv (comma separated values) filter for electrical nets as shown below and tick the Keep XML File
box if it is not already ticked.
Note: this dialog allows you to filter the xml waveform output for both pin and electrical net waveforms.
Simulation-21
.csv files are suitable for reading into most spreadsheet applications
8. Click OK in this dialog.

9. Click OK in the Options dialog.
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Simulation-22
Lesson: Batch Simulation
Purpose
Obtain batch simulation results for selected enets.
Steps
1. Select under the branch.
2. Click with the shift key depressed so that -OPEN2-,-OPEN- and –RAS- are selected.
3. Click the tab.
4. Click the Update Selected ( ) Icon.
Simulation results appear for -OPEN- and -RAS- but not for -Open2- because that enet has no valid driver/receiver pairs
5. Select [Simulation]-[Update and Export] in the Constraint Manager. The spreadsheet is updated with
simulation results, and xml/csv files are generated according to the xml filter selections you made earlier. The
xml and csv files are written to folder hs_tra_routed/hotstage/data/hs_tra_routed/export.
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Simulation-23
Lesson: Coupled Simulation
Purpose
Obtain coupled simulation results for selected enets.
Steps
1. Select [Tools]-[Options] in the Constraint Manager.
2. Click the Simulation tab in the Options dialog.
3. Set the coupling rules as shown below.
This dialog lets you set the maximum coupling distance to consider.
The settings are interpreted as shown below.
Only traces whose coupled length is greater than or equal to Min Length and which are separated by no more than Max
Distance in the horizontal plane are considered. The maximum number of coupled traces to consider is specified by Max
Lines. Min Length, Max Distance and Max Lines set the coupling window for coupled simulation.
4. Click OK in the Options dialog.

5. Select E-net D00 in Constraint Manager.
6. Click the Simulate Coupled ( ) icon in the Constraint Manager.

The simulation window will appear.
Simulation-24
All drivers have the same stimulus so you cannot check crosstalk in this simulation. You need to change the stimulus of
the driver on the victim net to a constant level to assess crosstalk.
7. Press the RMB on U14-2 in the tree view of the Simulation Control Window and Select Stimulus…. The
Stimulus dialog will appear.
8. Enter ‘100’ in the Simulation Time box, terminating your entry with a carriage return.
Simulation-25
9. Change the bit pattern from Periodic to Constant Low and Click OK.
Changing the stimulus to a constant level isolates the crosstalk.
10. Click the Simulate ( ) icon in the Simulation Control window.
Simulation-26
11. Select pin U18-34 in the simulation window and zoom in on the waveform to observe crosstalk from the other
nets.
The crosstalk signal is now isolated and can be measured. You can also set the stimulus in the Constraint Manager.
12. Close the simulation windows then select [File]-[Exit] in the Constraint Manager.
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Simulation-27
Display Differential Impedance Results
Lesson: Display differential impedance results

Differential impedance represents the ideal termination value to be placed between a pair of differential lines, to
terminate the condition where the + and – lines are switching in opposite directions at exactly the same time. Differential
impedance (ZDIFF) is double the Odd Mode impedance, which is the termination value to use when terminating to a fixed
voltage from either the + or – lines as suggested by signaling specifications for technologies such as Differential SSTL
Class I, 1.5V.
+ -
ZDIFF
Purpose
Check the differential impedance.
Steps
1. Open the design DiffTrunkRouted in SI Verify, selecting ch4_scs\DIffTrunkRouted\pcb\router\DiffTrunkRouted.rif
2. In Constraint Manager, select [Tools]-[Options] and select the Simulation tab.
3. In the Options dialog, make sure that Min Length, Max Distance and Max Lines are set so as to capture
coupling within differential pair DP_P_RX27-DP_N_RX27.
Note: Max Distance is the maximum track edge-to-edge distance within which differential coupling will be
detected.
4. Click [OK] in the Options dialog.

5. In Constraint Manager, select the Impedance tab.
6. In Constraint Manager, select differential pair DP_P_RX27-DP_N_RX27 and click the Update Selected ( )
icon.
7. Check the value of Min Differential Z and Max Differential Z: differential impedance, relevant when one line is
Simulation-28
switching low to high and the other high to low. Min Common Z and Max Common Z represent Common Mode
Impedance, relevant when lines are switching in the same direction (identical noise appearing on both lines also
propagates in common mode). Min Zo and Max Zo are the single-ended impedance values.
8. Close SI Verify.
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Simulation-29
in//Die Measurements
Extended Waveform Display and Pin
Lesson: Display pin, die, test load transition and unloaded transition waveforms
Purpose
Display waveforms and measure results at both the pin and die so that packaging effects can be clearly seen.
Steps
1. Open the design routed in SI Verify, selecting ch4_scs\ routed\pcb\router\routed.rif
2. Select electrical net RD[20] in Constraint Manager.
3. Click the Simulate Uncoupled ( ) icon in Constraint Manager to start a simulation.
4. In the simulation window, use [View]-[Diagram Options…] to make settings as shown in the following
illustration then OK the dialog.
Note: These settings allow you to view test load, pin and die waveforms simultaneously.
Simulation-30
5. Adjust your view so that you can see the final part of the rising edge for the driver pin (blue in the illustration)
and die (red in the illustration) of the driver. Notice that after reflections, the waveform at the pin seems ahead of
the waveform at the die, because the reflection from the far end arrives at the pin first.
Note: For clarity, in the illustration that follows, some waveforms have been hidden by selecting their pins and using
[RMB]-[Hide Waves], and the Diagram Options have been adjusted. You also may need to adjust your colors.
Important: The buffer models for the pins used on this net have Explicit package models, meaning that the Pin and Die
Simulation-31
waveforms can be separately displayed. If a buffer model instead has an Implicit package model, then the die
waveform cannot be separately displayed. You can find out the type of package model being used by selecting the
Models tab in the Simulation Library Manager then double-clicking on the buffer model name to see its textual
description. For instance, the text for the ABT_000_SO_in model in the Base library contains the statement Package
Signal = Implicit, meaning that separate Pin and Die waveforms could not be displayed for this device.
6. Under pin U401-8 in the view in the left of the simulator window, select Pin Testload (L->H), Pin Testload (H-
>L), Pin Unloaded (L->H) and Pin Unloaded (H->L) so that each waveform in turn is highlighted.
Note: These waveforms are:
• Pin Testload (L->H): The driver low to high transition with a standard load as defined in the simulation
library.
• Pin Testload (H->L): The driver high to low transition with a standard load as defined in the simulation
library.
• Pin Unloaded (L->H): The driver low to high transition when driving an open circuit.
• Pin Unloaded (H->L): The driver high to low transition when driving an open circuit.
Note: Timing (when measured by simulation) is measured relative to the response with the test load, when such a load
is defined in the simulation library. Some IBIS models include the test load information. You can also associate a
technology with a device in the simulation library and define test load values in the technology.
7. Make sure the waveforms for pin U404-25 are displayed, then select this pin and use [Measure]-[Rising Edge]-
[First Max Overshoot] to display overshoot values at both pin and die. Take a note of the pin and die overshoot
voltages.
8. [File]-[Close] the simulation window.
Simulation-32
9. Select [Tools]-[Options] in Constraint Manager, select the Simulation tab then click [Simulator…] to obtain
the Simulator Options dialog.
10. Make settings as shown in the following illustration in the General and Batch tabs then click OK in the
Simulator Options and Options dialogs.
Note: You can choose to either measure at the first simulated pulse or at a subsequent pulse by setting
Measure at Pulse to a number greater than 1. This option is useful when there is a data preamble to allow the
signal to settle into a stable mode. In this case, please leave this setting at 1.
11. Select electrical net RD[20] in Constraint Manager and click the Update Selected ( ) icon.
st
12. Click on the Distortion tab in Constraint Manager and check the result for 1 Overshoot (Rising Edge). The
value should be the same as the Pin overshoot voltage you noted earlier.
13. Use [Simulation]-[Model Library] to launch the Simulation Library Manager at the project level.
Note: The two devices used on the net you simulated are ALVTH16374_DGG and XC9500XV. Both of these models
were derived from their IBIS definition.
14. In the Devices tab of Simulation Library Manager, double-click on ALVTH16374_DGG to get the dialog shown
in the following illustration and change SI Location and Timing Location from PIN to DIE as shown then OK the
dialog. Repeat the whole of this step for device XC9500XV.
Note: The IBIS file for this device stated that the model was defined at the pin level, as shown in the Comment pane,
and SI Location and Timing Location were automatically set to an initial value of Pin when the model was imported.
This information is not always available in IBIS models, and has to be manually defined for non-IBIS models. These
values are being set to DIE in this exercise so you can see the effect of the settings on simulator results.
Simulation-33
15. [File]-[Close] the Simulation Library Manager.

16. In Constraint Manager use [File]-[Library Reload…] to invoke the Library Reload dialog, selecting Simulation
Models Only in that dialog then click OK and wait for the library reload to take effect, acknowledging any popup
messages that appear.
17. Select electrical net RD[20] in Constraint Manager and click the Update Selected ( ) icon.
st
18. Click on the Distortion tab in Constraint Manager and check the result for 1 Overshoot (Rising Edge). The
value should be the same as the Die overshoot voltage you noted earlier.
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Simulation-34
Lesson: Display current and stimulus waveforms
Purpose
Display separate waveforms showing current and the stimulus for the simulation.
Steps
1. Select electrical net RD[20] in Constraint Manager.
2. Click the Simulate ( ) icon in Constraint Manager to start a simulation.
3. In the simulation window, use the Waveform tab of [View]-[Diagram Options…] to turn on additional diagram
Stimulus as shown in the following illustration then OK the dialog.
4. Adjust the pane sizes and select pin U401-8 in the left pane of the Simulation Window to obtain a display
similar to that shown in the following illustration, where the stimulus waveform is shown in the lower pane.
Note: This is the pure original driver stimulus as defined for the driver pin without considering any electrical effects.
Simulation-35
5. In the simulation window, use the Waveform tab of [View]-[Diagram Options…] to turn off Stimulus and turn
on Current then OK the dialog.
6. Adjust the panes as needed to get a display similar to that shown below.
Note: The Current waveform shows the current into or out of each node. As with voltage waveforms you can highlight
the pin, die, test load and unloaded waveforms by selecting the appropriate item in the left pane.
Simulation-36
7. [File]-[Close] the simulation window.
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Simulation-37
Connector Models
Lesson: Define and use connector models
Purpose
More detailed connector models allow more accurate simulation of system-level connections.
Steps
1. Start the Simulation Library Manager at the Project level using [Simulation]-[Model Library…] in Constraint
Manager then select the Models tab.
2. In Simulation Library Manager, invoke the New Model dialog using [Edit]-[New…], selecting Kind and Type
and entering Name as shown in the following illustration then click OK.
3. Now specify the lumped element values for CAi, CBi and Li as shown in the following illustration. Click Add
when you have entered the values. The values are CA1=1fF, L1=700pH, CB1=300fF (Note: femtofarads).
Note: Please be careful that the units are correct. The displayed units can change during operation and application of
entered values. You can add further elements but they are not required for this example.
Note: This model roughly represents an SMA connector.
Simulation-38
4. Select the Impedance tab to see the impedance and its phase angle at a range of frequencies then click OK to
create the model.
6. Now specify the single line values for C1, C2, Impedance, Delaytime and Linelength as shown in the following
illustration to represent a length of coaxial cable with soldered joints at each end then click OK to create the
model.
Simulation-39
8. Select the Single Pair tab and enter values as shown in the following illustration then click Calculate Single
Line… to calculate the transmission line values.
Simulation-40
9. The calculated model is now shown in the Single Line tab as shown. Click OK to commit the model to the
library.
Important Note: This is still a single-line connector model, but the line parameters have been calculated considering
internal coupling.
Simulation-41
10. [File]-[Close] the Simulation Library Manager.
11. In Constraint Manager, select routed in the Tree View on the left then [RMB]-[New]-[Scenario], selecting
Empty in the Create Scenario dialog before clicking Finish.

12. Enter a scenario name of connects in the Name dialog then click OK.
13. Select your new scenario (connects) in the Tree View then click the Scenario Editor ( ) icon.
14. Use [Add]-[Symbol…] to add three driver symbols, six transmission lines, three connector symbols and three
receiver symbols then connect them together as shown in the following illustration.
15. Use [Edit]-[Tidy] to get a neat diagram.
Simulation-42
16. Assign the connector models you have created (LUMPS_xle, TRANS_xtr, CPLTRANS_xtr) one to each of the
three connectors, working from the bottom to the top of the diagram (double-click on the connector symbol then
Select Model…as shown, then OK both dialogs.
Simulation-43
17. Starting with the connector at the bottom of the scenario diagram, and working upwards, double-click on each
connector symbol in turn and assign reference designators on both sides of each connector. The values for
each connector should be (CN1A, CN1B), (CN2A, CN2B) and (CN3A, CN3B) respectively.
18. Double-click on each driver symbol in turn, in each case selecting the Pin tab in the Model Information dialog
and using Select Model…to assign model LVT_040_S0_out.

19. Double-click on each receiver symbol in turn, in each case selecting the Pin tab in the Model Information
dialog and using Select Model…to assign model LVT_040_S0_in.
Note: This buffer type has fast rise and fall times which are better for illustrating connector model operation than default
buffers.
20. [File]-[Apply] to save your scenario.
21. Click the Simulate ( ) icon in Scenario Editor to start a simulation. Each of the three nets is simulated with a
different connector model.

22. Zoom in closely to the waveforms at each receiver pin to see the differences in the simulated response with
different connector models.

23. [File]-[Close] the simulation window and [File]-[Close] Scenario Editor. Do not exit from Constraint Manager.
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Simulation-44
Package Models
Lesson: Define package models
Purpose
You can add package models when they are not already contained in device models and you can edit package models
that were created on IBIS model import.
Steps
1. Start the Simulation Library Manager at the Project level using [Simulation]-[Model Library…] in Constraint
Manager.
2. Select the Packages tab in Simulation Library Manager.
3. Double-click on ALVTH16374_DGG_ibs, which is in the library as a result of importing an IBIS model. View the
information in the Pin Data tab
Note: For each pin there is an R, L and C value. If you change these values the new values will be used in simulation.
R L
Die Pin
Package
L R
Pin Die
Package
4. Cancel the package data dialog.
Simulation-45
Note: You can also create an entirely new package using [Edit]-[New…] as shown in the following illustration while you
have the Package tab selected in Simulation Library Manager. After you have entered the package name and number of
pins as shown in the following illustration, and clicked OK, you can double-click on the new package and add
information in the same form as seen in Step 3.
5. Select the Devices tab in Simulation Library Manager then double-click on device ALVTH16374_DGG. The
association with the package you examined is made in the Package field in the dialog.
6. Cancel this dialog and close all open applications.

0.
Simulation-46
Eye Diagrams
Eye diagrams are used to analyze jitter in high-speed channels, by superimposing an eye mask that represents the
boundaries of correct response.

A typical application of eye diagrams is to analyze the response to a defined or pseudo-random bit stream of a high-
speed differential port.
The distribution of possible responses is shown in a diagram that looks like an eye – hence the term Eye Diagram.
Jitter is defined as the deviation from the ideal timing of an event. For differential signals, as in the training example, this
deviation is measured relative to the zero differential crossing point.
You can generate jitter based on Uniform or Gaussian distribution (called Type in the dialog) and simulate the result of it.
Here are the main categories of jitter, together with the appropriate distribution for measuring it:
Deterministic Jitter is jitter due to regularly-occurring interference such as crosstalk and simultaneous switching. The
stimuli for measuring Deterministic Jitter should have a Uniform distribution.
Random Jitter is jitter due to random effects that affects reliability and therefore, unlike Deterministic Jitter, it is
unbounded. The stimuli for measuring Random Jitter should have a Gaussian distribution.
Simulation-47
mean
Peak-To-Peak
Gaussian distribution
The results of a single pulse stimulus can be different depending on the bit pattern applied as a stimulus, so the results
of “010” at the end of a sequence “0101010” can easily be different from the results at the end of the sequence
“0111010”. Eye Diagrams can be used to model a range of sequences to make sure the results of different sequences
do not close the eye too much.
Simulation-48
Lesson: Simulate jitter for a differential signal
Purpose
Create a stimulus that will be used to generate an eye diagram
Steps

2. Browse to eye\pcb\router in the Open High Speed Design dialog and open file eye.rif.
3. Select differential pair SIGN664-SIGN663 in Constraint Manager.
4. Click the Simulate Uncoupled ( ) icon in Constraint Manager to generate a simulation window.
5. In the simulation window, [Simulation]-[Eye Pattern] and select SIGN663 in the Eye Diagram dialog then click
Set Stimulus…to obtain the Stimulus dialog.
Click
Simulation-49
6. Now select each bit pattern in turn from the Bit Pattern combo box, understanding each setting with the help of
the descriptions and diagram below and adjusting the settings to see the effect.
Notes: Constant High and Constant Low are useful for isolating the effect of crosstalk. Pseudo Random bit patterns
are generated anew each time you change a setting. The 8-10 Bit pattern is optimized for hardware testing and works
together with a specified Character Word; it is a standard and that standard can be reproduced in simulation. Periodic
pulses are for simulation with repeated bit patterns. You can specify the bit pattern to repeat. You can also specify a
Custom bit pattern where you specify the bit pattern yourself.
Pseudo Random
Data sequence length

is 2Bit Order
Enable for tristate

outputs
Shows current bit position

when editing Data or
Enable sequence
Data bit Clock edges that trigger

sequence data or enable. Both
edges are used in some
DDR memory types
Automatically adjusted
for sequence length and
can be edited
A new pseudo-random sequence is generated each time you change a setting
Simulation-50
7. Set Bit Pattern to Periodic with a Data pattern of 01 and Simulation Time of 320ns, terminating your
Simulation Time entry with a carriage return.

8. Tick the Jitter Generation box so that you can edit the amount and type of jitter. Set Jitter to 10% with Type of
Uniform.
Note: This is the way to simulate jitter due to effects you cannot otherwise simulate, such as internal chip variations. The
Uniform distribution is normally used for repeatable, rather than random, effects.

10. Click Start Simulation in the Eye Diagram dialog.
11. Select the Eye Pattern tab in the simulation window, selecting differential pin pair U902-14 – U902-15 in the left-
hand pane, observing that the zero crossing point of the differential signal jitters by 10 percent of the clock Duty
Cycle.
This signal has moved out of specification due to jitter
12. In the simulation window, click [Simulation]-[Eye Pattern] again.

13. Select SIGN663 in the Eye Diagram dialog and then [Set Stimulus…].
14. Set the stimulus as shown in the following illustration, remembering to un-tick Jitter Generation.
Simulation-51
Note: With these settings we will check Inter-Symbol Interference, where the waveform for the same stimulus can
change depending on the preceding bit sequence. Inter-Symbol Interference gets worse with higher frequency.
15. Click [OK] then [Start Simulation]. When simulation is complete, view the display in the Eye Pattern tab in the
simulation window as shown, observing that the eye has started to close and some waveforms are out of
specification due to Inter-Symbol Interference.
Simulation-52
16. Set the eye diagram stimulus as shown in the next illustration, introducing 5 percent jitter with uniform probability
distribution, then OK the dialog and click Start Simulation. The expected response is shown for reference.
17. Using [View]-[Diagram Options…] create an Eye Mask as shown in the following illustration, loading the
Simulation-53
predefined mask DiffEyeMask.
Note: The inside of the Eye Mask represents the limits of correct operation, so the waveforms should not cut the Eye
Mask.
18. Click [OK] in the Diagram Options dialog so that the eye mask appears on the Eye Diagram as shown in the
following illustration.
Note: The response cuts the Eye Mask, so signal integrity needs improvement.
Simulation-54
0.
Lesson: Skip leading bits when generating an eye diagram
Purpose
You can skip some bits before simulation results are considered, to guarantee stable simulator behavior before
displaying the results. This is particularly needed if you use techniques such as AC (capacitive) series termination,
where the signal takes a several cycles to stabilize.
Steps
2. Browse to hs_tra_routed\pcb\router in the Open High Speed Design dialog and open file hs_tra_routed.rif.
3. In Constraint Manager, select Enet -BS- and click the Simulate Uncoupled ( ) icon to obtain a simulation as
shown below.
4. In the simulator window, click [View]-[Diagram Options] and select the Eye Pattern tab.
5. Tick the Show Legend box and click OK.
Simulation-55
6. In the simulator window, click the Eye Pattern ( ) icon to launch the Eye Diagram dialog and click Set
Stimulus.
7. In the Stimulus dialog, select Bit Pattern 8/10 Bit,, tick the Jitter Generation box, and select 5 % Uniform Jitter as
shown in the following screenshot.
8. Click [OK] in the Stimulus dialog.
9. Click Start Simulation in the Eye Diagram dialog.

An eye pattern with Legend will appear similar to the one shown below.
10. Press the Eye Pattern icon again, but this time set Number of leading bits to skip to 5 in the Eye Diagram
dialog.
Simulation-56
11. Click [Start Simulation] in the Eye Diagram dialog.
12. Observe that the eye diagram result looks like the one below, showing fewer waveforms as 5 of the 10 bits have
been skipped.
13. Close the simulation window. Do not close Constraint Manager.
0.
Simulation-57
Measure Directly from Waveforms
Lesson: Measure directly from waveforms
Purpose
The waveform measurement cursor automatically follows waveforms to allow very accurate measurements.
Steps
1. In Constraint Manager, select Enet -BS- and click the Simulate Uncoupled ( ) icon.
2. Select [Measure]-[Point] and measure maximum undershoot falling edge by clicking where you think that point
lies on the waveform, then move the cursor between the two waveforms, observing the resulting data values for
Time and Amplitude.
3. Select the Diagram Options ( ) icon, or click [View]-[Diagram Options])

4. Select the General tab.
5. Change from Mouse Position to Data Point.

6. Again perform a point measurement in the simulator window and observe the different behavior of the cursor
following the mouse – measurement is snapped to the waveform data points, which allows very accurate
measurement.
Simulation-58
7. Open Diagram Options again and select Graphic Point
8. Zoom in and perform point measurement along the waveform.
Important Note: The number of graphic points usually differs from the number of data points due to interpolation
between data points needed for drawing.
9. Close the simulation window but do not close Constraint Manager.
Simulation-59
Lesson: Measure directly from waveforms
Purpose
The waveform measurement cursor automatically follows waveforms to allow very accurate measurements.
Steps
1. In Constraint Manager, select Enet -BS- and click the Simulate Uncoupled ( ) icon.
2. Select [Measure]-[Point] and measure maximum undershoot falling edge by clicking where you think that
point lies on the waveform, then move the cursor between the two waveforms, observing the resulting data
values for Time and Amplitude.
3. Select the Diagram Options ( ) icon, or click [View]-[Diagram Options])

4. Select the General tab.
5. Change from Mouse Position to Data Point.
6. Again perform a point measurement in the simulator window and observe the different behavior of the cursor
following the mouse – measurement is snapped to the waveform data points, which allows very accurate
measurement.
Simulation-60
7. Open Diagram Options again and select Graphic Point
8. Zoom in and perform point measurement along the waveform.
Important Note: The number of graphic points usually differs from the number of data points due to interpolation
between data points needed for drawing.
0.
Simulation-61
ackdrilled
Simulate Backdrilled Vias
Lesson: Simulate Backdrilled Vias

Vias can be Backdrilled to reduce parasitic capacitance and inductance.
Purpose
Modify via models to consider backdrilling.
Steps
1. Open the design DiffTrunkRouted in SI Verify, selecting
ch4_scs\hs_tra_routed\pcb\router\DiffTrunkRouted.rif
2. In Constraint Manager, select [Tools]-[Options].
3. In the Options dialog, select the General tab.

4. Enable enhanced via extraction and back-drilling as shown and click [OK].
5. In Constraint Manager Tree View, select differential pair DP_P_RX27-DP_N_RX27.
Simulation-62
6. Click the Scenario Editor ( ) icon to launch Scenario Editor.
7. Double-click on one of the complex via symbols.
Note: The Via dialog, like the one below which forms part of the trunk layer change, shows only the layer span
needed to connect the transmission lines, so the extra capacitance and inductance of the back-drill part is
omitted from simulation.
8. Cancel the Via Model Information dialog and Scenario Editor. Do not close Constraint Manager.
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Simulation-63
Waveforms
Subtract W aveforms
Lesson: Subtract Waveforms
The result of subtracting one waveform from another can be displayed to allow differences to be visualized and
measured.
Purpose
Subtract the original signal from the same signal with induced crosstalk noise.
Steps
1. In Constraint Manager, select SCENARIO_SUB_WAVES and click the Scenario Editor ( ) icon.
Simulation-64
2. In Scenario Editor, click the Simulate ( ) icon.

3. In the simulation window select IC4-1, select [Measure]-[Subtract Wave], then select IC8-1. A comparison
waveform will be displayed showing the difference between the waveforms – effectively, and with slight
approximation, the difference waveform represents the induced noise when all Enets are dynamically switching.
Note: The comparison waveform is a snapshot, so it will not change dynamically when simulation results
change.
0.
Simulation-65
Mutual Inductance
Lesson: Simulate Including Effects of Mutual Inductance

Mutual inductance is supported when a SPICE subcircuit is imported but not by the Circuit Model Editor.
In SPICE, coupling is modeled by coupling coefficient K.

Lm
K=
L1 L2
Where Lm is mutual inductance between the two coils and L1 and L2 are their self inductance values.
I1 O1
I2 O2
Purpose
Simulate a scenario including mutual inductance.
Steps
1. Open the design Mutual_L in SI Verify, selecting ch4_scs\hs_tra_routed\pcb\router\Mutual_L.rif
2. In Constraint Manager, select scenario MUTUAL_IND_K_0.5 and click the Scenario Editor ( ) icon.
Simulation-66
I1 O1
I2 O2
3. In Scenario Editor, click the Simulate ( ) icon.

4. Referring to the circuit displayed in Scenario Editor, examine the driven waveform and the waveform resulting
from mutual inductance coupling.
5. In Constraint Manager, select [Simulation]-[Model Library].
6. In Simulation Library Manager, select the Models tab.

7. Double-click on MUT_IND_K_0_5_cir to examine the SPICE model that has been imported for this mutual
inductance element.
Simulation-67
0.
0.
Simulation-68
Chapter 5 Simulation Library

In order to simulate you need simulation models. The simulation library is structured to maximize productivity, having
Base, Site and Project levels. The Base library is supplied by Zuken at each release and should not be edited. You can
use the Site library as a multiple-user resource with controlled contents. The Project library resides with the design;
engineers can quickly create and use models for new components. You can import IBIS models or create your own
using well-structured library management tools. Simulation Library Manager
The Simulation Library Manager has the ability to manage, generate and import device models for signal integrity
simulation.
Please use only the data in ch5_simlib for the lessons in this chapter. The correct file to open is not selected by
default.
Simulation Library-1
Lesson: Start the Simulation Library Manager
Purpose
Manage the Site Library that can be used in multiple designs. The Base Library is supplied by Zuken at each release
and should not be modified, but you can use the Simulation Library Manager to examine its contents. You can also keep
a simulation library that is local to your design, which is useful for fast prototype modeling. You start the Simulation
Library Manager from the Constraint Manager in SI Verify.
Steps
1. Open the design dr_res_rcv in SI Verify, selecting ch5_simlib\dr_res_rcv\pcb\router\dr_res_rcv.rif.
2. Select [Simulation]-[Model Library…] in the Constraint Manager.
3. Change the library type to Base.
You can now see the Base library.
Click
Click
0.
Lesson: Start the Simulation Library Manager for the Project Library
Purpose
Manage the Project Library. The Project Library is held in the project directory (local to the design) and models in the
Project Library are used only in one design.
Steps
1. Select the Project library as shown below.
The Project Library is local to the design
0.
Use IBIS Model Files
Lesson: Import an IBIS file into the Project Library
Purpose
Import an IBIS simulation model that will be available to this design only.
Steps
1. Choose [File]-[Import IBIS] in the Simulation Library Manager;
the IBIS import window will appear.
2. Select [Options]-[Renaming] in the Import IBIS window. The Renaming options dialog will appear.
Each IBIS file has models which describe driver and receiver characteristics.
The name of each model should be unique in each IBIS file, but the IBIS format does not describe how to
manage unique model names in a library of models.
The dialog allows you to use prefix the IBIS model names so that they are unique within the model library.
3. Set the Renaming options dialog as shown below then click OK.
Using the component name as a prefix makes the model name unique
4. Select [File]-[Open] （）
5. Select the IBIS file ch5_simlib\z_risc.ibs in the File Selector. This IBIS file is within the data for Chapter 5
(ch5_simlib).
6. Click Open in the File Selector dialog. Errors and warnings are shown in the IBIS import dialog if the IBIS file
has problems.
Expand the bottom pane of the IBIS import dialog so that you can see detailed errors and warnings. You can
jump to the target line when by clicking the ERROR ( ) or WARNING ( ) button.
The IBIS errors can be selected to see where the problem is
7. Click OK in the Error dialog.

8. If necessary, expand the Parser log pane so you can see the details of the errors.
9. Click on on “(line 831 ) - Keyword Missing Ending Bracket ]

10. Add the character ‘]’ at the end of line 831 so that it reads “[Ramp]”. Errors below line 831 are caused by this
line and these errors can be solved by fixing line 831.
11. Click [File]-[Save As] （）

12. Click Save in the file selector.
13. Click Yes in the overwrite confirmation dialog. The model’s IBIS syntax is checked again when you save it.
You can see that the error is solved in the IBIS import dialog in this case.
14. Click on on “(line 428) - Pulldown Typical data is non-monotonic line”
15. Click the tab in the Import IBIS dialog
16. Select Z_RISC_OUT

17. Edit the unrealistic characteristic curve as illustrated below
You can move points by holding down the left mouse button and dragging
18. Click the tab in the Import IBIS window.
19. Select [File]-[Import to Library] （）
20. Click OK in the Import device dialog. You can choose best, typical or worst case models.
IBIS models can contain typical, best and worst case information
21. Click OK in the information dialog.
22. Choose [File]-[Close] in the IBIS import window.
Note: To import a complete device model, you need to import from the Devices tab. If you import from the Models tab,
then only the buffer models are imported. For example, a hex buffer chip has six input pins and six output pins. All the
inputs are the same type of buffer, and the same applies to the outputs, so the device has two buffer models. There are
three input pins that reference the same input buffer model, and three outputs that reference the same output buffer
model. If you import from the Models tab, then only the two buffer models are imported, not the six device pins that point
to them. If, on the other hand, you import from the Devices tab, then the complete device is imported, including the pins
and the buffer models. You can rename buffer models before they are imported to ensure that they are unique, or for
easy recognition.
0.
Lesson: Use IBIS Model Selectors
Purpose
IBIS Model Selectors exist in IBIS models where there is a choice of buffer types to be made. For instance, an FPGA
might have the possibility of using 12mA or 24mA drivers, and the choice has to be made when the model is imported,
because the model does not contain the final pin assignment. In the example used for the exercise, the Model Selector
is provided to account for variations in supply voltage.
12mA
24mA
The final pin assignment must be made when the model is imported
Steps
1. If you have not already done so, download an IBIS model that uses a model selector from the Internet for the
74AC86N. At the time of writing, you could use the Texas Instruments model of this component for this exercise.
You can navigate to this model from the Web page http://www.eigroup.org/ibis/ibis%20table/models.htm
2. Import the IBIS model as you did in the earlier lesson and click the Devices tab, choosing the DB package.
Choose the DB device. By default the first of the alternative models listed next to each pin will be selected. If you do not
specifically assign models to pins you will get a warning message to let you know which selection is being made for
model import.
3. Notice that there are buffer variants for 2.8V, 3.3V and 5.0V power supplies shown next to each input and output
pin.
4. Click on the Models tab, and click each of the buffer model types in turn to see their characteristic curves.
Buffer models are provided for three different power supply levels
5. Import the model from the Devices tab as in the earlier lesson. You will see an Import Device window telling
you that the model includes Model Selectors as shown below – click YES in this window then click OK to
confirm your selection.
6. Select [File]-[Close] in the Import IBIS window.
7. In the Simulation Library Manager, select the Devices tab and double-click on the device you have imported to
invoke a dialog for your imported device.
8. In the dialog for the device, select the Pin Data tab as shown below.
The Pin Data tab shows the initial pin model assignments. For each pin, the first listed model in the model selector has
been chosen.
9. Select the first input (type=IN) pin, and with the cursor over the selection, use [RMB]-[Select by Model] to
select the other similar inputs.
10. In the left-hand Set Active Model box, select the AC86_DB_AC86_IN_33_typ_in input model from the list
provided; this represents the 3.3V version of the input model.
11. Select the first output (type=OUT) pin, and with the cursor over the selection, use [RMB]-[Select by Model] to
select the other similar outputs.

12. In the right-hand Set Active Model box, select the AC86_DB_AC86_OUT_33_typ output model from the list
provided; this represents the 3.3V version of the output model. Note: You can change these assignments later to
see the effect of different pin models.
13. Click OK in this dialog. The importation of the device model and selection of pin models is now complete.
0.
Lesson: Set the Model ID to map to simulation models

Purpose
There are several ways to map parts and component instances to device models. One of the easiest ways is to assign
an ID to the model in the Simulation Library manager that matches the part name, or the value of the hs_model
attribute as in this lesson.
Steps
1. Click the tab in the Simulation Library Manager window.
2. Double-click the device TA030128; this invokes a dialog. Please note: this device was created when you
imported the IBIS file z_risc.ibs.
3. Click the ID cell in the dialog.
4. Enter ZS00128.
Note: The name entered here should match either the part name or the value of the HS_MODEL attribute.
5. Click OK.
Note: The next diagram shows how CADSTAR SI Verify maps parts to simulation models based on attributes. You can
also map both parts and component instances to simulation models from the Constraint Manager without the need to set
attributes.
CADSTAR Part Simulation

Attribute Library
There are several ways to assign simulation models using attributes. These methods are useful if you want to fix the
mapping to simulation models in your parts library
0.
Lesson: Add a vendor
Purpose
Device models in the simulation library are associated with Vendors, which have a 3-letter short form. If the vendor you
required is not already defined, you need to define it yourself before creating a new device model.
Steps
1. Click the tab in the Simulation Library Manager.
2. Select [Edit]-[New] from the Menu bar.
3. Enter KOA in the New vendor dialog.
4. Click OK in the New vendor dialog.
Defining a new vendor for devices in the simulation library

0.
Create a Model for a Resistor Pack
Lesson: Create a model for a resistor network (four 22Ω

Ω resistors)
Purpose
To simulate a resistor network, you need to describe its internal structure. You can model a discrete 2-pin resistor in the
same way.
Steps
1. Click the tab in the Simulation Library Manager window.
2. Select [Edit]-[New] in the Simulation Library Manager window.
3. Enter each value as shown below.
Please ensure you

have changed Type
to Resistor
Change Type to Resistor, assign the vendor, the name and ID, and the number of pins. The name and ID can be the
same.
4. Click OK in the New Device dialog.
5. Double click array_res22 in the Simulation Library Manager window. A new popup dialog will appear.
6. Click the tab in the dialog.
7. Click the Assign Structure ( ) button.

8. Click ( ) in the Assign Default Structure dialog.
9. Click Opposite for Order. This assigns the structure to be resistors between opposite pins, in this case 1-8, 2-7,
3-6 and 4-5. If we had specified the order as Successive, the resistors would have been between pins 1-2, 3-4,
5-6 and 7-8.
10. Enter 22 as the default value.
11. Click OK in the Assign Default Structure dialog.

12. Click OK in the dialog for defining the resistor pack, so that you return to the Simulation Library Manager.
0.
Model
Create a Linear Model
Lesson: Create a linear model
Purpose
Linear models are the simplest form of buffer model and they can be used where more detailed modeling information is
not available. Unlike IBIS models and nonlinear models, linear models describe inputs and outputs in a simplified way.
Most semiconductors are nonlinear, so that the ratio of voltage to current is not always the same for different values. It is
possible, however, to define an approximate model that describes the behavior sufficiently to make design decisions
without specifying the nonlinear behavior.
Steps
1. Click on the tab in the Simulation Library Manager
2. Choose [Edit]-[New] on the menu bar
3. Enter information in the New Model dialog as shown below then click on OK to invoke the dialog for defining the
model.
This dialog is for defining a buffer model that will later be associated with device pins
4. Enter information in the dialog as shown below. You can select units for the values you enter. Please check that
the units are correct.
3.3
Check units
Buffertype
Voltage
Technology Tab
Resistance Tab
Check units
Check units
Switching
Capacitance Tab Clamping Tab
The tabbed dialog has fields for entering the basic buffer characteristics, such as rise and fall time and output voltage
levels.
5. Click OK.
0.
Examine Test Load Settings
Lesson: Examine test load settings
Purpose
Test loads are the load conditions under which reference simulations can be performed. These test loads are often
contained in IBIS models, and can otherwise be specified in the simulation library as part of the Technology definition.
When you measure the signal Flight Time, either in the simulation window, or in the Constraint Manager’s spreadsheet,
the times on the simulated waveform are measured relative to the test load waveform. This means it is possible for the
measured flight times to be negative if the actual load delays the signal less than the test load.
This kind of delay value is useful to know because circuits are usually designed to operate correctly under nominal (or
test) load conditions. By knowing the difference between the actual and test load response, you will know how much
extra delay has been added by the tracking that was not accounted for by considering nominal (test) loads only.
Driver with actual load
Receiver
Driver with test load

t (shortest)
t (typical)
t (longest)
The Flight Time is measured relative to the response with the test load
Steps
1. Select the Base Library in the Library box.
2. Select the Technologies tab.
3. Double-click on LVT.
4. Observe the reference load at the bottom of the display in the General tab (V0Ref, C0Ref, R0Ref).
The reference conditions are V0Ref, C0Ref and R0Ref.
500Ω
0.0V
50pF
The reference load comprises a resistance, a capacitance and a voltage
5. Click Cancel in the Technology dialog.
6. Select the Devices tab.

7. Use [Edit]-[Search] to find the device SN74LVT16500DL, entering the name of the device in the Name field
and clicking Find. When the device is selected, click Cancel in the Find dialog. Please note that the search is
case-sensitive.
8. Double-click on device SN74LVT16500DL to invoke a dialog for the device.

9. Click on the Device Data tab and observe the Technology setting.
10. Click on the Pin Data tab and observe that you can set the technology on each pin if you wish.
11. Click Cancel in the SN74LVT16500DL window.

12. Switch to the Project library by selecting it in the Library combo box.
13. If you have not already imported an IBIS component model with reference load conditions, such as the device
model imported in lesson Use IBIS Model Selectors, then do so now.
14. Click the Models tab in the Simulation Library Manager (project).
15. Double-click on an imported output model, such as AC86_DB_AC86_OUT_33_typ_out.
16. Observe the R0ref, C0Ref and V0Ref values imported from the IBIS model. These values override any settings
at the technology level.
The reference (test) load is described by V0ref, R0ref and C0ref
17. Click OK to close this dialog.
0.
Create a Device Model
Lesson: Create a device model
Purpose
Create a model for a device, mapping the pins to buffer models that are already defined. This method of model creation
is useful if you know the logic family or other basic characteristics of the parts you need to model, but do not have an
IBIS model, and the part is not already in the library.
Steps
1. Click the tab in the Simulation Library Manager window
2. Choose [Edit]-[New] in the Simulation Library Manager window
3. Enter information shown below in the New Device dialog.
In this case, the device has 14 pins numbered from 1 to 14. You can also use alphanumeric pin naming, so that if the
highest pin number were L10, then the device would have 120 pins (A to L with numbering 1 to 10).
4. Click OK in the New Device dialog. This creates a list of pins which you then need to map to buffer models.
5. Double click the device named TEST in the Simulation Library Manager to invoke the dialog for defining the pin
mappings.
6. Click in this dialog.
7. Select all the pins that you want to map as shown below.
You can select multiple pins by pressing the CTRL key and clicking the left mouse button.
8. Change Type to OUT for all selected pins.
9. Change the output model to test_out for all selected pins.
Click
All the output models can be assigned at the same time for this device. Select test_out from the list of available models
as shown.
10. Click OK.

0.
Lesson: Export the device model into an ASCII (IXF) file
Purpose
You can export and import device models as ASCII (IXF) files if you want to copy devices between the Base, Site and
Project simulation libraries.
Steps
1. Click the Devices tab in the Simulation Library Manager.
2. Select TEST
3. Select [File]-[Export] in the Simulation Library Manager.
4. Click Browse in the Export Device dialog and browse to a folder of your choice (the desktop is OK for this
purpose).
Click
5. Enter test as the file name.

6. Click Save.
7. Click OK in the Export Device dialog.
Note: You can import selected devices and models that you export in this way into other simulation libraries – for
instance, you might be importing an Engineer’s verified Project Library models into the Site Library.
8. Click OK in the confirmation dialog.

9. Close all CADSTAR SI Verify windows.
0.
N--Port Devices to Model Passive Networks

Use N
Lesson: Create and use an N-Port device
Purpose
Create a circuit model and include it in an N_Port device. N-Port devices contain one or more circuit models. The
external nodes of the circuit models are mapped to the pins of the N-Port device model as illustrated below.
N-Port Device
N-Port N-Port
Device Pin Device Pin
External Nodes
Circuit
Model
Internally-connected
N-Port external nodes combined
Device Pin automatically to form one
node using a shortcut
Consider the example of a low-pass filter. A low-pass filter allows lower frequency sine waves to pass through
unchanged while higher frequencies are attenuated. Since digital waveforms are formed from a sum of sine waves of
different frequency, phase and amplitude, passing a digital waveform through the low-pass filter described below
increases the rise time, because some of the higher frequency sine wave components that are present in the rising and
falling edges have been attenuated.
This low-pass filter has a cutoff frequency, fco of just over 50MHz. The matching load, Zo, varies with frequency but is
stable at lower frequencies.
Steps
1. Open the design n_port in SI Verify, selecting ch5_simlib\n_port\pcb\router\n_port.rif.
2. Click [Simulation]-[Model Library] to start Simulation Library Manager.

3. In Simulation Library Manager, click the Models tab.
4. Click [Edit]-[New].
5. In the New Model dialog, select Kind Equival-Cir., Type Circuit, and enter Name lowpass_cir.
6. Click [OK] in the New Model dialog to obtain the dialog shown below.
This dialog is used for entering circuit models
7. Enter the low-pass filter circuit using the Model canvas, making sure that the component values are correct
when expressed in the units shown on the canvas. Your result should be similar to the arrangement shown
below.
Note: Enter model elements by clicking [RMB] on the faint component symbols ( ); you will
then be presented with a dialog from which you can select the passive component you want to occupy that position. You
can edit component values by clicking [LMB] on the value in the canvas, after which the value becomes editable. A
numbered node around the edge of the canvas may be designated an external node by clicking [RMB] with the cursor
positioned over the node then clicking [LMB] on [Set to External Node]. The symbol then changes from filled to unfilled.
Only external nodes become visible for use inside N-Port models, so you should designate the four numbered nodes
that form part of the circuit as external nodes.
8. Click [OK] in the Model dialog, clicking OK in the popup dialog warning you that two of the external nodes are
connected together.
Note: In this case, one of the nodes automatically becomes a shortcut. This model will contain only three external nodes
that will be available in scenarios or for using inside N-Port models.
9. Click the Devices tab.
10. Click [Edit]-[New].

11. In the New Device dialog, enter Vendor ZUKEN, name trainnp, ID trainnp, Type N-Port, Highest pin
number/name 8.
12. Click [OK] in the New Device dialog.
13. In Simulation Library Manager, double-click on the new device you have created (trainnp), to obtain the Device
dialog as shown below.
14. In the Device dialog, click the Pin Data tab.
15. Click and drag using [LMB] to select pins 1, 2 and 3 in the Pin List in the Device Dialog.
16. Click [RMB] with the cursor positioned over your selection and click Create Independent Element with the LMB
to obtain the result shown below.
17. Click the Independent Elements tab.

18. In the Model combo box, select model lowpass_cir, which you created earlier. The N-Port device pins are
automatically assigned to the external nodes in your circuit model as shown below.
Note: External node 11, 15 represents the two external circuit nodes that are connected together. You can edit the pin-
to-node assignments in this dialog.
19. Click [OK] in the Device dialog.

20. Click [File]-[Close] in Simulation Library Manager.
21. In the Constraint Manager Tree View, position the cursor over component U1, and click [RMB]-[Devices]-[Set
Device].
22. In the Device Selection dialog, select type N-Port , device trainnp and click [OK].
23. Click [OK] in the Auto generation and simulation access report dialog that pops up.
24. In Constraint Manager Tree View, select E-Net SIGN11.
25. Click the Scenario Editor ( ) icon, and OK the popup dialog that appears. You will see a topology including
the N-Port model on the Scenario Editor canvas.
Note: Scenarios containing N-Port models are not always drawn tidily; in these cases you can improve the diagram by
editing and clicking [File]-[Apply]. The transmission lines were derived from the physical routing.
26. Click the Simulate ( ) icon in Scenario Editor to obtain a result similar to that shown below.
The wave shape has been changed by the low-pass filter
Note: The low-pass filter has made the digital signal invalid. As an additional exercise, see if you can slow down the
stimulus frequency so that a valid digital signal is transmitted to the receiver.
27. Close the simulation window and Scenario Editor. Do not close Constraint Manager.
0.
IBIS Series Switch Models
Lesson: Import IBIS Series Switch Models

IBIS files can contain Series Current and Series MOSFET models. Only series switch MODELS are imported – the
devices containing them cannot be imported.
On/Off Controlled
in Data Tab of
Simulation
Window
Series switch circuit
Vg
models for use in
Vds
scenarios only
Purpose
Import and simulate an IBIS model containing series switch elements.
Steps
1. In Constraint Manager, select [Simulation]-[Model Library].
2. In Simulation Library Manager, select [File]-[Import IBIS].
3. Select [File]-[Open] in the Import IBIS dialog.

4. Open file ZukSw.ibs which is within the same folder as this design.
Note: You will receive two warnings indicating that some features are not supported. Series switches are only
supported at the model level, not the device level, so you can only use them in scenarios and in simulation
directly, not as models of devices in your design.
5. Click the Models tab, which shows the imported models plus detailed information on how they can be used.
6. Select model CH_IO_S.

7. Click [RMB]-[Search]. The view will change to the model entry for that device in the IBIS file.
Note: This kind of search also works in the Devices tab, but that is not applicable to this exercise.
8. In the Models tab, select model CH_IO_S and click the Import Selected Model ( ) icon, choosing to import a
typical model.
9. Close the Import IBIS dialog.
10. Close Simulation Library Manager.

11. In Constraint Manager, create a new, empty scenario using [Edit]-[New]-[Scenario] and click the Scenario Editor
( ) icon.
12. In Scenario Editor, add a driver ( ), a receiver ( ), two transmission lines ( ) and a 2-pin circuit
model ( ) and connect them as shown.
13. Double-click on the driver (IC1 in the diagram below) symbol and assign model LVT_040_S0_out.
14. Double-click on the driver (IC2 in the diagram below) symbol and assign model LVT_040_S0_in.
15. Double-click on the circuit model symbol.
16. In the Circuit Model tab of the Model Information dialog, click [Select Model].
17. Select model CH_IO_S_typ_ser (the one you just imported) and click [OK].
18. In the Model Information dialog, click [OK] to assign the model in Scenario Editor.
19. In Scenario Editor, click the Simulate ( ) icon. The simulator will initially show the result with the series switch
turned ON as shown.
20. In the simulation window, click the Data tab.

21. In the Data tab, select the row containing CH_IO_S_typ and [RMB]-[Toggle State], which will turn the series
switch OFF.
Notes: Extend the window to the right, and you will see the change of state appear in the Data tab. Notice also
that you can swap the two nodes of the series model for the purpose of simulation only.
22. In the simulation window, click the Simulate ( ) icon to see the result with the switch turned OFF.
23. Toggle the switch and re-simulate to observe the effect.

24. Examine the contents of the ZukSw.ibs file in Wordpad or another text editor.
Note: Voltage/current curves at various values of Vds (drain-source voltage) in the ON state are listed under
[Series MOSFET] statements. Each current in each [Series MOSFET] curve is the current at a specific gate
voltage. It is the gate voltage, Vg, that makes the switch turn ON or OFF. The action of the Enable input is not
modeled by the simulator, so switches are modeled only in constant ON or OFF states.
Voltage/current curves at various values of Vds (drain-source voltage) in the OFF state are listed under [Series
Current] statements. In this model, the switches are described as perfect insulators in the OFF state, so there is
no current at any voltage.
0.
0.
Chapter 6 Constraint Manager

The Constraint Manager is the control center for CADSTAR SI Verify, controlling analysis, simulation and presentation of
results. CADSTAR SI Verify does not constrain the physical routing and placement tools, but you can analyze your
design and check results.
Please use only the data in ch6_cm for the lessons in this chapter. The correct file to open is not selected by
default.
Constraint Manager-1
General
If you have a version of P.R.Editor in which you can set constraints, or if you have set appropriate attributes in
CADSTAR, you can check your design’s performance against constraints. The tree view (shown below) is for navigating
your design. Some ways of organizing the design, such as buses and differential pairs, are only available if you also use
P.R.Editor XR, since that tool allows you to create them.
The tree view is organized as a hierarchy for easy design navigation
Lesson: Use the tree view
Purpose
Navigate elements of your design (electrical nets, components, parts etc.).
Steps
1. Start SI Verify and load the design ch6_cm\hs_tra\pcb\router\hs_tra.rif
2. Click of in the Constraint Manager, and look at the folders that become visible.
Note: Is the top level of the design, captured in System Designer/Board Designer.
• Scenarios
Scenarios are experimental circuits that are kept separate from the design data, so that you can add or delete
transmission lines or buffers and simulate for what-if analysis.
• Stimuli
Stimuli used for simulations are held in this branch.
3. Click of to open the design data folder.
Note: The items at this level are as follows:
• Electrical Nets
All electrical nets in the design, except for defined power nets, appear in this branch. Electrical nets can contain
series components used for termination (resistors, capacitors, inductors and diodes), and thus can contain one
or more Logical nets (nets as they appear on a schematic without electrical net functionality).
• Paths
Electrical Electrical Electrical Electrical

net 1 net 2 net 3 net 4
• Busses
Busses are groups of electrical nets, differential pairs or paths that generally perform a single function, such as
address or data busses.
• Differential Pairs
Differential pairs are pairs of electrical nets that carry complementary signals and require special consideration
in routing and simulation.
• Power Nets
Power nets carry a fixed voltage and are usually identified as power nets in the schematic. Power nets should
have a ref_voltage attribute that specifies their voltage.
• Net Classes
Net classes identify types of signals and can be used to apply constraints that apply to signals of those types.
• Components
The Components branch contains all of the component instances in the design, for instance U21 and U22
might be instances of part FPGA123.
• Parts
The Parts branch contains all the parts in the design (the Components branch contains all instances of these
parts).
• Skew Groups
Skew groups are sets of pin pairs between which a skew constraint in terms of length or delay is required. For
instance, you may require a maximum difference in routed length between all microprocessor address output
pins and the address input pins on the most distant memory devices for each bit of the address.
• Relative Delay Pairs
Relative delay pairs are used where one signal requires a minimum delay with respect to another, for instance
where a clock signal should be delayed by 500ps relative to a data signal.
• Waveforms
Waveform created by the simulator can be saved for later reference.
• Boards
Boards form parts of a multi-board system. Boards other than the main design can be described by EMD
(Electrical Board Description) models.
4. Click of to make the electrical nets visible.

5. Select
6. Press the right mouse button.
7. Select [Tree]-[Expand branch]. You can now see the logical nets, pins and components. Pin pairs are pairs of
pins between which you can set length and delay constraints.
0.
Check Results Against Constraints
Lesson: Check constraints
Purpose
Understand how to check constraints in the spreadsheet.
Steps
1. Click on each of the tabs in the spreadsheet. The columns with a bold heading are results that you can get for
your design, while the columns headed by normal text are constraints that you might have set in P.R.Editor XR
2000/5000 HS (if you have it). You cannot set constraints in CADSTAR SI Verify, but you can check compliance
against constraints.
2. Select [Tools]-[Options]-[Sheet]. This dialog specifies the color coding for the background to spreadsheet cells
containing results. You can change a color by clicking on the colored square and selecting a new color.
3. Click on the Tabs and Columns button in this dialog as shown below. This operation starts a wizard for
changing tabs and their contents or adding new tabs.
You can modify existing tabs, delete them or add new ones
4. Click on Add, creating a new tab called Train.

5. Click Next then Add.
You can add constraints, results and attributes to tabs using this dialog
6. Select Settled Flight Time (Rise) and add the item to your new tab by clicking OK.
7. In the next dialog, specify the number of decimal places you wish to see in the result. In this case, zero is
appropriate as the results are in picoseconds. Click Finish then click OK in the [Tools]-[Options]-[Sheet]
dialog.
This dialog controls the number of decimal places displayed in the spreadsheet
0.
Topology Viewer
Lesson: Topology Viewer
Purpose
The Topology Viewer allows you to view topology constraints that you can set in CADSTAR. You can route according to
these constraints if you also have P.R.Editor XR 2000/5000 HS.
Steps
1. Select
2. Click the Topology Viewer icon ( ) on the toolbar.

3. The characteristic impedance, propagation delay and length of transmission lines are nominal values that you
can set in [Tools]-[Options]-[General] and are for documentation purposes only.
When you double-click a transmission line you can view its parameters
4. Observe the topology of this electrical net. The order in which the buffers, resistor and transmission lines have
been interconnected was determined by the settings of attributes pin order and pin branch. You can use the
topology viewer to visualize how high speed routing will be constrained if you use P.R.Editor XR 2000/5000 HS.
5. Select [File]-[Close] in Topology Viewer.
6. With the electrical net CLK_Zuken still selected in the tree view, click the Scenario Editor ( ) icon on the
toolbar, accepting the suggested scenario name. This will launch the Scenario Editor, giving a result like the
picture below. The results look quite similar to those you obtained using the Topology Viewer, but there is a
crucial difference: While the Topology Viewer showed you the routing constraint (instruction to P.R.Editor XR
2000/5000 HS), the Scenario Editor shows you the actual placed or routed topology derived from the physical
design.
The Scenario Editor shows you the actual physical topology
7. Select [File]-[Close] in Scenario Editor. Do not close Constraint Manager.
0.
imulation
Map to Simulati on Models
Simulation models are managed using the Simulation Library Manager. There are several ways to tell SI Verify which
model to use for parts (e.g. SN74ALVC04N) and individual component instances (e.g. U25 or R53). You can easily see
which model is assigned using the Modeling tab in the Constraint Manager.
Vendor and Device are the device vendor and name as defined in the simulation library.
Pin Model appears for active device pins, and is the name of the pin buffer model as defined in the simulation library.
Source is the simulation library (Project, Site or Base) containing the model that is being referenced.
Status indicates whether a specific (library) or default model is being used.

Part Name is the part name as defined in the Constraint Manager.
Resistance, Capacitance and Inductance are shown for discrete resistors, capacitors and inductors only.
Lesson: View device model information in Constraint Manager
Purpose
Device models are models of components and parts that are used in simulation. The Modeling tab is for seeing which
models are being used and related information.
Steps
1. Click of
2. Select
3. Click the tab. You can see assigned part and device model information in Constraint Manager, e.g.
Part Name, Vendor, Device, Source, Status.
Details of the components are visible in the spreadsheet
4. Press the LMB on under the logical net CLK_Zuken.
5. Drag the cursor to

R5-1, U5-89, U5-94, U16-36 and U17-68 will be selected. The names of the buffer models for each pin will
become visible in the spreadsheet. You may need to drag the column dividing line with the LMB to make the
modeling information fully visible.
Buffer models assignments are shown for the active component pins
0.
Lesson: Use Set Device in Constraint Manager to map to device models
Purpose
Map a specific component instance to a device model.
Steps
1. Select
2. Click the Simulate Uncoupled icon ( ) in the Constraint manager
3. Click the tab in the Simulation Control window
4. Look at the Status column in the Modeling tab of the Constraint Manager.
The Status column for U2-3 shows “Default” in this case. This means the buffer model is not defined and a
default model has been assigned automatically.
5. Click of in the Constraint Manager.
6. Click of in the Constraint Manager.

7. Click U2.
8. Press the RMB and select [Devices]-[Set Device] in the menu. The Device Selection dialog will appear. By
default, this dialog shows only devices with the same number of pins as your selection. Please note that it is
also possible to select a device with a different number of pins if you uncheck Filter by number of pins in this
dialog.
9. Click OK in the Device Selection dialog
10. Select
11. Click the Simulate Uncoupled Icon ( ) in the Constraint manager
12. Click the tab in the Simulation Control window
13. Look at the Status column. The Status column for U2-3 shows “Assigned”; this means the model is defined.
0.
Define and Assign Stimuli
Lesson: Create a Stimulus
Purpose
Create a stimulus waveform.
Steps
1. Select in the Constraint Manager.

2. Press the RMB.
3. Select [New]-[Stimulus].
4. Set Bit Pattern to Periodic, Frequency to 27MHz and Duty Cycle to 50%.
5. Enter ‘27MHz’ in the Filename column.
6. Click
7. Enter 10MHz as the frequency in the Stimulus dialog.
8. Enter ‘10MHz’ in the Filename column.
9. Click
10. Click OK in the Stimulus window.
11. Click of so that 10MHz and 27MHz stimuli are shown in the tree view.
0.
Lesson: Set stimulus
Purpose
Assign a stimulus waveform at different design levels.
Steps
1. Select
2. Click the tab.
3. Click the Stimulus column.

4. Choose 10MHz. Setting the stimulus at this level sets the default for the entire design.
Setting the stimulus in the spreadsheet with the Misc tab selected.
5. Select
6. Click the Stimulus column.
7. Choose 27MHz.
8. Click the Simulate Uncoupled Icon ( ) in the Constraint manager

and observe that the 27MHz stimulus is being used.
9. Select
10. Click the Simulate Uncoupled Icon ( ) in the Constraint Manager, observing that the 10MHz stimulus has
been inherited from the design level.
Note: You can also set stimuli at the net class and bus levels.
0.
Lesson: Switch a bidirectional pin to be a driver
Purpose
Select which bidirectional pins should be treated as drivers for the purposes of interactive simulation.
Steps
1. Select
2. Click the Simulate Uncoupled icon ( ) in the Constraint Manager.

Please note that if you do not specify which pin is driving the electrical net, one will be chosen for you.
3. Select below in Constraint Manager.

4. Click [RMB]-[Drive Electrical Net]
(the symbol for the selected driver pin will change; for instance if you select U14.-2 as the driver,
will change to )
5. Select
6. Click the Simulate Uncoupled Icon ( ) in the Constraint manager, observing that U14 pin 2 has been
selected as the driver.

0.
Export Simulation Library Data
Lesson: Export Simulation Library Data

Simulation library data can be exported for items selected within Constraint Manager, such as specific electrical nets,
parts and buses.
IXF File
Constraint Manager
Simulation
Library
Purpose
Export simulation library data required for simulation of a specific set of electrical nets, and import it for use in another
design. The process is the same for one or more other selected items.
Steps
1. Open the design hs_tra_var in SI Verify, selecting ch6_cm\hs_tra_var\pcb\router\hs_tra_var.rif
2. In Constraint Manager Tree View, select Enet CLK_Zuken.
3. In Constraint Manager, select [File]-[Export]-[Simulation Library Data].
Note: The set of models exported is much larger than the set of buffers used on this Enet, because all models
for all components on the net are exported, whether or not their pins are on the Enet.
4. Select a name and location for your exported model file and save it.
Note: The file is not actually saved until you hit [OK].
5. Open design ch6_cm\Empty\pcb\router\Empty.rif in SI Verify.

6. Select [Simulation]-[Model Library] to launch Simulation Library Manager on the design-level Project Library.
7. In Simulation Library Manager, select [File]-[Import]. Browse for, and open, the model file you saved in step 4 so
that the models are imported.
8. In the Empty design, create a new, empty scenario using [Edit]-[New]-[Scenario] and open it in Scenario Editor.
9. Create a circuit of your own choice, for instance the H_Tree shown below.
10. Double-click on the buffer symbols to assign simulation models. In the Model Information dialog, select the Pin
tab and click [Select Model] to assign a simulation model.
11. In the Model Selection dialog, use [Advanced Filter] to choose Project Library only, so that you choose only from
the buffer models you imported.
Note: Output and input models Z_RISC_OUT_typ_out and Z_RISC_IN_typ_in are compatible.
12. Simulate the result.

0.
Chapter 7 Importing and Using

Electrical Board Description (EBD)
Files
Electrical Board Descriptions (EBDs) contain equivalent circuit descriptions of printed circuit boards,
modeling only the nets that have off-board connections. When you connect an imported EBD to your board
you can simulate connections between the board and EBD, allowing you to model the behavior of
connections between multiple boards.
Please use only the data in ch7_mb for the lessons in this chapter. The correct file to open is not
selected by default.
Importing and Using EBDs-1

General
General
EBDs form part of the IBIS modeling definition, and you import EBD files using the same library
management tools that you use for component models. Once an EBD is imported, it is converted to a CBD
(CTF format) description for use within SI Verify.
EBDs are connected to the main board via System Connectors. The System Connectors of the EBD are
created automatically, but you have to create the System Connectors on the main board in the Constraint
Manager.
You can model connectors in the Simulation Library; connector models can also be used to obtain a simple
model of board-to-board cabling that can be used in simulation. Since the connector models are specified in
the Simulation Library, the EBD itself should not separately represent connectors used to attach it to the
main board; otherwise these connectors would be modeled twice.
Daughterboard Daughterboard
System
Connectors
Motherboard
You can use EBDs to model motherboard/daughterboard systems

Import an EBD
Lesson: Import an EBD
Purpose
Import an EBD into the Project Library and connect it to a design loaded into SI Verify.
Steps
1. Load the design EBD-sample into SI Verify, selecting the file ch7_mb\EBD-
Sample\pcb\router\EBD-Sample.rif.
2. Start the Project Library Manager from the Constraint Manager using [Simulation]-[Model
Library…].
3. In Simulation Library Manager, click the Vendors tab.
4. Select [Edit]-New] to add a vendor, specifying ZUKEN as the vendor name before clicking OK.
Note: Manufacturer names in imported IBIS files must match vendor names that have been defined in the
simulation library.
5. Select [File]-[Import IBIS] in the Project Library Manager. The Import IBIS dialog will appear.
6. Select [File]-[Open] in the Import IBIS dialog.
7. Use the selector to change the Files of Type field to IBIS EBD (*ebd).
8. Select zuken1.ebd (this file is in folder ch7_mb) and click Open.
Browsing for EBD files
9. Select the EBD tab in the Import IBIS dialog.

10. Select [File]-[Import to Library…], clicking Yes, Save and OK in the popup dialogs that appear.
Note: The resultant CBD file will be saved in the default location (ch7_mb\EBD-
Sample\hotstage\templates\ebd) clicking OK in any popup dialogs that appear. CBD is a general, internal
format used by SI Verify to describe boards at the interface level.

11. Select [File]-[Close] in the Import IBIS dialog.

12. Select [File]-[Close] in the Simulation Library Manager.
0.

Connect your Board to an EBD
Lesson: Connect an EBD to your board
Purpose
Select a connector and attach the EBD to your board via that connector, making pin assignments as
required.
Steps
1. Select component CN1, then use [RMB]-[Multi-Board]-[Connect] to start connecting the CBD
(converted EBD) to your board.
EBDs are connected to boards via connectors
2. Accept the default System Connector name SystemConnector1 in the Name dialog by clicking OK.
3. Select zuken1(EBD) in the Connect dialog as shown and click OK.

Note: A new board will now appear in the Tree View as shown below.
4. Open the folders beneath the System Connectors on the main board (EBD_sample1) and the
daughterboard (zuken11) as shown below.
Note: You can see that the first four pins on the main board have been connected to the first four pins on the
daughterboard.

These four pins are connected
5. Select SystemConnector1 and click [RMB]-[Multi-Board]-[Pin Mapping…].
Note: This dialog allows you to change the default connections between system connectors on the main
board and daughterboard.
6. Click Cancel in the System Connector Pin Mapping dialog.

7. Select System Electrical Net 1:EBD1.

Note: System Electrical Nets are created when you have more than one board in your system; they contain
each connected electrical net on each board in the system, but further detail is only available in the Tree
View for the electrical net on the main board, as shown below.
Main Board
Daughterboard
8. Click the Scenario Editor ( ) icon in Constraint Manager and accept the default scenario name
shown in the Name dialog by clicking OK to obtain a scenario as shown below, representing the
combined circuit on the motherboard and daughterboard, connected together by a connector.
Daughterboard
9. Simulate this electrical net using the Simulate Uncoupled ( ) icon on the toolbar in Scenario
Editor, so that the board and EBD part of the signal are simulated together.

The signal is simulated across the board-to-board connection
END OF CADSTAR SI VERIFY TRAINING

CADSTAR SI Verify Self Teach

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SI Verify with CADSTAR

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CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION,

DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS

USE OF OR INABILITY TO USE THE SI VERIFY WITH CADSTAR SELF-TEACH TUTORIAL,

WHETHER IN AN ACTION BASED ON CONTRACT OR TORT, INCLUDING NEGLIGENCE AND

POSSIBILITY OF SUCH DAMAGES.

1. Design Flow, including:

• Set up your CADSTAR design for SI Verify.

2. Scenario Editor, including:

• Create and save design scenarios for what-if analysis.

• Define configurations to represent track and board layer cross-sections.

• Get simulated waveforms.

• Interpret simulated results.

• Import IBIS models or create your own.

• Understanding the Tree View and spreadsheet.

• Viewing net topology.

• Simulating including the effects of attached boards.

Installing the Training Data

Main Changes since Previous Version

training exercises in the parts of the training manual referenced below.

window. Chapter 4 contains several simulation exercises.

Chapter 1 Design Flow

(project libraries) that are part of the design data.

SI Verify Design Data Structure

2. Invoke the Layers dialog using [Settings]-[Layers…].

GND (Not embedded)

continuous conductor sheets

6. Close the Material Details dialog by clicking Cancel.

7. Invoke the Field Solver menu using [Tools]-[Field Solver].

8. Click on the Parameters… button in this menu.

that no problem was indicated, so you can close this dialog.

you should not use directly.

Lesson: Set net classes

2. Cancel the Assignments dialog.

6. Cancel the Item Properties dialog.

Lesson: Setting net topology

pin_source=TRUE Net attribute net_topology = ordered

Net attribute net_topology = ordered

Defining differential pairs makes differential simulation easier in SI Verify.

Net attribute net_topology = ordered

topology in Chapter 6 Constraint Manager.

Swappable pin order

U7-32 U11-30 U17-24

order of the three swappable pins

Lesson: Setting attributes that affect SI Verify

CADSTAR Attribute SI Verify Constraint or Comments

pin_delay_grp Skew Group Used to specify maximum skew

2. Close the User Attributes dialog.

4. Select [Actions]-[Edit Attributes…].

6. Select net –RAS- and click OK.

8. Set net_max_stub to 25mm, net_max_length to 100mm, net_min_length to 50mm, net_max_xtalk to

100mV and char_Z to 50 on net -RAS-.

constrain the maximum difference in length between the nets.

observe the values set for the ref_voltage attribute.

14. Select [Tools]-[Options] in SI Verify and click on the General tab.

GND, VCC_+1.8V, VCC_+3.3V and VCC_+5V are listed as power nets.

Impedance constraints are set at the logical net level

23. Use [File]-[Save] in SI Verify to save your design, then [File]-[Exit].

Lesson: Run CADSTAR and SI Verify independently

To use CADSTAR and SI Verify independently on the same design.

CADSTAR when you click the telephone ( ) symbol on the toolbar.

2. Click the Simulate （）icon.

4. Change the topology to Remote Star （）and Simulate（）.

5. Change the topology to H-Tree ( ) and Simulate （）.

7. Change the topology to Star ( ) and Simulate （）.