ELE 3230

Microprocessors and Computer

Systems
Chapter 6
8284 Clock Generator
Bus Demux
Bus Cycle
(Brey: ch8; Hall: ch7)
ELE 3230 - Chapter 6 1
 8284 Clock Generator
z 8284 is an integrated circuit which generates the CLOCK,
READY and RESET signals needed in the 8088.
z Internally the 8284 consists of an oscillator circuit (which
needs an external crystal oscillator), dividers, flip-flops,
buffers and logic gates. The external crystal frequency is
divided by 3 to produce the basic clock frequency as shown
below: 10 ns Max 10 ns Max

6
+5
3.9

118.33 ns
Min
68.66 ns
1.5 Min

.6
0
-.5
200 ns Min
500 ns Max

ELE 3230 - Chapter 6 2

 8284 Clock Generator
RES D
Q RESET
X1 CK
CRYSTAL
X2 OSCILLATOR
OSC

F/C
÷3 ÷2 PCLK
SYNC SYNC
EFI
CSYNC
RDY1
CLK
AEN1

CK CK
RDY2 D Q D Q READY

AEN2 FF1 FF2

ASYNC

Internal Block Diagram of the 8284 clock generator

ELE 3230 - Chapter 6 3
8284 Clock Generator

CSYNC 1 18 Vcc
PCLK 2 17 X1
AEN1 3 16 X2
RDY1 4 15 ASYNC
8284A
READY 5 14 EFI
RDY2 6 13 F/C
AEN2 7 12 OSC
CLK 8 11 RES
GND 9 10 RESET

ELE 3230 - Chapter 6 4

 8284 Output Pins
z PCLK - peripheral clock outputs clock signal which is at half the
frequency of the main CLK output.
z CLK - clock outputs a 33% duty cycle periodic clock which runs at
one third the frequency as the EFI or crystal frequency.
z OSC - oscillator output provides a buffered periodic waveform
running at the crystal frequency. Output is suitable for driving the
EFI input of another 8284.
z RESET - generates an output suitable for the reset input of the
8088.
z READY - generates READY signal suitable for 8088 READY input.

ELE 3230 - Chapter 6 5

Relation between CLK and PCLK

OSC

CLK

PCLK

ELE 3230 - Chapter 6 6

 8284 Input Pins
z VCC, GND - power supply pins
z RDY1 and RDY2 - bus ready accepts input of the bus ready signal
z AEN1, AEN2 - address enable (qualifies RDY1 and RDY2)
z ASYNC - ready synchronization select (selects one or two stages of
synchronization for the RDY1 and RDY2 inputs
z X1, X2 - crystal inputs (for connection of external clock signal input)
z EFI - external frequency input (external clock signal input)
z CSYNC - clock synchronization used with the EFI to synchronize
the clock output in multiprocessor systems. MUST BE
GROUNDED if the crystal oscillator is used.
z F/C - frequency/crystal (selects crystal oscillator or EFI as source)
z RES - reset input (accept input from a switch for generating reset)
ELE 3230 - Chapter 6 7
 Example - A simple 8284 circuit
• The 8284 can be used simply to generated the CLOCK signal as shown below:
5V
4.7K

8088

RDY1 RDY2
EFI
CLK CLK
F/C
CSYNC
5V AEN1 READY READY
AEN2
4.7K
ASYNC RESET RESET

510 8284
X1
510 15MHz
X2 RES
5V
4.7K

100nF
Reset Switch

• If WAIT states for slow memory or IO peripherals are needed, the circuit must be
modified.
ELE 3230 - Chapter 6 8