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Department of E.C.

E ELECTRONICS-1 LABORATORY MANUAL

DADI INSTITUTE OF ENGINEERING & TECHNOLOGY POLYTECHNIC

ANAKAPALLI, VISAKHAPATNAM-531002

DEPARTMET OF E.C.E

DIPLOMA OF III-I SEMSTER (E.C.E)

ELECTRONICS-1 LABORATORY MANUAL

DADI INSTITUTE OF ENGINEERING & TECHNOLOGY


(Approved by AICTE, New Delhi & Affiliated to JNTU, SBTET, HYDERABAD)
National Highway-5, Anakapalle-531162, Visakhapatnam Dt.

Phone: 08924-221111/ 221122, e-mail: hodece@diet.edu.in

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

V-I CHARACTERISTICS OF PN JUNCTION DIODE


AIM:

To study the volt ampere characteristics of a given semiconductor diode both in


forward and reverse bias and to calculate the dynamic and static resistance of the PN
junction diode.

APPARATUS:

 DC Power supply (0-30V)


 1N4007 Semiconductor diode – 1no.
 Voltmeters: 0-1V – 1no.
0-15v – 1no.

 Ammeters: 0-100mA – 1no.


0-100uA – 1no.

 Resistors: 270Ω – 1no.


1K Ω – 1no.

 Bread board
 Connecting Wires.

THEORY:

The PN junction diode is a device with two semiconductors in physical contact,


one with excess of holes(P-type) and the other with excess of electrons (N -
type).

When the positive terminal of the battery is connected to the P type and
negative to the N type. The diode is in forward bias. Under forward bias
condition the applied positive potential repels holes which move towards the
junction and negative potential repels electrons towards the junction.
Eventually when the applied potential is more than the internal barrier
potential the depletion region and the internal barrier potential disappear and
the diode starts conducting.

When the negative terminal of the battery is connected to the P type of positive
terminal of the battery to N type, the PN junction diode is said to be in reverse
bias condition. Under the reverse bias condition holes from the P side move
towards the negative terminal of the battery and electrons from the N side are
attracted towards the positive terminal of the battery. Hence the width of
depletion layers increases and the resultant potential battier increases which
prevent the flow of majority carriers in both directions. Therefore theoretically

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

mp current flows or negligible current flows due to minority charges called


reverse saturation current in the circuit.

CIRCUIT DIAGRAM:

270ohms (0-100mA)
+ + A -
If
Vf +
A
(0-1V)
TRPS 1N4007 V
0-30V -
K

FORWARD BIAS

270ohms (0-100mA)
+ + A -
If
Vf +
A
(0-1V)
TRPS BY127 V
0-30V -
K

FORWARD BIAS

1K (0-1000uA)
A
+ + -
Ir
Vr +
K
V (0-30V)
TRPS BY127
0-30V -
A

REVERSE BIAS

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

TABULAR FORMS:

Forward bias:

VS Vf If

(Volts) (Volts) (mA)

Reverse bias:

VS Vr Ir

(Volts) (Volts) (mA)

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

PROCEDURE:

Forward Bias:

The connections are made as shown in the figure.


Vary the supply voltage gradually starting from zero increase the supply voltage
and note the voltmeter reading (V).
 For each 0.1V step in voltage note the corresponding forward current (I f) till
voltage becomes say 0.8V. Current If should not exceed 50mA in any case.
 Tabulate the result and draw V-I characteristics under forward bias condition.
Reverse Bias:

Reverse the diode which corresponds to reverse bias condition.



Measure IR (reverse saturation currents) and voltage V as the supply voltage is

varied from 0-15V in steps of 1V.
 Tabulate the results and plot the reverse bias characteristics.
 Here current will be in micro amps.
MODEL GRAPH:

I(ma)

V (volt) 0

0 V (volt) I(ma)

FORWARD BIAS REVERSE BIAS

PRECAUTIONS:

 Connections must be tight.


 Readings must be taken without parallax error.
 Operate the knobs of the RPS smoothly from one position to another.
 Current knob must always be at minimum position.
 Voltage coarse and fine knobs must be at minimum position.
RESULT:

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

V-I CHARACTERISTICS OF ZENER DIODE


AIM:

To study the V-I characteristics of Zener Diode under forward and reverse bias
conditions. To determine zener breakdown voltage in reverse bias.

APPARATUS:

 DC power Supply
 Zener diode
 0-100mA Ammeter – 1no.
 0-1V voltmeter – 1no,
 470Ω resistor – 1no.
 Bread board
 Connecting wires.
THEORY:

The operation of zener diode is some as ordinary PN function diode under


for5ward bias condition. Whereas under reverse bias condition breakdown of
the junction occurs. The breakdown voltage depends upon the amount of
doping. The sharp increasing currents under breakdown conditions are due to
following two mechanisms.

1. Avalanche breakdown - As applied reverse bias increases, the field across the
junction increases correspondingly. Thermally generated carriers while
traversing the junction acquire a amount of kinetic energy from this field and
increase their velocity. These electrons disrupt the covalent bonds by colliding
the immobile ions and create a new electron hole pair. These new carriers again
acquire sufficient energy from the field and collide with other immobile ions and
thereby creating further electron hole pairs. This process results in large
amounts of current flow at same value of reverse bias.

When the P-N regions are heavily doped, direct rupture of covalent bonds takes
place because of strong electric fields at the junction. The new electron hole
pairs so created increase the reverse current in a reverse biased PN diode. As a
result of heavy doping of P and N regions the width of depletion region becomes
very small for a voltage of 6V on less, the field across the depletion region
becomes very high )of order 107V/m) conditions suitable for zener break down.

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

CIRCUIT DIAGRAMS:

470ohms (0-100mA)
A
+ + -
If
Vf +
A
V (0-1V)
TRPS 9V1 or 6V2
0-30V -
K

FORWARD BIAS

470ohms (0-100mA)
A
+ + -
Ir
Vr +
K
V (0-10V)
TRPS 9V1 or 6V2
0-30V -
A

REVERSE BIAS

TABULAR FORM:

Forward bias:

VS (Volts) VZ (Volts) IZ (mA)

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

Reverse Bias:

VS (Volts) Vr (Volts) Ir (mA)

PROCEDURE:

Forward bias condition:

 Make the connections as shown in the figure.


 Vary the supply voltage gradually from zero initially.
 Increase the supply voltage and note the voltmeter reading (V).
 For each 0.1V step in voltage note the corresponding forward current (I R) till
voltage becomes 0.8V.
 Currents are not to exceed 50mA in any case.
 Tabulate the results and draw V-I characteristics in forward bias condition.
Reverse bias condition:

Make connections as shown in the figure.



The zener diode is now in reverse bias.

The supply voltage is increases suitably and the corresponding values of reverse

current (IR) noted.
 The results are tabulated and the graph between V and IR is drawn for reverse
bias.
MODEL GRAPHS:

I V

FORWARD BIAS REVERSE BIAS

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PREAUTIONS:

 Connections must be tight.


 Readings must be taken without parallax error.
 Operate the knobs of the RPS smoothly from one position to another.
 Current knob must always be at minimum position.
 Voltage coarse and fine knobs must be at minimum position.

RESULT:

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

ZENER DIODE VOLTAGE REGULATOR

AIM:

To verify the zener diode as a voltage regulator.

APPARATUS:

 TRPS (0-30V)
 1MZ 5.1 zener diode – 1no.
 0-10V voltmeter
 470Ω resistor – 1no.
 Decade resistance box (DRB)
 Bread board
 Connecting wires.

THEORY:

Zener diode as a voltage regulator:

From the zener characteristics, under the reverse bias condition, the voltage
across the diode remains almost constant although the current through the diode
increases. The large reverse current through the diode which results by the
application of reverse breakdown voltage is termed as zener current (Iz). The voltage
across a zener diode thus serves as a reference and the diode is used as a voltage
regulator. It is required and to provide constant voltage across load resistance R L,
whereas the input voltage may be varying over a range. As the zener diode is reversed
biased and as long as the input voltage does not fall below Vz (zener breakdown
voltage) the voltage across the diode will be constant and hence the load voltage will
also be calculated. Due to this property, zener diode acts as voltage regulators.

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

CIRCUIT DIAGRAM:

470ohms (0-100mA)
A
+ + -
Ir
Vr +
K
V (0-10V)
TRPS 9V1 or 6V2
0-30V -
A

REVERSE BIAS

PROCEDURE:

 Connect the circuit as per the circuit diagram.


 Draw a graph showing voltage and current characteristics of reverse biased
conditions.
 Now connect the decade resistance box in parallel to the zener diode in reverse
condition.
 Now, resistance across the load is varied and thus the voltages of load VL are
noted.
Then, we calculate the percentage regulation i.e. VNL – VL x 100

VL

 Then plot the graph with % regulation on y axis and RL on x axis.

TABULAR FORMS:

Zener diode characteristics as voltage regulator:

% reg = VNL – VL x 100


RL (Ω) VL (V)
VL

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

MODEL GRAPHS:

GRAPH:

Plot a graph between voltage and current to obtain the reverse biased
characteristics. Similarly, plot another graph between load resistance and %
regulation to verify zener diode as a voltage regulator.

PRECAUTIONS:

 Do not apply input voltage exceeding maximum rated input voltage.


 Avoid wrong connections.
 The readings must be taken carefully.

RESULT:

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

3 TERMINAL VOLTAGE REGULATOR


AIM:To construct a voltage regulator using IC 7812 & to determine the line regulation.

APPARATUS REQUIRED:

1 RPS (0-30V) 1
2 Voltmeter (0-15V)MC 1
3 Ammeter (0-100mA) MC 1
4 DRB - 1
5 IC 7812 1
6 Capacitor 1000μF 2
7 Bread board - 1
8 Connecting Wires - 1 set

THEORY:

Initially voltage regulator circuits were constructed using discrete components


which had the problem of unreliable operation, occupying more space, frequent
breakdown of components. Nowadays, voltage regulators are available on integrated
circuits form to avoid the above drawbacks.
IC 7805 has 3 pins. Pin 1 is input 2 output and pin 3 is ground. IC 7805 has
the output of +5V. In the same way negative voltage regulators are designed.

PROCEDURE:

LINE REGULATION:

1. Rig up the circuit as per the circuit diagram.


2. Connect the load resistance of higher wattage.
3. Vary the input DC supply in regular steps.
4. Note down the corresponding output voltage using a voltmeter.
5. Plot the graph: Vin Vs Vo

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MODEL GRAPHS:

O/p Voltage

0 I/P Voltage

TABULAR FORMS:

Line Regulation:

Input
S.No Output Voltage
Voltage

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RESULT:
Thus the voltage regulator IC 7812 was constructed & its load & line
regulation was determined.
Line regulation = -------

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HALF WAVE RECTIFIER


WITH AND WITHOUT FILTER

AIM:

To calculate ripple factor and % regulation of Half Wave Rectifier with and
without filter.

APPARATUS:

 1N4007 diode – 1no.


 (0-30V) Voltmeter – 1no.
 1000uF capacitor – 1no.
 230V/12v, 1A step down transformer – 1no.
 Decade Resistance Box – 1no
 CRO & CRO probe
 Bread board
 Connecting Wires

THEORY:

A rectifier is defined as an electronic device used for converting ac voltage or


current into unidirectional voltage or current. For this purpose a unidirectional
conduction device such as PN diode is used. A half wave rectifier is one which
converts ac current into a pulsating voltage using only one half cycle of the
applied ac voltage. The ac voltage to the rectified is applied to a single diode
connected in series with the load resistor RL. The ac voltage applied is the
output of step down transformer. For the positive half cycle of the input ac
voltage the diode D is forward biased and hence it conducts. Now a current
flows in the circuit and there is a drop across load resistance RL. This
constitutes the output voltage. For the negative half cycle, the diode D is reverse
biased and hence it does not conduct. Now no current flows in the circuit and
no power is delivered to the load.

The output of the rectifier is not pure dc but pulsating d. In order to change
into pure dc a filter i.e. a capacitor in parallel with load resistance RL is used.

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CIRCUIT DIAGRAMS:

Without filter:

WITHOUT FILTER
A K

1N4007

1 T1 5 +
230V,50Hz RL VL
Vo(CRO)
AC I/P 4 8 0-30V -

STEPDOWN TRANSFORMER
(230V/12V,1A)

With filter:

WITH FILTER
A K

1N4007

1 T1 5 +
230V,50Hz RL VL
Vo(CRO)
C(1000uF)
AC I/P 4 8 0-30V -

STEPDOWN TRANSFORMER
(230V/12V,1A)

TABULAR FORMS:

Without filter: VNL = ------

RL(Ω) VL(V) Vm(V)  % regulation

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With filter: VNL = ------

RL(Ω) VL(V) Vm(V) Vr(V)  % regulation

PROCEDURE:

Without filter:

 The circuit for the half wave is as shown in the figure.


 The ac input of 230V, 50Hz is applied to the rectifier after stepping it down
through step down transformer to 12V,1A.
 This voltage after stepping down and applied to the rectifier be Vm.
 Note the no load voltage across points A and B without load resistance. Let this
be VNL.
 Now load resistance is connected and adjusted to 10KΩ initially load resistance
is varied in steps of 1KΩ and corresponding values of Vm and voltage across
load resistance VL are noted. The output voltage can be seen in the CRO by
applying it as input signal.

With filter:

 The capacitor is used as filler.


 It is connected in parallel across the resistor.
 The same procedure used in without filter is again repeated here.
 The no load voltage is noted.
 Load resistance RL is varied in steps of 1KΩ starting from 10KΩ.
 Corresponding values of Vm and VL are noted and the output is applied to the
CRO to see the waveforms.

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MODEL GRAPH:

WAVEFORMS:

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PRECAUTIONS:

 Connections must be tight.


 Readings must b e taken without parallax error.
 Load resistance must not be kept zero.

RESULT:

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FULL WAVE RECTIFIER


WITH AND WITHOUT FILTER

AIM:

To calculate ripple factor and % regulation of Full Wave Rectifier with and
without filter.

APPARATUS:

 1N4007 diode – 2no.


 (0-30V) Voltmeter – 1no.
 1000uF capacitor – 1no.
 (12-0-12V) center tapped step down transformer – 1no.
 Decade Resistance Box – 1no
 CRO & CRO probe
 Bread board
 Connecting Wires
THEORY:

In full wave rectifier two diodes are used which share the input alternately for
positive and negative half cycles.

When input ac is switched on the extreme ends of the secondary are positive
and negative alternately. During positive half cycle the terminal M is at positive,
the center tapped position is at zero and N is at negative potentials. Now diode
D1 is forward biased i.e. it conducts current causing voltage drop across RL.
But diode D2 is reverse bias so it remains non conducting. During the negative
half cycle, terminal N becomes positive, G is at zero potential and M is at
negative potential. During this cycle diode D2 is forward biased and conducts
current causing voltage drop across RL. In this cycle diode D 1 does not conduct
because it s reverse biased. Thus current flows in the resistor for both the
cycles in the same direction. The output voltage is of twice the input frequency.
To purify the output to pure dc a capacitor filter is used.

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

CIRCUIT DIAGRAMS:

Without filter:

WITHOUT FILTER

1N4007
D1
+
1 T2 5
230V,50Hz RL VL Vo(CRO)
AC I/P 0-30V
4 8

D2 -

CENTRE TAPSTEPDOWN 1N4007


TRANSFORMER
(12-0-12,1A)

With filter:

WITH FILTER

1N4007
D1
+
1 T2 5 1000uF
230V,50Hz RL VL Vo(CRO)
AC I/P C - 0-30V
4 8

D2

CENTRE TAPSTEPDOWN 1N4007


TRANSFORMER
(12-0-12,1A)

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

TABULAR FORMS:

Without filter: VNL = ------

RL(Ω) VL(V) Vm(V)  % regulation

With filter: VNL = ------

RL(Ω) VL(V) Vm(V) Vr(V)  % regulation

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

WAVE FORMS:

MODEL GRAPH:

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PROCEDURE:

Without filter:

 The circuit for full wave rectifier is as shown in the figure.


 The ac input voltage of 230V; 50Hz is applied to the step down transformer
which gives 12V as input to the rectifier.
 This input voltage to the rectifier is Vm.
 Note the no load voltage after removing the load resistance.
 This is denoted as VNL.
 Ad resistance is connected and adjusted to 10KΩ initially.
 Load resistance is varied in s steps of 1KΩ and corresponding values of Vm and
voltage across load resistance VL are noted.
 The output voltage can be seen in the CRO by applying it as input signal.

With filter:

 The capacitor is used as a filter.


 It is connected across resistor in parallel.
 The same procedure as in without filter is repeated.
 The no load voltage is noted.
 Load resistance RL is varied in steps of 1KΩ starting from 10KΩ.
 Corresponding values of Vm and VL are noted and the output waveform is seen
in the CRO.

PRECAUTIONS:

 Connections must be tight.


 Readings must be taken without parallax error.
 Load resistance must not be kept zero.

RESULT:

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

COMMON EMITTER CONFIGURATION


AIM:

To obtain input and output characteristics of a BJT in common emitter


configuration.

APPARATUS:

 BC 107 transistor – 1no.


 (0-30V) TRPS
 Resistors: 300KΩ – 1no.
1KΩ – 1no.

 Ammeters: 0-100uA – 1no.


0-100mA – 1no.

 Voltmeters: 0-1V -1no.


0-30V – 1no.

 Bread board
 Connecting wires

THEORY:

In common emitter configuration, the input signal is applied between base and
emitter and the output is taken from collector and emitter. An emitter is
common to input and output, hence the name is common emitter configuration.

The battery VBB supplies forward bias to emitter base junction through the
potential divider R1. The voltmeter V1 measures the base emitter voltage VBE.
The micro ammeter measures the base current IB. The battery VCC is connected
between collector and emitter through the potential divider RL such that the
collector is in reverse bias. The voltmeter measure the collector emitter voltage
VCE and milli ammeter measures the collector current IC.

Input characteristics:

The curve between base current IB and base emitter voltage VBE at constant
emitter voltage VCE represents the input characteristics. For plotting this VCE is
kept constant. The base emitter voltage VBE is varied with the help of potential
divider R1 and the base current IB is for each value of VBE is plotted. The graph
characteristic resembles that of a forward bias of a diode because the base
emitter section is forward bias. IB increases less rapidly with VBE which shows
that input resistance is higher.

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Output characteristics:

The curve between collector current IC and collector emitter voltage VCE at
constant base current IB represents output characteristic. For plotting this IB is
kept fixed with the help of potential divider R2 the value of VCE is varied in steps
and corresponding collector current IC is noted. In this configuration the
current gain is greater than unity.

CIRCUIT DIAGRAM:

0-100mA
- + +
C IC

2
300K 0-100uA
B RC 1K
1 Bc107
+ + -
RB IB
E
VBE + VCC
3

+
0-30V VCE
0-1V VBE 0-30V
- -
0-30V

- -

TABULAR FORM:

Input characteristics:

VCE = 5V VCE = 5V

VBE (V) IB (uA) VBE (V) IB (uA)

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Output characteristics:

IB = 20uA IB = 20uA

VCE (V) IC (mA) VCE (V) IC (mA)

PROCEDURE:

Input characteristics:

 The connections are made as shown in the figure.


 Output voltage VCE is kept constant at suitable values 5V and 10V.
 The input voltage VBE is varied.
 Input current IB is noted for corresponding values of VBE.
 The same is repeated for other value of VCE (10V)
 The graph is drawn between VBE (x-axis) and IB (y-axis).
Output characteristics:

 The circuit is unchanged.


 Base current IB is kept constant at a suitable value (20uA).
 Output voltage VCE is varied.
 Corresponding values of IC are noted.
 The same is repeated with another value of IB (40uA).
 The values are tabulated.
 Graph is drawn between VCE (x-axis) and IC (y-axis).

MODEL GRAPH:

Input characteristics Output characteristics

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PRECAUTIONS:

 Connections must be tight.


 Readings must be taken without parallax error.
 The current knob in the RPS must be in maximum position.

RESULT:

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COMMON BASE CONFIGURATION


INPUT AND OUTPUT CHARACTERISTICS

AIM:

To obtain input and output characteristics of a BJT in common base


configuration.

APPARATUS:

 BC 107 transistor – 1no.


 TRPS
 Voltmeters: 0-1v – 1no.
0-20V – 1no.

 0-100mA ammeter – 2no.s


 1KΩ resistor – 2no.s
 Bread board
 Connecting wires.
THEORY:

In common base configuration the input signal is applied between emitter and
base while the output is taken from collector and base. A base is common to
input and output circuits. Hence the name is common base configuration.

The battery VEE supplies forward bias to emitter base junction and VCC
provides reverse bias to collector base junction. The emitter to base voltage V EB
and emitter current IE correspond to input circuit while collector to base voltage
VCB and collector current IC correspond to output circuit. The complete electrical
behavior of the transistor described by relationship between different dc
currents and voltages can be obtained by the two graphs input and output
characteristics.

Input characteristics:

The curve between emitter current IE and emitter base voltage VBE at constant
collector base voltage VCB represents the input characteristics. When VCB is
equal to zero the emitter base junction behaves as a forward biased diode i.e.
the emitter current IE increases rapidly with a small increase in VEB after cut in
voltage. When VCC value is fixed at higher value (say 10V) base width decreases
IE increases and the curve shifts towards the left.

Output characteristics:

The curve between collector current IC and collector to base voltage VCB at
constant emitter current IE represent output characteristics for constant value
of IE , IC is independent of VCB and the curve is parallel to VCB axis. An emitter

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base junction is forward biased electrons are injected into base region. Due to
the action of internal potential barrier at reverse biased collector base junction
electrons flow to collector region and give rise to IC even when VCB is zero. For
higher values of IE, IC value increases.

CIRCUIT DIAGRAM:

(0-100mA) BC107 (0-100mA)


1K E C 1K
- + - +
- +
IE IC
- B - VCC
VEE
VEB(0-1V)
VCB(0-30V)
+ + (0-30V)
(0-30V)

+ -

TABULAR FORM:

Input characteristics:

VCB = 0V VCB = 5V

VEB (V) IE (mA) VEB (V) IE (mA)

Output characteristics:

IE = 5mA IE = 10mA

VCB (V) IC (mA) VCB (V) IC (mA)

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PROCEDURE:

Input characteristics:

 The connections are made as shown in the figure.


 The input voltage VEB is kept constant at a suitable value (0V).
 The input voltage VEB is varied in steps of 0.05 and corresponding input current
values of IE are noted.
 The experiment is repeated for different constant values of output voltage VCB.
 The results are tabulated and graph between IE and VEB are drawn taking IE on
y-axis and VEB on x-axis.
Output characteristics:

The same circuit in input characteristics is used.


The input current IE is kept constant at a suitable value.
The output voltage is varied in steps of 1V and corresponding values of output
current are noted.
 The experiment is repeated for different values of input current IE.
 The results are tabulated and the graph between IC and VCB is drawn taking IC
on y-axis and VCE on x-axis.
MODEL GRAPH:

I(ma) I(ma)

V V

Input characteristics Output characteristics

PRECAUTIONS:

 Connections must be tight.


 Readings must be taken without parallax error.
 The current knob in the RPS must be in maximum position.

RESULT:

Dadi institute of Engineering and Technology Page 32


Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

FET CHARACTERISTICS
AIM:

To obtain drain and transfer characteristics ofa Field Effect Transistor and to
calculate amplification factor.

APPARATUS:

 BFW 10 FET – 1no.


 0-100mA ammeter – 1no.
 Voltmeters: 0-10V – 1n0.
0-30V – 1n0.

 1KΩ resistor – 1no.


 Dual RPS (0-30V) – 1no.
 Bread board
 Connecting wires

THEORY:

FET is a unipolar device depending upon only majority carriers. FET has input
resistance in order of 100MΩ. FET is less noisy than tube on bipolar transistor.
FET is relatively less affected by radiation. It has high thermal stability and
high power gain.

Construction:

Generally N channel FET is preferred. A narrow bar of N type semiconductor is


taken. Now on opposite sides of its middle part, two heavily doped P-type
regions are formed by diffusion. The junctions form two PN diodes or gates.
They are between the gates in channel. There are 3 terminals for a FET. Those
are Gate, Source and Drain.

The source is a terminal through which the majority carriers enter the bar.
Drain is a terminal through which majority carriers leave the bar. Gates are two
internally connected heavily doped impurity regions which form PN junctions.

Working:

Let us first suppose that the gate has been reverse biased by gate battery VGG
and the drain battery VDD is not connected. Now depletion region located
symmetrically about the gates are form. Further consider VDD while VGG is
removed. The voltage VD is dropped across the N channel resistance giving rise
to drain current ID. Due to this current there will be uniform voltage doing while
going from source to drain. So due to progressive voltage drop along the length
of the channel, reverse biasing effect on PN junction is stronger near the drain

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

than that near source, so depletion region penetrates more at that region. When
depletion region touch each other and drain current become zero. Since
negative gate voltage controls the drain current, FET is voltage controlled
device.

Drain characteristics:

The curves between drain current ID and drain to source voltage VDS for
different values of gate to source voltage VGS.

Transfer characteristics:

The curves between drain current ID and gate to source voltage VGS for different
values of drain to source voltage VDS.

CIRCUIT DIAGRAM:

0-100mA
+ -
+
ID
R 1k
D
+ VDS
G
BFW 10
+
- 0-30V VDD
VGG + S
VGS
0-30V
0-10V
0-30V -

- -

TABULAR FORM:

Drain characteristics:

VGS = 0V VGS = -1V

VDS (V) ID (mA) VDS (V) ID (mA)

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

Output characteristics:

VDS = 1V VDS = 2V

VGS (V) ID (mA) VGS (V) ID (mA)

MODEL GRAPH:

Drain characteristics Transfer characteristics

PROCEDURE:

Drain characteristics:

 The circuit is connected as shown in figure.


 Gate to source voltage is kept constant.
 Drain to source voltage VDS is change and corresponding values of ID are noted.
 This is repeated for two different values of VGS 0V and 1V.
 Tabular forms are made and graphs are drawn between ID and VDS.

Transfer characteristics:

 Drain to source voltage VDS is kept constant.


 Gate to source voltage VGS is changed and corresponding ID values are noted.

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Department of E.C.E ELECTRONICS-1 LABORATORY MANUAL

 This is repeated for two different values of VDS 1V and 2V.


 Tabular forms are made and graphs are drawn between ID and VGS.

PRECAUTIONS:

 Connections must be tight.


 Readings must be taken without parallax error.
 The current knob in the RPS must be in maximum position.

RESULT:

Dadi institute of Engineering and Technology Page 36

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