Memory in digital

circuits
 Digital Memory
• Memory enables making intelligent systems – no memory is a dumb system
• Concept of memory is fundamental to von Neumann's stored program concept of
information processing
• During data processing CPU reads and writes data to memory
• A memory unit is a collection of cells capable of storing a large quantity of binary
information

• Two types of memory - random access

Input Output
memory (RAM) or read only memory (ROM) Memory
• RAM – both read and write possible and is non
unit unit
permanent
• ROM – only read and is pre-programmed
(permanent)
• ROM also can be programmed called Processor
programmable logic device (PLD)
• To program a device means writing bits of
information in the device hardware Input lines connected
(gates/transistors) to gate through
• When we program a device certain electrical Array logic gate internal fuses
fuses are blown to connect or disconnect
available gates in the H/W to obtain desired
logic function

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 Static random access memory (SRAM)
• A FF is 1 bit memory, collection of FF together is called register which stores a string of
bits or word (4 bit, 8bit, 16 bit words etc.. )
• Each memory has a physical location on chip having an address
• Memory is accessed by reading or writing a word in a location specified by address.
• Read operation is non-destructive
• Contents of memory does not change ( latch action), as long as it is powered
• Memory size given by (number of word x word width) ie 4x4, 512x8 or 1MB (B: 8bits)
• To uniquely specify address of all word
location for M word memory k address (2k 
M) inputs are needed
• Any address location can be accessed
randomly with same delay time – hence
called random access

Also input called

data bus
Also called
address
bus

1024x16 memory
Also called
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output dataDr.bus
SanjeeV Manhas, E&CE IIT Roorkee
 Read/write operations
To store new word into memory
1. Transfer the binary address of the desired word to the address lines
2. Apply data bits that must be stored in memory to the data input lines
3. Activate the write input

To read a word from memory

• Transfer the binary address of the desired word to the address lines
• Activate the read input

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 Timing waveforms for r/w
A controller in external device such
as CPU controls the operation of
memory unit

Access time of memory is the time

required to select and read a word
Cycle time of memory is the time
required to complete a write operation

Eg if clock time of CPU is 20ns and

max access and cycle time of memory
is 50ns

Control signals memory enable and

read/write are enabled after data in
address line becomes stable
Address data should be present
during entire cycle of read/write
operation

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 Memory types – SRAM
• SRAM cell uses 6 transistors in cross coupled pair of inverters and a pair of access
transistors
• Bit line is asserted to read and write data through access transistors
• Complementary data lines are used for performing read/write operation
• Column driver use powerful transistors (high drive current i.e. large width, W) to
force set the state during write operation

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 Bitable state

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 SRAM memory Array 4x4
Use trigate to enable read
r/w’=1, and write r/w’ =0.
Trigate can be transmission
gate

2x4 decoder
selects word (4 bit
wide) location

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 SRAM alternative representation with DD FFs

Word lines` Bit lines

Array logic OR gates (ie having multi-

inputs originating from outputs of cells in a
column)
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 Two-dimentional decoding
• In general a decoder has k
inputs and 2k outputs having 2k Two-
AND gates with each gate dimentional 1K
having k inputs word memory
• Digital gates with large number
of inputs (~ more than 5) are
very difficult to design due to
mismatch in rise and fall time
and noise margins for different
input combinations
• Number of inputs can be
reduced by two dimensional
address selection scheme by
using two k/2 inputs decoders

• Each word in memory array is selected by

intersection of outputs of two 5x32 decoder with
each decoder having 32 AND gates with 5 inputs
• A single decoder would have needed 1024 AND
gates with 10 inputs
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 Computer mother board

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 Dynamic random access memory (DRAM)
1. DRAM use 1T (Transistor) memory cells
and significantly reduce number of
transistor (hence chip size) needed to
store 1 bit (6 for SRAM) of information
2. Using DRAM memory more bits can be
stored in a single chip (6x SRAM)
3. A 1 bit DRAM cell has pass/access
transistor and capacitor
4. Capacitor stores memory bit in the form
of charge (and voltage V = Q/C)
5. Remember capacitor is energy storage
device (To have memory is thus ability to
do work, and hence memory can be
interpreted as a form of energy)
6. Reading the DRAM cell destroys the
contents of memory and needs to be
written back after a read
7. Stored charge (ie the stored bit) leaks
away from the cell in about few 100s of
ns and thus requires periodic refreshing
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of its memory contents
8. Like SRAM cells, DRAM cells are laid out
on the surface of a chip
9. Since stored charge is very small it
needs very sensitive (unlike SRAM)
sense amplifier which makes read
process it slow
10. Needs more time (10x) to read the
memory as compared SRAM
11. In computers main system memory is in
DRAM chips on the motherboard, while
registers and cache memory in
microprocessor is implemented in SRAM
cells
12. Thus speed of computers is also function
memory speed
 Addressing DRAM memory
1. DRAM chips reduce number of address
pins by dividing address into two parts – 6. Row address strobe (RAS) and column
also called address multiplexing
2. Row address – determines which row in
2D array is selected
3. Column address – selects one or more
bits in row
4. Column address can be given after row
address without slowing down memory
access
5. Allows same address pins to supply row
and column address
address strobe (CAS) used to load row
and column addresses into on-chip
registers
7. Refresh circuitry periodically read each
row in memory array and writes back the
same data (since in DRAM read is
destructive)
8. Refresh circuitry is in-build in DRAM
memory chips

256x256 DRAM array address multiplexing

1. 8-bit address is supplied into address pins and
RAS goes low storing address in row address
register
2. After a settling time RAS goes high, and column
address applied to input pins is shifted to column
address register by CAS going low
3. Row and column decoders then select a particular
memory cell
4. r/w operation can be performed on selected
cell/rows of cells
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Types
Read Only Memory (ROM)
• ROM - Read Only Memory
• PROM - Programmable Read Only Memory
• EPROM - Erasable Programmable Read Only Memory
• EEPROM - Electrically Erasable Programmable Read Only Memory Each intersection of
• Flash EEPROM memory (your pen drives, most popular today) row and column is 1
bit cell
Basic ROM concept
1. Non-volatile memory – uses no storage
elements like SRAM or DRAM hence need
no power to retain the memory
2. Data stored in these chips is either
unchangeable or requires a special
operation to change

Row address Output data (D2D1D0)

A0 111 So called permanently
A1 101 programmed hard wired
A2 110 memory

3x3
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 Programmable ROM - PROM
• PROM chips have a grid of columns and rows
just as ordinary ROMs
• But intersection of a column and row in a
PROM chip has a fuse connecting them
• The initial (blank) state of a PROM chip is 1s
for all address outputs
• A device called programmer can be used to
send a specific amount of current to the cell fuses
to burn the fuse hence disconnect row and
column setting it to 0

Address Initial state (D2D1D0) After programming

A0 111 101
A1 111 001 Fuses blown
A2 111 110

• PROMs can only be programmed once • EPROM and E2PROM are modified from
• There can be different schemes for for PROM which can be written many times
making/breaking row-column connection – • Uses a floating gate MOSFET instead of
such as floating gate memory device BJT and fuse. Allows making and breaking
• PROM are inexpensive and used in of row/col interconnection multiple times
prototyping of ROMs
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