Chapter 7

Regenerative circuits
This document is intended only for educational purposes of students of CTU. User
(student) may use this document only to the learning needs. Its distribution and
transfer to the printed form is allowed only with the consent of the author.

c Jiří Hospodka

1
7.1. Oscillators
7.1.1. Principle of feedback oscillators

A
→
A ui

× ×
β
β
uo Rz

(a) (b)
Figure 7.1: Basic structure of feedback oscillator with marks, where feedback loop
may be disconected (a), configuration to analysis of transfer of disconected feedback
loop (loop gain) (b).

2
7.1.2. Phase-shift oscillator

R1 R2 R3
× −A0
→ C1 C2 C3

(a)
β
R1 R2 R3
−A0
ui C1 C2 C3 uo
A
(b)
Figure 7.2: Configuration of phase-shift oscillator (a) and analysis of transfer dis-
conected feedback loop (open-loop gain) (b).

3
 β
R1 R2 R3
−A0
ui C1 C2 C3 uo
A

0
|β(jf )| [dB]
−20 . .
|β(f0 )| = −18 dB = 1/8
−40

−60
102 103 f0 104
0
ϕβ (jf ) [◦ ]

−100
ϕβ (f0 ) = −180◦
−200

102 103 f0 104

f [Hz]
Figure 7.3: Magnitude and phase frequency response of feedback circuit.

4
 Rz
Rv
R1 R2 R3

→
C1 C2 C3

(a)
Rz
Rv
R1 R2 R3 uo
ui C3
C1 C2 Rv

(b)
Figure 7.4: Example of phase-shift oscillator (a), and analysis of its open-loop
gain.(b)

5
6
7.1.3. Bridge-based oscilators

|β + (jf )|
β+ β + = konst.

u+ → f [Hz]
−
u

|β − (jf )|
β− β − = konst.
f [Hz]

(a) (b) (c)

Figure 7.5: Priciple of bridge-based oscillators (a) with frequency dependent circuit
in positive feedback loop (b) or in negative feedback loop (c).

7
 C R β
A
+
× u → R C uo
C u− ui
R C
R2 R2 R

R1 R1

(a) (b)
Figure 7.6: Wien-bridge oscillator (a) and configuration to analyse open-loop gain
(b).

8
 A β

R C uo
ui
R2 C
R

R1

0.4 |β(f0 )| = 1/3

0.3
|β(jf )|

0.2
0.1

101 102 10
f0
3
104 105

90
ϕβ (jf ) [◦ ]

45
0
−45
−90
101 102 10
f0
3
104 105
f [Hz]
Figure 7.7: Magnitude and phase frequency response of feedback circuit. 9
 R2

+
× u → uoz
u− ui
R1
R R R2

C C C C uo

R R R1

(a) (b)
Figure 7.8: Configuration of oscillator with bridged-T network in negative-feedback
path (a) and configuration to analyse open-loop gain (b).

10
 uoz
Uoz (p) 1
ui
PA (p) = = ⇒
R R2 Ui (p) β(p)
C C uo
3
⇒ PA (jf0 ) = , ϕPA (jf0 ) = 0
R R1
2

|β(jf )| 1

0.8
|β(f0 )| = 2/3
0.6
101 102 10
f0
3
104 105

40
20
ϕβ (jf ) [◦ ]

0
−20
−40
101 102 10
f0
3
104 105
f [Hz]
Figure 7.9: Magnitude and phase frequency response of feedback circuit. 11
7.1.4. LC-tuned oscillators +UN +UN

RC R1
L
→
C2 C1 C2
RB L →

C3 C1 R2 RE
CB → ∞

(a) (b)
Figure 7.10: Two commonly used configurations of LC-tuned oscillators (with one
transistor as active part): (a) Colpitts oscillator (b) Clapp oscillator.
L

C1 C2
ui ube gm ube RC rπ uo

Figure 7.11: Analysis of the open-loop gain of oscillator on figure 7.10 (a).

12
7.1.5. Crystal oscillators

L1

Cp induktivní

ℑZx (jf )
R1 f [Hz]

Cs1 fs fp
kapacitní
charakter

(a) (b) (c)

Figure 7.12: Circuit symbol of piezoelectric crystal (a), equivalent circuit of crystal
(b) and crystal reactance versus frequency (c).

13
 +UN

R1
R
X C2 X
→
→
C3 C1 R2 RE
C2 C1

(a) (b)
Figure 7.13: Examples of crystal oscilators: (a) with transistor or (b) with inverter
(logic gate).

14
7.1.6. Amplitude stabilization of oscillators

C R
C R

uo
uo
C →
R C →
R2 R
R2

R1
R1

(a) (b)
Figure 7.14: The idea of amplitude stabilization of Wien-bridge oscillator (a),
specific configuration of Wien-bridge oscillator with bulb as stabilizer (b).

15
 C R uo
→
D
C R −Ur
C
R
R2
uo Ra Rb
C →
R R11 Ci
R21 R22
R1 T
D1
R1
D2

(a) (b)
Figure 7.15: Configuration of oscillator with two limiting diodes as stabilizer (a),
or amplitude stabilization by JFET transitor (in linear region), which is controled
by auxiliary Op Amp (b).

16
7.2. Regenerative circuits
7.2.1. Astable multivibrator with Op amp

u1 R2

R1 uo
→
R

uC C

Figure 7.16: Configuration of astable multivibrator with Op-Amp.

17
 Uo+ u1
U1+ uo

u1 , uo
t
0
t1 T t2 T t3 3T
U1− 2 2

Uo−
u1 R2
Uo+
→ Uo+
R1 uo
U1+
→ T
2
R uC t
0
t1 T t2 T t3 3T
2 2
uC C U1−
→ Uo−
Uo−

(a) (b)
Figure 7.17: Configuration of astable multivibrator with Op-Amp (a) and wave-
forms at marked nodes (b).
18
Example 7.1
Determine the values of astable multivibrator with Op-Amp according Fig. 7.18,
if UN ≡ Uo± = ±10 V, fo = 1 kHz and R1 = R2 .

Solution
The output signal duty cycle is 1:1, because the output (supply) voltage is symmet-
rical, U1± = ±5 V. Solution can be proceeded only in one period of output signal,
for example between times t2 , t3 . Time t2 is a beginning of transient – choose for
simplicity, but without limiting the generality t2 = 0 and then t3 = T /2. Then
uC (0) = −5 V and uC (∞) = +10 V – it is need to solve charging of capacitor by
linear circuit:

uC = 10 − 15e−t/τ , pro t2 ≤ t ≤ t3 , where τ = RC,

it is necessary to determine the time constant τ from a known value uC in t = t3 :
uC (t3 ) = 10 − 15e−T /(2τ ) = U1+ = 5 V,
1 T 1 T
15e−T /(2τ ) = 5 ⇒ e−T /(2τ ) = ⇒ − = − ln(3) ⇒ τ = .
3 2τ 2 ln(3)
For T = 1/fo = 1 ms is τ = 455 µs. Choose for example R1 = R2 = R = 10 kΩ,
.
then C = 45,5 nF.

19
7.2.2. Monostable multivibrator with Op amp
ud Ud = U1+ − UD2
Ud
UD1 ≈ 0,7
UD1 t
Cd
ui u d D2 u1 , uo
Uo+
u1 R2
U1+
t
0
Rd R1 uo 0 T uo
U1−
→ u+
Uo−
R
uC UD1 ≈ 0,7
C UD1 t
D1 uC 0 T

U1−

(a) (b)
Figure 7.18: Configuration of monostable multivibrator with op Amp (a) and
waveforms at marked nodes (b).
20
7.2.3. Timer 555
+UN
2
555 u1 > UN ⇒ Q ≡ log 0, D ≡ 0,
3
Ri 1
u2 < UN ⇒ Q ≡ log 1, D ≡ open.
1 3
Q
Uth R Q

Ri S Q
Utr
2 D
T
Ri

Figure 7.19: Block diagram representation of internal circuit of 555 integrated-

circuit timer and description of its behaviour on input voltages u1 and u2 .

21
 u2

Utr
+UN
t
555 0
R Ri uC → UN
1 Uth
Q
C Uth R Q
uC
Ri S Q t
Utr ≈0
0 T
u2 2 D Q
T log 1
Ri

t
log 0
0 T

(a) (b)
Figure 7.20: Configuration of monostable multivibrator with 555 timer (a) and
waveforms at marked nodes (b).

22
 uC
UN
+UN
→ UN
Uth
555
R1 Ri
1 Utr τ1 τ2
Q
Uth R Q T →0 t
≈0
S Q 0 t1 t2 t3 t4
R2 Ri
Utr Q
2 D log 1
C T
uC Ri
t
log 0
0 t1 t2 t3 t4

(a) (b)
Figure 7.21: Configuration of astable multivibrator with 555 timer (a) and wave-
forms at marked nodes (b).

23
 +UN

555
R1
Ri
1
Q
Uth R Q
R2

D2 D1 Ri S Q
Uth
2 D
C T
uC Ri

Figure 7.22: Astable multivibrator with 555 timer with independent

charge/discharge time of C (duty cycle of output signal).

24
7.2.4. Function generators

uC
R2
C −i
R
R1
0 u2
i u1

Figure 7.23: Configuration of function generator with Op Amp.

25
 uC
R2
C −i
R
R1
0 u2
i u1

(a)
Uo+ uo
uC
U1+
T
∆t = 2
∆U1
uo , uC

t
0
T T 3T 2T 5T 3T
2 2 2
U1−

Uo−
(b)
Figure 7.24: Configuration of function generator with Op Amp (a) and waveforms
at marked nodes (b).
26
Example 7.2
Determine the values of astable function generator with Op-Amp according Fig. 7.24,
if ±UN ≡ Uo± = ±10 V, U1± = ±5 V a fo = 5 kHz.

Solution
Condition U1± = ±5 V leeds to R1 = R2 /2. Solution can be proceeded only in
one period of output signal, for example between times t1 , t2 . Capacitor C is
U−
charging by current source I = −i = − Ro and voltage uc = u1 rise linearly in
time. Capacitance voltage and current can be expressed by:
1 t
Z
∆Q = I∆t = C∆uC z uc (t) = iC (τ ) dτ pro iC (t) = I,
C 0
Uo−
For ∆uC = ∆U1 = 10 V, ∆t = T2 = 1
2fo = 0,1 ms, I = −i = − R = 10
R and choice
C = 10 nF, leeds to R = 10 kΩ.

27
 +UN
I1

D1 D2 K +UN
+UN 0 uK
I1 D3 D4 C
0 K
uK uC −UN
P
C
I2 uC I2
−UN −UN

(a) (b)
Figure 7.25: General configuration of function generator with comparator and
switching current sources (a), implementation of switch by diodes (b).

28
 +UN

α α1
T4 T5
Ui
I1
+UN I
I1 R
0 K
uK I I2
P T1 T2 T3
C
I2 uC
α α α2
−UN −UN

(a) (b)
Figure 7.26: Function generator with comparator (a) and possible configuration of
current sources, that can be controled by Ui (b).

29
 +UN

α α
T4 T5 K +UN
Ui 0
I uK
I
C
R S uC −UN

T2 I 2I
T1
T3
α α α2
−UN

Figure 7.27: Alternative configuration of function generator with comparator and

switching current sources.

30
7.3. Phase-locked loop (PLL)
fmax
u1 ud ur u f2
FD DP VCO f 2
f1 2 f0
f2
fmin ur
0 UN /2 UN

(a) (b)
Figure 7.28: Principle of phase-locked loop (a), typical dependence of frequency
VCO (Voltage controlled oscillator) on controling voltage (b).

u1 (t) = U1m sin(ω1 t + ϕ1 ), u2 (t) = U2m sin(ω2 t + ϕ2 ),

 ud
UN


ud (t) = KF D U1m U2m − cos (ω1 + ω2 )t + (ϕ1 + ϕ2 ) +

 UN
+cos (ω1 − ω2 )t + (ϕ1 − ϕ2 ) 2
∆ϕ
ud (t) = KF D U1m U2m cos ∆ϕ, pro ω1 = ω2 , filtr. 0
0 π/2 π 3π/2 2π
Phase detector output voltage vs. input signals.

31
 u1 u1

t t
u2 u2

t t
ud ud

t t

Figure 7.29: Input and output signals of phase detector (detector is realised by
XOR).

R1

R R2
ud ur
C C
ud ur

Figure 7.30: Commonly used filters in Phase-locked loop.

32
 fmax Lock range
fmax
Capture
fzh
range

f2
f2

f0 f0

fzl fzl
f1 f1
fmin
fzl f0 fmax fmin fzl f0 fzh fmax

(a) (b)
Figure 7.31: PLL output frequency f2 vs. PLL input frequency f1 : (a) f1 is tuned
from low to high frequency, (b) f1 is tuned from high to low frequency.

33
7.3.1. Application of phase-locked loop
u1 ud ur
FD DP →
f1

u2
f2 VCO

Figure 7.32: FM demodulator.

fi f1 fo
÷N1 FD DP VCO →
f2
÷N2

fi fo fi
f1 = f2 = , f2 = ⇒ fo = N2
N1 N2 N1

Figure 7.33: "Frequency multiplier", i.e. frequency synthesis with PLL.

34