2120
4, AUGUST 2007
A Three-Phase UPS That Complies
With the Standard IEC 62040-3
Fernando Botterón and Humberto Pinheiro
Abstract—This paper proposes a down-sampled discrete-time
internal-model-based controller in the synchronous reference
frame with a reduced number of poles. This controller is suit-
able for three-phase pulsewidth modulation inverters with output
transformer for double-conversion uninterruptible power supply
applications. It is demonstrated that the use of a down-sampled
rate and fewer poles in the internal model results in a number
of benefits, among which are the following: 1) improvement of
the transient response; 2) increase of the stability margin of
the closed-loop system; 3) a straightforward implementation in
fixed-point digital signal processor (DSP) and microcontroller
implementation as well as a reduction of the required mem-
ory space; and 4) a simple solution for the saturation of the
output transformer. As a result, it is possible to obtain output
voltages with reduced total harmonic distortion while ensuring
good transient performance for both linear and nonlinear loads.
To confirm the advantages claimed for the proposed synchro-
nous reference dq frame internal-model-based controller and to
demonstrate the steady-state and transient performance under the
test conditions of the International Electrotechnical Commission
Standard 62040-3, the experimental results from a 10-kVA
space-vector-modulated three-phase inverter, which is fully con-
trolled by a DSP TMS320F241, are presented.
Index Terms—Digital control, discrete-time control, internal
model principle, power transformers, uninterruptible power
systems (UPSs).
I. I NTRODUCTION
T HE USE of uncontrolled rectifiers within critical loads,
e.g., in computers and medical equipment, requires unin-
terruptible power supplies (UPSs) that are capable of maintain-
ing low total harmonic distortion (THD) at the output voltages
even under highly distorted load currents [1]. These types of
loads distort the UPS output voltages as a result of unbalanced
nonlinear currents drawn by them, thus causing voltage drops
across the output inductance–capacitance (LC) filter, which is
used to attenuate the pulsewidth-modulation (PWM) inverter
high-frequency harmonics. This becomes a concern in medium-
and high-power UPS, where the switching frequency is low
to limit the switching losses. Other factors also contribute to
UPS output voltage distortion. Among them are the inherent
Manuscript received November 7, 2005; revised February 28, 2006. This
work was supported in part by CAPES and in part by CNPq.
F. Botterón is with the Departamento de Electrónica, Facultad de Ingeniería,
Universidad Nacional de Misiones, Obera 3360, Argentina (e-mail: botteron@
gmail.com).
H. Pinheiro is with the Power Electronics and Control Research Group,
Federal University of Santa Maria, Santa Maria 97105-900, Brazil (e-mail:
humberto@ctlab.ufsm.br).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2007.894782
0278-0046/$25.00 © 2007 IEEE
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO.
nonlinearities of the PWM inverter, fluctuations of the dc
bus voltage, and power semiconductor voltage drops. More-
over, transformerless UPSs are susceptible to interference from
spikes and transients caused by assorted devices connected to
the utility grid. These interferences, transferred through the
UPS to the load, reduce the UPS output voltage quality. Thus,
UPSs with output transformer provide a safer and more robust
solution than transformerless UPSs since the transformer offers
a galvanic isolation to the load from undesirable disturbances
of the main supply [2].
In digitally controlled systems, quantization of the analog-
to-digital converters, digital PWMs, and roundoff resulting
from fixed-point arithmetic can generate errors that result in
a dc component at the inverter output voltage. These errors,
added to the inevitable nonideal features of real live circuit
implementation and amplified by an inappropriate selection
of the controller, can lead the output transformer to saturate,
degrading the overall performance of the system [13]–[15]. It is
important to point out that a standard such as the International
Electrotechnical Commission (IEC) 62040-3 recommends that
the output voltage dc component shall be less than 0.1% of
its root mean square (rms) rated value and specifies that the
distortion factor “D” of sinusoidal UPS output voltages must
to be less than 8%. To deal with these issues, many discrete-
time control structures for single-phase and three-phase UPSs
are reported in the literature.
With the well-known Repetitive Controller [4]–[6], which
is established on the internal model principle [3], several
high-performance approaches have been proposed to achieve
high-quality output voltages in three-phase and single-phase
PWM inverters [7]–[23]. Reference [7] proposes a discrete-
time control strategy using a repetitive controller extended
to a proportional–integral (PI) compensator structure in sta-
tionary αβ frame to compensate voltage distortions due to
nonlinear and unbalanced loads. The steady-state performance
is improved by using a 30th-order low-pass finite-impulse
response (FIR) filter after implementing the measures to at-
tenuate the high-frequency components so that the voltage
error contains only lower frequencies. However, the proposal
referenced above presents a cancellation issue: the zero at
z = 1 (in the discrete-time domain) of the plant introduced
by the transformer cancels with the pole at z = 1 of the
repetitive controller, which violates the internal model principle
[3], as demonstrated in [15]. This problem may eventually
lead the transformer to saturation. In [9], the modified plug-
in repetitive controller combined with the conventional One-
sampling-ahead preview compensator in stationary αβ frame
has been reported to improve the output voltage distortion when
BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3
Fig. 1. Three-phase PWM inverter, ∆Y transformer, filter, and load.
three-phase rectifier loads are connected at the UPS output.
However, in this case, the output transformer is not considered.
Therefore, connecting an insulating transformer at the inverter
output, a pole–zero cancellation occurs with the plug-in repet-
itive controller in closed loop. In [10], the author proposes
a two-layer voltage controller scheme in synchronous frame
with a PI regulator to ensure zero steady-state error at the
fundamental frequency and a repetitive-based controller with a
high-pass filter to compensate for the harmonics at the inverter
output voltages. However, inadequate choices of the high-pass
filter cutoff frequency may result in dc components that can
saturate the transformer at the inverter output. Moreover, the
repetitive controller with a high-pass filter produces pole–zero
cancellation, which may lead to output transformer saturation.
Other solutions that are also based on the internal model
principle were presented in [11] and [12]. In [11], a three-
layer control scheme is proposed. It consists of a proportional
compensator in stationary αβ frame, an integral controller in
synchronous frame to compensate the fundamental component,
and a selective harmonic compensator in stationary frame based
on a passband FIR filter with unit gain and zero phase at
the selected harmonics. Reference [12] proposes a robust con-
troller based on the passivity theory framework for three-phase
UPS. This controller guarantees asymptotic stability with good
steady-state performance for nonlinear and unbalanced loads.
Although the controllers proposed in [11] and [12] may be ad-
equate solutions for reducing distortion in output voltages and
for operating with an insulating transformer, the computational
requirements to implement them increase significantly with
the number of compensating harmonics. In addition, since the
controller coefficients are not integer numbers, this controller
is sensitive to quantization and roundoff errors, and as a result,
the tracking at selected harmonics is compromised. References
[18] and [19] propose a down-sampled repetitive controller in
synchronous frame with reduced number of poles, which only
compensate odd harmonics in stationary frame. This controller
gives reduced THD output voltages of a three-phase UPS. It
also makes it possible to solve the output transformer satu-
ration; still more due to the slower sampling rate, it is not
necessary to include a zero-phase-shift low-pass FIR filter [6] to
improve the robustness of the closed-loop system. On the other
2121
hand, [20] proposes an odd-harmonic digital repetitive plug-
in controller to reject these kinds of disturbances in stationary
frame. This odd-harmonic repetitive controller does not have
a pole at z = 1, so it is suitable for operating with an output
transformer. However, a low-pass FIR filter must be included
in the periodic signal generator loop to reduce the repetitive
frequency gains, and this consequently increases the closed-
loop system robustness. As a result, this filter compromises
tracking and disturbance rejection.
On the other hand, it is important to emphasize that few
papers explore the UPS transient behaviors. Moreover, few
papers explore the controller transient behaviors using the
discrete-time internal model principle. Hence, to obtain output
voltages with reduced THD and an improved load transient,
this paper proposes a down-sampled internal-model-based con-
troller in synchronous reference frame with a reduced number
of poles. This internal-model-based controller acts together
with a proportional–derivative (PD) predictive compensator,
which has the function to stabilize the closed-loop system. This
compensator results in a simple form for digital implementation
and only requires the measure of the UPS output voltage [15],
[23]. The main feature of the proposed internal-model-based
controller is that it is a straightforward solution for output
transformer saturation. In addition, the reduced number of poles
of the proposed internal model in synchronous frame improves
the transient performance for linear and nonlinear loads as well
as enhancing the stability margin of the closed-loop system.
Thus, it is demonstrated that the transient performance with
the proposed controller can be improved by satisfying the
rigorous output dynamic performance classification 1 of the
standard IEC 62040-3, which classifies UPS by performance.
To demonstrate the advantages claimed, the proposed discrete-
time controller structure is digitally implemented in a 16-bit
fixed-point digital signal processor (DSP), and experimental
results in steady state and transient conditions from a 10-kVA
prototype are given.
II. S YSTEM D ESCRIPTION
A typical double-conversion UPS power circuit is shown in
Fig. 1. Among the three-phase inverter configurations, the one
2122 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

shown is a strong candidate since: 1) it provides galvanic iso- B. Synchronous Reference Frame State-Space Model
lation to the load; 2) it allows the output voltage to be selected
Transforming (1)–(3) to αβ and then to synchronous frame
according to customer needs; and 3) it provides a neutral by
as in [25], using the linear transformations given in the
the delta-star (∆Y) connection. The dc-bus voltage is almost
Appendix, the state-space model is given by ẋdq (t) =
constant and supplied by a six-pulse three-phase uncontrolled
Adq xdq (t) + Bdq udq + Fdq wdq , where the matrices Adq ,
diode rectifier, which provides energy to the inverter in normal
Bdq , and Fdq are given as
operation mode. The dc-to-ac conversion is accomplished by
a space-vector-modulated three-phase three-leg inverter with  
0 −ω 0 0 −M/D 0
insulated-gate bipolar transistor. The high-frequency harmonics ω 0 0 0 0 −M/D 
 
introduced by the modulation are attenuated by the LC filter. It 0 0 −ω −(3L+M )/D 
 0 0 
is important to point out that the filter inductors are located at Adq =  
0 0 ω 0 0 −(3L+M )/D 
the transformer primary side so as not to introduce distortions  
in the output voltages that result from zero-sequence voltages  0 0 1/C 0 0 −ω 
produced by unbalanced load currents, which will be shorted 0 0 0 1/C ω 0
on the delta connection at the transformer primary side [15].  
Since this inverter is not capable of controlling zero-sequence (M + Ld )/D 0
 0 (M +Ld )/D 
voltages, it is important to minimize the zero-sequence im-  
 
pedance to reduce the distortions in the output voltages. Hence,  M/D 0 
Bdq =  
the topology in Fig. 1 offers a degree of freedom to minimize  0 M/D 
 
the zero sequence impedance.  0 0 
0 0
III. T HREE -P HASE PWM I NVERTER , ∆Y T RANSFORMER ,  
0 0
F ILTER , AND L OAD M ODEL  0
 0 
A. Stationary Frame Model  0 0 
 
Fdq =  . (4)
From the circuit in Fig. 1, the dynamic equations of the  0 0 
 
inverter, transformer, filter, and load can be obtained by ap-  −1/C 0 
plying Kirchhoff’s laws. To simplify the system modeling, it 0 −1/C
is considered that the leakage inductances of the primary and
secondary sides of the transformer are lumped at the secondary The state vector has been selected as xdq (t) =
side. The coil resistances are also neglected. The following [idp iqp ids iqs vd vq ]T , and the input and disturbance
equations are then obtained: vectors as udq (t) = [ud uq ]T and wdq (t) = [iod ioq ]T ,
respectively. In these matrices, D is defined as D = 3LM +
 M L
 3LLd + M Ld .
  2L+ M+Ld
−L −L  
u12  d
 d iab From (1), it is seen that the voltages applied at the trans-
u23 =  


ibc 
ML
 −L 2L+ M +Ld
−L  former input are the line-to-line voltages produced by the
 d dt inverter. To avoid an additional transformation from line-to-
u31 ML
ica
−L −L 2L+ M +Ld
line to phase voltages that must be performed in the DSP, the
d
   space vector modulation is accomplished using the line-to-line
van
M    voltages referred above.
+ vbn (1)
M + Ld 
vcn
        C. Synchronous Reference Frame Discrete-Time Model
ias iab vas
d   M d   1    To obtain a discrete-time model for the discrete-time con-
ibs = ibc − vbs (2)
dt  M + Ld dt M + Ld  troller design, the synchronous frame state equation in the
ics ica vcs
continuous time domain obtained above is solved throughout a
        
v̇an i i sampling period T . For this purpose, it is considered that the
 v̇bn
  1  as 1  oa
=  ibs −  iob  .
 
(3) control action udq (t) remains constant in a sampling period

C C T . Thus, the discrete-time state-space equation of the plant
v̇cn ics ioc
that takes into account the delay of a digital implementation is
In these equations, M is the mutual inductance, L is the filter given by
inductance, Ld is the equivalent leakage inductance, and C  is       
xdq (k+1)T G H0 xdq (kT ) H1
the filter capacitance. In addition, u12 , u23 , and u31 are the line- = + udq (kT ).
  udq_d (k+1)T 0 0 udq_d (kT ) I
to-line PWM voltages produced by the inverter; van , vbn , and
    (5)
vcn , and ioa , iob , and ioc are the phase-to-neutral voltages and
load currents referred to the transformer primary side; and iab , In (5), the additional state variable udq_d represents the
ibc , and ica are the phase current in the delta connection. delayed control action that models the real-time digital
BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2123

Fig. 2. Timing chart of DSP controller. Tpwm : switching period. T : sampling period and PD compensator computing period. Td : time delay. Tim : internal-
model-based controller computing period. Tim = 2T , and Td = T .

implementation delay, and the matrices G, H0 , and H1 are In this case, the resulting sampled transfer function matrix
given as can be written as
 
G = eAdq T g1 (z) g2 (z)
Gp (z) = (9)
H0 = eAdq (T −Td ) A−1 Adq Td
− I)Bdq −g2 (z) g1 (z)
dq (e

H1 = A−1
dq e
Adq (T −Td )
− I Bdq (6) where the sampled transfer functions g1 (z) and g2 (z) are given
by the proper rational functions
where Td is the time delay mentioned above, which is related
to a given DSP implementation. b0 z 4 + b1 z 3 + b2 z 2 + b3 z + b 4
g1 (z) =
It is important to note that to obtain (5), the sampling of z 5 − a1 z 4 + a2 z 3 − a3 z 2 + a4 z
the variables of interest and the updating of the control law −c0 z 4 − c1 z 3 − c2 z 2 + c3 z + c4
are performed as shown in the timing chart of Fig. 2. With g2 (z) = . (10)
z 5 − a1 z 4 + a2 z 3 − a3 z 2 + a4 z
this sampling scheme, it is possible to use a low switching
frequency to limit the switching losses while preserving an Note that (9) shows that the system presents a cross coupling
acceptable sampling frequency. Also, since sampling is carried given by the transfer functions g2 (z) and −g2 (z). In order
out at zero vectors, the resulting low-frequency harmonics over to simplify the controller design, is useful to work with a
the sampled data are reduced when compared with one sample single-input–single-output (SISO) system. It is shown that the
per sampling period [24]. influence of the cross transfer functions is negligible, or in
Since the discrete-time controller proposed here is modeled another words, the system is weakly coupled. It is possible to
using an input–output approach, it is useful to obtain the see in Fig. 3 that for a large variation in frequency, the transfer
input–output description of the plant, which can be found from function g2 (z) significantly attenuates the output vq when an
(5), by applying the Z transform. Strictly speaking, since the input signal in ud is applied or vice versa. Hence, the system can
plant represented by (5) is multiple-input–multiple-output, it is be treated as a SISO control problem with a transfer function
obtained a sampled transfer function matrix of the system, i.e., given by g1 (z) without significantly affecting the closed-loop
performance.
Gp (z) = Cdq (zI − Gdq )−1 Hdq + Ddq (7)
In order to define a proper discrete-time voltage controller for
where the plant described by g1 (z), upon the internal model principle
  foundation, it is important to show the impact that the zeros of
G H0 the plant have in the selection of the controller structure. Fig. 4
Gdq =
0 0 shows the zeros of g1 (z).
  Fig. 4 shows that this plant presents a pair of zeros at the fun-
H1
Hdq = damental frequency in synchronous frame, which is associated
I
with the insulating transformer. These zeros indicate that the
Cdq = [ 02×4 I2×2 02×2 ] transformer does not transfer the dc component to its output.
Ddq = [02×2 ] . (8) This means that an inadequate selection of the discrete-time
2124
Fig. 3. Frequency responses of g1 (z) and g2 (z). T = 198.41 µs.
Fig. 4. Zero map of the input–output-sampled transfer function of the
plant g1 (z).
controller may produce a pole–zero cancellation, which causes
any residual dc component from the digital implementation
to be amplified, which in turn may lead the transformer to
saturate, as demonstrated in [15]. To avoid this problem, a new
discrete-time voltage controller in synchronous frame based on
the internal model principle, and adequate for the system in
Fig. 1, will be described in the next section.
IV. P ROPOSED D ISCRETE -T IME I NTERNAL -M ODEL -B ASED
C ONTROLLER IN S YNCHRONOUS R EFERENCE F RAME
This section develops the proposed discrete-time voltage
controller based on the internal model principle in synchronous
reference frame. Let us consider the design problem of a SISO
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007
Fig. 5. Discrete-time feedback SISO LTI system.
linear time-invariant (LTI) system in the discrete-time domain
shown in Fig. 5, where the strictly proper transfer function of
the plant is given by g1 (z). The problem is to design a controller
with a proper transfer function gc (z) so that the feedback
system is asymptotically stable and meets the specifications of
zero error tracking in steady state even with disturbance signals
present in the plant.
The design procedure, which was developed from the inter-
nal model principle theory presented in [15] for discrete-time
systems, can be summarized in two steps: 1) introduction of
1/φ(z), a model of the reference and disturbance signals inside
the loop, where φ(z) is the least common denominator of the
unstable poles of r(z) and w(z) and 2) stabilization of the
feedback system using a conventional compensator. It must be
emphasized that neither root of the internal model φ(z) must be
a zero of the transfer function of the plant so as to ensure the
exact cancellations of the unstable modes of the reference and
disturbance signals.
A. Proposed Internal Model
With the aim of defining an adequate internal model for the
plant g1 (z), five candidate internal models are presented below.
Fig. 6 shows the pole map of a discrete-time internal model
that is often used in conventional repetitive controllers [5].
When this internal model is implemented in stationary frame,
the pole at z = 1 is cancelled with the zero of the plant at
the same location. On the other hand, if this internal model
BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3
Fig. 6. Pole map. Internal model of the conventional repetitive controller [5].
T = 198.41 µs, and 1/φ(z) = 1/(z N − 1).
Fig. 7. Pole map. Internal model with poles at odd multiples of 60 Hz.
T = 198.41 µs, and 1/φ(z) = 1/(z N/2 + 1).
is implemented in synchronous frame, the same pole–zero
cancellation occurs at 60 Hz. So this particular internal model
is inappropriate for this application as demonstrated in the
experimental result of Fig. 20. It can be seen that the output
phase voltages have the desired levels with a low THD, but
the currents at the transformer primary side appear with a
significant offset, which increases continuously, shutting down
the PWM inverter as a result of overcurrents.
Fig. 7 shows a discrete internal model with poles at frequen-
cies that are odd multiples of 60 Hz, while Fig. 8 presents an
internal model with poles at frequencies that are even multiples
of 60 Hz. These internal models have been employed in three-
phase UPS controllers [18], [19] as well as in an odd-harmonic
repetitive controller [20] for single-phase applications [21],
[22]. When the internal model in Fig. 8 is implemented in
2125
Fig. 8. Pole map. Internal model with poles at even multiples of 60 Hz.
T = 198.41 µs, and 1/φdq (z) = 1/(z N/2 − 1).
Fig. 9. Pole map. Internal model with reduced number of poles.
T = 198.41 µs.
synchronous frame, there is no pole–zero cancellation with the
plant. Similarly, the pole–zero cancellation is not a concern
for the internal model of Fig. 7 in stationary frame. On the
other hand, when operating with low switching frequencies, it
is desirable to keep the sampling frequency as high as possible
to improve the closed-loop performance. Usually, Tpwm = 2T .
In this case, the high gains of the poles close to the Nyquist
frequency may lead to system instability. In order to overcome
this limitation, a zero-phase-shift low-pass FIR filter can be
included [6] to improve the robustness at high frequencies.
However, this filter will increase the tracking error and com-
promise disturbance rejection.
Fig. 9, on the other hand, presents an internal model with a
reduced number of poles. In this case, the internal model has
been chosen to compensate the fundamental and the harmonics
2126
Fig. 10. Internal model with reduced number of poles and roundoff error in
coefficients. T = 198.41 µs.
Fig. 11. Pole map of the proposed internal model in synchronous frame.
N = T1 /2 T , T1 = 1/60, T = 198.41 µs, Tim = 2T , and 1/φdq (zim ) =
N/2
1/(zim − 1).
from 2nd to 7th. Note that it is possible to include more poles
if desired. This internal model is adequate for the system in
Fig. 1 since it does not cancel the zeros of g1 (z). However, the
poles of this internal model are sensitive to roundoff errors in
the polynomial coefficients, which are a concern in fixed-point
arithmetic implementation. As a result, the pole location of
the internal model can be significantly modified, as illustrated
in Fig. 10.
Based on the internal models presented above, and having
considered them inadequate for the system in Fig. 1, we now
propose a suitable discrete-time internal model for the plant
g1 (z). The pole map of the proposed internal model in syn-
chronous frame is shown in Fig. 11. This internal model has
half the poles of the internal model shown in Fig. 8, and no
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007
root of φdq (zim ) is a zero of the plant. Also, this proposed
internal model is computed with a reduced sampling rate. As
a result, the Nyquist frequency of the internal-model-based
controller is smaller than the first set of harmonics generated
by the switching operation of the PWM inverter, i.e., there are
no internal model poles in the model uncertainty region of the
plant. Note that this internal model results in a reduced compu-
tational effort controller without the roundoff error of the fixed-
point implementation since the coefficients of its polynomial
are integer numbers. Therefore, we propose here a discrete-time
control structure with a faster loop at a sampling period T to
keep a satisfactory sampling rate and a down-sampled internal-
model-based controller. This results in a multirate closed-loop
system, as presented in Fig. 12.
From the two-step design procedure presented at the begin-
ning of this section, the proposed internal-model-based con-
troller, which operate at a sampling period Tim = 2T , can be
included in the closed loop. To complete the internal-model-
based controller design, the numerator Nim (z) of the transfer
function Gim (z) shown in Fig. 12 must be selected. To avoid
compromising the simplicity of this controller being consid-
d
ered, this numerator can be selected as Nim (zim ) = kim zim . As
a result, the sampled transfer function of this controller can be
written as
Nim (zim ) N/2
Gim (zim ) = , where φdq (zim ) = zim −1. (11)
φdq (zim )
In this transfer function, the controller gain kim determines
the convergence time of the voltage error to zero, and the pa-
rameter d is the time advance step size used to compensate the
closed-loop phase at high frequencies [23]. These parameters
must be chosen to ensure the asymptotic stability of the closed
loop and to meet a desired performance.
The next step is to design the conventional compensator
Gc (z) to stabilize the closed loop with the plant Gp (z) = g1 (z).
In this case, a predictive PD compensator has been selected
whose proper transfer function Gc (z) is given as
Gc (z) = k1 z −1 + k2 z −2 . (12)
This compensator has been selected mainly for its simple
structure, which only requires the measurement of the phase
to neutral output voltages. In addition, it provides a significant
phase and gain margin to the closed-loop system. The predictive
PD controller gains k1 and k2 are determined by placement
of the dominant poles of the closed-loop system [23]. It is
important to point out that the tandem connection of Gc (z)
with Gp (z) is completely characterized by the proper transfer
function Gc (z)Gp (z) since there is no pole–zero cancellation
between Gc (z) and Gp (z), as established in [15].
B. Stability Analysis
Since the closed-loop system operates with two different
sampling rates, the stability analysis can be performed in
two steps.
Step 1: The closed-loop stability of the tandem connection of
the plant with the PD compensator must be ensured. This faster
BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3
Fig. 12. Control structure of the proposed closed-loop multirate SISO discrete-time voltage controller in synchronous frame for axis “d.” z = eT s , and
zim = eTim s .
Fig. 13. Closed-loop system. Tandem connection of the plant plus predictive PD compensator.
Fig. 14. Nyquist plot of Gc (z)Gp (z). k1 = 0.12, k2 = −0.08, and T =
198.41 µs.
loop operates with a sampling period T , which results in the
control structure shown in Fig. 13.
To ensure the closed-loop asymptotic stability of the sys-
tem represented in Fig. 13, the roots of the polynomial 1 +
Gc (z)Gp (z) = 0 must be inside the unit circle. To demonstrate
that this closed loop is stable, the Nyquist plot of the open-loop
transfer function Gc (z)Gp (z) can be used, as shown in Fig. 14.
It can be seen that the tandem connection of Gp (z) with Gc (z)
has a large gain margin, which in this case is about 16 dB, and
an infinite phase margin. Therefore, the closed-loop system in
Fig. 13 is asymptotically stable.
Step 2: This step is to ensure the overall stability when the
proposed internal-model-based controller (11) is introduced. To
extend the previous stability criteria to the multirate controller
2127
Fig. 15. Single-rate equivalent of the multirate closed-loop system with a
sampling period Tim .
system in Fig. 12, we transform it to an equivalent system
sampled at slower rate Tim . As a result, the equivalent closed-
loop system becomes as that shown in Fig. 15.
The sampled transfer function of the equivalent slow-rate
plant GMF (zim ) can be found from the equivalent slow-rate
state-space representation of the plant and PD compensator,
which is given in the Appendix. This transfer function can be
expressed as
GMF (zim )
6
n0 zim − n1 zim
5
− n2 zim
4 3
+ n3 zim − n4 zim
2
+ n5 zim
= .
zim −d1 zim −d2 zim + d3 zim + d4 zim −d5 zim + d6 zim −d7
7 6 5 4 3 2
(13)
The closed-loop stability of the tandem connection of
Gim (zim ) with GMF (zim ) can be proved using the Nyquist
criterion plots of the open-loop transfer function, i.e.,
Gim (zim )GMF (zim ). Fig. 16 shows the Nyquist plot for
N = 42, kim = 1, and d = 1. It can be seen that the closed-loop
system with an internal-model-based controller remains stable
with a significant gain and phase margin.
To demonstrate the benefit of performing the proposed
discrete-time down-sampled internal-model-based controller,
2128
Fig. 16. Nyquist plot of G(zim ) = Gim (zim )GMF (zim ). N = 42, and
Tim = 396.82 µs.
Fig. 17. Nyquist plot of the single-rate system operating at lower sampling
frequency. G(z) = Gim (z)Gp (z)/(1 + Gp (z)Gc (z)), N = 42, kim = 1,
d = 1, and T = 396.82 µs.
the Nyquist plot of the closed-loop system in Fig. 12, which op-
erates with a single rate at lower sampling frequency, is shown
in Fig. 17. It can be seen that the gain margin stays almost
the same if compared with the gain margin in Fig. 16, but the
phase margin decreases significantly when the system operates
at a single rate. Therefore, the stability margin of the proposed
multirate system in Fig. 12 is significantly bigger than the
single-rate system at lower sampling frequency, which therefore
represents the benefit of the proposed multirate controller.
Concerning digital implementation, by applying the inverse
Z-transform to (12) and (11), we can obtain the respective re-
cursive difference equations of the predictive PD controller and
the proposed down-sampled internal-model-based controller as
ucd (kT ) = k1 ed (k − 1) + k2 ed (k − 2)
uimd (mTim ) = kim ed [mTim − (N/2) + d]
+ uimd [mTim − (N/2)] .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007
From Fig. 12, we can see that the control law applied to the
plant is given by
ud (kT ) = ucd (kT ) + uimd (mTim ). (16)
Note that (14)–(16) are written for the axis “d”; therefore,
similar equations can be written for the axis “q.” Regarding the
gain, kim must be selected to guarantee a fast convergence of
the voltage error to zero, maintaining the closed-loop system
stability. The values of kim and d are given in Table II. It
is important to emphasize here that simplicity is a significant
advantage of the proposed controller if compared with the
controller presented in [11]. It becomes clear by realizing that
the proposed internal-model-based controller implementation
is just (15). In fixed-point arithmetic, the quantization and
rounding errors may result in roots of the polynomial internal
model to be quite different from the desired one (see Fig. 10).
However, since the proposed internal-model-based controller
polynomial coefficients are 1s or 0s, the internal model roots
have low sensitivity to these errors. This is another advantage if
compared with the controllers of [11, eq. (9)] and [12, eq. (27)].
V. S TEADY -S TATE AND D YNAMIC O UTPUT V OLTAGE
C HARACTERISTICS OF THE UPS
The UPS output specifications according to IEC 62040-3
must have output voltage dynamic performance characteristics
not exceeding the limits in [1, Figs. 1, 2, or 3] for the application
of increasing/decreasing load steps under linear and reference
nonlinear load for the test conditions in Section 6.3 of this
standard. The objective of classifying UPS by performance is
to provide a common base on which all UPS manufacturer and
supplier data are to be compared. This enables purchasers of
equipment with similar UPS power ratings to compare products
from different manufacturers under the same measurement
conditions.
A. Reference Nonlinear Load Steps in Normal Mode
Step nonlinear loading is defined as the application of the
test circuit, which is shown in Fig. 18, for dissipating the
required steady-state output active power for the percentage
load step relative to the rated steady-state output active power
of the UPS. The load circuit is then first deenergized before
application so that its capacitor voltage starts from zero voltage
when applied to the UPS output. To determine the UPS output
dynamic performance, the deviation from the under/overvoltage
limits defined [1] must be obtained. Then, using the test circuit
in Fig. 18, the required step loads (33% of the rated output
apparent power) must be applied or reduced in accordance
with those in [1, Section 6.3.8.5] monitoring the load capacitor
voltage. The capacitor voltage changes should remain within
the stated tolerances in [1, Figs. 1 or 2, Section 5.3.1]. In
(14) Fig. 18, Uc is the rectified voltage, R1 is the load resistor set
to dissipate an active power equal to 66% of the total apparent
power, and Rs is a series line resistor set to dissipate an active
(15) power equal to 4% of the total apparent power. The procedure
BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2129

TABLE I
SETUP PARAMETERS

Fig. 18. Reference nonlinear load test [1].

TABLE II
CONTROLLER PARAMETERS

Fig. 19. Resistive load test [1].

for calculating the passive elements of this reference nonlinear

load is described in [1, Annex E].

B. Linear Load Steps

With the UPS operating in normal mode, a resistive load
equal to 100% of the output active power must be applied in
two steps using the circuit in Fig. 19: one equal to 20% and one
equal to 80%. The step must be performed at the peak value of
the output waveform. Similarly, unloading must be measured
by reducing the load to 20% of the rated output active power by
switching off the 80% load. In both cases, the output waveform
Fig. 20. Experimental result. Line current ia at the transformer primary side
must be observed and stored so as to permit calculation of any with dc component. With the internal model of the conventional repetitive
dynamic performance deviation. This deviation is referred as controller. Output phase-to-neutral voltages. Voltage scale: 50 V/div. Current
the rms value above or below the rated value, which is obtained scale: 10 A/div. N = 84, and T = 198.41 µs. φ(z) is in Fig. 6.
on a successive half-cycle by half-cycle. The computed values
of this dynamic deviation must remain within the stated limits a load resistor R1 = 30 Ω, and a filter capacitor Cc = 4700 µF,
in [1, Figs. 1, 2, or 3, Section 5.3.1]. and allow to obtain a crest factor of 3. The setup parameters
are given in Table I, and the controller parameters are given
in Table II.
VI. E XPERIMENTAL R ESULTS
The circuit in Fig. 1 has been tested experimentally to
A. Steady-State Performance
verify the proposed discrete-time-voltage internal-model-based
controller using a DSP TMS320F241 to control a 10-kVA Fig. 20 shows the output phase voltages and the input current
UPS. The steady-state load tests have been performed using at the transformer primary side with a significant dc component
resistive linear loads and nonlinear single-phase and three- when the system in Fig. 1 operates with an internal model
phase uncontrolled diode rectifiers. The reference nonlinear based on the conventional repetitive controller. This fact can
load, as described in Fig. 18 and designed according to the be proven through the harmonic spectrum presented in Fig. 21,
standard IEC 62040-3, has an input series resistor Rs = 0.5 Ω, which denote a dc component around 140%. On the other
2130
Fig. 21. Transformer primary side line current harmonics spectrum with dc
component. With the internal model of the conventional repetitive controller.
Fig. 22. Experimental result. Line current ia at the transformer primary
side without dc component. With the proposed internal-model-based con-
troller. Output phase-to-neutral voltages. Voltage scale: 50 V/div. Current scale:
10 A/div. N = 42. φ(z) is in Fig. 11.
Fig. 23. Transformer primary-side line current harmonics spectrum without
dc component. With the proposed internal-model-based controller.
side, Fig. 22 shows the same waveforms as Fig. 20 with the
system in Fig. 1 operating with the proposed internal-model-
based controller. It can be seen that this current appears without
offset, as demonstrated in the harmonic spectrum of this current
given in Fig. 23, where the dc component is less than 1%,
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007
Fig. 24. Experimental result. Unbalanced linear load. With the pro-
posed controller. Output phase-to-neutral voltages van , vbn , and vcn , and
load current ia . THD = 0.7%. Unbalance factor = 0.6%. Voltage scale:
50 V/div. Current scale: 20 A/div.
Fig. 25. Experimental result. Open-loop operation. Three-phase uncontrolled
rectifier at 10 kVA. Output phase-to-neutral voltages van , vbn , and vcn , and
load current ia . THD = 7%. Voltage scale: 50 V/div. Current scale: 20 A/div.
which can be attributed to sensor error. These tests validate that
the proposed internal-model-based controller does not produce
pole–zero cancellation and consequently does not saturate the
output transformer.
The performance of the proposed controller with linear load
has been tested using an unbalanced resistive rated load con-
nected between a phase and a neutral wire; the experimental
result is shown in Fig. 24. It can be seen that the UPS output
voltages have a low THD as well as a reduced unbalance
factor. On the other hand, Figs. 25 and 26 show the three-
phase line-to-neutral voltages and the nonlinear load current
in phase a, which is drawn by three-phase and single-phase
uncontrolled rectifiers, when operating without the proposed
controller. It can be seen that the THD of the output voltages
is very high, around 7% and 10%, respectively. Figs. 27 and 28
show the operation of the proposed controller with the same
nonlinear loads. It is seen that with the proposed controller,
high-quality output voltages are obtained. Also, in Fig. 28, the
single-phase uncontrolled rectifier is connected between one
phase and neutral.
BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3
Fig. 26. Experimental result. Open-loop operation. Single-phase uncontrolled
rectifier at 10 kVA. Output phase-to-neutral voltages van , vbn , and vcn ,
and load current ia . THD = 9.8%. Voltage scale: 50 V/div. Current scale:
50 A/div.
Fig. 27. Experimental result. With the proposed controller. Three-phase un-
controlled rectifier at 10 kVA. Output phase-to-neutral voltages van , vbn , and
vcn , and load current ia . THD = 0.8%. Voltage scale: 50 V/div. Current scale:
20 A/div.
Fig. 28. Experimental result. With the proposed controller. Unbalanced load.
Single-phase uncontrolled rectifier at 3.3 kVA. Output phase-to-neutral volt-
ages van , vbn , and vcn , and load current ia . THD = 1.2%. Unbalance
factor = 0.92%. Voltage scale: 50 V/div. Current scale: 50 A/div.
2131
This represents the worst case with the phase-rated unbal-
anced nonlinear load. It can be seen from these experimental
results that the THD of the output voltages is very low, which is
around 1%, even with this severe operational condition. Also,
with the proposed controller, the unbalance factor has been
reduced below 1%. The THDs of the UPS output voltages
presented in Figs. 24, 27, and 28 are well below the limits
of IEC 62040-3. In addition, the individual odd and even
harmonics does not exceed the limits of this standard, as shown
in Fig. 29 and Table III.
B. Transient Performance
To verify the transient performance of the UPS output, the
standardized tests described in Section 6.3.7 of the standard
IEC 62040-3 were performed, and the deviations from the
undervoltage and overvoltage limits defined in [1, Figs. 1, 2, or
3] were obtained, as described in Section VI, for nonlinear and
linear loads. Fig. 30 shows the dynamic deviation of the load
capacitor voltage of each phase of the reference nonlinear loads
(Fig. 18) at loading steps. On the other hand, Fig. 31 presents
the deviation of the load capacitor voltage due to the removal
of reference nonlinear loads. Figs. 30 and 31 demonstrate
that the proposed controller satisfies the voltage limits under
dynamic conditions not exceeding the undervoltage and over-
voltage transient limits of classification 1. Figs. 32 and 33 show
the dynamic deviation of the output voltage rms value when
performing the linear load steps as described in Section VI.
These experimental results again demonstrate that the proposed
controller ensures that the dynamic deviation values do not
exceed the undervoltage and overvoltage transient limits of
classification 1 both in the load application and when it is
removed. Thus, this UPS is suitable for feeding most types
of critical loads with high-quality output voltages. The ex-
perimental results for loading and removal of the reference
nonlinear load are presented in the time domain in Figs. 34
and 35. Fig. 34 shows the reference nonlinear load step from
33% to 66%, while Fig. 35 shows the reference nonlinear
removal from 66% to 33%. It can be seen that the undershoot
and overshoot require no more than one fundamental period
before returning to the rated value. It is important to note that
the output voltage transient during the nonlinear load step is
a consequence of the fact that the large reference nonlinear
load capacitor Cc is uncharged when it is connected to the
UPS output. Even in this case, the minimum load rectifier
average output voltage value does not exceed the transient
limits imposed by classification 1 in [1]. This transient can be
reduced by increasing the inverter output current capability.
The experimental waveforms for the dynamic test with linear
load are presented in Figs. 36 and 37 to complement the
information given by Figs. 32 and 33. Fig. 36 shows the linear
load step from 20% to 80% of the rated output active power,
and Fig. 37 presents the unloading step from 80% to 20%.
VII. S UMMARY
This paper has proposed a new discrete-time down-sampled
internal-model-based controller in the synchronous reference
2132 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

Fig. 29. Levels for individual harmonics UPS output voltages with the proposed controller and IEC 62040-3.

TABLE III
LEVELS FOR INDIVIDUAL HARMONICS UPS OUTPUT VOLTAGES WITH THE PROPOSED CONTROLLER

Fig. 30. Output dynamic performance characteristics of the three-phase UPS. Step reference nonlinear loading from 33% to 66% and from 66% to full load.
BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2133

Fig. 31. Output dynamic performance characteristics of the three-phase UPS. Step reference nonlinear removal from 100% to 66% and from 66% to 33%.

Fig. 32. Output dynamic performance characteristics of the three-phase UPS. Step linear loading from 20% to 80% rated active power load.

Fig. 33. Output dynamic performance characteristics of the three-phase UPS. Step linear removal from 80% to 20% rated active power load.
2134 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007
Fig. 34. Experimental result. Output phase-to-neutral voltage van . Reference
nonlinear load step from 33% to 66%. Voltage scale: 50 V/div. Current scale:
50 A/div.
Fig. 35. Experimental result. Output phase-to-neutral voltage van . Reference
nonlinear load removal from 66% to 33%. Voltage scale: 50 V/div. Current
scale: 50 A/div.
Fig. 36. Experimental result. Output phase-to-neutral voltage van . Linear
load step from 20% to 80%. Voltage scale: 50 V/div. Current scale: 50 A/div.
frame, which is adequate for three-phase three-leg PWM in-
verters that operate with an insulating transformer, for UPS
applications. The proposed discrete-time control system results
Fig. 37. Experimental result. Output phase-to-neutral voltage van . Linear
load step from 80% to 20%. Voltage scale: 50 V/div. Current scale:
50 A/div.
in a multirate system with the plant plus a PD compensator
to stabilize the closed loop in one sampling rate and the
internal-model-based controller with half of the former sam-
pling frequency. This paper demonstrates that, by modifying the
order of the polynomial of the internal model in synchronous
frame, it is possible to ensure that the residual dc components
(in stationary abc frame) are not amplified, thus avoiding trans-
former saturation. In addition, it is not necessary to include a
zero-phase-shift low-pass FIR filter in the loop of the internal-
model-based controller. With regard to digital implementation,
the proposed discrete-time controller is an attractive solution
for fixed-point DSPs because it is easy to implement and has
low sensitivity to roundoff error. In addition, for DSP and
microcontrollers with reduced random access memory, this pro-
posed internal model saves the memory space that is required
to store the voltage error in a circular buffer. Furthermore, the
predictive PD compensator that stabilizes the closed loop has
a straightforward design and only requires the measure of the
UPS output voltages. The experimental results presented in this
paper demonstrate that the steady-state output voltages have
high quality under both linear and nonlinear loads with a low
THD and a reduced imbalance factor for unbalanced loads.
In addition, the output voltage dynamic performance of the
three-phase UPS is found to be very good, meeting the severe
classification 1 of IEC 62040-3, for both linear and nonlinear
loads.
A PPENDIX
The linear transformation that converts the state variables
from the stationary abc to the stationary αβ0 frame, and from
αβ to dq synchronous frame, is given by
 
 1 −1/2 −1/2
2 √ √ 
Tabc_αβ0 =  0 3/2 − 3/2 
3 √ √ √
1/ 2 1/ 2 1/ 2
 
cos(ωt) sin(ωt)
Tαβ _dq = . (17)
− sin(ωt) cos(ωt)
BOTTERÓN AND PINHEIRO: THREE-PHASE UPS THAT COMPLIES WITH THE STANDARD IEC 62040-3 2135

(1,j)
The real coefficients of the transfer functions in (10) are where Cdq is the first row of the Cdq matrix in (8), and
given as j = 1, 2, . . . 8. The state variable representation of the PD is
given as
b0 = 0.2276 b1 = 0.7325 b2 = 0.08777
xc (k + 1)T = Gc xc (kT ) + Hc ed (kT ) (20)
b3 = 0.2166 b4 = 0.03064
   
c0 = 0.01096 c1 = 0.111 c2 = 0.008563 0 0 1
where Gc = , Hc = , and ed (kT ) is the sampled
1 0 0
c3 = 0.03678 c4 = 0.001553
voltage error of axis “d” given by
a1 = 0.2007 a2 = 0.5854
a3 = 0.06041 a4 = 0.09056. ed (kT ) = rd (kT ) − yd (kT ). (21)

The control action can be written as

These coefficients have been obtained with a sampling rate of
T = 198.41 µs.
ud (kT ) = Cc xc (kT ) + Dc ed (kT ) + uim (mTim ) (22)
The real coefficients of the closed-loop transfer func-
tion GMF (zim ) in (13) obtained at 2T = 396.83 µs are the
where Cc = [k1 k2 ], Dc = 0, uim (mTim ) is the internal-
following:
model-based control action at sampling rate Tim , and xc (kT ) =
[ed (k − 1) ed (k − 2)]T . In order to obtain an equivalent
n0 = 1.01 n1 = 0.274 n2 = 0.0366 slow-rate state-space representation of the plant plus a PD
n3 = 0.013 n4 = 0.0010 n5 = 2.99 × 10−5 compensator at 2T , we can write (18) and (20) as

d1 = 0.12 d2 = 0.103 d3 = 0.012    (i,1)  

xp (k + 2)T G2dq Hdq Cc Gc xp (kT )
=
d4 = 0.0037 d5 = 0.00079 d6 = 5.23 × 10−5 xc (k + 2)T (1,j) xc (kT )
−Hc Cdq Gdq G2c
d7 = 1.36 × 10−6 .  (i,1) (i,1)
Hdq Cc Hc Gdq Hdq
+
(1,j) (i,1)
Space-state representation of the single-rate equivalent Gc Hc −Hc Cdq Hdq
closed-loop system in Fig. 15.    (i,1)
ed (kT ) Hdq
Here, we describe the state-space representation of the + + rd (k + 1)
ud (kT ) Hc
single-rate closed-loop system operating at sampling rate Tim ,

which has been used to obtain the sampled transfer function (i,1)
Hdq
GMF (zim ) in (13). + uim (mTim ). (23)
Consider the state-space equations of the plant and the PD 0
compensator, i.e.,
Substituting (21) and (22) in (23), we find the equivalent
(i,1) single-rate state-space representation of the system in Fig. 15,
xp (k + 1)T = Gdq xp (kT ) + Hdq ud (kT ) (18)
i.e., (24) shown at the bottom of the page.
Finally, the sampled transfer function GMF (zim ) in (13) can
(i,1)
where Gdq is given in (8), and Hdq is the first column of the be obtained by applying the Z transform to (24), which leads to
Hdq matrix in (8), where i = 1, 2, . . . 8. The output of the plant
is given by GMF (zim ) = Csr (zim I − Gsr )−1 Hsr (25)
(1,j)
yd (kT ) = Cdq xp (kT ) (19) where the matrix Csr = [01×4 1 01×5 ].

   (i,1) (1,j) (i,1) (i,1)  

xp (k + 2)T G2dq − Hdq Cc Hc Cdq Hdq Cc Gc + Gdq Hdq Cc xp (kT )
=
xc (k + 2)T (1,j) (1,j) (1,j) (i,1) xc (kT )
−Hc Cdq Gdq − Gc Hc Cdq G2c − Hc Cdq Hdq Cc
 (i,1) (i,1)
 (i,1)
 (i,1) (i,1)

Hdq Cc Hc + Gdq Hdq Hdq Hdq + Gdq Hdq
+ rd (k) + rd (k + 1) + uim (mTim )
(1,j) (i,1) (1,j) (i,1)
Gc Hc − Hc Cdq Hdq Hc −Hc Cdq Hdq
   
xp (k + 2)T xp (kT )
= Gsr + Hr rd (k) + Hrr rd (k + 1) + Hsr uim (mTim ) (24)
xc (k + 2)T xc (kT )
2136 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007
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[24] F. Botterón, H. Pinheiro, H. A. Gründling, J. R. Pinheiro, and
H. L. Hey, “An improved discrete model for three-phase voltage-fed space
vector modulated converters,” in Proc. 7th Brazilian Power Electron.
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[25] F. Botterón, H. Pinheiro, H. A. Gründling, J. R. Pinheiro, and
H. L. Hey, “Digital voltage and current controllers for three-phase
PWM inverter for UPS applications,” in Conf. Rec. IEEE IAS Annu.
Meeting, Oct. 2001, vol. 4, pp. 2667–2674.
Fernando Botterón was born in Rosário, Argentina,
in 1967. He received the B.S. degree in electri-
cal engineering from the Universidad Nacional de
Misiones, Misiones, Argentina, in 1995, and the
M.S. and Ph.D. degrees in electrical engineering
from the Federal University of Santa Maria, Santa
Maria, Brazil, in 2001 and 2005, respectively.
Since 1996, he has been a Professor in the
Departamento de Electrónica, Universidad Nacional
de Misiones. His research interest includes discrete-
time control and digital modulation techniques ap-
plied to static converters for medium- and high-power uninterruptible power
supplies (UPS).
Dr. Botterón is a member of the Brazilian Power Electronics Society
(SOBRAEP) and the Brazilian Society of Automatic (SBA).
Humberto Pinheiro was born in Santa Maria,
Brazil, in 1960. He received the B.S. degree from the
Federal University of Santa Maria, Santa Maria, in
1983, the M.Eng. degree from the Federal University
of Santa Catarina, Florianópolis, Brazil, in 1987,
and the Ph.D. degree from Concordia University,
Montreal, QC, Canada, in 1999.
From 1987 to 1990, he was a Research Engineer
of a Brazilian UPS company and joined the Pontíficia
Universidade Católica do Rio Grande do Sul, Brazil,
where he lectured on power electronics. Since 1991,
he has been with Federal University of Santa Maria, as an Adjunct Professor.
His research interests are uninterruptible power supplies, wind power systems,
and control applied to power electronics.