A collaborative design from schematic to layout: based on MCP technology

Maoyun Pan 1, Fengman Liu 1, Liqiang Cao 1, Ziguan Zhou 2 Yang Li 3

1.
Institute of Microelectronics of Chinese Academy of Sciences
B503, 3#, BEITUCHENG West, CHAOYANG District, Beijing, 100029, China
2.
Branch company of Communication and Electricity technology of State Grid Electricity Research Institute
16#, NANSHAO Town South Middle, CHANGPING District, Beijing, 100029, China
3.
Acconsys science and technology limited company
Telephone: 1. 86-010-82995675 3.86-10-68058081 Fax: 1. 86-010-82995591
Email: panmaoyun@ime.ac.cn liufengman@ime.ac.cn caoliqiang@ime.ac.cn 2. zzg@epri.sgcc.com.cn
1. 1. 1.
3.
sunyli@acconsys.com

market, since including several die in one package reduces

Abstract
design time and allows products to be introduced into the
With the rapid development of electronics technology,
market compared to integrating all the desired functions on a
the technology continues to be miniaturization, multi-
new single chip more quickly[3-5]. Therefore, MCP
functionality, high bandwidth and low power consumption.
technology is gradually becoming the main stream in system
System integration becomes more and more important.
integration.
Multi-chip package (MCP) technology is one of the advanced
technologies for system integration. A system or subsystem In this paper, four bare chips and some passive
components are integrated into one substrate by using MCP
contains two-dimensional spaced multi-chips and a mass of
passive components can be integrated into one single package technology. It is a BGA (Ball Grid Array) package design.
using MCP technology. In this paper, there are four wire bond The remainder of this paper is organized as follows. In
section 2, schematic design is firstly introduced. The layout
(WB) based bare chips and many passive components such as
resistors and capacitors. To reduce the dimension of system, and routing is presented in section 3. Then in section 4, a test
the MCP technology was used. Because of the complex of the circuit board for this package chip is described. Finally,
conclusions are presented.
system, a collaborative design process is necessary. It
includes schematic design, layout and routing, design for 2. Schematic design
manufacturability (DFM) and design for testability (DFT). In There are a lot of design tools about schematic and
order to test the performance of the package, a test board was layout design in the market. A collaborative design from
designed and manufactured. schematic to layout by Mentor Graphics software is presented
in this paper. Before the schematic design, we should
1. Introduction
establish a component library, which includes schematic
Nowadays small size, multi-functional, high-speed, and
symbols and layout cells. The schematic symbols include
high performance are the development of electronic
electric information of electronic components, such as net
technology. In order to meet the requirements of a rapidly
information. The layout cells contain the information about
increasing integration density and decreasing form factor in
the frame size of components and their pads shape and size.
electronic devices, two kinds of technology have developed
Then one schematic symbol and one corresponding layout
rapidly. One is system on chip (SOC) technology and the
cell should be combined into one part. Through this way we
other is System-in-Package (SiP). The SOC technology
can realize a collaborative design from schematic to layout.
makes the high-performance digital circuits and analog
circuits into a single bare chip. There are big challenges for Now, component library for the following packaging
design is established. Schematic can be designed in the case
actual product application due to manufacture process
of knowing the chip information and the logical connection.
complexity, test difficulty and high cost. An alternative that
achieves the same function as the SOC is SiP technology, Due to a decoupling capacitor need to be connected to each
power input pin of the digital chip in order to avoid the
which combing more than one bare chip and passive
power system noise affecting the performance of the digital
components with a multilayer substrate structure in two
dimension or three dimension[1-2]. As a type of SiP chip, a complex net is presented among multi-chips, passive
components and BGA balls. After four bare chips and some
technology, the multi-chip package (MCP) is one of the most
passive components are connected, what we are considered is
practical and effective technology for miniaturizing the
dimension and reducing the design and manufactory circle. the quantity of the BGA balls. This involves the distribution
of the power pins and ground pins of the BGA balls. Usually
The obvious advantages of MCP technology are compatible
the number of signal pins, power pins and ground pins are
with single package, and reducing the system power
consumption and propagation delay between multi-chips and presented as a ratio that is 4:1:1. Fig.1 shows a typical
distribution of these three kinds of pins. There are three kinds
passive components. The utilization of MCP technology can
of power and two kinds of ground in this design.
also save space, weight and cost for the electronic device with
improving reliability. Meanwhile MCP help reduce time to

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Fig.1 The distribution of signal pins, power pins and
ground pins
Considering the DFM of package and the overall circuit
design, we determine the quantity of the BGA balls is
13*13=169, each BGA pins is defined as a swappable pin, in
order to facilitate the optimization of routing. Fig.2 shows the
schematic of the MCP design.
Fig.2 Schematic of the MCP design
Considering DFT of the packaging system, there are
some BGA pins reserved for test pins in order to detect the
state of the signal during schematic design process，such as
the BGA pin SCL1 and SDA1.
3. Layout and routing
This section contains placement, wire bonding, routing,
design rule checking and gerber file output. The gerber file is
sent to chip packaging factory for fabrication.
(1) Placement
A design library which contains the multi-chips and
passive components of this packaging design has been
obtained. We can place all of them into packaging. Because
of the net defined in the previous schematic, Flight-lines can
be displayed to guide in the optimal placement and
2012 International Conference on Electronic Packaging Technology & High Density Packaging
orientation of multi-chips and passive components. Fig.3
shows a good placement according to the flight-lines.
(2) Wire bonding
After placement, wire bonding technology is used in
DIE pins fan-out. Wire spacing, maximum and minimum
wire length is related to manufacturing capability of chip
packaging factory. So we need to consider the DFM. Fig.4
shows the wire bonding diagram of each chip.
Fig.3 Drawing of placement
Fig.4 The wire bonding diagram of each chip.
(3) Routing and design rule checking
There are four stacking layers for the substrate, in an
order of top signal layer, ground layer, power layer and
bottom signal layer. Before routing, the design rules should
be set, such as the width of the trace and the distance between
them. It is important to note that this package system owns
an analog bare chip and the others are digital bare chips.
According to conventional electrical design rules, ground
plane need to be divided into analog ground and digital
ground to prevent the simultaneous switching noise of digital
circuits from affecting analog circuits. This design can
effectively improve noise isolation. In addition, in order to
obtain better signal integrity, substrate stack-up and
transmission lines layout are based on the principle that
signal should always follow the shortest signal return path. In
91
order to ensure the correctness of the routing, design rules
check (DRC) is needed.
Fig.5 shows the layout routing of the overall packaging
system. If connections between chips and passive components
are modified in the schematic design, layout must be changed
accordingly. After repeated modification and DRC, A gerber
file is exported, It will be sent to chip packaging factory for
fabrication. Finally, we can get a packaging chip shown in
the bottom of Fig.6. Fig.6 is a comparison picture between
MCP and PCB assembly. In the upper portion of the diagram,
four bare chips with a lot of passive components around them
are very disorderly distributed on PCB, it will increase the
size of the overall PCB. While using MCP technology, these
bare and passive components can be greatly integrated into
one package so that space and PCB size can be largely
reduced.

Fig.6 A comparison picture between MCP and PCB

Assembly

4、Testing
In order to validate the correctness of this MCP, We
design a test board for the testing system. The test board can
be seen in Fig.7.

(a) Plan of layout routing

Fig.7 The diagram of the test board

(b) Three-dimensional diagram of layout routing
Fig.5 Layout routing of the overall packaging system Trough writing the MCU (Microprogrammed Control
Unit) in the package, the program will initialize all pins of
the MCU into IO model. We will observe the signal level of
the IO pins whether vary from height to low. For the other
chips, we can test them through the corresponding reading
and writing programs. This design tests the signal state of
each pin of packaging chip, and it displays that the
packaging system can work.

2012 International Conference on Electronic Packaging Technology & High Density Packaging 92
Conclusions
MCP technology provides advantages for space,
function, power consumption. This BGA package design
integrate four bar chips and some passive components in one
substrate by using MCP technology, we have test the
packaging chip, and find that it can work.
Acknowledgments
Thanks to the support of Mentor Graphics software and
the guidance of Yang Li engineer. Meanwhile, thanks to the
test environment provided by State Grid Electricity Research
Institute.
This work was supported by the National S&T Major
Project (No. 2009ZX02038), the CAS/SAFEA International
Partnership Program for Creative Research Teams and
Hundred Talent Program of the CAS.
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