National Institute of Technology, Raipur, CG- 492010

M.Tech( ETC-VLSI Design and Embedded system) -1st Semester

ET41112VL (ADVANCED VLSI DESIGN)
Second Examination (Oct-2018)

Time :01 hr 15min M. Marks: 15

Note: 1) Attempt the questions serially.
2) Assume suitable data wherever necessary Roll No.

Q1. Draw 6T SRAM cell with proper labelling. And explain the read and write cycle
with timing diagram. (1,2,2)

Q2. Draw DRAM cell with proper labelling. And explain the read and write cycle with
timing diagram. (1,2,2)

Q3. Design and explain 4-bit carry look ahead adder circuit.
OR
Design and explain 4-bit multiplier circuit. (5)
 National Institute of Technology, Raipur, CG- 492010
M.Tech( ETC-VLSI Design and Embedded system) -1st Semester
ET41112VL (ADVANCED VLSI DESIGN)
Second Examination (Oct-2018)

Time :01 hr 15min M. Marks: 15

Note: 1) Attempt the questions serially.
2) Assume suitable data wherever necessary Roll No.

Q1. Draw 6T SRAM memory cell with proper labelling. And explain the read and write
cycle with timing diagram. (1,2,2)

Q2. Draw DRAM memory cell with proper labelling. And explain the read and write
cycle with timing diagram.
(1,2,2)

Q3. Design and explain 4-bit carry look ahead adder circuit.
OR
Design and explain 4-bit multiplier circuit. (5)