National Institute of Technology, Raipur, CG- 492010

M.Tech( ETC-VLSI Design and Embedded system) -1st Semester

ET41112VL (ADVANCED VLSI DESGN)
End Semester Examination (Autumn-2018 )

Time :3 hr M. Marks: 100

Note: 1) Attempt two parts from each question. MIN MARKS:40
2) Assume suitable data wherever necessary Roll No.

Q1. (a) Design a 3-stage cascaded domino logic circuit for the following function
F= (A+B+C)(AB+CD)+ABC (10)
(b) Explain charge leakage and charge sharing problem in dynamic circuits with
neat diagram. How it can be avoided? (10)
(c) Derive the equation for optimized stage effort for a N-stage inverter chain.
Q2. (a) State the design rules and explain them with the help of suitable diagram.
(10)
(b) Sketch the stick diagram and Layout of the minimum size 2-input NAND
gate according to lamba rules with appropriate labelling. Take λ as a unit size
length. (10)
(c) Sketch the stick diagram and Layout of the minimum size 2-input NOR gate
according to lamba rules with appropriate labelling. Take λ as a unit size
length. (10)

Q3. (a) Implement a 2x2 DRAM array with 4T DRAM cell along with a sense
amplifier and R/W circuitry with appropriate aspect ratio. (10)
(b)State the steps for the implementation of Booth’s Algorithm for
multiplication. Multiply 4 x -5 using Booth’s Algo. (6+4)
(c) Explain the Construction and working of FGMOS. (5+5)

Q4. (a) Explain Maze routing algoritm with an example (10)

(b) Perform the first pass of KL algorithm clearly describing the steps for
partioning.

(10)
(c) Use Left edge Algorithm to route the following
 (10)

P.T.O
Q5. (a) Draw a 4:1 Mux using nFET pass transistor. Write the Verilog code using
structural modelling and using “nmos” as an instance. (4+6)
(b) Draw gated D-latch with enable control using AOI gate. Write the structural
Verilog code accordingly. (2+8)
(c) Draw a 4:1 priority encoder using CMOS combinational logic. Write the
Verilog code accordingly . (4+6)