//SR-FLIPFLOP

module srff(q,qb,clk,s,r);
input clk,s,r;
output reg q,qb;

always @(posedge clk)

begin
q=1'b0;
qb=1'b1;
case({s,r})
2'b00:begin
q=1'b0;
qb=1'b1;
end

2'b10:begin
q=1'b1;
qb=1'b0;
end

2'b01:begin
q=1'b0;
qb=1'b1;
end

default:begin
q=1'b0;
qb=1'b1;
end
endcase
end
endmodule

//TEST-BENCH for SR
module srtest();
reg tclk,ts,tr;
wire tq,tqb;

srff s1(tclk,ts,tr,tq,tqb);

initial
tclk=1'b0;

always #5 tclk=~tclk;

initial
begin
ts=1'b0; tr=1'b0;
#10 ts=1'b0; tr=1'b1;
#10 ts=1'b1; tr=1'b0;
#10 ts=1'b1; tr=1'b1;
end
endmodule

//D-FLIPFLOP

module dff(q,qb,clk,d);
input clk,d;
output reg q,qb;

always @(posedge clk)

begin
q=1'b0;
qb=1'b1;
if(d)
q=d;
qb=~q;
end
endmodule

//TEST-BENCH for D
module test();
reg tclk,td;
wire tq,tqb;

dff d1(tq,tqb,tclk,td);

initial
tclk = 1'b0;
always #5 tclk=~tclk;

initial
begin
td=1'b0;
#5 td=1'b1;
end
endmodule

(1)//T-flipflop
module tff(q,qb,clk,rst,t);
input t,clk,rst;
output q,qb;
reg q, qb;
reg [25:0]clkdiv;

always @(posedge clk)

begin
clkdiv=clkdiv+1;
end

always @(posedge clkdiv)

begin
if(rst==1'b1)
begin
#5 q=0;
#5 qb=1;
end
else
case(t)
1'b0: begin #5 q=q; qb=qb; end
1'b1: begin #5 q=~(q); qb=~(qb); end
default: begin end
endcase
end

endmodule
(1)//Test Bench for T-flipflop
module testt();
reg tt,tclk,trst;
wire tq,tqb;
tff t1(tq,tqb,tclk,trst,tt);

initial
begin
tclk=1'b0;
trst=1'b1;
end

always #5 tclk=~tclk;

initial
begin
#10 tt=1'b0;
#10 tt=1'b1;
end
endmodule

(2)//T-flipflop
module tff(q,qb,clk,rst,t);
input t,clk,rst;
output q,qb;
reg q,qb;

initial
begin
q=1'b0;
qb=1'b1;
end

always @(posedge clk)

begin
if(rst==1)
begin
q=1'b0;
qb=~q;
end

else if(t==1b1)
begin
q=1'b1;
qb=~q;
end

else
begin
q=1'b0;
qb=~q;
end
end
endmodule

(2)//Test Bench for T-flipflop

module test();
reg tt,tclk,trst;
wire tq,tqb;

tff t1(tq,tqb,tclk,trst,tt);

initial
begin
tclk=1'b0;
trst=1'b1;
tt=1'b0;
end

always #5 tclk=~tclk;

initial
#5 trst=1'b0;

always #5 tt=~tt;
endmodule

(1)// JK-Flipflop
module jkff(q,qb,clk,rst,j,k);
input clk,rst,j,k;
output reg q=0;
output reg qb=1;
reg [19:0]clkdiv;

always @(posedge clk)

begin
clkdiv=clkdiv+1;
end

always @(posedge clkdiv[17])

begin
if(rst)
begin
q=1'b0;
qb=~q;
end

else
begin
case({j,k})
2'b00: q=q;
2'b01: q=1'b0;
2'b10: q=1'b1;
2'b11: q=~q;
endcase
end
end
endmodule

(1)//Test for JK-Flipflop

module test();
reg tclk,trst,tj,tk;
wire tq,tqb;

jkff j1(tq,tqb,tclk,trst,tj,tk);

initial
tclk=1'b0;
always #5 tclk=~tclk;

initial
begin
trst=1'b0;
#15 trst=1'b1;
#15 trst=1'b0;
end

initial
begin

tj=1'b0; tk=1'b0;
#5 tj=1'b0; tk=1'b1;
#5 tj=1'b1; tk=1'b0;
#5 tj=1'b1; tk=1'b1;
end
endmodule

(2)//JK-Flipflop

module jkff(q,qb,clk,rst,j,k);
input clk,rst,j,k;
output q.qb;
reg q,qb;

reg [19:0]clkdiv;

always @(posedge clk)

begin
clkdiv=clkdiv+1;
end

always @(posedge clkdiv[17])

begin
if(rst==1)
begin
q=1'b0;
qb=~q;
end

else
begin
case({j,k})
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=~q;
endcase
end
end
endmodule

---------------------------------------------------------

//Dataflow model

module halfadd(a,b,s,c);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

//Structural model

module ha(a,b,s,c);
input a,b;
output s,c;
xor a1(s,a,b);
and a2(c,a,b);
endmodule
//Behavioral model
module ha(a,b,s,c);
input a,b;
output reg s,c;
always @(a,b)
begin
if(a==1'b0 && b==1'b0)
begin
s=1'b0;
c=1'b0;
end

else if(a==1'b0 && b==1'b1)

begin
s=1'b1;
c=1'b0;
end

else if(a==1'b1 && b==1'b0)

begin
s=1'b1;
c=1'b0;
end

else
begin
s=1'b0;
c=1'b1;
end

end
endmodule