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Team Nexperia
 PHD108NQ03LT
N-channel TrenchMOS logic level FET
Rev. 04 — 5 June 2009 Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.

1.2 Features and benefits

„ Low conduction losses due to low „ Suitable for logic level gate drive
on-state resistance sources
„ Simple gate drive required due to low
gate charge

1.3 Applications
„ DC-to-DC convertors „ Switched-mode power supplies

1.4 Quick reference data

Table 1. Quick reference
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 25 V
ID drain current Tmb = 25 °C; VGS = 5 V; see - - 75 A
Figure 1; see Figure 3
Ptot total power Tmb = 25 °C; see Figure 2 - - 187 W
dissipation
Avalance ruggedness
EDS(AL)S non-repetitive VGS = 10 V; Tj(init) = 25 °C; - - 180 mJ
drain-source ID = 43 A; Vsup ≤ 25 V;
avalanche energy unclamped; tp = 0.25 ms;
RGS = 50 Ω
Dynamic characteristics
QGD gate-drain charge VGS = 4.5 V; ID = 25 A; - 5.6 - nC
VDS = 12 V; Tj = 25 °C; see
Figure 12; see Figure 13
Static characteristics
RDSon drain-source VGS = 10 V; ID = 25 A; - 5.3 6 mΩ
on-state resistance Tj = 25 °C; see Figure 10;
see Figure 11
NXP Semiconductors PHD108NQ03LT
N-channel TrenchMOS logic level FET

2. Pinning information
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1 G gate
mb D
2 D drain [1]
3 S source
G
mb D mounting base; connected to
drain mbb076 S
2
1 3

SOT428
(SC-63; DPAK)

[1] It is not possible to make a connection to pin 2.

3. Ordering information
Table 3. Ordering information
Type number Package
Name Description Version
PHD108NQ03LT SC-63; plastic single-ended surface-mounted package (DPAK); 3 leads (one SOT428
DPAK lead cropped)

4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 25 V
VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 25 V
VGS gate-source voltage -20 20 V
ID drain current VGS = 5 V; Tmb = 25 °C; see Figure 1; see Figure 3 - 75 A
VGS = 5 V; Tmb = 100 °C; see Figure 1 - 75 A
IDM peak drain current tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3 - 240 A
Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 187 W
Tstg storage temperature -55 175 °C
Tj junction temperature -55 175 °C
Source-drain diode
IS source current Tmb = 25 °C - 75 A
ISM peak source current tp ≤ 10 µs; pulsed; Tmb = 25 °C - 240 A
Avalance ruggedness
EDS(AL)S non-repetitive VGS = 10 V; Tj(init) = 25 °C; ID = 43 A; Vsup ≤ 25 V; - 180 mJ
drain-source avalanche unclamped; tp = 0.25 ms; RGS = 50 Ω
energy

PHD108NQ03LT_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 5 June 2009 2 of 12

NXP Semiconductors PHD108NQ03LT
N-channel TrenchMOS logic level FET

03ar58 03aa16
120 120

Ider Pder
(%) (%)

80 80

40 40

0 0
0 50 100 150 200 0 50 100 150 200
Tmb (°C) Tmb (°C)

Fig 1. Normalized continuous drain current as a Fig 2. Normalized total power dissipation as a
function of mounting base temperature function of mounting base temperature

03ar59
103

ID Limit RDSon = VDS / ID

(A)
tp = 10 µs

102
100 μ s

DC 1 ms
10
10 ms

1
1 10 VDS (V) 102

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

PHD108NQ03LT_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 5 June 2009 3 of 12

NXP Semiconductors PHD108NQ03LT
N-channel TrenchMOS logic level FET

5. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-mb) thermal resistance from see Figure 4 - - 0.8 K/W
junction to mounting
base
Rth(j-a) thermal resistance from minimum footprint; mounted on a - 75 - K/W
junction to ambient printed-circuit board; vertical in still air
mounted on a printed-circuit board; - 50 - K/W
vertical in still air; SOT404 minimum
footprint

03ar60
1

Zth(j-mb) δ = 0.5
(K/W)

0.2

0.1
10-1

0.05 tp
P δ=
T
0.02

single pulse

tp t
T
-2
10
10-5 10-4 10-3 10-2 10-1 1
tp (s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

6. Characteristics
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source ID = 250 µA; VGS = 0 V; Tj = 25 °C 25 - - V
breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 22 - - V
VGS(th) gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C; see 1 1.5 2 V
voltage Figure 8; see Figure 9
ID = 1 mA; VDS = VGS; Tj = 175 °C; see 0.5 - - V
Figure 8; see Figure 9
ID = 1 mA; VDS = VGS; Tj = -55 °C; see - - 2.2 V
Figure 8; see Figure 9
IDSS drain leakage current VDS = 25 V; VGS = 0 V; Tj = 25 °C - - 1 µA
VDS = 25 V; VGS = 0 V; Tj = 175 °C - - 500 µA
IGSS gate leakage current VGS = 10 V; VDS = 0 V; Tj = 25 °C - 0.02 100 nA
VGS = -10 V; VDS = 0 V; Tj = 25 °C - 0.02 100 nA
PHD108NQ03LT_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 5 June 2009 4 of 12

NXP Semiconductors PHD108NQ03LT
N-channel TrenchMOS logic level FET

Table 6. Characteristics …continued

Symbol Parameter Conditions Min Typ Max Unit
RDSon drain-source on-state VGS = 5 V; ID = 25 A; Tj = 25 °C; see - 6.7 7.5 mΩ
resistance Figure 10; see Figure 11
VGS = 5 V; ID = 25 A; Tj = 175 °C; see - 12.1 13.5 mΩ
Figure 10; see Figure 11
VGS = 10 V; ID = 25 A; Tj = 25 °C; see - 5.3 6 mΩ
Figure 10; see Figure 11
RG internal gate resistance f = 1 MHz; Tj = 25 °C - 1.2 - Ω
(AC)
Dynamic characteristics
QG(tot) total gate charge ID = 25 A; VDS = 12 V; VGS = 4.5 V; - 16.3 - nC
Tj = 25 °C; see Figure 12; see Figure 13
ID = 0 A; VDS = 0 V; VGS = 4.5 V; - 12.5 - nC
Tj = 25 °C
QGS gate-source charge ID = 25 A; VDS = 12 V; VGS = 4.5 V; - 4 - nC
QGS1 pre-threshold Tj = 25 °C; see Figure 12; see Figure 13 - 2.5 - nC
gate-source charge
QGS2 post-threshold - 1.5 - nC
gate-source charge
QGD gate-drain charge - 5.6 - nC
VGS(pl) gate-source plateau ID = 25 A; VDS = 12 V; Tj = 25 °C; see - 2.4 - V
voltage Figure 12; see Figure 13
Ciss input capacitance VDS = 12 V; VGS = 0 V; f = 1 MHz; - 1375 - pF
Tj = 25 °C; see Figure 14
VDS = 0 V; VGS = 0 V; f = 1 MHz; - 2120 - pF
Tj = 25 °C; see Figure 14
Coss output capacitance VDS = 12 V; VGS = 0 V; f = 1 MHz; - 640 - pF
Crss reverse transfer Tj = 25 °C; see Figure 14 - 250 - pF
capacitance
td(on) turn-on delay time VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V; - 15 - ns
tr rise time RG(ext) = 5.6 Ω; Tj = 25 °C - 38 - ns
td(off) turn-off delay time - 32 - ns
tf fall time - 25 - ns
Source-drain diode
VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see - 0.86 1.2 V
Figure 15
trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; - 34 - ns
Qr recovered charge VDS = 25 V; Tj = 25 °C - 21 - nC

PHD108NQ03LT_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 5 June 2009 5 of 12

NXP Semiconductors PHD108NQ03LT
N-channel TrenchMOS logic level FET

03ar67 03ar63
4000 80
C ID
(pF) (A)
Ciss
3000 60

2000 Crss 40

1000 20
Tj = 175 °C 25 °C

0 0
0 2 4 6 8 10 0 1 2 3 4
VGS (V) VGS (V)

Fig 5. Input and reverse transfer capacitances as a Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values function of gate-source voltage; typical values

03ar61 03aa33
80 2.5
VGS (V) = 10 6 5 4.5 4
VGS(th)
ID
3.5 (V)
(A)
2 max
60

1.5 typ
3
40

1 min

2.5
20
0.5

2
0 0
0 0.2 0.4 0.6 0.8 1 -60 0 60 120 180
VDS (V) Tj (°C)

Fig 7. Output characteristics: drain current as a Fig 8. Gate-source threshold voltage as a function of
function of drain-source voltage; typical values junction temperature

PHD108NQ03LT_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 5 June 2009 6 of 12

NXP Semiconductors PHD108NQ03LT
N-channel TrenchMOS logic level FET

03aa36 03ar62
10-1 15
ID VGS (V) = 3.5
(A) RDSon
10-2 (mΩ)

10
10-3 4

min typ max 4.5

5
6
10-4
10
5

10-5

10-6 0
0 1 2 3 0 20 40 60 80
VGS (V) ID (A)

Fig 9. Sub-threshold drain current as a function of Fig 10. Drain-source on-state resistance as a function
gate-source voltage of drain current; typical values

03af18 03ar64
2 10
VGS ID = 25 A
a (V) Tj = 25 °C
8
1.5

6
12 V VDS = 19 V
1

0.5
2

0 0
-60 0 60 120 180 0 10 20 30 QG (nC) 40
Tj (°C)

Fig 12. Gate-source voltage as a function of gate

Fig 11. Normalized drain-source on-state resistance charge; typical values
factor as a function of junction temperature

PHD108NQ03LT_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 5 June 2009 7 of 12

NXP Semiconductors PHD108NQ03LT
N-channel TrenchMOS logic level FET

03ar66
104
VDS
C
ID (pF)

VGS(pl)

Ciss
VGS(th) 103

VGS
Coss
QGS1 QGS2

QGS QGD
QG(tot)
Crss
003aaa508

Fig 13. Gate charge waveform definitions 102

10-1 1 10 102
VDS (V)

Fig 14. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical
values

03ar65
80
IS
(A)

60

40

175 °C Tj = 25 °C
20

0
0.2 0.4 0.6 0.8 1 1.2
VSD (V)

Fig 15. Source current as a function of source-drain voltage; typical values

PHD108NQ03LT_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 5 June 2009 8 of 12

NXP Semiconductors PHD108NQ03LT
N-channel TrenchMOS logic level FET

7. Package outline

Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428

E A A

b2 A1 E1

mounting
base D2

D1
HD

2
L2 L
1 3 L1

b1 b w M A c

e1

0 5 10 mm
scale

DIMENSIONS (mm are the original dimensions)

D2 E1 L1 y
UNIT A A1 b b1 b2 c D1 E e e1 HD L L2 w
min min min max
2.38 0.93 0.89 1.1 5.46 0.56 6.22 4.0 6.73 4.45 10.4 2.95 0.5 0.9
mm 2.285 4.57 0.2 0.2
2.22 0.46 0.71 0.9 5.00 0.20 5.98 6.47 9.6 2.55 0.5

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
06-02-14
SOT428 TO-252 SC-63
06-03-16

Fig 16. Package outline SOT428 (DPAK)

PHD108NQ03LT_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 5 June 2009 9 of 12

NXP Semiconductors PHD108NQ03LT
N-channel TrenchMOS logic level FET

8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PHD108NQ03LT_4 20090605 Product data sheet - PHB_PHD_PHU108NQ03LT_3
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Type number PHD108NQ03LT separated from data sheet
PHB_PHD_PHU108NQ03LT_3.
PHB_PHD_PHU108NQ03LT_3 20050418 Product data sheet 2004070095 PHP_PHB_PHD108NQ03LT-02
(9397 750 14707)
PHP_PHB_PHD108NQ03LT-02 20020911 Product data - PHP_PHB_PHD108NQ03LT-01
(9397 750 10159)
PHP_PHB_PHD108NQ03LT-01 20011218 Product data - -
(9397 750 09065)

PHD108NQ03LT_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 5 June 2009 10 of 12

NXP Semiconductors PHD108NQ03LT
N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

Document status [1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.

9.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.

Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PHD108NQ03LT_4 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 04 — 5 June 2009 11 of 12

NXP Semiconductors PHD108NQ03LT
N-channel TrenchMOS logic level FET

11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 General description . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features and benefits . . . . . . . . . . . . . . . . . . . . .1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
3 Ordering information . . . . . . . . . . . . . . . . . . . . . .2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4
6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .4
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
9.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10 Contact information. . . . . . . . . . . . . . . . . . . . . . 11

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2009. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 June 2009
Document identifier: PHD108NQ03LT_4