RAM

jump
000 BSA 200 ret
001 HLT map next
MDR

ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U FC FD
A 0- I
201 LDA 300 0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
000
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
PC points to next
FC NOP NOP NOP F JMP 88
instruction in RAM.
BUN routine FD NOP PCTAR NOP U JMP FE
CAR points to
BSA routine FE NOP READ INCPC U JMP FF
address of the
micro instruction FF NOP DRTAR NOP U MAP --
of fetch (FC) in
ROM
Indirect routine

Fetch routine
Fetch Clock 1
Power ON, PC at 000 of RAM and CAR at FC(Bold letters )at ROM
First Clock fetches micro Instruction at address FC from ROM (red lines)
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U FD FD
A 0- I
201 LDA 300 0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
000
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Execute Clock 2
Interrupt bit F=0, NO external interrupt
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U FD FE
A 0- I
201 LDA 300 0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
000
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Fetch Clock 3
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U FE FE
0- I
201 LDA 300 000 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
000
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Execute Clock 4
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U FE FF
0- I
201 LDA 300 000 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
000
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Fetch Clock 5
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BSA 200
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U FF FF
0- I
201 LDA 300 000 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
001
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Execute Clock 6
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

BSA 200
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U FF 00
0- I
201 LDA 300 000 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
001
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Fetch Clock 7
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BSA 200
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U 58 FF
0- I
201 LDA 300 200 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
001
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
PC points to next
FC NOP NOP NOP F JMP 88
instruction in RAM.
BUN routine FD NOP PCTAR NOP U JMP FE
CAR points to
BSA routine FE NOP READ INCPC U JMP FF
address of the
micro instruction FF NOP DRTAR NOP U MAP --
of BSA (58) in ROM
Indirect routine

Fetch routine
Execute Clock 8
MAP-decodes Instruction :Loads address of micro instruction of BSA
in CAR and address given in BSA(I=0 direct) in MAR
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BSA 200
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U 58 59
0- I
201 LDA 300 200 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
001
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
58 NOP NOP PCTDR I JMP 59
BUN routine 59 ARTPC NOP NOP U JMP 5A

BSA routine 5A NOP WRITE INCPC U JMP FC

5B NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Fetch Clock 9
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

001 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U 59 59
0- I
201 LDA 300 200 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
001
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
58 NOP NOP PCTDR I JMP 59
BUN routine 59 ARTPC NOP NOP U JMP 5A

BSA routine 5A NOP WRITE INCPC U JMP FC

5B NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Execute Clock 10
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

001 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U 59 5A
0- I
201 LDA 300 200 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
001
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
58 NOP NOP PCTDR I JMP 59
BUN routine 59 ARTPC NOP NOP U JMP 5A

BSA routine 5A NOP WRITE INCPC U JMP FC

5B NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Fetch Clock 11
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

001 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U 5A 5A
0- I
201 LDA 300 200 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
1- F
200
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
58 NOP NOP PCTDR I JMP 59
BUN routine 59 ARTPC NOP NOP U JMP 5A

BSA routine 5A NOP WRITE INCPC U JMP FC

5B NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Execute Clock 12
External interrupt (F=1)arrives during execution of BSA
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

001 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U 5A 5B
0- I
201 LDA 300 200 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
1- F
200
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
58 NOP NOP PCTDR I JMP 59
BUN routine 59 ARTPC NOP NOP U JMP 5A

BSA routine 5A NOP WRITE INCPC U JMP FC

5B NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Fetch Clock 13
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

001 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FC 5A
0- I
201 LDA 300 200 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
1- F
201
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
58 NOP NOP PCTDR I JMP 59
BUN routine 59 ARTPC NOP NOP U JMP 5A

BSA routine 5A NOP WRITE INCPC U JMP FC

5B NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Execute Clock 14
Instruction BSA executed. Jump to fetch block to get next instruction
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

001 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FC FD
0- I
201 LDA 300 200 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
1- F
201
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
PC points to next
FC NOP NOP NOP F JMP 88
instruction in RAM.
BUN routine FD NOP PCTAR NOP U JMP FE
CAR points to
BSA routine FE NOP READ INCPC U JMP FF
address of the
micro instruction FF NOP DRTAR NOP U MAP --
of fetch (FC) in
ROM
Indirect routine

Fetch routine
Fetch Clock 1
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

001 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 88 FD
0- I
201 LDA 300 200 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
1- F
201
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Execute Clock 2
External interrupt (F=1) detected in fetch block, CAR jumps to interrupt block
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

001 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 88 89
0- I
201 LDA 300 200 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
1- F
201
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
PC points to next
88 NOP NOP PCTDR U JMP 89
instruction in RAM.
BUN routine 89 INTAR NOP NOP U JMP 8A
CAR points to
BSA routine 8A NOP WRITE NOP U JMP 8B
address of the
interrupt handling 8B NOP INTPC NOP U JMP FD
block (88) in ROM
Indirect routine

Fetch routine
Fetch Clock 3
External interrupt (F=1) processing starts
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 89 89
0- I
201 LDA 300 200 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
1- F
201
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
88 NOP NOP PCTDR U JMP 89
BUN routine 89 INTAR NOP NOP U JMP 8A

BSA routine 8A NOP WRITE NOP U JMP 8B

8B NOP INTPC NOP U JMP FD

Indirect routine

Fetch routine
Execute Clock 4
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 89 8A
0- I
201 LDA 300 200 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
1- F
201
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
88 NOP NOP PCTDR U JMP 89
BUN routine 89 INTAR NOP NOP U JMP 8A

BSA routine 8A NOP WRITE NOP U JMP 8B

8B NOP INTPC NOP U JMP FD

Indirect routine

Fetch routine
Fetch Clock 5
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 8A 8A
0- I
201 LDA 300 7FE A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
1- F
201
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
88 NOP NOP PCTDR U JMP 89
BUN routine 89 INTAR NOP NOP U JMP 8A

BSA routine 8A NOP WRITE NOP U JMP 8B

8B NOP INTPC NOP U JMP FD

Indirect routine

Fetch routine
Execute Clock 6
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 8A 8B
0- I
201 LDA 300 7FE A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
1- F
201
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
88 NOP NOP PCTDR U JMP 89
BUN routine 89 INTAR NOP NOP U JMP 8A

BSA routine 8A NOP WRITE NOP U JMP 8B

8B NOP INTPC NOP U JMP FD

Indirect routine

Fetch routine
Fetch Clock 7
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 8B 8B
0- I
201 LDA 300 7FE A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
1- F
201
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
88 NOP NOP PCTDR U JMP 89
BUN routine 89 INTAR NOP NOP U JMP 8A

BSA routine 8A NOP WRITE NOP U JMP 8B

8B NOP INTPC NOP U JMP FD

Indirect routine

Fetch routine
Execute Clock 8
External interrupt (F=1) processing
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 8B 8C
0- I
201 LDA 300 7FE A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
1- F
201
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
88 NOP NOP PCTDR U JMP 89
BUN routine 89 INTAR NOP NOP U JMP 8A

BSA routine 8A NOP WRITE NOP U JMP 8B

8B NOP INTPC NOP U JMP FD

Indirect routine

Fetch routine
Fetch Clock 9
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FD 8B
0- I
201 LDA 300 7FE A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
7FF
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
88 NOP NOP PCTDR U JMP 89
BUN routine 89 INTAR NOP NOP U JMP 8A

BSA routine 8A NOP WRITE NOP U JMP 8B

8B NOP INTPC NOP U JMP FD

Indirect routine

Fetch routine
Execute Clock 10
External interrupt (F) processing, reset interrupt flag F
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FD FE
0- I
201 LDA 300 7FE A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
7FF
3FF
IN OUT

7FE 201.
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Fetch Clock 11
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FE FE
0- I
201 LDA 300 7FF A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
7FF
3FF
IN OUT

7FE 201.
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Execute Clock 12
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FE FF
0- I
201 LDA 300 7FF A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
7FF
3FF
IN OUT

7FE 201.
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Fetch Clock 13
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BUN 100
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FF FF
0- I
201 LDA 300 7FF A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
000
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Execute Clock 14
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BUN 100
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FF 00
0- I
201 LDA 300 7FF A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
000
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Fetch Clock 15
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BUN 100
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 24 FF
0- I
201 LDA 300 100 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
000
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
PC points to next
FC NOP NOP NOP F JMP 88
instruction in RAM.
BUN routine FD NOP PCTAR NOP U JMP FE
CAR points to
BSA routine FE NOP READ INCPC U JMP FF
address of the
micro instruction FF NOP DRTAR NOP U MAP --
of BUN (24) in ROM
Indirect routine

Fetch routine
Execute Clock 16
MAP-decodes Instruction :Loads address of micro instruction of BUN
in CAR and address given in BUN (I=0, direct) in MAR
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BUN 100
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 24 25
0- I
201 LDA 300 100 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
000
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
24 NOP NOP NOP I CALL 80
BUN routine 25 ARTPC NOP NOP U JMP FC

BSA routine 26 NOP NOP NOP U JMP --

27 NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Fetch Clock 17
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BUN 100
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 25 25
0- I
201 LDA 300 100 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
000
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
24 NOP NOP NOP I CALL 80
BUN routine 25 ARTPC NOP NOP U JMP FC

BSA routine 26 NOP NOP NOP U JMP --

27 NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Fetch Clock 18
BUN (I=0, direct) , CALL condition fails
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BUN 100
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 25 26
0- I
201 LDA 300 100 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
000
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
24 NOP NOP NOP I CALL 80
BUN routine 25 ARTPC NOP NOP U JMP FC

BSA routine 26 NOP NOP NOP U JMP --

27 NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Fetch Clock 19
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BUN 100
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FC 26
0- I
201 LDA 300 100 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
100
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
24 NOP NOP NOP I CALL 80
BUN routine 25 ARTPC NOP NOP U JMP FC

BSA routine 26 NOP NOP NOP U JMP --

27 NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Fetch Clock 20
Instruction BUN executed. Jump to fetch block to get next instruction
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

BUN 100
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FC FD
0- I
201 LDA 300 100 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
100
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
PC points to next
FC NOP NOP NOP F JMP 88
instruction in RAM.
BUN routine FD NOP PCTAR NOP U JMP FE
CAR points to
BSA routine FE NOP READ INCPC U JMP FF
address of the
micro instruction FF NOP DRTAR NOP U MAP --
of fetch (FC) in
ROM
Indirect routine

Fetch routine
Fetch Clock 1
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

BUN 100
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FD FD
0- I
201 LDA 300 100 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
100
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Execute Clock 2
Interrupt bit F=0, NO external interrupt
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

BUN 100
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FC FD
0- I
201 LDA 300 100 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
100
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Fetch Clock 3
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

BUN 100
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FE FE
0- I
201 LDA 300 100 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
100
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Execute Clock 4
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

BUN 100
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FE FF
0- I
201 LDA 300 100 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
100
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Fetch Clock 5
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BUN 7FE
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FF FF
0- I
201 LDA 300 100 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
101
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Execute Clock 6
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BUN 7FE
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FF 00
0- I
201 LDA 300 100 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
101
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Fetch Clock 7
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
BUN 7FF
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 24 FF
1- I
201 LDA 300 7FE A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
101
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
PC points to next
FC NOP NOP NOP F JMP 88
instruction in RAM.
BUN routine FD NOP PCTAR NOP U JMP FE
CAR points to
BSA routine FE NOP READ INCPC U JMP FF
address of the
micro instruction FF NOP DRTAR NOP U MAP --
of BUN (24) in ROM
Indirect routine

Fetch routine
Execute Clock 8
MAP-decodes Instruction :Loads address of micro instruction of BUN
in CAR and address given in BUN (I=1, indirect) in MAR
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

BUN 7FE
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 24 25
1- I
201 LDA 300 7FE A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
101
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
24 NOP NOP NOP I CALL 80
BUN routine 25 ARTPC NOP NOP U JMP FC

BSA routine 26 NOP NOP NOP U JMP --

27 NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Fetch Clock 9
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

BUN 7FE
ALU 4-1 MUX 25
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 80 25
1- I
201 LDA 300 7FE A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
101
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
24 NOP NOP NOP I CALL 80
BUN routine 25 ARTPC NOP NOP U JMP FC

BSA routine 26 NOP NOP NOP U JMP --

27 NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Execute Clock 10
BUN (I=1, indirect) , CALL takes place
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

BUN 7FE
ALU 4-1 MUX 25
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 80 81
1- I
201 LDA 300 7FE A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
101
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
80 NOP READ NOP U JMP 81
BUN routine 81 NOP DRTAR NOP U RET ---

BSA routine 82 NOP NOP NOP U JMP --

83 NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Fetch Clock 11
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX 25

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 81 81
1- I
201 LDA 300 7FE A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
101
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
80 NOP READ NOP U JMP 80
BUN routine 81 NOP DRTAR NOP U RET ---

BSA routine 82 NOP NOP NOP U JMP --

83 NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Execute Clock 12
(I=1, indirect) routine
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX 25

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 81 82
1- I
201 LDA 300 7FE A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
101
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
80 NOP READ NOP U JMP 81
BUN routine 81 NOP DRTAR NOP U RET ---

BSA routine 82 NOP NOP NOP U JMP --

83 NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Fetch Clock 13
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX 25

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 25 81
1- I
201 LDA 300 201 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
101
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
80 NOP READ NOP U JMP 80
BUN routine 81 NOP DRTAR NOP U RET ---

BSA routine 82 NOP NOP NOP U JMP --

83 NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Execute Clock 14
(I=1, indirect) , routine Returns
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 25 26
1- I
201 LDA 300 201 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
101
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
24 NOP NOP NOP I CALL 80
BUN routine 25 ARTPC NOP NOP U JMP FC

BSA routine 26 NOP NOP NOP U JMP --

27 NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Fetch Clock 15
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FC 26
1- I
201 LDA 300 201 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
201
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
24 NOP NOP NOP I CALL 80
BUN routine 25 ARTPC NOP NOP U JMP FC

BSA routine 26 NOP NOP NOP U JMP --

27 NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Excute Clock 16
Instruction BUN executed. Jump to fetch block to get next instruction
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FC FD
1- I
201 LDA 300 201 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
201
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
PC points to next
FC NOP NOP NOP F JMP 88
instruction in RAM.
BUN routine FD NOP PCTAR NOP U JMP FE
CAR points to
BSA routine FE NOP READ INCPC U JMP FF
address of the
micro instruction FF NOP DRTAR NOP U MAP --
of fetch (FC) in
ROM
Indirect routine

Fetch routine
Fetch Clock 1
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FD FD
1- I
201 LDA 300 201 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
201
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Execute Clock 2
Interrupt bit F=0, NO external interrupt
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FC FD
1- I
201 LDA 300 201 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
201
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Fetch Clock 3
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FE FE
1- I
201 LDA 300 201 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
201
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Execute Clock 4
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

201 ALU 4-1 MUX

Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FE FF
1- I
201 LDA 300 201 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
201
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Fetch Clock 5
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
LDA 300
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FF FF
1- I
201 LDA 300 201 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
202
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Execute Clock 6
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
LDA 300
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U FF 00
1- I
201 LDA 300 201 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
202
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
FC NOP NOP NOP F JMP 88
BUN routine FD NOP PCTAR NOP U JMP FE

BSA routine FE NOP READ INCPC U JMP FF

FF NOP DRTAR NOP U MAP --

Indirect routine

Fetch routine
Fetch Clock 7
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

LDA 300
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 18 FF
0- I
201 LDA 300 300 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
202
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
PC points to next
FC NOP NOP NOP F JMP 88
instruction in RAM.
BUN routine FD NOP PCTAR NOP U JMP FE
CAR points to
BSA routine FE NOP READ INCPC U JMP FF
address of the
micro instruction FF NOP DRTAR NOP U MAP --
of LDA (18) in ROM
Indirect routine

Fetch routine
Execute Clock 8
MAP-decodes Instruction :Loads address of micro instruction of LDA
in CAR and address given in LDA (I=0, direct) in MAR
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR
LDA 300
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 001 1- U 18 19
0- I
201 LDA 300 300 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
202
3FF
IN OUT

7FE 201
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
18 NOP NOP NOP I CALL 80
BUN routine 19 NOP READ NOP U JMP 1A

BSA routine 1A DRTAC NOP NOP U JMP FC

1B NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Fetch Clock 9
 RAM
jump
000 BSA 200 ret
001 HLT map next
MDR

LDA 300
ALU 4-1 MUX
Logic
Ckt
SBR
100 BUN 7FE

MAR
200 1- U 19 19
0- I
201 LDA 300 300 A
0- S CAR+1
202 BUN 200 0- Z 8-1 CAR
0- C MUX
300 ABC 0- R
PC
0-W
0- F
202
3FF
IN OUT

7FE …....
7FF BUN 100
ROM
F1 F2 F3 CD BR Addr
18 NOP NOP NOP I JMP 80
BUN routine 19 NOP READ NOP U JMP 1A

BSA routine 1A DRTAC NOP NOP U JMP FC

1B NOP NOP NOP U JMP --

Indirect routine

Fetch routine
Execute Clock 10