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  • Neso HDMI VGA Framebuffer Block Diagram Rotated

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    Jesus Salvador
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    The document describes a MicroBlaze subsystem containing a MicroBlaze processor, AXI interconnect, and DDR3 memory controller. The MicroBlaze processor is connected to the AXI interconnect via the S00 and S01 ports. The AXI interconnect is connected to the memory controller via the M00, M01, M02, and M03 ports to interface with the external DDR3 SDRAM memory. Clocks and resets are provided to synchronize the different components.

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    The document describes a MicroBlaze subsystem containing a MicroBlaze processor, AXI interconnect, and DDR3 memory controller. The MicroBlaze processor is connected to the AXI interconnect via the S00 and S01 ports. The AXI interconnect is connected to the memory controller via the M00, M01, M02, and M03 ports to interface with the external DDR3 SDRAM memory. Clocks and resets are provided to synchronize the different components.

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    © All Rights Reserved
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    19 views1 page

    Neso HDMI VGA Framebuffer Block Diagram Rotated

    Uploaded by

    Jesus Salvador
    The document describes a MicroBlaze subsystem containing a MicroBlaze processor, AXI interconnect, and DDR3 memory controller. The MicroBlaze processor is connected to the AXI interconnect via the S00 and S01 ports. The AXI interconnect is connected to the memory controller via the M00, M01, M02, and M03 ports to interface with the external DDR3 SDRAM memory. Clocks and resets are provided to synchronize the different components.

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    © All Rights Reserved
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    of 1

    microblaze_subsystem

    microblaze_0_axi_periph

    S00_AXI
    S01_AXI
    S01_AXI
    ACLK
    ARESETN

    S00_ACLK
    S00_ARESETN

    M00_ACLK M00_AXI mig_7series_0


    M00_ARESETN M01_AXI ddr3_sdram
    DDR3 ddr3_sdram
    M01_ACLK M02_AXI S_AXI
    ui_clk_sync_rst
    M01_ARESETN M03_AXI sys_rst
    ui_clk
    M02_ACLK sys_clk_i
    mmcm_locked
    rst_mig_7series_0_100M M02_ARESETN aresetn
    init_calib_complete
    M03_ACLK
    slowest_sync_clk mb_reset
    M03_ARESETN Memory Interface Generator (MIG 7 Series)
    ext_reset_in bus_struct_reset[0:0] usb_uart
    S01_ACLK usb_uart
    aux_reset_in peripheral_reset[0:0] M03_AXI
    S01_ARESETN
    mb_debug_sys_rst interconnect_aresetn[0:0]
    axi_uartlite_0
    dcm_locked peripheral_aresetn[0:0]
    AXI Interconnect
    S_AXI
    Processor System Reset UART
    s_axi_aclk
    interrupt
    s_axi_aresetn

    microblaze_0 microblaze_0_local_memory AXI Uartlite


    mdm_1 s_axi_aresetn[0:0]
    INTERRUPT
    DLMB DLMB
    rst_clk_wiz_0_100M MBDEBUG_0 DEBUG
    ILMB ILMB
    Debug_SYS_Rst Clk
    slowest_sync_clk mb_reset M_AXI_DP LMB_Clk
    reset Reset
    ext_reset_in bus_struct_reset[0:0] MicroBlaze Debug Module (MDM) SYS_Rst
    sys_clk_i MicroBlaze
    aux_reset_in peripheral_reset[0:0]
    Clk
    mb_debug_sys_rst interconnect_aresetn[0:0]
    dcm_locked
    dcm_locked peripheral_aresetn[0:0]

    Processor System Reset

    microblaze_0_axi_intc

    s_axi

    microblaze_0_xlconcat s_axi_aclk

    In0[0:0] s_axi_aresetn
    In0[0:0] interrupt
    dout[1:0] intr[1:0]
    reset In1[0:0]
    processor_clk
    clk_wiz_0 Concat processor_rst

    clk100
    AXI Interrupt Controller
    clk200
    resetn clk40

    sys_clock clk_in1 clk_pix_5x


    clk_pix_5x_180
    locked vsync
    video_subsystem
    Clocking Wizard vga_decimate_0
    axi_vdma_0
    red[2:0] red[2:0]
    S_AXI_LITE active
    S_AXI_LITE M_AXI_MM2S green[2:0] green[2:0]
    M_AXI_MM2S din[23:0]
    s_axi_lite_aclk blue[1:0] blue[1:0]
    M_AXIS_MM2S
    m_axi_mm2s_aclk
    clk mm2s_frame_ptr_out[5:0] vga_decimate_v1_0
    m_axis_mm2s_aclk
    mm2s_introut hsync
    axi_resetn
    hdmi_subsystem
    AXI Video Direct Memory Access
    dvi_top_0
    proc_sys_reset_0 clk_pix_1x
    clk_pix_1x
    clk_pix_5x
    slowest_sync_clk mb_reset clk_pix_5x
    reset clk_pix_5x_180
    ext_reset_in bus_struct_reset[0:0] clk_pix_5x_180
    aux_reset_in peripheral_reset[0:0] rst
    util_vector_logic_0
    mb_debug_sys_rst interconnect_aresetn[0:0] red[7:0] tmds[3:0]
    dcm_locked tmds[3:0] tmds[3:0]
    dcm_locked peripheral_aresetn[0:0] de[0:0] blue[7:0] tmdsb[3:0]
    m_axi_mm2s_aclk Op1[0:0] Res[0:0] tmdsb[3:0] tmdsb[3:0]
    green[7:0]
    axi_resetn
    Processor System Reset v_axi4s_vid_out_0 vid_active_video
    de
    Utility Vector Logic
    vsync
    v_tc_0 vid_io_out blank
    hsync hsync
    vid_active_video hsync
    clk video_in vid_data[23:0] vsync
    vid_data[23:0] vsync
    clken vtiming_out vtiming_in mm2s_introut
    vid_hsync blue8
    gen_clken fsync_out[0:0] aclk peripheral_reset[0:0]
    dvi_top_v1_0
    vid_vsync din[23:0]
    resetn aclken Din[23:0] Dout[7:0]
    vtg_ce
    aresetn
    Video Timing Controller locked Slice
    fid
    overflow
    vid_io_out_ce red8
    underflow

    constant_1 status[31:0] Din[23:0] Dout[7:0]

    dout[0:0] AXI4-Stream to Video Out Slice

    Constant green8

    Din[23:0] Dout[7:0]

    Slice
    rst

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