Electric Power Components and Systems

ISSN: 1532-5008 (Print) 1532-5016 (Online) Journal homepage: http://www.tandfonline.com/loi/uemp20

A Grouping Strategy Based on Prime Factorization

for Capacitor Voltage Balancing of the Modular
Multilevel Converter

Chengyong Zhao, Ye Wang, Maolan Peng, Zhipeng He & Chunyi Guo

To cite this article: Chengyong Zhao, Ye Wang, Maolan Peng, Zhipeng He & Chunyi Guo
(2018) A Grouping Strategy Based on Prime Factorization for Capacitor Voltage Balancing of
the Modular Multilevel Converter, Electric Power Components and Systems, 46:5, 570-580, DOI:
10.1080/15325008.2018.1460421

To link to this article: https://doi.org/10.1080/15325008.2018.1460421

Published online: 31 May 2018.

Submit your article to this journal

Article views: 45

View Crossmark data

Full Terms & Conditions of access and use can be found at

http://www.tandfonline.com/action/journalInformation?journalCode=uemp20
Electric Power Components and Systems, 46(5):570–580, 2018
Copyright C Taylor & Francis Group, LLC
ISSN: 1532-5008 print / 1532-5016 online
DOI: 10.1080/15325008.2018.1460421

A Grouping Strategy Based on Prime

Factorization for Capacitor Voltage Balancing of the
Modular Multilevel Converter
Chengyong Zhao, Ye Wang, Maolan Peng, Zhipeng He, and Chunyi Guo
State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources, North China Electric Power
University, Beijing, China

CONTENTS
Abstract—The modular multilevel converter (MMC) is attractive
1. Introduction for high-power applications because of the advantages of its high
2. Topology and Basic Control Strategy of MMC modularity and high power quality. This paper proposes a prime
3. The Proposed Capacitor Voltage Control Strategy Based on factorization-based grouping strategy for capacitor voltage balanc-
ing of MMC. With prime factors arranged from the largest to the
Prime Factorization smallest, the computation burden has been reduced significantly,
4. Simulation Analysis which is proved mathematically. Then, a 401-level MMC adopting
5. Investigation of the Switching-Frequency the proposed grouping strategy is implemented and evaluated in
the PSCAD/EMTDC environment. Simulation results confirm the
6. Conclusion effectiveness of the proposed strategy for capacitor voltage bal-
Funding ancing performance under both steady and dynamic states. And
References by comparing with conventional sorting algorithm, it can be con-
cluded that the prime factorization pattern can significantly improve
the simulation efficiency. Finally, the switching frequency of the
proposed algorithm is discussed.

Keywords: capacitor voltage balancing, voltage-source converter (VSC),
modular multilevel converter (MMC), prime factorization,
switching-frequency
Received 14 July 2016; accepted 24 March 2018
Address correspondence to Chunyi Guo, State Key Laboratory of Alternate
Electrical Power System with Renewable Energy Sources, North China
Electric Power University, Beijing, 102206, China. E-mail:
chunyiguo@outlook.com
Color versions of one or more of the figures in the article can be found online
at www.tandfonline.com/uemp.
I. INTRODUCTION
VSC-HVDC based on self-commutated source converters is
an attractive technology, by which fast and independent con-
trol of real and reactive power is realized. [1], [2]. The mod-
ular multilevel converter (MMC) topology provides several
advantages over two- or three-level voltage-source converter
(VSC) technologies, such as modularity and scalability. Thus,
MMC is widely used for medium- or high-voltage and high-
power applications [3]–[6]. Depending on the application and
power capability requirements, the number of sub-modules
(SMs) in each arm can vary from tens to hundreds. For exam-
ple, in Trans Bay Cable (TBC) project (400 MW, ±200 kV),
each arm has 216 SMs [7] and the INELFE project will adopt
more than 400 SMs per arm [8]. For the MMC with exces-
sive number of submodules in each arm, it will take a large
amount of computation resources for the simulation process.
Thus accelerating the simulation of MMCs with numerous
SMs per arm efficiently becomes one of the significant tech-
nical challenges.

570
 Zhao et al.: Capacitor Voltage Control Strategy Based On Prime Factorization
Two main approaches proposed to resolve the difficul-
ties mentioned above focus on two aspects: enhancing the
equivalent model of MMC, such as highly accurate models
based on Thevenin equivalents, the continuous model, and the
average-value models (AVM) [6]–[10], etc, or improving sort-
ing algorithms for balancing capacitor voltages. The latter as
a feasible solution has been widely studied and suggested for
the capacitor voltage balancing process [3], [9]–[17]. How-
ever, for an MMC with a large number of SMs, sorting the
capacitor voltage as introduced in [3] is time-consuming, and
requires considerable computational resources. Besides, it is
costly and difficult to compress the computation time via the
improvement of hardware in practical occasions. Reference
[9] proposes a modified capacitor voltage balancing strategy
for the carrier phase-shift PWM (CPS-PWM) scheme [10],
[11] to improve the performance of capacitor voltage bal-
ancing. A series of reduced switching-frequency voltage bal-
ancing strategies have been proposed in [12]–[14], where a
limited number of SMs are sorted during every control period
to avoid the unnecessary switching transitions. However, it
still requires significant computational resources when the
number of SMs connected in series within each arm is large.
A grouping method is proposed in [15] to save sorting time
compared with the conventional method. However, there is no
mathematical proof for the grouping strategy adopted. Refer-
ences [16] and [17] have investigated the predictive algorithm
for capacitor voltage balancing. However, it is not applicable
for large-scale MMCs due to the large computation burden of
sorting capacitor voltages.
This paper aims at balancing a mass of capacitor voltages,
with a significant enhancement in simulation speed, and the
prime factorization method is proposed for this purpose. Com-
pared with the conventional sorting strategy, such as bubble
sorting, selection sorting, and insertion sorting, it can sub-
stantially reduce the sorting steps of sorting capacitor volt-
ages by dividing large numbers of SMs into several groups
and sorting the capacitor voltages in each group, which is
referred to as the grouping strategy for submodule selection
process of MMC. Since there is lack of established princi-
ples for determining grouping patterns of submodules, the
grouping pattern based on the prime factorization is proposed,
and the corresponding mathematical process is presented. The
performances of capacitor voltage balancing and acceleration
effect of the proposed grouping strategy have been studied in
a 401-level MMC-HVDC model built in the PSCAD/EMTDC
environment.
The rest of this paper is organized as follows. Section II
introduces the basic operation principle and conventional
capacitor voltage balancing strategy of the MMC. Section III
571
describes the conventional grouping strategy, explains the
proposed grouping pattern based on prime factorization and
provides its mathematical proof that the sorting strategies is
optimal among all kinds of grouping patterns. The simulation
results are demonstrated in Section IV. Section V discusses
the trade-off between the switching-frequency and grouping
layers. Finally, conclusions are presented in Section VI.
II. TOPOLOGY AND BASIC CONTROL STRATEGY
OF MMC
A. Basic Operation Principles of MMC
Figure 1 shows the structure of a three-phase MMC, which
consists of six arms. Each phase is divided into the upper arm
and the lower arm with N identical series-connected submod-
ules, respectively. Udc is the DC-link voltage of MMC and
two arm inductance L are connected in series between the dc
terminals as shown in Figure 1. Typically, the SM is the half-
bridge structure which includes two IGBTs (T1 and T2 ), two
antiparallel diodes (D1 and D2 ), and a capacitor C. The output
voltage is either zero or the rated capacitor voltage uSM , which
is determined by the switching states of T1 and T2 .
The AC-side output voltage of each phase depends on the
number of inserted SMs in the upper and the lower arms
(nu or nl ). Meanwhile, to maintain the DC-link voltage, nu and
nl must meet the relation depicted in (1):
Udc
nu + nl = =N (1)
Uc
where Uc is the nominal capacitor voltage.
As a result, a modulation strategy aiming to decide nu and
nl of three phases during every control interval is necessary.
FIGURE 1. Structure of MMC.
572 Electric Power Components and Systems, Vol. 46 (2018), No. 5
Typical modulation strategies, such as CPS-PWM and near-
est level control (NLC) [18], have been applied widely for
MMCs. Compared with other strategies, NLC is characterized
for its ease of implementation and advantage emerges with the
increase in the number of SMs [11]. Therefore, NLC is more
suitable for an MMC with numerous SMs. This paper mainly
focuses on the large-scale MMCs; thus, NLC is chosen in this
paper. According to the NLC, nu and nl of each phase can be
calculated as shown by (2a) and (2b), respectively:
 
N (1 − m sin(ω0t + ϕ))
nu = round (2a)
2 determined. It is assumed that N SMs in each arm are divided
 
N (1 + m sin(ω0t + ϕ))
nl = round (2b)
2 The steps of VBG algorithm are explained as following steps.
where m is the modulation index, ω0 is the fundamental fre-
quency, ϕ is the initial phase, and round() is the nearest integer
round function.
B. Conventional Capacitor Voltage Balancing Strategy
To avoid the capacitor voltage imbalance within one arm,
some SMs are selected to be inserted during the sorting pro-
cess. The principle of conventional capacitor voltage balanc-
ing strategy [3] is that during every control interval, firstly the
capacitor voltages of each arm are sorted based on their val-
ues; then SMs with the lowest (highest) capacitor voltage are
selected to be inserted if the capacitor is charged (discharged)
by the arm current [3]. Hence, the submodule selection pro-
cess determines the computational burdens of the capacitor
voltage balancing process.
Many practical sorting algorithms have been studied and
applied in the computer programming mentioned in Chapter 1,
the common point of those sorting algorithms is that the aver-
age computational complexity is O(n2 ) [19]. To express the
computational complexity of those sorting algorithms intu-
itively, the accumulated times of comparing figures during the
whole sorting process is defined as sorting steps, which can be
calculated by
N (N − 1)
T = 1 + 2 + · · · (N − 1) = (3)
2 where m1 is the number of SMs in each group, Q and R are
The sorting steps and simulation time will be overwhelm-
ing if the number of SMs is large. Moreover, with high number
of levels, the control of SMs (balancing SM capacitor volt-
ages) may be separated from the global control (current and
power controls) [11].
III. THE PROPOSED CAPACITOR VOLTAGE
CONTROL STRATEGY BASED ON PRIME
FACTORIZATION
A. The Conventional Grouping Strategy
By dividing the SMs into several groups, sorting steps can
be reduced and the speed of sorting will be enhanced. How-
ever, this grouping method will result in voltage imbalance
among different groups if it cannot be suppressed by an effec-
tive voltage balancing strategy. Therefore, a Voltage Balanc-
ing algorithm among Groups (VBG) is developed. Before the
grouping strategy is activated, the grouping pattern needs to be
into m groups evenly. Then, the VBG algorithm is activated.
Step 1: Divide N SMs into m groups evenly and calculate
the sum of capacitor voltages within each group,
then sort the voltage sums from the lowest (highest)
group to the highest (lowest) group by the direction
of arm current.
Step 2: Perform a division operation. The number of
required inserted SMs (nu or nl ) is divided by m
to assign SMs evenly among groups, and the result
contains quotient Q and remainder R. Q is the basic
number of the required inserted SMs assigned for
each group.
Step 3: Distribute the remainder R based on the sorting
result of Step 1 and the direction of arm current.
Groups with the lowest (highest) voltage sums are
assigned to add one more SM from the remainder
R until the distribution of R is completed, if the arm
carries the charging (discharging) current.
Step 4: Combine the basic number Q with the distribution
result. Then, the required number of inserted SMs
of each group is determined.
Assume that during a control period the number of required
inserted SMs is Non , the principle of the VBG algorithm is
shown as follows:
N = m · m1 (4)
Non = m · Q + R (5)
the quotient and remainder of Non divided by m, respectively.
Then, if the arm carries the charging (discharging) current,
there are R groups with the lowest (highest) voltage sums from
the sorted list which need to be inserted Q + 1 SMs within
each group, and the rest of the groups need to be inserted Q
SMs.
 Zhao et al.: Capacitor Voltage Control Strategy Based On Prime Factorization 573

By applying the VBG algorithm to assign the required

inserted SMs for each group, the voltage balance among
different groups is maintained. Then the conventional sort-
ing algorithm (i.e., the bubble algorithm) is adopted by each
group. The sorting steps of grouping strategy contain two
components. One is produced in the VBG process when sort-
ing the voltage sums of all groups; the other is produced in
each group by the conventional sorting algorithm. Then, the
sorting steps T of grouping strategy is calculated by (6)
 
N N
−1 m(m − 1)
T = m m
·m+
 2  2
N N m(m − 1)
= −1 + (6)
2 m 2
To compare the sorting steps of grouping strategy with that
FIGURE 2. Process of dividing N SMs based on the prime
of the conventional strategy, subtract (6) from (3):
factorization grouping pattern.
(m − 1)(N − m)(N + m)
T = (7)
2m
The grouping process of the prime factorization grouping
The number of groups satisfies 1 ࣘ m ࣘ N. Therefore, it pattern is shown in Figure 2. It shows that N SMs are divided
can be concluded that T ࣙ 0. As a result, the sorting steps into m1 groups at the first layer. Then SMs within each group
of grouping strategy is much less than that of the conventional at the first layer are divided into m2 groups at the second layer.
strategy except the SMs are divided into one group (m = 1) or As a result, at the nth layer each group is divided into mn
N groups (m = N). groups with mn+1 SMs inside. The VBG algorithm is invoked
to assign the required inserted SMs to groups at each layer
B. The Proposed Grouping Pattern Based on Prime to maintain the voltage balance among different groups. The
Factorization assignment process is described by
Since the sorting steps can be significantly decreased by divid- ⎧
⎪
⎪ Non = m1 · Q1 + R1
ing SMs into groups, it is easy to conclude that dividing the ⎪
⎪
⎪
⎪ N1 = Q1 or Q1 + 1
SMs of each group over again can reduce the sorting steps fur- ⎪
⎪
⎪
ther more. The method that the SMs in each group are divided ⎨ N1 = m2 · Q2 + R2
⎪
N2 = Q2 or Q2 + 1 (9)
multiple times is referred to as multilayer grouping method, ⎪
⎪
⎪ ..
and there are different kinds of grouping patterns. Among the ⎪
⎪ .
⎪
⎪
wide variations of grouping patterns, the one based on the ⎪
⎪ N n−1 = m n · Qn + Rn
⎪
⎩
prime factorization possesses the least sorting steps, which is Nn = Qn or Qn + 1
mathematically proved in this section.
According to the number theory, a positive integer can be Here, N1 , N2 . . .Nn–1 , and Nn are the required number of
written as a list of prime factors with their exponents multiply- inserted SMs of each group at the first, second …(n−1)th,
ing [20]. The process of determining these factors is referred and nth layer, Q1 , Q2 . . .Qn–1 , and Qn are the quotients of Non ,
to as prime factorization. Inspired by the prime factorization N1 . . .Nn–1 divided by the corresponding number of groups
method, N SMs in each arm can be divided as prime factoriza- (m1 , m2 . . .mn ) at each layer, and R1 , R2 . . .Rn–1 , and Rn are
tion pattern. Accordingly, the corresponding remainders.
The Non required inserted SMs are distributed layer by
N = m1 · m2 · mi · mn+1 layer. Consequently, Qn+1 SMs need to be switched on in Rn
× (1 < m1 , m2 · · · mi · · · mn+1 < N ) (8) groups and the others need Qn inserted SMs at the nth layer.
Another problem appears after prime-factorizing the N
where m1 . . .mn and mn+1 are prime factors of N and some of SMs. There are various kinds of permutation orders of prime
them may be identical, since the prime factors are all listed factors. Therefore, it is important to seek out the permutation
without any exponent. order with the least sorting steps. It is found that if the prime
574 Electric Power Components and Systems, Vol. 46 (2018), No. 5

⎛ ⎞
factors are arranged from the largest to the smallest, the sort- +1
n
mi1 mi2 (mi1 − 1)
k i−1
⎝ m − 1
mj ⎠ +
k
ing steps are the minimum. Accordingly, T = mj
2 2
k=1 j=1 j=1

m1 ≥ m2 ≥ · · · ≥ mn+1 (10) mi2 (mi2 − 1)

i−1
mi − 1
i
+ mj − mj (13)
2 2
j=1 j=1
In conclusion, the prime factorization grouping pattern
includes two points. Firstly, prime-factorize the number of
Subtract (13) from (11) to obtain
SMs within each arm; then arrange the prime factors from the
largest to the smallest to group SMs by the multilayer group-
1   i−1
ing method. Ti = mi2 (mi2 − 1) m2i1 − 1 · mj (14)
2
j=1

C. Mathematical Demonstration
To prove the sorting steps of prime factorization pattern with
prime factors arranged from the largest to the smallest is the
minimum, the demonstration contains two parts. One is pro-
vided to prove the sorting steps of the prime factorization pat-
tern is the least compared with other factorization patterns.
The other is to demonstrate the permutation order with prime
factors arranged from the largest to the smallest possesses the
least sorting steps.
1) Factorization Pattern
Since mi1 and mi2 satisfy the inequality 1 < mi1 , mi2 <mi ,
the difference Ti in (14) is greater than 0, which means the
sorting steps decreases by dividing the SMs at the ith layer
once again. Through similar deduction, it can be concluded
that if the SMs are grouped layer by layer thoroughly accord-
ing to the prime factorization method until they cannot be
divided into any prime factor anymore, the sorting steps will
be the minimum. As a result, the numbers of groups at each
layer are all prime numbers, which is in agreement with the
prime factors of N.

To prove the sorting steps of prime factorization pattern is
the least, the mathematical process is given as follows. Cal-
culate the sorting steps of a certain incomplete factorization
pattern. Then, factorize one of the decomposable factors and
compare the sorting steps with that of original factorized pat-
tern. If the sorting steps are less after the factorization, then it
implies that factorizing promotes the decrease in sorting steps.
Therefore, it can be deduced that if all the decomposable fac-
tors are factorized to the prime factors, the sorting steps are
1) The Optimal Permutation order
To find out the optimal permutation order of prime factors
with the least sorting steps, the Lagrange multiplier method
is adopted. It is assumed that N SMs are divided as the prime
factorization pattern shown in (8). With the objective function
shown in (11) and the constraint condition shown in (8), the
Lagrange objective function is expressed as
⎛ ⎞ ⎛ ⎞

n+1
k n+1
⎝ m − 1
mj ⎠ + λ ⎝ mj − n⎠
k
reduced to the minimum extend. Thus, according to the afore- L= (15)
2
mentioned analysis, it is assumed that the number of SMs (i.e., k=1 j=1 j=1
N) is factorized as shown in (8) and at least one of the factors
can be factorized further. Then, the sorting steps can be cal- where λ is the Lagrange multiplier.
culated by To find out the extreme points (m1 . . .mn+1 and λ), it
should derive the partial differential equations of the extreme
⎛ ⎞
+1
n

k points, i.e.,
m
⎝ k − 1
T = mj ⎠ (11) ⎧ ∂L   n n
2 = mn + 1 − 12
k=1 j=1 ⎪
⎪ ∂mn + 1 j=1 mj + λ j=1 mj = 0
⎪
⎪  2  n−1  
⎪
⎪ ∂L 1 n−1
⎪
⎪ ∂mn
= 2 mn+1 − mn+1
1
j=1 mj + mn − 2 j=1 mj
⎪
⎪ n−1
Assuming that mi is one of the composite numbers which ⎪
⎪ + λmn+1 j =1 mj = 0
⎪
⎪
can be factorized further, N can be factorized as ⎪
⎨
..
⎪ .
N = m1 · mi−1 · mi1 · mi2 · mi+1 · mn+1 ⎪
⎪    
(12) ⎪
⎪ ∂L  k
⎪
⎪ = n+1 1
(m − 1) m + m1 − 12
⎪
⎪ ∂m 1 k=2

2 k j=2 j
⎪
⎪
where mi1 and mi2 are the factors factorized by mi . ⎪
⎪ + λ n+1j=2 mj = 0
⎪
⎪
⎩ ∂L n+1
The sorting steps of the grouping pattern shown in (12) are ∂λ
= j=1 mj − N = 0
given by (16)
 Zhao et al.: Capacitor Voltage Control Strategy Based On Prime Factorization 575

Then, solving the differential equations, yields

⎧
⎪
⎪ m1 = 12 + 12 m22
⎪
⎪
⎪
⎪ ..
⎪
⎪ .
⎪
⎪
⎪
⎨mi = 2 + 2 mi+1
1 1 2

.. (17)
⎪
⎪ .
⎪
⎪
⎪
⎪ mn = 2 + 12 m2n+1
1
⎪
⎪m
⎪
⎪ n+1 = 2 − λ
1
⎪
⎩
m1 · m2 · . . . · mn+1 = N

Subtract mi+1 from mi to obtain:

1 2 
mi − mi+1 = m + 1 − mi+1
2 i+1
1
= (mi+1 − 1)2 (18) FIGURE 3. Proposed prime factorization grouping pattern
2
for the TBC project.
Since mi + 1 is greater than 1, mi and mi + 1 satisfy the
unequal relation of mi > mi + 1 . However, the calculation
The conventional strategy can be regarded as a special kind
results of the extreme points may not fully comply with
of grouping pattern that SMs are divided into one group, i.e.,
the prime factors. The reason is that some prime factors
1 × 216. Meanwhile, the prime factorization pattern of the
shown in (8) are identical. By making mi equal to mi+1 , the
SMs of one arm with prime factors arranged from the largest
prime factorization pattern is achieved and the extreme points
to the smallest is 3 × 3 × 3 × 2 × 2 × 2, and Figure 3 shows
are obtained. In other words, the inequality of mi and mi+1
the grouping process.
becomes mi ࣙ mi + 1 . Through similar deduction, m1 …mn and
It is observed that the sorting steps of prime factorization
mn + 1 all meet the relation that the latter one is not greater than
pattern with prime factors arranged from the largest to the
the former one which is shown in (10).
smallest is the minimum, and decreases by nearly 100 times
According to the aforementioned demonstration, it proves
compared with that of conventional strategy.
that the sorting steps of prime factorization pattern is less than
other grouping patterns, and the permutation order with prime
factors arranged from the largest to the smallest can minimize IV. SIMULATION ANALYSIS
the sorting steps. A 401-level MMC-HVDC model is studied in the
PSCAD/EMTDC environment to verify the proposed group-
D. Case Study ing strategy. With such a large number of SMs, the simulation
To compare the sorting steps of different grouping patterns, process is excessively time-consuming. Thus, one kind of
the TBC project is chosen as a study case. Eight different MMC bridge equivalent module is adopted to replace the
grouping patterns of 216 SMs within each arm and their sort- detail model of arm [22]. The system parameters are shown
ing steps calculated by (11) are shown in Table 1. in Table 2. Since the system parameters of two converter
stations are identical, Table 2 only shows the parameters of
one converter station. The closed loop dq-based controllers
Grouping pattern Sorting steps and bubble sorting algorithm are adopted and not repeated
1 × 216 23220 here [19], [21]. For the purpose of validating the performance
9 × 24 2520 of capacitor voltage balancing, the capacitor voltages of
9×8×3 504 three different grouping patterns, under both steady and
9×4×2×3 342 dynamic states, are compared. Then, in order to validate the
3×3×4×2×3 318
acceleration effect of the proposed grouping strategy, the
3×3×2×2×2×3 312
actual running time of simulation applying different grouping
3×2×3×2×3×2 258
3×3×3×2×2×2 228 patterns with the set simulation time is presented. All the sim-
ulation results were conducted on a Microsoft Windows XP
TABLE 1. Sorting steps of eight different grouping patterns of the Operating System with a 4-GB RAM and 2.0-GHz Intel(R)
TBC project. Core 2 Duo CPUs.
576 Electric Power Components and Systems, Vol. 46 (2018), No. 5

Item Value

AC system voltage US 230 kV

AC system inductance LS 20.33 mH
Voltage frequency f0 50 Hz
Transformer ratio K 230 kV/341.3 kV(Y0 /)
Transform leakage inductance Lt 50 mH (secondary side)
Arm inductance L 85 mH
Rated transformer capacity STN 1022.2 MVA
Transmission active power PS 500 MW
DC-link voltage Udc ±320 kV
Capacitance in SM C0 20 mF
Capacitor voltage in SM UC 1.6 kV
Number of SMs in one arm N 400

TABLE 2. System parameters of the 401-level MMC-HVDC model.

A. Validation of Capacitor Voltage Balancing

Performance
The three different grouping patterns, which are conventional
FIGURE 4. DC voltages and capacitor voltages of 400 SMs
strategy, two-layer pattern, and prime factorization pattern in the upper arm of phase A.
with the prime factors arranged from the largest to the small-
est, are investigated respectively to validate the effectiveness
of the proposed strategy. And the two-layer grouping pattern
Case 3: Single-phase-to-ground Fault
is 5 × 80, and the prime factorization pattern is 5 × 5 × 2 × 2
At 1.0 s, a single-phase-to-ground fault of the ac bus occurs
× 2 × 2. Then, the accelerated effect will be further validated
and lasts for 50 ms. The responses of the RMS voltage and
in part B.
capacitor voltages of the three different grouping patterns are
Case 1: Steady State Operation shown in Figure 6.
Figure 4 shows the DC-voltages and instantaneous capac-
itor voltages of 400 SMs within the upper arm of phase A
under steady state, the start-up process is neglected. It clearly
shows that DC voltages under three sorting methods are all
kept at 640 kV during steady operation. The capacitor voltage
balancing performances of the two-layer pattern and the prime
factorization pattern are close to that of conventional strategy,
and capacitor voltages are all maintained at the nominal value
basically. The maximum voltage deviations among capacitor
voltages of three grouping patterns are ±2.5%.
For the purpose of validating the capacitor voltage bal-
ancing performance of the proposed grouping strategy under
dynamic states, the following two dynamic cases are applied
to the MMC model:

Case 2: Voltage Reference Steps

At 0.5 s, the DC voltage reference jumps from 640 kV to
680 kV; then, at 1.0s, it drops to 600 kV; at 1.5 s, it restores
to 640 kV. The responses of the DC voltage and capacitor
voltages of the three different grouping patterns are shown in FIGURE 5. Responses of 401-level MMC-HVDC model
Figure 5. under DC-voltage steps condition.
 Zhao et al.: Capacitor Voltage Control Strategy Based On Prime Factorization 577

Acceleration ratio (%)

Grouping Sorting Running (conventional strategy /
pattern steps time (s) grouping strategy)
1 × 400 78900 3620 —
5 × 80 15810 1056 343
5 × 5 × 16 3060 556 651
5×5×2×8 1485 484 748
5×5×2×2 735 468 774
×4
5×5×2×2 435 452 801
×2×2

TABLE 3. Sorting steps and running time of six grouping patterns.

The 401-level MMC-HVDC model is also studied to inves-

FIGURE 6. Responses of 401-level MMC-HVDC model
under single-phase-to-ground fault condition.
In Figure 5 and Figure 6, the DC voltage and capacitor
voltages can track after the orders exactly, and the response
time is less than 0.1 s. Under the single-phase-to-ground fault
state, the system can recover to the normal operation within
less than 0.2 s. It shows that the capacitor voltages can be kept
balanced under both voltage reference steps and single-phase-
to-ground fault states regardless of the adopted grouping pat-
tern. This indicates that the proposed grouping strategy can
perform efficiently under dynamic states without affecting the
system behavioral characteristics.
tigate the acceleration effects of different permutation orders
of the prime factors. Table 4 shows the sorting steps and
corresponding running time. The result shows that the run-
ning time and sorting steps of the prime factors arranged
from the largest to the smallest are the minimum. All those
simulation results of acceleration effect are consistent with
the conclusions of the aforementioned mathematical proof in
Section III.
V. INVESTIGATION OF THE
SWITCHING-FREQUENCY
The trade-off between the switching frequency and the
number of grouping layers is discussed in this part. The
main challenge of the prime factorization method is that
the switching frequency is relatively high, because the sim-
ulation time decreases with the increase of the grouping

B. Validation of Acceleration Effect

Permutation order Sorting steps Running time (s)
By applying the grouping strategy, the actual running time of
simulation will be substantially reduced. In order to investi- 2×2×2×2×5×5 975 527
gate the acceleration effects of different grouping patterns, 2×2×2×5×2×5 927 525
the 401-level MMC-HVDC model with six different group- 2×5×2×2×2×5 891 523
5×2×2×2×2×5 885 480
ing patterns has been simulated. The simulation time is set to
2×2×5×2×2×5 883 471
10 sec. 2×2×2×5×5×2 687 469
Table 3 shows the sorting steps, actual running time, and 2×2×5×2×5×2 663 467
corresponding acceleration ratio compared with the conven- 2×5×2×2×5×2 650 466
tional strategy. As shown in Table 3, the conventional strategy 5×2×2×2×5×2 645 461
(shown in the 1st row) is the most time-consuming method, 2×2×5×5×2×2 543 457
which is set as the base of comparison of the acceleration 2×5×2×5×2×2 531 456
5×2×2×5×2×2 525 453
ratio of different grouping patterns, while the running time
2×5×5×2×2×2 471 447
of the prime factorization pattern (shown in the sixth row)
5×2×5×2×2×2 465 445
is the minimum. The acceleration ratio increases along with 5×5×2×2×2×2 435 443
the grouping layers, and the acceleration ratio of prime fac-
torization grouping pattern reaches 801% compared with the TABLE 4. Sorting steps and running time with different permutation
convention strategy. order.
578 Electric Power Components and Systems, Vol. 46 (2018), No. 5

layers (as shown in Figure 8(b) and Table 3). Hence, the
effectiveness of reduced switching frequency fades gradually.
This conclusion is validated by a 401-level MMC-HVDC
model in Figure 8(a), in which the dark dot stands for the
actual value acquired and we can see that it is nearly invariant
along with the increase of grouping layers.
However, the existing method in [21] can be adopted to
decrease the unnecessary switching transitions. Before the
capacitor voltages are gathered to sort, if the arm current is
positive, the capacitor voltages of SMs which are triggered on
during the last switching transition are multiplied by a con-
stant called maintaining factor (defined as “HF1 ”) which is
less than 1 (“HF1 < 1”). On the contrary, if the arm current
is negative, the capacitor voltages of the SMs which are trig-
gered on during the last switching transition are multiplied by
a maintaining factor (defined as “HF2 ”) which is more than 1
(“HF2 > 1”).
The flowchart of this method is shown in Figure 7, which
shows the detail principle to decrease the unnecessary switch-
ing transitions. In Figure 7, the Uc(i) (i = 1, 2 …N) is the
capacitor voltage of each submodule and UNUM is the number
of SMs triggered on during the last switching transition.
HF1 , HF2 are the maintaining factors used in sorting process.
As a result, the SMs triggered on during the last switching
transition will be continually chosen with a high probability,
and the switching frequency is reduced accordingly.
If the multilayer grouping method is applied, the reduced
switching frequency strategy employing the maintaining fac-
tors (HF1 , HF2 ) can be used in the last layer, of which SMs FIGURE 8. Relation between grouping layers and switching-
use the conventional sorting strategy, such as bubble sorting, frequency.
selection sorting, and insertion sorting.
A parameter “C” is defined to represent the difference
between the maintaining factor and the reference value:
C = |HM − 1| (19)
where HM is the value of the maintaining factor HF1 or HF2 . As
shown in Figure 8(a), the switching-frequency reduces more if
C becomes larger.
As shown in Figure 8(b), the running time decreases
sharply in the beginning, but the effectiveness of accelera-
tion is not obvious as the SMs are divided into more than two
layers. Therefore, there is a trade-off between the decrease of
switching frequency and the effectiveness of acceleration.
The relationship between the maintaining factor and ripple
of capacitor voltages is shown in Table 5, from which we can

Maintaining factor 0.96/1.04 0.94/1.06 0.92/1.08

Ripple of capacitor voltages ±4.69% ±5.56% ±7.86%

FIGURE 7. Flow chart of maintaining factor method. TABLE 5. Relationship between maintaining factor and ripple of
capacitor voltages.
 Zhao et al.: Capacitor Voltage Control Strategy Based On Prime Factorization
see that with the increase of the maintaining factor, the ripple
of capacitor voltages becomes higher as result.
To divide the SMs appropriately, we should principally
consider the fluctuation of capacitor voltages when choosing
the maintaining factor; secondly, choose the number of group-
ing layer with a comprehensive assessment of the accelera-
tion and switching frequency, considering with the increase
of grouping layers the running time cannot be reduced dra-
matically and the switching frequency increases, as shown in
Figure 8. Consequently, there is a favorable effectiveness of
acceleration with a relatively low switching frequency, which
reduces the complexity of multilayer grouping method to
some extent.
In conclusion, the frequency of IGBTs based on the prime
factorization strategy can be reduced by using the maintaining
factor method, and the calculation burden can also be reduced
in the meantime. Besides, it is noteworthy that if there is a lim-
itation for the quality of the waveform of the capacitor volt-
age, the ripple of the capacitor voltages should be taken into
consideration.
VI. CONCLUSION
This paper proposes a grouping strategy based on prime
factorization for capacitor voltage balancing of MMC. The
sorting steps of the prime factorization pattern are the mini-
mum when prime factors are arranged from the largest to the
smallest. The computation burden is substantially reduced
and a significant method for determining the grouping pattern
of sub modules is acquired and the conclusion is mathe-
matically proved. Effectiveness of the proposed grouping
strategy is evaluated based on the simulation of a 401-level
MMC-HVDC model in PSCAD/EMTDC environment. Sim-
ulation results verify that the capacitor voltage balancing
performance of the grouping strategy is close to that of
conventional method while the sorting steps of the prime
factorization pattern with prime factors arranged from the
largest to the smallest is reduced substantially, which agrees
with conclusions of the mathematical conclusion. To limit
the switching frequency, there is a trade-off between the
switching frequency and the grouping layers, which should
be taken into consideration for the guarantee of the quality of
the waveform of capacitor voltages.
FUNDING
National Natural Science Foundation of China [51507060];
the State Key Laboratory of Alternate Electrical Power Sys-
tem with Renewable Energy Sources [LAPS15017].
579
REFERENCES
[1] F. Schettler, H. Huang, and N. Christl, “HVDC transmission
systems using voltage sourced converters-design and applica-
tions,” Presented at Proc. IEEE PES Summer Meeting, Seattle,
WA, 2000.
[2] M. Guan, Z. Xu, and H. Chen, “Control and modulation strate-
gies for modular multilevel converter based HVDC system,”
Presented at IECON 2011-37th Conference on IEEE Industrial
Electronics Society, 2011, pp. 849–854.
[3] A. Lesnicar and R. Marquardt, “An innovative modular multi-
level converter topology suitable for a wide power range,” Pre-
sented at IEEE Bologna Power Tech Conf., 2003.
[4] S. Kouro et al., “Recent advances and industrial applications
of multilevel converters,” Ind. Electron., IEEE Trans., vol. 57,
no. 8, pp. 2553–2580, 2010. doi:10.1109/TIE.2010.2049719.
[5] S. Rohner, S. Bernet, and M. Hiller, “Modulation, Losses, and
Semiconductor Requirements of Modular Multilevel Convert-
ers,” IEEE Trans. Ind. Appl., vol. 57, pp. 2633–2642, 2010.
[6] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A new
multilevel converter topology with reduced number of power
electronic components,” IEEE Trans. Ind. Electron., vol. 59,
pp. 655–667, 2012. doi:10.1109/TIE.2011.2151813.
[7] S. P. Teeuwsen, “Modeling the trans bay cable project as
voltage-sourced converter with modular multilevel converter
design,” Presented at Power and Energy Society General Meet-
ing, Detroit, USA, 2011.
[8] J. Peralta et al., “Detailed and averaged models for a 401-level
MMC–HVDC system,” Power Deliv., IEEE Trans., vol. 27, no.
3, pp. 1501–1508, 2012. doi:10.1109/TPWRD.2012.2188911.
[9] F. Deng and Z. Chen, “A control method for voltage
balancing in modular multilevel converters,” IEEE Trans.
Power Electron., vol. 29, no. 1, pp. 66–76, January 2014.
doi:10.1109/TPEL.2013.2251426.
[10] B. P. Mcgrath and D. G. Holmes, “Natural capacitor volt-
age balancing for a flying capacitor converter induction motor
drive,” IEEE Trans. Power Electron., vol. 24, no. 6, pp. 1554–
1561, June 2009. doi:10.1109/TPEL.2009.2016567.
[11] B. P. Mcgrath and D. G. Holmes, “Natural current bal-
ancing of multicell current source converters,” IEEE Trans.
Power Electron., vol. 23, no. 3, pp. 1239–1246, May 2008.
doi:10.1109/TPEL.2008.921166.
[12] Q. Tu, Z. Xu, and L. Xu, “Reduced switching-frequency mod-
ulation and circulating current suppression for modular multi-
level converters,” IEEE Trans. Power Del., vol. 26, no. 3, pp.
2009–2017, July 2011. doi:10.1109/TPWRD.2011.2115258.
[13] J. Qin and M. Saeedifard, “Reduced switching-frequency
voltage-balancing strategies for modular multilevel HVDC
converters,” IEEE Trans. Power Del., vol. 28, no. 4, pp. 2403–
2410, October 2013. doi:10.1109/TPWRD.2013.2271615.
[14] K. Ilves, A. Antonopoulos, S. Norrga, and H. P. Nee, “A
new modulation method for the modular multilevel con-
verter allowing fundamental switching frequency,” IEEE Trans.
Power Electron., vol. 27, no. 8, pp. 3482–3494, August 2012.
doi:10.1109/TPEL.2012.2185832.
[15] Z. Chu, Y. Li, P. Wang, and Z. Li, “An improved voltage bal-
ancing method of modular multilevel converters,” Presented at
2014 9th IEEE Conference on Industrial Electronics and Appli-
cations, 2014, pp. 360–363.
580 Electric Power Components and Systems, Vol. 46 (2018), No. 5
[16] K. Ilves, L. Harnefors, S. Norrga, and H. P. Nee, “Predictive
sorting algorithm for modular multilevel converters minimiz-
ing the spread in the submodule capacitor voltages”, in Proc.
IEEE ECCE Asia Downunder, 2013, pp. 325–331.
[17] J. Qin and M. Saeedifard, “Predictive control of a modular
multilevel converter for a back-to-back HVDC system,” IEEE
Trans. Power Del., vol. 27, no. 3, pp. 1538–1547, July 2012.
doi:10.1109/TPWRD.2012.2191577.
[18] J. Rodriguez, J.-S. Lai, and F. Z. Peng, “Multilevel invert-
ers: a survey of topologies, control, and applications,” IEEE
Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, August 2002.
doi:10.1109/TIE.2002.801052.
[19] R. Sedgewick, Algorithms in C: Fundamentals, Data Struc-
tures, Sorting, Searching. Boston: Addison-Wesley Profes-
sional, 1997. Chap. 7.
[20] C. Gauss and A. A. Clarke, Disquisitiones Arithemeticae. New
Haven: Yale University Publication, 1965. Chap. 3.
[21] M. Saeedifard and R. Iravani, “Dynamic performance of a
modular multilevel back-to-back HVDC system,” IEEE Trans.
Power Del., vol. 25, no. 4, pp. 2903–2912, October 2010.
doi:10.1109/TPWRD.2010.2050787.
[22] U. N. Gnanarathna, A. M. Gole, and R. P. Jayasinghe, “Efficient
modeling of modular multilevel HVDC converters (MMC)
on electromagnetic transient simulation programs [J],” Power
Deliv., IEEE Trans., vol. 26, no. 1, pp. 316–324, 2011.
doi:10.1109/TPWRD.2010.2060737.
BIOGRAPHIES
Chengyong Zhao received the B.S., M.S., and Ph.D. degrees
in 1988, 1993, and 2001 respectively from North China Elec-
tric Power University (NCEPU), Beijing, China. Now he is
a professor and director of the State Key Laboratory of Alter-
nate Electrical Power System with Renewable Energy Sources
in NCEPU, and he is an IEEE senior member. His research
interests include HVDC and FACTS.
Ye Wang was born in Hebei province, China. She received
the B.Sc. degree in power systems and its automation from
NCEPU in 2016. Currently, she is pursuing the M.Sc. degree
in power system and its automation in NCEPU. Her research
field is HVDC.
Maolan Peng was born in Jiangxi, China. She received the
B.Sc. and M.Sc. degrees in power systems and its automation
from NCEPU in 2012 and 2015. Now she works as an engi-
neer for the Maintenance & Test Center of Extra High Voltage
Power Transmission Company of China Southern Power Grid
Co., Ltd, Guangzhou, China. Her research field is the control
and protection strategy of VSC-HVDC.
Zhipeng He was born in Sichuan province, China. He
received the B.Sc. degree in power systems and its automa-
tion from Xi’an University of Technology, Shaanxi, China, in
2013, and the M.Sc. degree in in power system and its automa-
tion from NCEPU in 2016. Now he is currently working in
the Electric Power Research Institute (EPRI), China Southern
Power Grid. His research field is HVDC.
Chunyi Guo received his B.Sc. and Ph.D degrees in power
system and its automation in 2007 and 2012 from NCEPU.
Now he is an associate professor of Power Grid with New
Energy Institute in NCEPU and he is an IEEE member.
His research interests include LCC-HVDC, VSC-HVDC, and
AC/DC interaction analysis.