THE DESIGN OF PHASE-LOCKED LOOP IN CONVERTOR IN GRID

A Project

Presented to the faculty of the Department of Electrical and Electronic Engineering

California State University, Sacramento

Submitted in partial satisfaction of

the requirements for the degree of

MASTER OF SCIENCE

in

Electrical and Electronic Engineering

by

Ming Lei

FALL
2016
 © 2016

Ming Lei

ALL RIGHTS RESERVED

ii
 THE DESIGN OF PHASE-LOCKED LOOP IN CONVERTOR IN GRID

A Project

by

Ming Lei

Approved by:

__________________________________, Committee Chair

Lianqing Zheng

__________________________________, Second Reader

Preetham Kumar, Ph.D

____________________________
Date

iii
Student: Ming Lei

I certify that this student has met the requirements for format contained in the University format

manual, and that this project is suitable for shelving in the Library and credit is to be awarded for

the project.

__________________________, Graduate Coordinator ___________________

Preetham Kumar, Ph.D Date

Department of Electrical and Electronic Engineering

iv
 Abstract

of

THE DESIGN OF PHASE-LOCKED LOOP IN CONVERTOR IN GRID

by

Ming Lei

Statement of Problem

Phase-locked loop (PLL) is a key technology in grid connected converters. It is also a most basic

technique in the grid connected inverter control system. The performance of the phase locking

synchronous circuit will directly influence the technical function and operation stability of the grid

connected converter. The phase angle and the frequency of the grid voltage are the most basic

information in the grid connected converter. Tracing this information accurately and rapidly is the

guarantee of the stable operation of grid connected inverter control systems.

Under the condition that voltage distortion and unbalance phenomenon becomes more and more

serious, the task of grid connected converters synchronous is to correctly detect the grid voltage

signal. Usually the most effective way is to use phase-locked-loop.

Sources of Data

1. Some papers, books from website;

2. Guidance from my advisors;

v
3. Simulation tools such as MATLAB

Conclusions Reached

This project uses two methods to design the phase locked loop of grid connected converter. The

ultimate goal of PLL is to obtain the phase angle difference between the original voltage and the

reference parameter. The first method uses the instantaneous multiplication principle of

trigonometric function to eliminate the harmonic component in the filter. The performance is

mainly related to the design parameters of filters. The second method applies Fourier discrete

transform of the original voltage to get the fundamental wave. The performance depends on the

design of the proportion integral regulator. Also a brief introduction is given for the third method

(zero crossing comparison method), which was the earliest one to be adopted in the single-phase

grid. Though this method is simple and easy to implement, it can break down quickly when

the power grid voltage distortion happens. To test the feasibility of the methods above, simulation

studies, based on these two methods, have been performed on MATLAB/SIMULINK, and tracking

results of PLL have been observed under different parameters conditions. Also, according to the

Bode diagram, stability of the designed system has been analyzed. By adjusting the system

parameters, it is hoped that the designed system can track the phase accurately and be in a stable

condition simultaneously.

_______________________, Committee Chair

Lianqing Zheng

vi
_______________________
Date

ACKNOWLEDGEMENTS

With the help of my advisor Dr. Kumar and Prof. Zheng, I have successfully completed my

project. I appreciate them giving a chance to explore this challenging and interesting project,

which can make me apply what I have learnt to this case.

I am highly indebted to Prof. Zheng and Dr. Kumar for their guidance and encouragement in my

life and my study. Whenever I had difficulty in understanding the academic knowledge and

simulating the complex model, Prof. Zheng would give me a lot of guidance and taught me

patiently. At the same time, I would thank Dr. Kumar for giving me constant supervision on the

completion of the project and reading my report.

Finally, I would like to thank my family and friends, who provided me support at any time. The

accomplishment of the project would not have been possible without them.

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 TABLE OF CONTENTS

Page

Acknowledgements..................................................................................................................... viii

List of Figures…………………………………………………………………………….…....... x

Chapter

1. INTRODUCTION……………………………………………………………………….............1

1.1 An Overview of Grid Connected Converters…………………………………………......1

1.2 Application Background of Phase-Locked Loop…………………..........................…......2

1.3 Research Status of Phase Locked Technology on Grid Connected Converter......................2

2. THE BASIC WORKING PRINCIPLE OF PLL...........................................................................4

2.1 Some Basic Concepts of PLL and Phase Relationships........................................................4

2.2 Working Conditions of PLL.................................................................................................6

2.3 Basic Components of PLL Loop..........................................................................................7

2.3.1 Phase detector (PD)..................................................................................................8

2.3.2 Loop filter...............................................................................................................10

2.3.3 Voltage controlled oscillator (VOC) ......................................................................11

2.3.4 Frequency synthesis................................................................................................12

viii
 2.4. Phase Model of PLL.........................................................................................................13

3. VIRTUAL MULTIPLIER PHASE DETECTOR.........................................................................17

3.1 Principle of Phase Discrimination.....................................................................................17

3.2 Low Pass Filter Design......................................................................................................18

3.3 Parameter Tuning of Single Phase Locked Loop PI Controller..........................................19

3.4 MATLAB Simulation........................................................................................................19

4. DFT AND FFT SIMULATIONS.................................................................................................27

4.1 Basic Principle Analysis....................................................................................................27

4.2 Engineering Realization....................................................................................................27

4.3 MATLAB/SIMULINK Simulations..................................................................................28

5. COMPARISON OF TWO PHASE-LOCKED LOOP METHOD...............................................34

5.1 Phase Identification Using Virtual Multiplier....................................................................34

5.2 Phase Discrimination Using DFT and FFT........................................................................34

6. SUMMARY.................................................................................................................................36

References.......................................................................................................................................37

ix
 LIST OF FIGURES

Figure Page

1. Simple PLL system...................................................................................................................4

2. Phase relationship of the input and output signal......................................................................5

3. Typical PLL structure................................................................................................................7

4. Idea phase detector character.....................................................................................................8

5. Mathematical model of multiplication phase discriminator......................................................9

6. Characteristics of multiplication phase discriminator...............................................................9

7. Low pass filter mathematical model.......................................................................................10

8. Structure and transfer function of loop filters.........................................................................11

9. Voltage control oscillator character.........................................................................................11

10. Voltage control oscillator mathematical model.......................................................................12

11. Phased-locked frequency multiplication schematic diagram..................................................13

12. Phased-locked frequency division schematic diagram............................................................13

13. PLL phase model....................................................................................................................14

x
14. PLL of Multiplication phase detector......................................................................................17

15. MATLAB/SIMULINK diagram of method using virtual multiplier detector..........................20

16. Simulation diagrams of method using virtual multiplier detector...........................................26

17. MATLAB/SIMULINK diagram of method using DFT..........................................................29

18. Simulation diagrams of method using DFT............................................................................34

xi
 1

CHAPTER 1

INTRODUCTION

1.1 An Overview of Grid Connected Converters

Our whole society has presented a new challenge to the quality of power supply. The majority of

power users not only require the power system to provide sufficient power, but also put

importance on the high reliability of power supply. Therefore, the flexible AC transmission

systems (FACTS) based on power electronics technology for enhancing the transmission capacity

of the power grid and custom power (CP) technology and improving the power quality of the

power distribution system, are proposed. At present, widely used FACTS and CP devices are

static VAR compensator (SVC), thyristor controlled series compensator (TCSC), gate turnoff

(GTO), insulated gate bipolar transistor (IGBT), static synchronous compensator (STATCOM)

and so on.

These power converters (rectifier or inverter) based on power electronics technology have a

common characteristic: they are connected in parallel or in series with the grid either directly or

through transformers and reactors, and they rely on the supply voltage to synchronize with the

grid. Therefore, we call such converters as grid-connected converters. The grid-connected

converters must run synchronously with the connected grid. To realize the synchronous operation

of the grid-connected converters and the grid, the frequency and phase of grid voltage must be

detected first.
 2

1.2 Application Background of Phase-Locked Loop

Phase lock synchronization technology and its specific implementation cannot be separated

from its specific application background. The focus of the requirements of the phase locked

synchronization circuit will be different if the application background is different.

On the one hand, the voltage quality of the grid is threatened by many aspects (including

distortion of voltage waveform and three-phase unbalance), which seriously affect the working

reliability and stability of synchronous phase-locked circuit. The grid voltage, as the synchronous

reference voltage, is not a sinusoidal waveform of constant frequency. On the other hand, the

grid-connected converters put forward higher requirements on the tracking performance and

stability of the phase-locked synchronous circuits. How to adopt new phase-detecting strategy

and algorithm to eliminate the influence of the voltage distortion on the grid phase detection is

what we should consider.

1.3 Research Status of Phase Locked Technology on Grid Connected Converter

Phase locked loop (PLL) is a closed-loop control system that automatically tracks the frequency

and phase of the input signal, and is based on the theory of synchronous detection proposed by

DeBellescize in 1932, when he first published the description of the PLL concept. The phase locked

loop was applied to the synchronization of the horizontal and vertical scanning of the TV receiver

until 1947. Because the technology was relatively complex and costly, it was mainly used in

satellite communications. With the development of semiconductor and related circuit technology
 3

in the seventies, a variety of monolithic phase-locked loop chip appeared gradually, which reduced

the cost of phase-locked technology and provided the advantages for the progress and development

of the phase lock technology.

Nowadays, there are a variety of different principles and solutions to achieve the phase-

locked goal. From the synchronous mode, it is divided into single-phase synchronization and

three-phase synchronization. In terms of principle, there is simple vector transformation method,

zero-crossing phase-locked loop which is based on the waveform and vector-based phase-locked

loop with hardware and software implementation.

 4

CHAPTER 2

THE BASIC WORKING PRINCIPLE OF PLL

2.1 Some Basic Concepts of PLL and Phase Relationships

PLL system is a phase track system, as shown below in Figure 1

Figure 1. Simple PLL system

Assuming that the input signal is ui (t)

ui (t) = Ui sin[wi t + θi (t)]

Assuming that the output signal is uo (t)

u0 (t) = U0 sin[w0 𝑡𝑡 + θ0 (t)]

where Ui and Uo are the peak amplitudes of input and output, which are always constant. We

want to find out the relationship between these two phases; it can be figured out that the difference

between the instantaneous phase of the input and the instantaneous phase of output is:

θe (t) = [wi (t) + θi (t)] − [w0 (t) + θ0 (t)] = (wi − w0 )t + θi (t) − θ0 (t)

As the frequency between the input and output signal is different, it is difficult to compare their

phases directly. It is a necessity to find a unified reference phase. Assuming that w0 t is the

reference phase, the instantaneous phase of input signal can be written as below:

wi (t) + θi (t) = w0 t + (wi − w0 )t + θi (t)

 5

Assuming that:

∆w0 = wi − w0

θ1 (t) = ∆w0 t + θi (t)

then we can get:

wi (t) + θi (t) = 𝑤𝑤0 𝑡𝑡 + 𝜃𝜃1 (𝑡𝑡)

Similarly, the instantaneous phase of output signal can be written as:

w0 (t) + θ0 (t) = 𝑤𝑤0 𝑡𝑡 + 𝜃𝜃2 (𝑡𝑡)

𝜃𝜃2 (𝑡𝑡) = 𝜃𝜃0 (𝑡𝑡)

As the input signal and the output signal have a common reference phase, it is much more easily

to get the phase difference between the input signal and the output signal.

(a) (b)

Figure.2 Phase relationship of the input and output signal

The input signal Ui (t) can be replaced by vector Ui ej[wi(t)+θi(t)] and the instantaneous phase

can be represented by the angle between the vector and real axis, as shown in Figure 2. Similarly,
 6

the output

uo (t) can be expressed by vector Uo ej[wo (t)+θo (t)] .

When wo (t) is chosen as the reference phase, we can get Figure 2 (b)

θe (t) = 𝜃𝜃1 (𝑡𝑡) − 𝜃𝜃2 (𝑡𝑡)

The instantaneous frequency difference can be expressed as:

dθe (t) ̇ = θ1 (t)

dθ (t) dθ (t)
̇ = ∆w0 + 1 − 2
̇ − θ2 (t)
= θe (t)
dt dt dt
̇ is different from θ2 (t)
When θ1 (t) ̇ , the angle difference between the input signal vector and

̇ is the same as θ2 (t)

output signal vector will increase over time. When θ1 (t) ̇ , these two vectors

will rotate with the same velocity. And the angle difference between these two vectors will be

constant, which is called the locking state of the system.

2.2 Working Conditions of PLL

There are three basic working conditions in PLL system including capture process,

synchronization state and locking state.

Capture process: It contains the whole process from the input signal put into the PLL system to

the locking state of the system. The instantaneous phase difference and the instantaneous

frequency difference vary over time. The time required for the capture process is related to the

system parameters and the initial state of the input signal. For some certain PLL system, whether

the capture process can be achieved totally depends on the initial frequency difference. If the

initial frequency is out of a certain range which is called capture zone, the capture process will
 7

not be implemented.

Synchronization state: When the capture process ends, the PLL system stays in a steady state.

Locking state: When the PLL circuit is in synchronization state, the frequency difference between

the input signal and the output signal is zero and the phase difference between them is constant.

This assumes the condition that the frequency of input signal is constant

θė (t)=0

θe (t)=constant

2.3 Basic Components of PLL Loop

PLL is a negative feedback phase control system, which can make the phase difference between

the output signal and the reference phase become zero. The typical PLL structure is shown below

in Figure 3.

Figure 3. Typical PLL structure

It consists of phase detector (PD), loop filter (LF) and voltage controlled oscillator (VCO). There

are many other different types of PLL loop in the practical applications; however, they all

evolve from this typical PLL structure. The difference between the PLL feedback control system
 8

and other normal control system is that normal control systems collect voltage and current signal

while the PLL system collects phase signal.

2.3.1 Phase detector (PD)

The phase detector is used to detect the phase difference θe (t) between the input signal

phase θ1 (t) and the output signal phase θ2 (t), and the relationship between the output error

signal ud (t) and θe (t) can be described as below:

𝑢𝑢𝑑𝑑 (𝑡𝑡) = 𝑓𝑓[θe (t)]

This function relationship can be called phase detector character. The ideal phase detector

character is linear (𝐾𝐾𝑑𝑑 is the coefficient gain of PD), as shown below in Figure 4, with the

condition:

ud (t) = K d θe (t)

Figure 4. Idea phase detector character

There are many different kinds of phase detector character like sinusoidal character, triangular

character, zigzag character and so on. When signal to noise ratio (SNR) reduces, many PD
 9

characters tend to be sinusoidal character. Hence, sinusoidal phase detector is always adopted to

analyze the principle of PLL. Assuming that the function of PD is fulfilled by multiplier unit.

and the coefficient of the multiplier is 𝐾𝐾𝑚𝑚

ud (t) = K m ui (t)u0 (t) = K m Ui sin[w0 t + θ1 (t)]U0 cos[w0 t + θ2 (t)

= 0.5K m Ui U0 sin[2w0 t + θ1 (t) + θ2 (t)] + 0.5K m Ui U0 sin[θ1 (t) − θ2 (t)]

When ud (t) passes through low pass filter, frequency of 2𝑤𝑤𝑜𝑜 part can be removed, as shown

below in Figure 5, and output shown in Figure 6. Then we can obtain:

ud (t) = 0.5K m Ui U0 sin[θ1 (t) − θ2 (t)]

Assuming that Ud = K m Ui U0 /2, then:

ud (t) = Ud sinθe (t)

Figure 5. Mathematical model of multiplication phase discriminator

 10

Figure 6. Characteristics of multiplication phase discriminator

2.3.2 Loop Filter

Loop filter (LF) is used to suppress the high-frequency signal portion of the PD output and

produce DC control signal to voltage controlled oscillator (VCO). In addition to its low pass

characteristics, it plays a decisive role in adjusting the loop parameters.

Loop filters can be divided into two kinds: passive filters and active filters and both of them

are mainly composed of resistors, capacitors, inductors or linear components. The difference is

that only active filters include operational amplifiers. Either filter can be regarded as a linear

system and the complex domain expression for the loop filter can be written as:

uc (s) = F(s)ud (s)

am s m + am−1 sm−1 + ⋯ + a0
F(s) =
bn s n + bn−1 sn−1 + ⋯ + b0

ud (s)and uc (s) are respectively the Laplace transform of input signal and output signal in LF,as

shown below in Figure 7.

Figure 7. Low pass filter mathematical model

There are three conventional loop filters: RC integral filter (RCIF), passive proportional integral

filter (PPIF) and active proportional integral filter (APIF). Their circuit configuration and transfer
 11

function are shown in Figure 8

RCIF PPIF APIF

Figure 8. Structure and transfer function of loop filters

2.3.3 Voltage Controlled Oscillator (VCO)

VCO is actually a voltage-frequency converter and its character can be expressed in Figure 9.

Figure 9. Voltage control oscillator character

wv (t) is instantaneous angular frequency and Uc (t) is control voltage. In a certain range, the

relationship between wv (t) and Uc (t) is linear: wv (t) = w0 + K 0 Uc (t), where w0 is the free

oscillation angular frequency and k 0 is the gain of VCO. From PD character, it is easy to know

that wv (t) cannot function on PD. Instead, the instantaneous phase angle θv (t) should function

on PD and θv (t) is the integral result of wv (t).

 12

t
θv (t) = w0 t + K 0 � uc (t)dt
0

Putting this equation into the form of transfer operator:

θv (t) = w0 t + K 0 uc (t)/p

From the equation above, it is easy to get the output, as shown in Figure 10:

𝜃𝜃2 (𝑡𝑡) = 𝐾𝐾0 𝑢𝑢𝑐𝑐 (𝑡𝑡)/𝑝𝑝

Figure 10. Voltage control oscillator mathematical model

There is an integral factor 1/p in the VCO model, which resulted from the integral relationship

between phase and angular frequency. The output of the voltage controlled oscillator is required to

be a phase in the phase locked loop and the integral part is inherent in the VCO. Hence the voltage

controlled oscillator is called the inherent integral part of the phase locked loop.

2.3.4 Frequency Synthesizer

Frequency synthesizer can produce a large number of frequency sources which have the same

accuracy and stability as the high precision and high stability reference frequency input. After the

process of frequency mixing, frequency multiplication and frequency division, the reference

frequency can be made full use of by the frequency synthesizer.

The method of frequency synthesis using phase locked loop is called indirect synthesis, which is
 13

the most widely used method of frequency synthesis. The most commonly used circuits are phase-

locked frequency multiplication circuit and phase-locked frequency division circuit.

Phase-locked frequency multiplication circuit (there is a frequency divider in the feedback branch)

is shown below Figure 11:

w0 = Nwi

Figure 11. Phased-locked frequency multiplication schematic diagram

Phase-locked frequency division circuit (there is a frequency multiplier in the feedback branch) is

shown below Figure 12:

w0 = wi /N

Figure 12. Phased-locked frequency division schematic diagram

2.4. Phase Model of PLL

It is easy to conclude that this is a phase negative feedback error control system from Figure 13.
 14

The error phase θe (t) can be obtained by comparing the input phase θ1 (t) and the feedback

output phase θ2 (t) and the error voltage ud (t) is resulted from the error phase θe (t). After the

error voltage passes through the loop filter, the control voltage uc (t) can be obtained. Then the

control voltage is applied to the voltage controlled oscillator to generate a frequency offset to

track the input signal frequency wi (t). If the input frequency is a fixed frequency, the output

frequency will get close to the input frequency under the effect of the control voltage. Once the

two frequencies are equal, the loop will be able to stabilize and reach to the lock state if some

certain conditions are meet. After they enter the locking state, the controlled VCO frequency will

be the same as the input signal frequency and there is a steady state phase difference between the

two phases. The steady-state error is a necessity to maintain the error voltage and the control

voltage. If the steady-state difference does not exist, the control voltage will disappear and then

the VCO oscillation frequency will return to its free oscillation frequency, which will make the

loop not able to reach the locking state. The residual error is a characteristic of the error control

system. This model directly gives out a relationship between the input phase and the output phase,

so it is also called the phase model of the loop, which is the basis of the further analysis of the

phase locked loop.

 15

Figure 13. PLL phase model

From the phase model, we can get the loop dynamic equation:

pθe (t) = pθ1 (t) − KF(p)sinθe (t)

where k = ud k 0 is the loop gain. Obviously, the loop dynamic equation is a nonlinear

differential equation, which results from the nonlinear characteristics of the phase detector. The

order of the equation depends on the loop filter F(p). Since the voltage-controlled oscillator is an

inherent integral part, the order of the loop dynamic equation is equal to the order of the loop

filter plus one. It can be seen that the simplest phase-locked loop which has no loop filter is the

first order ring. The phase-locked loop using a first-order loop filter is the second order ring.

Though the full performance of the loop can be obtained by solving the differential equation, only

the first-order loop can be precisely solved. The second-order loop or above can only be analyzed

by some approximate methods or make use of computers to get the numerical solution. Because

many of the first-order loop performance is not satisfactory, it is rarely used. The most commonly

used PLL is the second order phase locked loop.

Loop filters as shown in Figure 8 are the most commonly used loop filters which are all the

first order

in the second order phased locked loop. In the physical sense, pθe (t) in the the loop equation is

the instantaneous frequency difference of the loop. Taking θ1 (t) = ∆w0 t + θi (t) into account,

θi (t) is constant when the frequency of input is fixed, and pθ1 (t) is the natural frequency of the
 16

loop. The last term in the loop equation KF(p)sinθe (t) = K 0 Uc (t) is the frequency difference

between the voltage-controlled oscillator frequency wv (t) caused by the control voltage relative

to the free-running frequency w0 . Thus, the loop dynamic equation describes the following

relationship:

instantaneous frequency difference = inherent frequency difference - control frequency

difference. This relationship is the basic formula of the phase-locked loop, which is always true in

the loop.
 17

CHAPTER 3

VIRTUAL MULTILIER PHASE DETECTOR

3.1 Principle of Phase Discrimination

Virtual multiplier phase detector is a traditional sinusoidal phase detector and its principle block

diagram is shown below Figure 14

Figure 14. PLL of Multiplication phase detector

The input signal is typically a normalized, processed power supply voltage ui

ui = sin(wi t + φi )

and the base angular frequency is generally set to the angular frequency corresponding to 50 Hz of

the center frequency of the grid voltage. The setting of base angular frequency is used to generate

the initial sine and cosine signals ua and ub .

ua = sin(wa t + 𝜑𝜑𝑎𝑎 )

ub = sin(wb t + 𝜑𝜑𝑏𝑏 )

After the function of the multiplier, the expression of ua and ub is as following:

ua ub = 0.5 sin[(wi − wa )t + φi − φa ] + 0.5 sin[(wi + wa )t + φi + φa ]

wi + wa ≈ 2wi
 18

When ua ub passes through the low-pass filter whose cut-off frequency is far less than wi , only

0.5 sin[(wi − wa )t + φi − φa ] part can go through. Then, this signal is input to the PI controller

to correct the frequency and the phase of the output until ua and ui have the same frequency

and the same phase.

In order to simplify the control structure, the approximation algorithm of the sinusoidal

function near the zero phase could be used. By using this approximation algorithm, the phase-

locked loop output signal sin[(wi − wa )t + φi − φa ] near the operating point could be replaced

by the approximate expression (wi − wa )t + φi − φa, where

wb is the basic angular frequency setpoint.

Generally, wb = 2𝜋𝜋𝑓𝑓𝑏𝑏 = 100𝜋𝜋

3.2 Low Pass Filter Design

According to the computing ability of the control system, the low-pass filter can adopt the first-

order structure, such as the first order inertial filter or the periodic average filter. It can also adopt

the second order structure, such as Butterworth low-pass filter. In order to effectively filter the

noise of the angular frequency of more than 𝑤𝑤𝑖𝑖 , the cut-off angle frequency of the low-pass filter

can be generally set below wi /10, but too-low cut-off angle frequency will make the adjustment

time of PLL be too long.

The Transfer Function of a first order inertial filter or a periodic average filter can be expressed

as:
 19

G(s)=0.5/(Ts+1)

Where T is the time constant of the first-order inertia filter or the filter period of the period

averaging filter. 1 / T is also the cut-off frequency of the low-pass filter and 1 / T should be less

than wi /10.

The Transfer Function of a second order structure can be expressed as:

G(s)=0.5/(Ts+1)2

Similarly, the cut-off frequency 1 / T should also be less than wi /10. When the frequency is

greater than the cut-off frequency, the gain of the decay rate in the second order filter is much

faster than in the first order, so the filtering effect in the second order filter is significantly

improved. As the phase shift increases in the second order filter, the adjustment time also

increases.

3.3 Parameter Tuning of Single Phase Locked Loop PI Controller

Assuming that the PI controller transfer function can be expressed as:

G(s) = K(τs + 1)/τs

For the first order low pass filter, the open loop transfer function of the phase locked loop can be

written as:

G(s) = K(τs + 1)/[τs 2 (Ts + 1)]

This is a typical form of type II system.

 20

3.4 MATLAB Simulation

The MATLAB/Simulink block of the method one (virtual multiplier method) is shown below in

Figure 15

Figure 15. MATLAB/SIMULINK diagram of method using virtual multiplier detector

After the phase angle of the grid signal which has been processed by the sine wave and the phase

angle of the feedback signal which has been processed by the cosine wave are subjected to the

multiplier, uab can be obtained.

ua = sin(wa t + 𝜑𝜑𝑎𝑎 )
 21

ub = sin(wb t + 𝜑𝜑𝑏𝑏 )

After uab is filtered through the first order filter, the higher harmonics have been filtered out.

After several such feedback filtering, the result of the rest of the signal wave is sin∆𝜃𝜃. ∆𝜃𝜃 will

be getting smaller and smaller after such repeated adjustment feedback. Therefore, the

approximation of sin∆𝜃𝜃 can be seen as ∆𝜃𝜃 . When ∆𝜃𝜃 is 0 or approximately 0 (there will

always be error in filter filtering and it cannot completely filter out higher harmonics), it can be

considered that the phase locked loop has tracked on the phase signal of the grid.

Assuming that:

the form of the first order filter is 1/(1+ τ s);

the standard frequency of the grid is 50hz;

the frequency of high order harmonics is around 100hz;

So we take tenth of 100hz (10hz) as the cut off frequency.

w=2πf=20π

𝜏𝜏=1/w=1/20π=0.016

Assume that the transfer function of PI controller is:

kp
f(s) = k i + = k(τs + 1)/s
s

the open loop transfer function of the whole closed loop feedback is:

F(s) = k(τs + 1)/[(1 + 0.016s)s2 ]

There are two conditions in the bode diagram:

 22

Condition 1: trend of the graph is from -40dB / decade to -20dB / decade and then back to -40dB /

decade.

Condition 2: trend of the graph is from -40dB / decade to-60dB / decade and then back to - 40dB /

decade.

From the bode diagram, it can be concluded that the system stability in condition 1 is higher

than in condition 2.

The line with a slope of -20 dB / decade between the two turning points in the bode diagram

should cross the lgw horizontal axis.

One of the turning points is 𝑤𝑤1 = 20𝜋𝜋 = 62.8; Another turning point is 𝑤𝑤2 = 1/𝜏𝜏. Assume that

1 20𝜋𝜋
= = 2𝜋𝜋 = 6.28, then 𝜏𝜏 =0.16.
𝜏𝜏 10

Take the point of intersection between the slope of -20dB / decade line in the bode map and lgw

axis is 10π (31.4). Then 20lg（31.4/6.2）=14dB.

So the line 𝑦𝑦1 = −40 lg 𝑤𝑤 + 20𝑙𝑙𝑙𝑙𝑙𝑙 pass through the point （lg6.28，14）

Then K=197.7

Then 𝐹𝐹(𝑠𝑠) = 197.7(0.16𝑠𝑠 + 1)/[(1 + 0.016𝑠𝑠)𝑠𝑠 2 ]

 23

Figure 16(a) below reflects two signals: one is the grid phase signal, another is tracking phase signal

of phase locked loop. These two signals should both increase over time. Due to the fact that tracking

error is very small, these two lines are basically coincident.

16(a) Simulation image of scope 2

 24

Figure 16(b) reflects the phase difference between the grid phase signal and the phase of the

tracking signal in the phase-locked loop. Due to the design factors of the first order filter and PI

regulator, there are some errors in the phase locked loop tracking. But the error which is in one

thousandth is small.

16(b) Simulation image of scope 2

 25

Figure 16(c) below gives that the purple line stands for the sine-processed phase signal of the grid,

the yellow line and the green line are basically coincident. The yellow line stands for the cosine-

processed phase signal of the grid and the green line represents the cosine-processed tracking phase

signal in the phase-locked loop. When the phase locked loop is stable, the phase difference between

the purple line and the green line is 90 degrees and the phase difference between the yellow line

and the green line is, which means that the phase locked loop has reached its phase-locked function.

16(c) Simulation image of scope

 26

The Bode diagram of the system is shown below in Figure 16(d).From this bode diagram, it can be

concluded that the margin of the system is about 50 degrees. Although the system margin is more

than 45 degrees, the system is relatively stable （because 50 degrees is not much more than 45

degrees

16(d) Bode diagram of method one

Figure 16. Simulation diagrams of method one

 27

CHAPTER 4

DFT AND FFT SIMULATIONS

4.1 Basic Principle Analysis

Phase tracking capability is an important index to evaluate the PLL performance. The phase-

locked method based on Fourier transform is realized by discrete Fourier transform, which can

perform a fast phase detection.Since the DFT is calculated once per power frequency cycle, the

equivalent delay time constant (Te) for this phase discriminator is about one power frequency

cycle. The principle of trigonometric functions maps time domain functions into the frequency

domain.

Let f (t) be a function of period T, then f (t) can be expanded to Fourier series:

𝑓𝑓(𝑡𝑡) = 𝑎𝑎0 + 𝑎𝑎1 sin(𝑤𝑤𝑤𝑤) + 𝑏𝑏1 cos(𝑤𝑤𝑤𝑤) + 𝑎𝑎2 sin(2𝑤𝑤𝑤𝑤) + 𝑏𝑏2 cos(2𝑤𝑤𝑤𝑤) + ⋯

1 𝑇𝑇 1 𝑇𝑇
𝑎𝑎0 = ∫0 𝑓𝑓(𝑡𝑡)𝑑𝑑𝑑𝑑, 𝑎𝑎1 = ∫0 𝑓𝑓(𝑡𝑡)sin(𝑤𝑤𝑤𝑤)𝑑𝑑𝑑𝑑
𝑇𝑇 𝑇𝑇

2 𝑇𝑇 2 𝑇𝑇
𝑏𝑏1 = ∫0 𝑓𝑓(𝑡𝑡)cos(2𝑤𝑤𝑤𝑤)𝑑𝑑𝑑𝑑, 𝑎𝑎2 = ∫0 𝑓𝑓(𝑡𝑡)sin(2𝑤𝑤𝑤𝑤)𝑑𝑑𝑑𝑑
𝑇𝑇 𝑇𝑇

2 𝑇𝑇
𝑏𝑏2 = � 𝑓𝑓(𝑡𝑡)cos(2𝑤𝑤𝑤𝑤)𝑑𝑑𝑑𝑑
𝑇𝑇 0
𝑏𝑏
The phase angle of the fundamental wave component 𝜃𝜃1 = tan−1 ( 1�𝑎𝑎1 ). If we take the output

signal of the phase locked loop as the reference phase and perform the Fourier transform on the

target signal (f (t)) of the phase locked loop, then 𝜃𝜃1 is the phase difference between the output

signal of the phase locked loop and the target signal of the phase locked loop.
 28

4.2 Engineering realization

To use DSP to achieve phase-locked algorithm in practical applications, the time-domain

continuous function of the Fourier transform should be converted to time domain DFT. If the

continuous function f (t) is sampled as a sequence of f (nTs) and Ts is the sampling period, the

expression for DFT is:

𝑓𝑓(𝑛𝑛𝑛𝑛) = 𝐴𝐴0 + 𝐴𝐴1 sin(𝑤𝑤𝑤𝑤𝑤𝑤𝑤𝑤) + 𝐵𝐵1 cos(𝑤𝑤𝑤𝑤𝑤𝑤𝑤𝑤) + 𝐴𝐴2 sin(2𝑤𝑤𝑤𝑤𝑤𝑤𝑤𝑤) + 𝐵𝐵2 cos(2𝑤𝑤𝑤𝑤𝑤𝑤𝑤𝑤) + ⋯

Where N is the number of sampling points per power frequency cycle. The coefficients are given

below:

1 𝑁𝑁
𝐴𝐴0 = ∑
𝑁𝑁 𝑛𝑛=1
𝑓𝑓(𝑛𝑛𝑛𝑛𝑛𝑛),

𝑁𝑁
2 2𝜋𝜋𝜋𝜋
𝐴𝐴1 = � 𝑓𝑓(𝑛𝑛𝑛𝑛𝑛𝑛) sin( )
𝑁𝑁 𝑁𝑁
𝑛𝑛=1

2 𝑁𝑁 2𝜋𝜋𝜋𝜋
𝐵𝐵1 = ∑ 𝑓𝑓(𝑛𝑛𝑛𝑛𝑛𝑛) cos( 𝑁𝑁 );
𝑁𝑁 𝑛𝑛=1

2 𝑁𝑁 4𝜋𝜋𝜋𝜋
𝐴𝐴2 = ∑ 𝑓𝑓(𝑛𝑛𝑛𝑛𝑛𝑛) sin( 𝑁𝑁 );
𝑁𝑁 𝑛𝑛=1

2 𝑁𝑁 4𝜋𝜋𝜋𝜋
𝐵𝐵2 = ∑ 𝑓𝑓(𝑛𝑛𝑛𝑛𝑛𝑛) cos( 𝑁𝑁 );
𝑁𝑁 𝑛𝑛=1

𝐵𝐵
The phase angle of the fundamental wave component 𝜃𝜃1 = tan−1 ( 1�𝐴𝐴 )
1

The sampling algorithm of the grid voltage is executed for a fixed Ts, where F (nTs) is the grid

voltage of the nth Ts sample. And 2π n/ N is the angle of the nth Ts phase-locked output signal.

Calculating every 𝐴𝐴1 , 𝐵𝐵1 and 𝜃𝜃1 when one power frequency cycle is over and in order to

simplify the operation process, the grid voltage is usually normalized. When the phase tends to be

𝐵𝐵
locked, 𝐴𝐴1 tends to be 1 and 𝐵𝐵1 tends to be 0. Then 𝜃𝜃1 = tan−1 ( 1�𝐴𝐴 ) ≈ 𝐵𝐵1
1
 29

4.3 MATLAB/SIMULINK Simulations

Figure 17 below gives the Simulink model of the method using DFT

Figure 17. MATLAB/SIMULINK diagram of method using DFT

Where Pi / 3 can be replaced by any angle; it only represents the initial phase angle of the grid.

The effective amplitude of the grid voltage is normalized and the grid voltage is set to be:

U = sin[wi t + 𝜑𝜑]

𝜑𝜑 is the initial phase angle and it could be any angle.

Assume that:

The fundamental frequency of the grid is 50hz;

The cycle time is 20ms;

 30

Samples are taken 20 times per cycle;

N=20; 2/N=0.1;

Since the cycle time is 20ms and samples are taken 20 times per cycle, it means that a data is

sampled every one millisecond and the sampled data updates every one millisecond. For

convenience, we add a tool that allows the signal to update 20 data every 20ms. After DFT

conversion, 𝐴𝐴1 , 𝐵𝐵1 and 𝜃𝜃1 could be obtained. Then MATLAB could put these results in the PI

regulator for closed loop feedback.

The transfer function of the entire DFT transform could represent as:
1
F1 (s) = Ts (T=0.02s)
+1
2

The open-loop transfer function of the whole feedback can be written as:

F(s) = k(τs + 1)/[s 2 (0.01s + 1)]

According to the above-mentioned calculation method for the virtual multiplication phase

detector, we could assume that:

1 100
= = 10, 𝜏𝜏 = 0.1
𝜏𝜏 10

Taking the point of intersection between the slope of -20dB / decade line in the bode map and lgw

50
axis is 50, the corresponding vertical coordinate is 20 log = 14𝑑𝑑𝑑𝑑
10

So the line

y1 = −40 lg w + 20lgk pass through （lg10,14）,

and then K=507.1

 31

The open-loop transfer function of the whole feedback can be written as:

F(s) = 507.1(0.1s + 1)/[(1 + 0.01s)s2 ]

Figure 18(a) below reflects two signals: one is the grid phase signal, another is tracking phase signal

of phase locked loop. These two signals should both increase over time. Due to the tracking error

is very small, these two lines are basically coincident.

18(a) Simulation image of scope

 32

A 0.1hz perturbation signal added to the system

From the picture in Figure 18(b) below, we can see that the phase-locked loop has already tracked

the phase of the grid at 0.3s. When there is a perturbation signal added to the system, the phase

locked loop tracked the the phase of the grid at 0.6s.

18(b) Simulation image of scope 1

 33

From the picture in Figure 18(c) below, we could see that ∆𝜃𝜃 becomes 0 at 0.6s, which means that

the phase locked loop has already tracked the phase of the grid.

18(c) Simulation image of scope 2

 34

From this bode diagram shown in Figure 18(d) below, it can be concluded that the margin of the

system is about 47 degrees. Although the system margin is more than 45 degrees, the system is

relatively stable.

18(d) Bode diagram of method two

Figure 18. Simulation diagrams of method using DFT

 35

CHAPTER 5

COMPARISON OF TWO PHASE-LOCKED LOOP METHOD

5.1 Phase identification Using virtual multiplier

For the phase identification using virtual multiplier, the phase detector which uses such multiplier

technology contains a filter in the PLL. Owing to the good tracking characteristics of PLL, it is

easy for the filter to filter out the harmonics of tens of Hertz or even several Hertz in the input

signal. However, if only the general low-pass filter is adopted, the inertia time constant of the

filter must be made very big to filter the harmonics which is above 100 Hz, which will reduce the

system's response speed. In addition, when there is high order harmonics in the power grid

voltage, some high-frequency components must exist in the input signal, which is difficult for the

general filter to filter out all the harmonics.

Since the output voltage of the analog multiplier varies with the amplitude of the input signal,

the gain of the phase detector is affected by the amplitude variation. So the virtual multiplier is

seldom used. However, in the case where the input signal contains some noises, this

multiplication is used to simulate the phase detector. In some cases, a multiplying analog phase

detector can also be used as a frequency detector.

5.2 Phase discrimination using DFT and FFT

Frequency domain digital phase detection technology performs Fourier transform to the discrete

signal and the result is a complex number, which contains a wealth of phase information. For a
 36

single frequency signal which is processed by the FFT transform, there is only one line in the

power spectrum (where f is the signal frequency, Vf is the frequency resolution and f = n · Vf).

For the two sequences which are processed by Fourier transform respectively, the phase

difference can be obtained by calculating the initial phase of the first n spectral lines of the

amplitude spectra respectively. The accuracy of the FFT phase detection technology can be very

high. As the accuracy of the system frequency resolution will affect the accuracy of the phase

resolution, an appropriate increase in the acquisition frequency can improve the accuracy of phase

discrimination. Compared with some analog phase detection methods, the digital phase detector

based on FFT has the advantages of high precision, small size, fast speed and so on. FFT phase

detection technology is widely used in laser ranging, positioning and other fields.

Phase discrimination technology has been widely used in various engineering fields, hence it is

helpful to find the necessary phase discrimination technology in different kinds of applications,

which is important to improve the speed of the engineering design.

 37

CHAPTER 6

SUMMARY

Phase-locked loop is very important to the status of the grid. Only by tracking the grid phase, the

electrical input power can be put into the grid at the right time and the electrical equipment can be

accurately connected to the grid.

In this project, two different methods of PLL design are used and simulated in the

MATLAB/SIMULINK. One is virtual instantaneous multiplication, and the other is using Fourier

discrete transform. It can be found that the effect of DFT is obvious better. The simulations with

virtual instantaneous multiplication cannot reach the zero error, which means that the ideal effect

is not achieved. However, the discrete Fourier method can achieve the zero error and the

simulation speed is relatively fast.

 38

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