DIGITAL ASSIGNMENT 1:

Step 1:
In Xilinx ISE, write Verilog module and test fixture to design using either structural, behavioral
and dataflow modelling techniques.
1) All logic gates
2) Half Adder
3) Full Adder
4) Half Subtractor
5) Full Subtractor
6) Full Adder using Two Half Adders
Capture the waveform in case 1) to 6) into a word file.

Step 2:
Handwrite the code in Verilog module using all three modelling techniques that you simulated
in case 1) to 6). Attach a printout of waveform from Step 1).

Step 3:
The hardcopies need to be signed by me. First page of hardcopy with sign, should be uploaded in
the Digital Assignment 1 link in moodle by 17th Jan 2020.