Precision, Very Low Noise, Low Input Bias Current,

Wide Bandwidth JFET Operational Amplifiers

Date Sheet AD8510/AD8512/AD8513
FEATURES PIN CONFIGURATIONS
Fast settling time: 500 ns to 0.1%
NULL 1 8 NC NULL 1 8 NC
Low offset voltage: 400 μV maximum AD8510 AD8510
–IN 2 7 V+ –IN 2 7V+
Low TCVOS: 1 μV/°C typical +IN 3 TOP VIEW 6 OUT +IN 3 TOP VIEW 6 OUT
(Not to Scale) (Not to Scale)
Low input bias current: 25 pA typical at VS = ±15 V V– 4 5 NULL V– 4 5 NULL

02729-003

02729-004
Dual-supply operation: ±5 V to ±15 V
NC = NO CONNECT NC = NO CONNECT
Low noise: 8 nV/√Hz typical at f = 1 kHz
Figure 1. 8-Lead MSOP (RM Suffix) Figure 2. 8-Lead SOIC_N (R Suffix)
Low distortion: 0.0005%
No phase reversal
OUT A 1 8 V+ OUT A 1 8 V+
Unity gain stable AD8512
–IN A 2 AD8512 7 OUT B –IN A 2 7 OUT B
TOP VIEW +IN A 3 TOP VIEW 6 –IN B
APPLICATIONS +IN A 3 6 –IN B
(Not to Scale)

02729-002
(Not to Scale)

02729-001
V– 4 5 +IN B V– 4 5 +IN B
Instrumentation
Multipole filters Figure 3. 8-Lead MSOP (RM Suffix) Figure 4. 8-Lead SOIC_N (R Suffix)
Precision current measurement
Photodiode amplifiers OUT A 1 14 OUT D OUT A 1 14 OUT D
Sensors –IN A 2 13 –IN D –IN A 2 13 –IN D
Audio +IN A 3 12 +IN D +IN A 3 12 +IN D
AD8513 AD8513
V+ 4 TOP VIEW 11 V– V+ 4 TOP VIEW 11 V–

+IN B 5 (Not to Scale) 10 +IN C +IN B 5 (Not to Scale) 10 +IN C

–IN B 6 9 –IN C –IN B 6 9 –IN C

02729-005

02729-006
OUT B 7 8 OUT C OUT B 7 8 OUT C

Figure 5. 14-Lead SOIC_N (R Suffix) Figure 6. 14-Lead TSSOP (RU Suffix)

GENERAL DESCRIPTION
The AD8510/AD8512/AD8513 are single-, dual-, and quad-
precision JFET amplifiers that feature low offset voltage, input
bias current, input voltage noise, and input current noise.
The combination of low offsets, low noise, and very low input
bias currents makes these amplifiers especially suitable for high
impedance sensor amplification and precise current measurements
using shunts. The combination of dc precision, low noise, and
fast settling time results in superior accuracy in medical
instruments, electronic measurement, and automated test
equipment. Unlike many competitive amplifiers, the AD8510/
AD8512/AD8513 maintain their fast settling performance even
with substantial capacitive loads. Unlike many older JFET
amplifiers, the AD8510/AD8512/AD8513 do not suffer from
output phase reversal when input voltages exceed the maximum
common-mode voltage range.
Fast slew rate and great stability with capacitive loads make the
AD8510/AD8512/AD8513 a perfect fit for high performance
filters. Low input bias currents, low offset, and low noise result
in a wide dynamic range of photodiode amplifier circuits. Low
noise and distortion, high output current, and excellent speed
make the AD8510/AD8512/AD8513 great choices for audio
applications.
The AD8510/AD8512 are both available in 8-lead narrow SOIC_N
and 8-lead MSOP packages. MSOP-packaged parts are only
available in tape and reel. The AD8513 is available in 14-lead
SOIC_N and TSSOP packages.
The AD8510/AD8512/AD8513 are specified over the −40°C to
+125°C extended industrial temperature range.

Rev. J Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2002–2017 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD8510/AD8512/AD8513
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics ............................................................. 4
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Typical Performance Characteristics ............................................. 7
General Application Information ................................................. 13
Input Overvoltage Protection ................................................... 13
REVISION HISTORY
6/2017—Rev. I to Rev. J
Changes to Figure 14 Caption......................................................... 8
Deleted Figure 39; Renumbered Sequentially............................. 12
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
2/2009—Rev. H to Rev. I
Changes to Figure 25 ...................................................................... 10
Changes to Ordering Guide .......................................................... 20
10/2007—Rev. G to Rev. H
Changes to Crosstalk Section ........................................................ 18
Added Figure 58.............................................................................. 18
6/2007—Rev. F to Rev. G
Changes to Figure 1 and Figure 2 ................................................... 1
Changes to Table 1 and Table 2 ....................................................... 3
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
6/2006—Rev. E to Rev. F
Changes to Figure 23 ........................................................................ 9
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
6/2004—Rev. D to Rev. E
Changes to Format ............................................................. Universal
Changes to Specifications ................................................................ 3
Updated Outline Dimensions ....................................................... 19
10/2003—Rev. C to Rev. D
Added AD8513 Model ....................................................... Universal
Changes to Specifications ................................................................ 3
Rev. J | Page 2 of 20
Date Sheet
Output Phase Reversal ............................................................... 13
Total Harmonic Distortion (THD) + Noise .............................. 13
Total Noise Including Source Resistors ................................... 13
Settling Time ............................................................................... 14
Overload Recovery Time .......................................................... 14
Capacitive Load Drive ............................................................... 14
Open-Loop Gain and Phase Response .................................... 15
Precision Rectifiers..................................................................... 16
I-V Conversion Applications .................................................... 17
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
Added Figure 36 through Figure 40 ............................................. 10
Added Figure 55 and Figure 57 .................................................... 17
Changes to Ordering Guide .......................................................... 20
9/2003—Rev. B to Rev. C
Changes to Ordering Guide ............................................................4
Updated Figure 2 ............................................................................ 10
Changes to Input Overvoltage Protection Section .................... 10
Changes to Figure 10 and Figure 11 ............................................ 12
Changes to Photodiode Circuits Section..................................... 13
Changes to Figure 13 and Figure 14 ............................................ 13
Deleted Precision Current Monitoring Section ......................... 14
Updated Outline Dimensions ....................................................... 15
3/2003—Rev. A to Rev. B
Updated Figure 5 ............................................................................ 11
Updated Outline Dimensions ....................................................... 15
8/2002—Rev. 0 to Rev. A
Added AD8510 Model ....................................................... Universal
Added Pin Configurations ...............................................................1
Changes to Specifications .................................................................2
Changes to Ordering Guide .............................................................4
Changes to TPC 2 and TPC 3 ..........................................................5
Added TPC 10 and TPC 12..............................................................6
Replaced TPC 20 ...............................................................................8
Replaced TPC 27 ...............................................................................9
Changes to General Application Information Section .............. 10
Changes to Figure 5 ........................................................................ 11
Changes to I-V Conversion Applications Section ..................... 13
Changes to Figure 13 and Figure 14 ............................................ 13
Changes to Figure 17...................................................................... 14
Date Sheet AD8510/AD8512/AD8513

SPECIFICATIONS
@ VS = ±5 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage (B Grade)1 VOS 0.08 0.4 mV
−40°C < TA < +125°C 0.8 mV
Offset Voltage (A Grade) VOS 0.1 0.9 mV
−40°C < TA < +125°C 1.8 mV
Input Bias Current IB 21 75 pA
−40°C < TA < +85°C 0.7 nA
−40°C < TA < +125°C 7.5 nA
Input Offset Current IOS 5 50 pA
−40°C < TA < +85°C 0.3 nA
−40°C < TA < +125°C 0.5 nA
Input Capacitance
Differential 12.5 pF
Common Mode 11.5 pF
Input Voltage Range −2.0 +2.5 V
Common-Mode Rejection Ratio CMRR VCM = −2.0 V to +2.5 V 86 100 dB
Large-Signal Voltage Gain AVO RL = 2 kΩ, VO = −3 V to +3 V 65 107 V/mV
Offset Voltage Drift (B Grade)1 ΔVOS/ΔT 0.9 5 µV/°C
Offset Voltage Drift (A Grade) ΔVOS/ΔT 1.7 12 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ 4.1 4.3 V
Output Voltage Low VOL RL = 10 kΩ, −40°C < TA < +125°C −4.9 −4.7 V
Output Voltage High VOH RL = 2 kΩ 3.9 4.2 V
Output Voltage Low VOL RL = 2 kΩ, −40°C < TA < +125°C −4.9 −4.5 V
Output Voltage High VOH RL = 600 Ω 3.7 4.1 V
Output Voltage Low VOL RL = 600 Ω, −40°C < TA < +125°C −4.8 −4.2 V
Output Current IOUT ±40 ±54 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 86 130 dB
Supply Current/Amplifier ISY
AD8510/AD8512/AD8513 VO = 0 V 2.0 2.3 mA
AD8510/AD8512 −40°C < TA < +125°C 2.5 mA
AD8513 −40°C < TA < +125°C 2.75 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 20 V/µs
Gain Bandwidth Product GBP 8 MHz
Settling Time tS To 0.1%, 0 V to 4 V step, G = +1 0.4 µs
Total Harmonic Distortion (THD) + Noise THD + N 1 kHz, G = +1, RL = 2 kΩ 0.0005 %
Phase Margin φM 44.5 Degrees
NOISE PERFORMANCE
Voltage Noise Density en f = 10 Hz 34 nV/√Hz
f = 100 Hz 12 nV/√Hz
f = 1 kHz 8.0 10 nV/√Hz
f = 10 kHz 7.6 nV/√Hz
Peak-to-Peak Voltage Noise en p-p 0.1 Hz to 10 Hz bandwidth 2.4 5.2 µV p-p
1
AD8510/AD8512 only.

Rev. J | Page 3 of 20
AD8510/AD8512/AD8513 Date Sheet
ELECTRICAL CHARACTERISTICS
@ VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage (B Grade)1 VOS 0.08 0.4 mV
−40°C < TA < +125°C 0.8 mV

Offset Voltage (A Grade) VOS 0.1 1.0 mV

−40°C < TA < +125°C 1.8 mV
Input Bias Current IB 25 80 pA
−40°C < TA < +85°C 0.7 nA
−40°C < TA < +125°C 10 nA
Input Offset Current IOS 6 75 pA
−40°C < TA < +85°C 0.3 nA
−40°C < TA < +125°C 0.5 nA
Input Capacitance
Differential 12.5 pF
Common Mode 11.5 pF
Input Voltage Range −13.5 +13.0 V
Common-Mode Rejection Ratio CMRR VCM = −12.5 V to +12.5 V 86 108 dB
Large-Signal Voltage Gain AVO RL = 2 kΩ, VCM = 0 V, 115 196 V/mV
VO = −13.5 V to +13.5 V
Offset Voltage Drift (B Grade)1 ΔVOS/ΔT 1.0 5 µV/°C
Offset Voltage Drift (A Grade) ΔVOS/ΔT 1.7 12 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ +14.0 +14.2 V
Output Voltage Low VOL RL = 10 kΩ, −40°C < TA < +125°C −14.9 −14.6 V
Output Voltage High VOH RL = 2 kΩ +13.8 +14.1 V
Output Voltage Low VOL RL = 2 kΩ, −40°C < TA < +125°C –14.8 −14.5 V
Output Voltage High VOH RL = 600 Ω +13.5 +13.9 V
RL = 600 Ω, −40°C < TA < +125°C +11.4 V
Output Voltage Low VOL RL = 600 Ω −14.3 −13.8 V
RL = 600 Ω, −40°C < TA < +125°C −12.1 V
Output Current IOUT ±70 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 86 dB
Supply Current/Amplifier ISY
AD8510/AD8512/AD8513 VO = 0 V 2.2 2.5 mA
AD8510/AD8512 −40°C < TA < +125°C 2.6 mA
AD8513 −40°C < TA < +125°C 3.0 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 20 V/µs
Gain Bandwidth Product GBP 8 MHz
Settling Time tS To 0.1%, 0 V to 10 V step, G = +1 0.5 µs
To 0.01%, 0 V to 10 V step, G = +1 0.9 µs
Total Harmonic Distortion (THD) + Noise THD + N 1 kHz, G = +1, RL = 2 kΩ 0.0005 %
Phase Margin φM 52 Degrees

Rev. J | Page 4 of 20
Date Sheet AD8510/AD8512/AD8513
Parameter Symbol Conditions Min Typ Max Unit
NOISE PERFORMANCE
Voltage Noise Density en f = 10 Hz 34 nV/√Hz
f = 100 Hz 12 nV/√Hz
f = 1 kHz 8.0 10 nV/√Hz
f = 10 kHz 7.6 nV/√Hz
Peak-to-Peak Voltage Noise en p-p 0.1 Hz to 10 Hz bandwidth 2.4 5.2 µV p-p
1
AD8510/AD8512 only.

Rev. J | Page 5 of 20
AD8510/AD8512/AD8513 Date Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3. Table 4. Thermal Resistance
Parameter Rating Package Type θJA1 θJC Unit
Supply Voltage ±18 V 8-Lead MSOP (RM) 210 45 °C/W
Input Voltage ±VS 8-Lead SOIC_N (R) 158 43 °C/W
Output Short-Circuit Duration to GND Observe derating curves 14-Lead SOIC_N (R) 120 36 °C/W
Storage Temperature Range −65°C to +150°C 14-Lead TSSOP (RU) 180 35 °C/W
Operating Temperature Range −40°C to +125°C 1
θJA is specified for worst-case conditions, that is, θJA is specified for device
Junction Temperature Range −65°C to +150°C soldered in circuit board for surface-mount packages.
Lead Temperature (Soldering, 10 sec) 300°C
Electrostatic Discharge 2000 V ESD CAUTION
(Human Body Model)

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. J | Page 6 of 20
Date Sheet AD8510/AD8512/AD8513

TYPICAL PERFORMANCE CHARACTERISTICS

120
100k
VSY = ±15V VSY = ±5V, ±15V
TA = 25°C
100
10k
NUMBER OF AMPLIFIERS

INPUT BIAS CURRENT (pA)

80

1k
60

100
40

20 10

02729-007

02729-010
0
–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 1
–40 –25 –10 5 20 35 50 65 80 95 110 125
INPUT OFFSET VOLTAGE (mV) TEMPERATURE (°C)
Figure 7. Input Offset Voltage Distribution Figure 10. Input Bias Current vs. Temperature

30 1000
VSY = ±15V
B GRADE
25

INPUT OFFSET CURRENT (pA)

NUMBER OF AMPLIFIERS

100
20
±15V

15 10
±5V
10

1
5
02729-008

02729-011
0 0.1
0 1 2 3 4 5 6 –40 –25 –10 5 20 35 50 65 80 95 110 125
TCVOS (µV/°C) TEMPERATURE (°C)
Figure 8. AD8510/AD8512 TCVOS Distribution Figure 11. Input Offset Current vs. Temperature

30 40
VSY = ±15V TA = 25°C
A GRADE 35
25
30
NUMBER OF AMPLIFIERS

INPUT BIAS CURRENT (pA)

20
25

15 20

15
10
10
5
5
02729-012
02729-009

0 0
0 1 2 3 4 5 6 8 13 18 23 28 30
TCVOS (µV/°C) SUPPLY VOLTAGE (V+ – V– )

Figure 9. AD8510/AD8512 TCVOS Distribution Figure 12. Input Bias Current vs. Supply Voltage

Rev. J | Page 7 of 20
AD8510/AD8512/AD8513 Date Sheet
2.0 2.8
TA = 25°C
TA = 25°C
1.9
SUPPLY CURRENT PER AMPLIFIER (mA)

2.6
1.8
2.4

SUPPLY CURRENT (mA)

1.7
2.2
1.6
2.0
1.5
1.8
1.4

1.3 1.6

1.2 1.4

02729-013

02729-016
1.1 1.2

1.0 1.0
8 13 18 23 28 30 8 13 18 23 28 33
SUPPLY VOLTAGE (V+ – V–) SUPPLY VOLTAGE (V+ – V–)

Figure 13. AD8512 Supply Current per Amplifier vs. Supply Voltage Figure 16. AD8510 Supply Current vs. Supply Voltage

16
VOL VSY = ±15V 70 315
14 VSY = ±15V
60 RL = 2.5kΩ 270
VOH
CSCOPE = 20pF
12 50 ΦM = 52° 225
OUTPUT VOLTAGE (V)

10 40 180

PHASE (Degrees)
30 135
GAIN (dB)

8
20 90
6
VOL 10 45
VSY = ±5V
4 0 0
VOH
2 –10 –45
02729-039

02729-017
–20 –90
0
0 10 20 30 40 50 60 70 80 –135
–30
LOAD CURRENT (mA) 10k 100k 1M 10M 50M
FREQUENCY (Hz)

Figure 14. Output Voltage vs. Load Current Figure 17. Open-Loop Gain and Phase vs. Frequency

2.50
2.50
SUPPLY CURRENT PER AMPLIFIER (mA)

2.25 ±15V
2.25
SUPPLY CURRENT (mA)

2.00 ±15V 2.00

±5V

1.75
1.75
±5V

1.50
1.50

1.25
1.25
02729-015

02729-018

1.00
–40 –25 –10 5 20 35 50 65 80 95 110 125 1.00
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)

Figure 15. AD8512 Supply Current per Amplifier vs. Temperature Figure 18. AD8510 Supply Current vs. Temperature

Rev. J | Page 8 of 20
Date Sheet AD8510/AD8512/AD8513
70 300
VSY = ±15V
60 VSY = ±15V, ±5V 270 VIN = 50mV

50 240
CLOSED-LOOP GAIN (dB)

OUTPUT IMPEDANCE (Ω)

40 210
AV = 100
30 180

20 150 AV = 1
AV = 10
10 120

0 90 AV = 100
AV = 1
–10 60
AV = 10

02729-022
02729-019
–20 30

–30 0
1k 10k 100k 1M 10M 50M 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 19. Closed-Loop Gain vs. Frequency Figure 22. Output Impedance vs. Frequency

120 1k
VSY = ±5V TO ±15V
VSY = ±15V

VOLTAGE NOISE DENSITY (nV/ Hz)

100

80 100
CMRR (dB)

60

40 10

20
02729-020

02729-023
0 1
100 1k 10k 100k 1M 10M 100M 1 10 100 1k 10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20. CMRR vs. Frequency Figure 23. Voltage Noise Density vs. Frequency

120
VSY = ±5V, ±15V VSY = ±15V
100

80
VOLTAGE (1µV/DIV)

–PSRR
PSRR (dB)

60

40

+PSRR
20

0
02729-024
02729-021

–20
100 1k 10k 100k 1M 10M 100M
TIME (1s/DIV)
FREQUENCY (Hz)

Figure 21. PSRR vs. Frequency Figure 24. 0.1 Hz to 10 Hz Input Voltage Noise

Rev. J | Page 9 of 20
AD8510/AD8512/AD8513 Date Sheet
280 90
VSY = ±5V TO ±15V VSY = ±15V
245 80 RL = 2kΩ
VOLTAGE NOISE DENSITY (nV Hz)

SMALL-SIGNAL OVERSHOOT (%)

70
210

60
175
50
+OS
140
40
–OS
105
30
70
20

35

02729-025

02729-028
10

0 0
0 1 2 3 4 5 6 7 8 9 10 1 10 100 1k 10k
FREQUENCY (Hz) LOAD CAPACITANCE (pF)

Figure 25. Voltage Noise Density vs. Frequency Figure 28. Small-Signal Overshoot vs. Load Capacitance

70 315
VSY = ±15V VSY = ±5V
RL = 2kΩ 60 RL = 2.5kΩ 270
CL = 100pF CSCOPE = 20pF
AV = 1 50 ΦM = 44.5° 225
OPEN-LOOP GAIN (dB)
40 180
VOLTAGE (5V/DIV)

PHASE (Degrees)
30 135

20 90

10 45

0 0

–10 –45
02729-026

02729-029
–20 –90

–30 –135
10k 100k 1M 10M 50M
TIME (1µs/DIV) FREQUENCY (Hz)

Figure 26. Large-Signal Transient Response Figure 29. Open-Loop Gain and Phase vs. Frequency

120
VSY = ±5V
VSY = ±15V
RL = 2kΩ 100
CL = 100pF
AV = 1
80
VOLTAGE (50mV/DIV)

CMRR (dB)

60

40

20
02729-030
02729-027

0
100 1k 10k 100k 1M 10M 100M
TIME (100ns/DIV) FREQUENCY (Hz)

Figure 27. Small-Signal Transient Response Figure 30. CMRR vs. Frequency

Rev. J | Page 10 of 20
Date Sheet AD8510/AD8512/AD8513
300
VSY = ±5V
270 VIN = 50mV VSY = ±5V
RL = 2kΩ
240 CL = 100pF
AV = 1
OUTPUT IMPEDANCE (Ω)

210

VOLTAGE (50mV/DIV)
180 AV = 1

150

120
AV = 100
90

60
AV = 10

02729-031
30

02729-034
0
100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) TIME (100ns/DIV)

Figure 31. Output Impedance vs. Frequency Figure 34. Small-Signal Transient Response

100
VSY = ±5V VSY = ±5V
90 RL = 2kΩ

SMALL-SIGNAL OVERSHOOT (%)

80

70
VOLTAGE (1µV/DIV)

60
+OS
50
–OS
40

30

20
02729-032

02729-035
10

0
TIME (1s/DIV) 1 10 100 1k 10k
LOAD CAPACITANCE (pF)

Figure 32. 0.1 Hz to 10 Hz Input Voltage Noise Figure 35. Small-Signal Overshoot vs. Load Capacitance

100
VS = ±15V
VSY = ±5V 90
RL = 2kΩ
80
CL = 100pF
NUMBER OF AMPLIFIERS

AV = 1
70

60
VOLTAGE (2V/DIV)

50

40

30

20
02729-036

10
02729-033

0
0 1 2 3 4 5 6
TIME (1µs/DIV) TCVOS (µV/°C)

Figure 33. Large-Signal Transient Response Figure 36. AD8513 TCVOS Distribution

Rev. J | Page 11 of 20
AD8510/AD8512/AD8513 Date Sheet
120 3.0
VS = ±5V

SUPPLY CURRENT PER AMPLIFIER (mA)

100 2.5
±15V
NUMBER OF AMPLIFIERS

80 2.0
±5V

60 1.5

40 1.0

20 0.5

02729-040
02729-037
0 0
0 1 2 3 4 5 6 –40 –25 –10 5 20 35 50 65 80 95 110 125
TCVOS (µV/°C) TEMPERATURE (°C)
Figure 37. AD8513 TCVOS Distribution Figure 39. AD8513 Supply Current per Amplifier vs. Temperature

2.5
TA = 25°C
2.4
SUPPLY CURRENT PER AMPLIFIER (mA)

2.3

2.2

2.1

2.0

1.9

1.8

1.7
02729-038

1.6

1.5
8 13 18 23 28 33
SUPPLY VOLTAGE (V+ – V–)
Figure 38. AD8513 Supply Current per Amplifier vs. Supply Voltage

Rev. J | Page 12 of 20
Date Sheet AD8510/AD8512/AD8513

GENERAL APPLICATION INFORMATION

INPUT OVERVOLTAGE PROTECTION 0.01
VSY = ±5V
The AD8510/AD8512/AD8513 have internal protective RL = 100kΩ
BW = 22kHz
circuitry that allows voltages as high as 0.7 V beyond the
supplies to be applied at the input of either terminal without

DISTORTION (%)
causing damage. For higher input voltages, a series resistor is
necessary to limit the input current. The resistor value can be
0.001
determined from the formula
VIN  VS
 5 mA
RS
With a very low offset current of <0.5 nA up to 125°C, higher

02729-056
resistor values can be used in series with the inputs. A 5 kΩ 0.0001
resistor protects the inputs from voltages as high as 25 V 20 100 1k 10k 20k
FREQUENCY (Hz)
beyond the supplies and adds less than 10 μV to the offset. Figure 41. THD + N vs. Frequency
OUTPUT PHASE REVERSAL TOTAL NOISE INCLUDING SOURCE RESISTORS
Phase reversal is a change of polarity in the transfer function of
The low input current noise and input bias current of the
the amplifier. This can occur when the voltage applied at the
AD8510/AD8512/AD8513 make them the ideal amplifiers for
input of an amplifier exceeds the maximum common-mode
circuits with substantial input source resistance. Input offset
voltage.
voltage increases by less than 15 nV per 500 Ω of source
Phase reversal can cause permanent damage to the device and resistance at room temperature. The total noise density of the
can result in system lockups. The AD8510/AD8512/AD8513 do circuit is
not exhibit phase reversal when input voltages are beyond the
supplies. e nTOTAL  e n 2  i n R S 2  4kTR S

where:
VSY = ±5V
AV = 1 en is the input voltage noise density of the parts.
RL = 10kΩ
in is the input current noise density of the parts.
RS is the source resistance at the noninverting terminal.
VOUT
VOLTAGE (2V/DIV)

k is Boltzmann’s constant (1.38 × 10–23 J/K).

T is the ambient temperature in Kelvin (T = 273 + °C).
For RS < 3.9 kΩ, en dominates and enTOTAL ≈ en. The current noise
VIN
of the AD8510/AD8512/AD8513 is so low that its total density
does not become a significant term unless RS is greater than
165 MΩ, an impractical value for most applications.
02729-057

The total equivalent rms noise over a specific bandwidth is

expressed as
TIME (20µs/DIV)
enTOTAL  enTOTAL BW
Figure 40. No Phase Reversal

TOTAL HARMONIC DISTORTION (THD) + NOISE where BW is the bandwidth in hertz.

The AD8510/AD8512/AD8513 have low THD and excellent gain Note that the previous analysis is valid for frequencies larger
linearity, making these amplifiers great choices for precision than 150 Hz and assumes flat noise above 10 kHz. For lower
circuits with high closed-loop gain and for audio application frequencies, flicker noise (1/f) must be considered.
circuits. Figure 41 shows that the AD8510/AD8512/AD8513 have
approximately 0.0005% of total distortion when configured in
positive unity gain (the worst case) and driving a 100 kΩ load.

Rev. J | Page 13 of 20
AD8510/AD8512/AD8513 Date Sheet
SETTLING TIME VSY = ±15V
AV = –100
Settling time is the time it takes the output of the amplifier to RL = 10kΩ
+15V

OUTPUT
reach and remain within a percentage of its final value after a
pulse is applied at the input. The AD8510/AD8512/AD8513
0V
settle to within 0.01% in less than 900 ns with a step of 0 V to

VOLTAGE
10 V in unity gain. This makes each of these parts an excellent
choice as a buffer at the output of DACs whose settling time is
typically less than 1 μs. 0V

INPUT
In addition to the fast settling time and fast slew rate, low offset –200mV

voltage drift and input offset current maintain the full accuracy

02729-054
of 12-bit converters over the entire operating temperature range.
OVERLOAD RECOVERY TIME TIME (2µs/DIV)

Overload recovery, also known as overdrive recovery, is the
time it takes the output of an amplifier to recover to its linear
region from a saturated condition. This recovery time is par-
ticularly important in applications where the amplifier must
amplify small signals in the presence of large transient voltages.
Figure 42 shows the positive overload recovery of the AD8510/
AD8512/AD8513. The output recovers in approximately 200 ns
from a saturated condition.
VSY = ±15V
VIN = 200mV
0V AV = –100
OUTPUT
Figure 43. Negative Overload Recovery
CAPACITIVE LOAD DRIVE
The AD8510/AD8512/AD8513 are unconditionally stable at all
gains in inverting and noninverting configurations. Each device
is capable of driving a capacitive load of up to 1000 pF without
oscillation in unity gain using the worst-case configuration.
However, as with most amplifiers, driving larger capacitive
loads in a unity gain configuration may cause excessive
overshoot and ringing, or even oscillation. A simple snubber
network significantly reduces the amount of overshoot and
ringing. The advantage of this configuration is that the output

RL = 10kΩ
swing of the amplifier is not reduced, because RS is outside the
–15V feedback loop.
VOLTAGE

V+
200mV
INPUT

0V
2 7
AD8510 6 VOUT
02729-053

4
200mV 3 RS

TIME (2µs/DIV)

02729-055
CS CL
Figure 42. Positive Overload Recovery V–

The negative overdrive recovery time shown in Figure 43 is less Figure 44. Snubber Network Configuration
than 200 ns.
In addition to the fast recovery time, the AD8510/AD8512/
AD8513 show excellent symmetry of the positive and negative
recovery times. This is an important feature for transient signal
rectification because the output signal is kept equally undistorted
throughout any given period.

Rev. J | Page 14 of 20
Date Sheet AD8510/AD8512/AD8513
Figure 45 shows a scope plot of the output of the AD8510/AD8512/ OPEN-LOOP GAIN AND PHASE RESPONSE
AD8513 in response to a 400 mV pulse. The circuit is configured in In addition to their impressive low noise, low offset voltage, and
positive unity gain (worst case) with a load experience of 500 pF. offset current, the AD8510/AD8512/AD8513 have excellent
loop gain and phase response even when driving large resistive
VSY = ±15V
CL = 500pF and capacitive loads.
RL =10kΩ
Compared with Competitor A (see Figure 48) under the same
VOLTAGE (200mV/DIV)

conditions, with a 2.5 kΩ load at the output, the AD8510/AD8512/

AD8513 have more than 8 MHz of bandwidth and a phase margin
of more than 52°.
Competitor A, on the other hand, has only 4.5 MHz of band-
width and 28° of phase margin under the same test conditions.
Even with a 1 nF capacitive load in parallel with the 2 kΩ load
at the output, the AD8510/AD8512/AD8513 show much better

02729-041
response than Competitor A, whose phase margin is degraded
to less than 0, indicating oscillation.
TIME (1µs/DIV)

Figure 45. Capacitive Load Drive Without Snubber 70 315

VSY = ±15V
60 RL = 2.5kΩ 270
When the snubber circuit is used, the overshoot is reduced from CL = 0pF
55% to less than 3% with the same load capacitance. Ringing is 50 225

virtually eliminated, as shown in Figure 46. 40 180

PHASE (Degrees)
30 135
VSY = ±15V GAIN (dB)
RL = 10kΩ 20 90
CL = 500pF
RS = 100Ω 10 45
CS = 1nF
VOLTAGE (200mV/DIV)

0 0

–10 –45

–20 –90

02729-043
–30 –135
10k 100k 1M 10M 50M
FREQUENCY (Hz)

Figure 47. Frequency Response of the AD8510/AD8512/AD8513

02729-042

70 315
VSY = ±15V
TIME (1µs/DIV)
60 RL = 2.5kΩ 270
Figure 46. Capacitive Load with Snubber Network CL = 0pF
50 225
Optimum values for RS and CS depend on the load capacitance 40 180
and input stray capacitance and are determined empirically.

PHASE (Degrees)
30 135
GAIN (dB)

Table 5 shows a few values that can be used as starting points.

20 90

Table 5. Optimum Values for Capacitive Loads 10 45

CLOAD RS (Ω) CS 0 0
500 pF 100 1 nF –10 –45
2 nF 70 100 pF
02729-044

–20 –90
5 nF 60 300 pF
–30 –135
10k 100k 1M 10M 50M
FREQUENCY (Hz)

Figure 48. Frequency Response of Competitor A

Rev. J | Page 15 of 20
AD8510/AD8512/AD8513 Date Sheet
PRECISION RECTIFIERS
Rectifying circuits are used in a multitude of applications. One
of the most popular uses is in the design of regulated power
supplies, where a rectifier circuit is used to convert an input

VOLTAGE (1V/DIV)
sinusoid to a unipolar output voltage.
However, there are some potential problems with amplifiers
used in this manner. When the input voltage (VIN) is negative,
the output is zero, and the magnitude of VIN is doubled at the
inputs of the op amp. If this voltage exceeds the power supply
voltage, it may permanently damage some amplifiers. In addition,

02729-046
the op amp must come out of saturation when VIN is negative.
This delays the output signal because the amplifier requires
TIME (1ms/DIV)
time to enter its linear region. Figure 50. Half-Wave Rectifier Signal (OUT A in Figure 49)
Although the AD8510/AD8512/AD8513 have a very fast
overdrive recovery time, which makes them great choices for the
rectification of transient signals, the symmetry of the positive
and negative recovery times is also important to keep the output
signal undistorted.

VOLTAGE (1V/DIV)
Figure 49 shows the test circuit of the rectifier. The first stage of
the circuit is a half-wave rectifier. When the sine wave applied at
the input is positive, the output follows the input response.
During the negative cycle of the input, the output tries to swing
negative to follow the input, but the power supply restrains it to
zero. In a similar fashion, the second stage is a follower during

02729-047
the positive cycle of the sine wave and an inverter during the
negative cycle. TIME (1ms/DIV)
R2 R3 Figure 51. Full-Wave Rectifier Signal (OUT B in Figure 49)
10kΩ 10kΩ

10V

VIN 6
2/2 4
3V p-p
3
1/2 8 AD8512 7
R1 8
OUT B
1kΩ AD8512 1 5
(FULL WAVE)
2 4

10V
02729-045

OUT A
(HALF WAVE)

Figure 49. Half-Wave and Full-Wave Rectifiers

Rev. J | Page 16 of 20
Date Sheet AD8510/AD8512/AD8513
I-V CONVERSION APPLICATIONS A typical value for Rd is 1000 MΩ. Because Rd >> R2, the
Photodiode Circuits circuit behavior is not impacted by the effect of the junction
resistance. The maximum signal bandwidth is
Common applications for I-V conversion include photodiode
circuits where the amplifier is used to convert a current emitted ft
f MAX =
by a diode placed at the positive input terminal into an output 2πR2Ct
voltage.
where ft is the unity gain frequency of the amplifier.
The AD8510/AD8512/AD8513’s low input bias current, wide
Cf can be calculated by
bandwidth, and low noise make them each an excellent choice
for various photodiode applications, including fax machines, Ct
Cf =
fiber optic controls, motion sensors, and bar code readers. 2πR2 ft
The circuit shown in Figure 52 uses a silicon diode with zero where ft is the unity gain frequency of the op amp, and it achieves
bias voltage. This is known as a photovoltaic mode; this a phase margin, φM, of approximately 45°.
configuration limits the overall noise and is suitable for
instrumentation applications. A higher phase margin can be obtained by increasing the value
Cf
of Cf. Setting Cf to twice the previous value yields approximately
φM = 65° and a maximal flat frequency response, but it reduces the
R2 maximum signal bandwidth by 50%.
Using the previous parameters with a Cf ≈ 1 pF, the signal
VEE
bandwidth is approximately 2.6 MHz.
Signal Transmission Applications
4
2
One popular signal transmission method uses pulse-width
AD8510 6

3
modulation. High data rates may require a fast comparator
Rd Ct 7
rather than an op amp. However, the need for sharp, undistorted
signals may favor using a linear amplifier.
02729-048

VCC
The AD8510/AD8512/AD8513 make excellent voltage
Figure 52. Equivalent Preamplifier Photodiode Circuit comparators. In addition to a high slew rate, the AD8510/
A larger signal bandwidth can be attained at the expense of AD8512/AD8513 have a very fast saturation recovery time. In
additional output noise. The total input capacitance (Ct) the absence of feedback, the amplifiers are in open-loop mode
consists of the sum of the diode capacitance (typically 3 pF to (very high gain). In this mode of operation, they spend much of
4 pF) and the amplifier’s input capacitance (12 pF), which their time in saturation.
includes external parasitic capacitance. Ct creates a pole in the The circuit shown in Figure 53 was used to compare two signals
frequency response that can lead to an unstable system. To of different frequencies, namely a 100 Hz sine wave and a 1 kHz
ensure stability and optimize the bandwidth of the signal, a triangular wave. Figure 54 shows a scope plot of the resulting
capacitor is placed in the feedback loop of the circuit shown in output waveforms. A pull-up resistor (typically 5 kΩ) can be
Figure 52. It creates a zero and yields a bandwidth whose corner connected from the output to VCC if the output voltage needs to
frequency is 1/(2π(R2Cf)). reach the positive rail. The trade-off is that power consumption
The value of R2 can be determined by the ratio is higher.
+15V
V/ID
where: 3 7
V is the desired output voltage of the op amp. 6
VOUT
ID is the diode current. 2
4
V1
For example, if ID is 100 µA and a 10 V output voltage is desired,
R2 may be 100 kΩ. Rd (see Figure 52) is a junction resistance –15V
02729-049

that drops typically by a factor of 2 for every 10°C increase in V2

temperature. Figure 53. Pulse-Width Modulator

Rev. J | Page 17 of 20
AD8510/AD8512/AD8513 Date Sheet
The AD8510 single has two additional active terminals that are
not present on the AD8512 dual or AD8513 quad parts. These
pins are labeled “null” and are used for fine adjustment of the
input offset voltage. Although the guaranteed maximum offset
VOLTAGE (5V/DIV)

voltage at room temperature is 400 μV and over the −40°C to

+125°C range is 800 mV maximum, this offset voltage can be
reduced by adding a potentiometer to the null pins as shown in
Figure 57. With the 20 kΩ potentiometer shown, the adjustment
range is approximately ±3.5 mV. The potentiometer parallels
low value resistors in the drain circuit of the JFET differential
input pair and allows unbalancing of the drain currents to

02729-050
change the offset voltage. If offset adjustment is not required,
TIME (2ms/DIV)
these pins must be left unconnected.
Caution must be used when adding adjusting potentiometers to
Figure 54. Pulse-Width Modulation
any op amp with this capability for several reasons. First, there is
Crosstalk gain from these nodes to the output; therefore, capacitive coupling
Crosstalk, also known as channel separation, is a measure of from noisy traces to these nodes will inject noise into the signal
signal feedthrough from one channel to another on the same path. Second, the temperature coefficient of the potentiometer
IC. The AD8512/AD8513 have a channel separation of better will not match the temperature coefficient of the internal resistors,
than −90 dB for frequencies up to 10 kHz and of better than so the offset voltage drift with temperature will be slightly affected.
−50 dB for frequencies up to 10 MHz. Figure 56 shows the Third, this provision is for adjusting the offset voltage of the
typical channel separation behavior between Amplifier A op amp, not for adjusting the offset of the overall system. Although
(driving amplifier) and each of the following: Amplifier B, it is tempting to decrease the value of the potentiometer to attain
Amplifier C, and Amplifier D. more range, this will adversely affect the dc and ac parameters.
Instead, increase the potentiometer to 50 kΩ to decrease the
VOUT
range if needed.
20kΩ 2.2kΩ
20kΩ
+VS V+
1
2 8 6
18V p-p 1 7 5
– 2
3 5 7
INPUT AD8510 6 OUTPUT
5kΩ 5kΩ 4
VIN + 3
VOUT –VS 4
02729-052

CROSSTALK = 20 log VOS TRIM RANGE IS

10V IN TYPICALLY ±3.5mV

02729-058
Figure 55. Crosstalk Test Circuit V–
Figure 57. Optional Offset Nulling Circuit
0

–20
CHANNEL SEPARATION (dB)

–40

–60 CH B

CH D CH C
–80

–100

–120

–140
02729-051

–160
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)

Figure 56. Channel Separation

Rev. J | Page 18 of 20
Date Sheet AD8510/AD8512/AD8513

OUTLINE DIMENSIONS
5.10
5.00 (0.1968) 5.00
4.80 (0.1890)
4.90

8 5
4.00 (0.1574) 6.20 (0.2441) 14 8
3.80 (0.1497) 1 5.80 (0.2284)
4 4.50
4.40 6.40
BSC
4.30
1.27 (0.0500) 0.50 (0.0196)
BSC 45°
1.75 (0.0688) 0.25 (0.0099) 1 7
0.25 (0.0098) 1.35 (0.0532)
8°
0.10 (0.0040) PIN 1
0°
COPLANARITY 0.51 (0.0201) 1.05 0.65
0.10 1.27 (0.0500) 1.00 BSC
0.31 (0.0122) 0.25 (0.0098) 0.20
SEATING 0.40 (0.0157) 1.20
PLANE 0.17 (0.0067) 0.80 0.75
MAX 0.09
8° 0.60
0.15 0.30
COMPLIANT TO JEDEC STANDARDS MS-012-A A 0° 0.45
0.05 SEATING
0.19 PLANE COPLANARITY
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

012407-A
0.10
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 58. 8-Lead Standard Small Outline Package [SOIC_N] Figure 60. 14-Lead Thin Shrink Small Outline Package [TSSOP]
Narrow Body (R-8) (RU-14)
Dimensions shown in millimeters and (inches) Dimensions shown in millimeters

3.20
3.00
2.80

8.75 (0.3445)
8 5 5.15
3.20 8.55 (0.3366)
4.90
3.00 4.65
1 14 8
2.80 4 4.00 (0.1575) 6.20 (0.2441)
1
3.80 (0.1496) 7 5.80 (0.2283)
PIN 1
IDENTIFIER
1.27 (0.0500) 0.50 (0.0197)
0.65 BSC BSC 45°
1.75 (0.0689) 0.25 (0.0098)
0.25 (0.0098) 8°
0.95 15° MAX 1.35 (0.0531)
0.10 (0.0039) 0°
0.85 1.10 MAX
0.75 COPLANARITY SEATING
0.10 0.51 (0.0201) 0.25 (0.0098) 1.27 (0.0500)
PLANE
0.80 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157)
0.15 6° 0.23
0.40 0.55
0.05 0° 0.09 0.40
COPLANARITY 0.25
10-07-2009-B

COMPLIANT TO JEDEC STANDARDS MS-012-AB

0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

060606-A
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
COMPLIANT TO JEDEC STANDARDS MO-187-AA REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 59. 8-Lead Mini Small Outline Package [MSOP] Figure 61. 14-Lead Standard Small Outline Package [SOIC_N]
(RM-8) Narrow Body (R-14)
Dimensions shown in millimeters Dimensions shown in millimeters and (inches)

Rev. J | Page 19 of 20
AD8510/AD8512/AD8513 Date Sheet
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8510ARMZ-REEL1 −40°C to +125°C 8-Lead MSOP RM-8 B7A#
AD8510ARMZ1 −40°C to +125°C 8-Lead MSOP RM-8 B7A#
AD8510ARZ1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8510ARZ-REEL1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8510ARZ-REEL71 −40°C to +125°C 8-Lead SOIC_N R-8
AD8510BRZ1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8510BRZ-REEL1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8510BRZ-REEL71 −40°C to +125°C 8-Lead SOIC_N R-8
AD8512ARMZ-REEL1 −40°C to +125°C 8-Lead MSOP RM-8 B8A#
AD8512ARMZ1 −40°C to +125°C 8-Lead MSOP RM-8 B8A#
AD8512ARZ1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8512ARZ-REEL1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8512ARZ-REEL71 −40°C to +125°C 8-Lead SOIC_N R-8
AD8512BRZ1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8512BRZ-REEL1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8512BRZ-REEL71 −40°C to +125°C 8-Lead SOIC_N R-8
AD8513ARZ1 −40°C to +125°C 14-Lead SOIC_N R-14
AD8513ARZ-REEL1 −40°C to +125°C 14-Lead SOIC_N R-14
AD8513ARZ-REEL71 −40°C to +125°C 14-Lead SOIC_N R-14
AD8513ARUZ1 −40°C to +125°C 14-Lead TSSOP RU-14
AD8513ARUZ-REEL1 −40°C to +125°C 14-Lead TSSOP RU-14
1
Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.

©2002–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D02729-0-6/17(J)

Rev. J | Page 20 of 20