ASSIGNMENT 2

EMBEDDED SYSTEMS

Hem Chaitanya Reddy(T19175)

1.Write a VHDL program to model a two input AND gate and a two input XOR gate using dataflow
style of modeling. Save the program files in your working library.

Two input AND gate dataflow code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity and1 is

port(a,b : in std_logic;

o: out std_logic);

end and1 ;

architecture df of and1 is

begin

o <= a and b;

end df;

Test bench

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity tb is

end tb;
architecture dx of tb is

signal r_a : std_logic;

signal r_b : std_logic;

signal r_o : std_logic;

begin

uut : entity work.and1

port map(a =>r_a,

b => r_b,

o =>r_o);

process is

begin

r_a <= '0';

r_b <= '0';

wait for 10ns;

r_a <= '1';

r_b <= '0';

wait for 10ns;

r_a <= '1';

r_b <= '1';

wait for 10ns;

r_a <= '1';

r_a <= '1';

wait for 10ns

end process;

end dx;
Two input xor gate:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity xor1 is

port(a,b : in std_logic;

o: out std_logic);

end and1 ;

architecture df of xor1 is

begin

o <= a xor b;

end df;

Test bench

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity tb is

end tb;

architecture dx of tb is

signal r_a : std_logic;

signal r_b : std_logic;

signal r_o : std_logic;

begin

uut : entity work.and1

port map(a =>r_a,

b => r_b,

o =>r_o);

process is

begin

r_a <= '0';

r_b <= '0';

wait for 10ns;

r_a <= '1';

r_b <= '0';

wait for 10ns;

r_a <= '1';

r_b <= '1';

wait for 10ns;

r_a <= '1';

r_a <= '1';

wait for 10ns

end process;

end dx;

2.Use the models of the AND gate and XOR gate created in problem 1 to
develop the structural model of a half adder.
Half adder: code

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ha is

port(a,b : in std_logic;

s,c : out std_logic);

end ha;

architecture df of ha is

component and1

port( a1,b1 : in std_logic;

o1 : out std_logic);

end component;

component xor1

port(ax,bx:in std_logic;

ox:out std_logic);

end component;

begin

c1:and1 port map(a1 =>a,b1=>b,o1=>c);

c2:xor1 port map (ax=>a,bx=>b,ox=>s);

end df;

and1:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;
entity and1 is

port(a1,b 1: in std_logic;

o1: out std_logic);

end and1 ;

architecture df of and1 is

begin

o <= a and b;

end df;

xor1:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity xor1 is

port(ax,b x: in std_logic;

ox: out std_logic);

end xor1 ;

architecture df of xor1 is

begin

o <= a xor b;

end df;

3. Write a VHDL program to model a half adder using dataflow style of

modeling.
Data flow model:

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity half_adder is

port(a,b : in std_logic;

s,c: out std_logic);

end half_adder;

architecture df of half_adder is

begin

s <= a and b;

c <= a xor b;

end df;

4. Write a VHDL program to model a half adder using behavioral style of

modeling.
Behaviriol modelling:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity half_adder is

port(a,b : in std_logic;

s,c: out std_logic);

end half_adder;

architecture df of half_adder is

begin
uux :process(a,b)

begin

if a='1' then

if b='1' then

s <= '1';

c <= '1';

else

s <= '1';

c <= '0';

end if;

else

if b = '1' then

s <= '1';

c <= '0';

else

s <= '0';

c <= '0';

end if;

end if;

end process;

end df;

5.Use the model of the half adder developed in problem 2 to develop the
model of a single bit full adder.
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is
Port (af,bf,ci : in std_logic;

sf,cf: out std_logic );

end full_adder;

architecture st of full_adder is

signal ct:std_logic;

signal st:std_logic;

signal ct2:std_logic;

component ha

port(a,b:in std_logic;

s,c:out std_logic);

end component;

component or1

port(ar,br:in std_logic;

o3:out std_logic);

end component;

begin

c1:ha port map(a =>af,b =>bf,s=>st,c=>ct);

c2:ha port map(a =>st,b =>ci,s=>sf,c=>ct2);

c3:or1 port map(ar=>ct,br=>ct2,o3=>cf);

end st;

Half adder: code

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;
entity ha is

port(a,b : in std_logic;

s,c : out std_logic);

end ha;

architecture df of ha is

component and1

port( a1,b1 : in std_logic;

o1 : out std_logic);

end component;

component xor1

port(ax,bx:in std_logic;

ox:out std_logic);

end component;

begin

c1:and1 port map(a1 =>a,b1=>b,o1=>c);

c2:xor1 port map (ax=>a,bx=>b,ox=>s);

end df;

and1:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity and1 is

port(a1,b 1: in std_logic;

o1: out std_logic);

end and1 ;

architecture df of and1 is

begin

o <= a and b;

end df;

xor1:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity xor1 is

port(ax,b x: in std_logic;

ox: out std_logic);

end xor1 ;

architecture df of xor1 is

begin

o <= ax xor bx;

end df;

or1:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity xor1 is

port(ar,b r: in std_logic;

o3: out std_logic);

end xor1 ;

architecture df of xor1 is

begin

o 3<= ar or br;

end df;

6. Use the model of the single bit full adder developed in problem 5 to develop
the model of a four bit ripple carry adder.
Ripple carry adder code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ripple_adder is

Port (az,bz:in std_logic_vector(3 downto 0);

oz: out std_logic_vector(4 downto 0) );

end ripple_adder;

architecture rip of ripple_adder is

component full_adder is

Port (af,bf,ci : in std_logic;

sf,cf: out std_logic );

end component;

signal cw:std_logic_vector(3 downto 0);

begin

cp:full_adder port map(af => az(0),bf=>bz(0),ci=>'0',sf=>oz(0),cf=>cw(0));

cp1:full_adder port map(af => az(1),bf=>bz(1),ci=>cw(0),sf=>oz(1),cf=>cw(1));

cp2:full_adder port map(af => az(2),bf=>bz(2),ci=>cw(1),sf=>oz(2),cf=>cw(2));

cp3:full_adder port map(af => az(3),bf=>bz(3),ci=>cw(2),sf=>oz(3),cf=>oz(4));

end rip;

Full adder:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is

Port (af,bf,ci : in std_logic;

sf,cf: out std_logic );

end full_adder;

architecture st of full_adder is

signal ct:std_logic;

signal st:std_logic;

signal ct2:std_logic;

component ha

port(a,b:in std_logic;

s,c:out std_logic);

end component;

component or1

port(ar,br:in std_logic;

o3:out std_logic);

end component;

begin

c1:ha port map(a =>af,b =>bf,s=>st,c=>ct);

c2:ha port map(a =>st,b =>ci,s=>sf,c=>ct2);

c3:or1 port map(ar=>ct,br=>ct2,o3=>cf);

end st;

Half adder: code

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity ha is

port(a,b : in std_logic;

s,c : out std_logic);

end ha;

architecture df of ha is

component and1

port( a1,b1 : in std_logic;

o1 : out std_logic);

end component;

component xor1

port(ax,bx:in std_logic;

ox:out std_logic);

end component;

begin

c1:and1 port map(a1 =>a,b1=>b,o1=>c);

c2:xor1 port map (ax=>a,bx=>b,ox=>s);

end df;

and1:
library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity and1 is

port(a1,b 1: in std_logic;

o1: out std_logic);

end and1 ;

architecture df of and1 is

begin

o <= a and b;

end df;

xor1:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity xor1 is

port(ax,b x: in std_logic;

ox: out std_logic);

end xor1 ;

architecture df of xor1 is

begin

o <= ax xor bx;

end df;

or1:
library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity xor1 is

port(ar,b r: in std_logic;

o3: out std_logic);

end xor1 ;

architecture df of xor1 is

begin

o 3<= ar or br;

end df;

7.Model a 3x8 decoder using dataflow style of modelling

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder is
Port ( s : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end decoder;

architecture Behavioral of decoder is

begin
with sel select
y<="00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111",
"00000000" when others;
end Behavioral
8.Design the mac
library ieee;

use ieee.std_logic_1164.all, ieee.fixed_pkg.all;

entity mac is

port ( clk, reset : in std_ulogic;

x_real : in u_sfixed(0 downto -15);

x_imag : in u_sfixed(0 downto -15);

y_real : in u_sfixed(0 downto -15);

y_imag : in u_sfixed(0 downto -15); s_real : out u_sfixed(0 downto 15);

s_imag : out u_sfixed(0 downto -15); ovf : out std_ulogic );

end entity mac;

architecture behavioral of mac is

signal x_complex, y_complex, s_complex : complex;
begin
x_complex <= ( to_real(x_real), to_real(x_imag) );
y_complex <= ( to_real(y_real), to_real(y_imag) );

behavior : process (clk) is

variable input_x, input_y : complex := (0.0, 0.0);
variable real_part_product_1, real_part_product_2,
imag_part_product_1, imag_part_product_2 := 0.0;

variable product, sum : complex := (0.0, 0.0);

variable real_accumulator_ovf,
imag_accumulator_ovf : boolean := false;
begin
if rising_edge(clk) then
if reset then
sum := (0.0, 0.0);
real_accumulator_ovf := false;
imag_accumulator_ovf := false;
else
sum := product + sum;
real_accumulator_ovf := real_accumulator_ovf
or sum.re < -16.0
or sum.re >= +16.0;
imag_accumulator_ovf := imag_accumulator_ovf
or sum.im < -16.0
or sum.im >= +16.0;
end if;
s_complex <= sum;
ovf <= '1' when real_accumulator_ovf or imag_accumulator_ovf
or sum.re < -1.0 or sum.re >= +1.0
or sum.im < -1.0 or sum.im >= +1.0 ) else '0';
-- Update product registers.
product.re := real_part_product_1 - real_part_product_2;
product.im := imag_part_product_1 + imag_part_product_2;
-- Update partial product registers
-- (actually with the full product).
real_part_product_1 := input_x.re * input_y.re;
real_part_product_2 := input_x.im * input_y.im;
imag_part_product_1 := input_x.re * input_y.im;
imag_part_product_2 := input_x.im * input_y.re;
-- Update input registers using MAC inputs
input_x := x_complex;
input_y := y_complex;
end if;
end process behavior;
s_real <= to_sfixed(s_complex.re, s_real);
s_imag <= to_sfixed(s_complex.im, s_imag);
end architecture behavioral;

9. Consider the same problem in problem no. 8. Devise a sequence of inputs values for the
MAC that can cause the sum in the accumulator to overflow.

entity mac_test is
end entity mac_test;
architecture bench_behavioral of mac_test is

signal clk, reset, ovf : std_ulogic := '0';

signal x_real, x_imag, y_real, y_imag, s_real, s_imag : u_sfixed(0 downto -15);

signal x, y, s : complex := (0.0, 0.0);

constant Tpw_clk : time := 50 ns;

begin x_real <= x.re;

x_imag <= x.im;

y_real <= y.re;

y_imag <= y.im;

dut : entity work.mac(behavioral)

port map ( clk, reset, x_real, x_imag, y_real, y_imag, s_real, s_imag, ovf );
 s <= (s_real, s_imag);

clock_gen : process is

begin

clk <= '1'

after Tpw_clk, '0'

after 2 * Tpw_clk;

wait for 2 * Tpw_clk;

end process clock_gen;

stimulus : process is begin

-- first sequence

reset <= '1'; wait until not clk;

x <= (+0.5, +0.5);

y <= (+0.5, +0.5);

reset <= '1';

wait until not clk;

x <= (+0.2, +0.2);

y <= (+0.2, +0.2);

reset <= '1';

wait until not clk;

x <= (+0.1, -0.1);

y <= (+0.1, +0.1);

reset <= '1';

wait until not clk;

x <= (+0.1, -0.1);

y <= (+0.1, +0.1);

reset <= '0';

 wait until not clk; -- should be (0.04, 0.58) when it falls out the other end
reset <= '0';

wait until not clk;

x <= (+0.5, +0.5);

y <= (+0.5, +0.5);

reset <= '0';

wait until not clk;

x <= (+0.5, +0.5);

y <= (+0.1, +0.1);

reset <= '0';

wait until not clk;

x <= (+0.5, +0.5);

y <= (+0.5, +0.5);

reset <= '1';

wait until not clk;

x <= (-0.5, +0.5);

y <= (-0.5, +0.5);

reset <= '0';

wait until not clk;

reset <= '0';

wait until not clk;

reset <= '0'; wait until not clk;

reset <= '0'; wait until not clk;

reset <= '1'; wait until not clk;

wait;

end process stimulus;

end architecture bench_behavioral