5 4 3 2 1

3.3V
SILKSCREEN : ORION ADD2-N DUAL PAD x16 CARD
R1 SiI-SC-0066-B1-TMP PCB Rev 1.45
2.5VSDA 316,1% SiI-GE-0046-B1 12V
LM317EMP/SOT-223

12V Note : -TMP is added to Schematic # on PCB to signify Turnkey Mass Production. U1
C1 Also Silkscreen for PCB Revision may change based on Gerber version used. 3 PVCC
R2 C2 3.3V VIN
1K,1%
1uF
3.3V PVCC POWER SUPPLY OUTPUT 2

0.1uF 4
VOUT

ADJ
D C3 D
10uF
3.3V CON1 R3
240,1% C4

1
B1 12V NC(A1) A1
R4 B2 A2 10uF
2.5VSCL 316,1% 12V 12V
B3 RSVD 12V A3
B4 GND GND A4
B5 NC(B5) NC(A5) A5
C5 B6 A6 R6
R5 C6 NC(B6) TDI 412,1%
1K,1% B7 GND TDO A7
1uF B8 A8
0.1uF 3.3V NC(A8)
B9 NC(B9) 3.3V A9
R7 R8 B10 A10
NC(B10) 3.3V
B11 NC(B11) RESET# A11 RESET# 2,3
5.6K 5.6K
KEY KEY
B12 RSVD(B12) GND A12
B13 GND NC(A13) A13
B14 A14 12V
2,3 SDVOB_R+ SDVOB_RED+ NC(A14) U2
2,3 SDVOB_R- B15 SDVOB_RED- GND A15
B16 A16 5.0V
GND SDVO_TVCLKin+
2,3 SDVO_SCL B17 SDVO_CtrlCLK SDVO_TVCLKin- A17 5V POWER SUPPLY 1 VIN NC 8
C B18 GND GND A18 2 VOUT VOUT 7 C
3 VOUT VOUT 6
4 ADJ NC 5
B19 A19 C7
2,3 SDVOB_G+ SDVOB_GREEN+ RSVD(A19) 10uF R9
2,3 SDVOB_G- B20 SDVOB_GREEN- GND A20
B21 A21 LM317L/SOIC 8 240,1% C8
GND SDVOB_INT+ SDVOB_INT+ 2
B22 GND SDVOB_INT- A22 SDVOB_INT- 2
B23 A23 10uF
2,3 SDVOB_B+ SDVOB_BLUE+ GND
2,3 SDVOB_B- B24 SDVOB_BLUE- GND A24
B25 GND SDVO_STALL+ A25
B26 GND SDVO_STALL- A26
B27 A27 R10
2,3 SDVOB_C+ SDVOB_CLK+ GND 732,1%
2,3 SDVOB_C- B28 SDVOB_CLK- GND A28
B29 GND NC(A29) A29
B30 RSVD(B30) NC(A30) A30
2,3 SDVO_SDA B31 SDVO_CtrlDATA GND A31
B32 GND RSVD(A32) A32

SDVO/PCI-EX4 1.8V
3.3V
U3
1.8V POWER SUPPLY
3 VIN OUTPUT 2
B 3.3V 12V B

TAB 4
C9
10uF 1
C12 C13 C14 C15 GND C10

0.1uF 10uF 0.1uF 10uF LM1117 1.8/SOT-223 10uF

PHYSICAL LENGTH OF X16 CONNECTOR

IS REQUIRED. SIGNALS BEYOND X4 SDVO
SHOULD BE BARE.

A A

ORION ADD2-N DUAL PAD x16 REFERENCE DESIGN Title

PCI EX x4 CONN + POWER SUPPLY

Size Document Number Rev

B SiI-SC-0066 B1

Date: Tuesday, April 20, 2004 Sheet 1 of 4

5 4 3 2 1
 5 4 3 2 1

TO SiI1362 48pin LQFP

TX2+ 3,4
R13 C16
EXT_RES 3
EXT_SWING 3
A1 3
300 0.1uF RULES
VCC 3
TX2- 3,4
AVCC 3 TX1+ 3,4 Route traces with 100 Ohm Differential Impedance
R14 C17
D D
PVCC1 3 Avoid placing GND Copper or traces adjacent to TMDS Trace
300 0.1uF Put these 4 resistors and 4 capacitors as close as possible
PVCC2 3
TX1- 3,4 to the TMDS output pins of the SiI1362/4
SVCC 3 TX0+ 3,4
R15 C18
SPVCC 3
300 0.1uF
S_INT+ 3 TX0- 3,4
S_INT- 3 TXC+ 4
C19 3.3V
R16 300 For 1364 : R11, R12 = 22ohm
TXC+* 3
TXC-* 3
22 0.1uF For 1362 : R11, R12 = 0ohm R17 NO_STUFF
R12 R11 22
TXC- 4
2.2K(NP)

TXC+*
TXC-*
EXT_SWING R18
1 SDVOB_INT+
0.1uF 360
1 SDVOB_INT- HPDET 3,4
C20 U4

29
28
26
25
23
22
20
19
31
S_INT+
R19

TX2-

TX1-

TX0-

TXC-
EXT_SWING
TX2+

TX1+

TX0+

TXC+
S_INT- 39 330(NP)
C HTPLG C
0.1uF C21 1.8V
9 VCC
VCC L1 BEAD
VCC 15
46 48 C22 C23 C24 C25 C26 C27 C28 C29 C30
SDI+ VCC
47 SDI- VCC 38
100pF 1nF 0.1uF 1nF 0.1uF 1nF 0.1uF 1nF 10uF

1,3 SDVOB_R+ 51 SDR+ GND 5

1,3 SDVOB_R- 52 SDR- GND 10
3.3V
54 2 RR0
1,3 SDVOB_G+ SDG+ RSVD0 RR6 3.3V
1,3 SDVOB_G- 55 SDG- RSVD6 37
AVCC
57 21 C31 C32 C33 C34 C35 L2 BEAD
1,3 SDVOB_B+ SDB+ AVCC
58 27 C37
1,3 SDVOB_B- SDB- AVCC 100pF 1nF 0.1uF 1nF 10uF C36
18 1uF 10uF
AGND
1,3 SDVOB_C+ 60 SDC+ AGND 24
1,3 SDVOB_C- 61 SDC- AGND 30
OVCC 64
EXT_RES 49 PVCC
3.3V EXT_RES PVCC1
R22 1K PVCC1 17
16 C38 C39 C40 L3 BEAD
PGND1 PVCC
B NO_STUFF 1,3 RESET# 1 RESET# B
R23 7 32 PVCC2 C43 0.1uF 1nF 1uF
1,3 SDVO_SCL SDSCL PVCC2
1K(NP) 6 33 C41 C42 L4 BEAD
1,3 SDVO_SDA SDSDA PGND2
A1 8 0.1uF 1nF 1uF
A1 1.8V
R24 1K 50 SVCC
SVCC L5 BEAD
3,4 SDADDC 12 SDADDC SVCC 56
C44 C45 C46 C47 C48
3,4 SCLDDC 11 SCLDDC
41 100pF 1nF 0.1uF 1nF 10uF
GND
4 SDAROM 13 SDAROM GND 45
SGND 53
14 59 PVCC RR0
4 SCLROM SCLROM SGND SPVCC RR1
62
RSVD9
RSVD8
RSVD7
RSVD5
RSVD4
RSVD3
RSVD2
RSVD1

SPVCC L6 BEAD RR2

TEST 40 63 C49 C50 C51 RR3
TEST SPGND RR4
100pF 1nF 10uF RR5
34
35
36
42
43
44

RR6
4
3

RR7
64PIN TQFP RR8
RR9
RR8
RR7
RR5
RR4
RR3
RR2
RR1

SiI1364 RR9

A A

Title

ORION ADD2-N DUAL PAD x16 REFERENCE DESIGN Size

SiI1364PIN TQFP PACKAGE

Document Number Rev

B SiI-SC-0066 B1

Date: Tuesday, April 20, 2004 Sheet 2 of 3

5 4 3 2 1
 5 4 3 2 1

TX2+ 2,4

TX2- 2,4
TX1+ 2,4

D D
TX1- 2,4
TX0+ 2,4

TX0- 2,4
TXC+* 2

TXC-* 2

2 S_INT+ EXT_SWING 2

2 S_INT-
U7
48PIN TQFP PAD WITHIN 64PIN PAD

23
22
20
19
17
16
14
13
25
TX2-

TX1-

TX0-

TXC-
EXT_SWING
TX2+

TX1+

TX0+

TXC+
29 HPDET
HTPLG HPDET 2,4

NO_STUFF 10 VCC
VCC VCC 2
C VCC 28 C
32 SDI+ VCC 34
33 SDI-
3.3V
1,2 SDVOB_R+ 37 SDR+ GND 31
1,2 SDVOB_R- 38 SDR- GND 7

1,2 SDVOB_G+ 40 SDG+ OVCC 1

1,2 SDVOB_G- 41 SDG- AVCC
AVCC 2
1,2 SDVOB_B+ 43 SDB+ AVCC 15
1,2 SDVOB_B- 44 SDB- AVCC 21

1,2 SDVOB_C+ 46 SDC+ AGND 18

1,2 SDVOB_C- 47 SDC- AGND 24
11 PVCC1
PVCC1 PVCC1 2
2 EXT_RES 35 EXT_RES AGND 12

26 PVCC2
PVCC2 PVCC2 2
1,2 RESET# 2 RESET#
1,2 SDVO_SCL 5 SDSCL
1,2 SDVO_SDA 4 SDSDA PGND2 27
B B

2 A1 6 A1
36 SVCC
SVCC SVCC 2
2,4 SDADDC 9 SDADDC SVCC 42

2,4 SCLDDC 8 SCLDDC

GND 39
GND 45

48 SPVCC
SPVCC SPVCC 2
30 TEST SPGND 3

SiI1366/62

48PIN LQFP

A A

ORION ADD2-N DUAL PAD x16 REFERENCE DESIGN

Title
SiI1366/SiI1362 48pin LQFP

Size Document Number Rev

B Sil-SC-0066 B1

Date: Tuesday, April 20, 2004 Sheet 3 of 4

5 4 3 2 1
 5 4 3 2 1

5.0V

3.3V

35
36
37
38
D CON2 D
TX2- C52
For 1364 : FLASH
1 13

GND
GND
GND
GND
2,3 TX2- TX2+ DATA2 DATA3 EEPROM TO
2,3 TX2+ 2 DATA2 VCC5 14
3 15 L7 BEAD 0.1uF U5
SHIELD24 GND5 ADD2-N-C02_01.SPD
4 DATA4 HPDET 16 1 A0 VCC 8
5 DATA4 DATA0 17 2 A1 WP 7
SCLDDC 6 18 3 6
SDADDC DDCCLK DATA0 A2 SCL SCLROM 2
7 19 C53 C54 4 5
DDCDATA SHIELD05 VSS SDA SDAROM 2
8 NC DATA5 20
TX1- 9 21 0.1uF 10uF 24LC02
2,3 TX1- TX1+ DATA1 DATA5
2,3 TX1+ 10 DATA1 SHIELDCLK 22
11 SHIELD13 CLK 23
12 DATA3 CLK 24
Shell 25
Shell 26

DVI-D SHIELDED
TXC-
2 TXC- TXC+
2 TXC+

C C

TX0+
2,3 TX0+ TX0-
2,3 TX0-
R29
10K

HOTPLUG INPUT IS
5.0V
OPTIONAL.IT REQUIRES 5.0V
MANUAL PROGRAMMING
OF THE SiI1364/1362/66
2,3 HPDET R30 R31

2.2K 2.2K

B B

SDADDC
2,3 SDADDC

SCLDDC
2,3 SCLDDC

A ORION ADD2-N DUAL PAD x16 REFERENCE DESIGN A

Title
DVI CONN, HOTPLUG & EEPROM

Size Document Number Rev

B SiI-SC-0066 B1

Date: Tuesday, April 20, 2004 Sheet 4 of 4

5 4 3 2 1