International Journal of Pure and Applied Mathematics

Volume 119 No. 16 2018, 4157-4166

ISSN: 1314-3395 (on-line version)
url: http://www.acadpubl.eu/hub/
Special Issue
http://www.acadpubl.eu/hub/

A Low Power Address Transition

Decoder Circuit using Conditional Data
Mapping Flip Flop Approach
Ngangbam Phalguni Singh1 , Ndyetabura Y. Hamisi1 ,
Hashimu Uledi Iddi1 and A Ranjith2
1
University of Dar es Salaam, Tanzania
phalsingh@gmail.com
2
St. Joseph University in Tanzania, Tanzania
aranjithece@gmail.com
April 12, 2018

Abstract
In recent years, there are discussions about the address
transition decoder (ATD) circuit used with delay blocks
in CMOS technology. This is mainly used in Read only
Memory (ROM). And the power consumption and dissi-
pation are always challenges in VLSI designs. This paper
presents the ATD circuit using Conditional Data Mapping
Flip Flop (CDMFF) for generating the pulses in decoder.
This flip flop reduces the redundant events and reduces the
power consumption and dissipation by avoiding unnecessary
switching or triggering the decoder while the outputs are ex-
pected to remain constant. So transient analysis and slew
rate are also calculated for validating its application in low
power devices. The power dissipation for 32 bits is 137 nW
with a slew rate of 24.5 x 10-6 V/ms and 50 % duty cycle.

Key Words and Phrases: CMOS, ROM, Flip flop,

CDMFF, Slew Rate.

4157
International Journal of Pure and Applied Mathematics Special Issue

1 Introduction
In VLSI design, low power consumption and dissipation are main
concerned. And especially in memory devices low power buffer and
ROM play very significant role in reducing power. And address
transition decoder (ATD) circuit is the key component in reducing
the power dissipation by using delay blocks and dual edge pulse
generator [1]. In the previous work, the outputs of the dual edge
pulse generators are fed to the OR gate. Figure 1 shows the Dual
Edge Pulse Generator Circuit. It generates the pulses on both ris-
ing and falling edges of the input clock signal. The operations are
exactly same with the dual edge triggered flip flop. The flip flops are
triggered by the clock signal to process the data. But sometimes
the output remains the same for various combinations of inputs.
In such cases, there is unnecessary switching or triggering by the
clock signals. In this circuit also the pulse generator is generating
the pulses to trigger the decoder irrespective of the redundant word
sequences in the decoder output. It also increases the power con-
sumption and dissipation since the switching activities are active
in both the edges of the clock signal.

Figure 1: Dual Edge Pulse Generator Circuit Source: Ref [1].

The unnecessary switching can be reduced in the data selec-

tive flip flops. Some unwanted transistors in the flip flop are not
triggered for redundant occurrence of the event. So the selective
triggering method is employed based on the inputs [2][3][4]. To
achieve low power with such technique, Conditional Data Mapping
Flip Flop (CDMFF) will be employed in the proposed design. Ex-

4158
International Journal of Pure and Applied Mathematics Special Issue

periments were conducted to observe the system efficiency and the

effectiveness. This proposed design can be coined as Conditional
Address Transition Decoder (CATD). In Computer, memory cells
contribute in the power consumption due to the switching activities
occurred in these cells. The addresses are generated and decoded
in the ATD cells. But there are some redundant event that again
make the pulse generator circuit to generate the address sequences.
This issue is eliminated in this proposed design. The paper ex-
plains the previous work in ATD. It also discusses the effectiveness
of the proposed pulse generator circuit validated by the slew rate
calculation. The comparison analysis in power dissipation is also
done.

2 Proposed Bock Diagram of ATD

There are various techniques to reduce the power dissipation based
on the size, memory areas, switching activities, data path, clock dis-
tribution system, etc. Many researchers have done various analysis
in all these fields. Recent development is the combination of the
data selective flip flop with the clock distribution system. Previ-
ously double edge flip flop was used for low power designing [1][4][5].
But recently it has been studies for Conditional Data Mapping Flip
Flop (CDMFF) with the AC analysis and power dissipation mea-
surement [6][7]. But this paper will present the CDMFF as the
pulse generating circuit to reduce the power consumption and dis-
sipation by removing the redundant events. The time-domain tran-
sient analysis is used to analyze the circuits response as a function
of time. The transient analysis gives the calculation of the voltage
with respect to time. The output waveform can be observed to
analyze the voltage. To validate its application in this proposed
design, the slew rate and overall power for 32 bits are calculated.

3 CDMFF as Pulse Generator Circuit

In this type of flip flop, the data is fed conditionally. The circuit
diagram is shown in figure 3 and the simulation in figure 4. When-
ever the redundant event occurs, the unwanted transistors are not
triggered [8]. In this this flop, the hold time and the output delay

4159
International Journal of Pure and Applied Mathematics Special Issue

Figure 2: Proposed Block Diagram of ATD.

are increased [6]. It has 22 transistors with 6W clock driving power

[7]. The NOT gate in the diagram has two transistors (PMOS
and NMOS). The circuit is realized with the CMOS technology in
Multisim software. An output feedback structure is introduced in
transistor Q4 to conditionally feed the data to the flip flop. This
eliminates the unwanted transitions or switching activities when a
redundant event is predicted. It helps in reducing the power dissi-
pation of the flip flop [3].

Figure 3: CDMFF as pulse generator circuit.

The proposed circuit has larger size but the efficiency is im-
proved with reduced power dissipation. Whenever the words are
repeating while decoding in CMOS ROM, this circuit will not gen-
erate the pulses to decode it again. Thus it avoids the redundant
events or words and the triggering is done selectively. Hence it

4160
International Journal of Pure and Applied Mathematics Special Issue

Figure 4: Simulation of CDMFF.

reduces the power dissipation by reducing the switching activities.

The tree based column decoder is shown in figure 5.

Figure 5: ROM column decoder.

To further validate this transient analysis is done and the slew

rate is calculated. The transient analysis for CDMFF for time
intervals 250s and 500 s is show in Table 1. Power dissipation
for 1bit is 4.290 nW [7]. So for 32 bits, the power dissipation is
calculated as 137.28 nW or 137.28 x 10-6 mW.
x = time, y = voltage,

dy 6.1309 × 10−6
Slew Rate = | |=| | (1)
dx 250.3864 × 10−6
Thus Slew rate = 24.5 × 10−6 V/ms. Proper Slew rate gives
the output faithfully in a VLSI circuit.

4161
International Journal of Pure and Applied Mathematics Special Issue

Table 1: CDMFF transient analysis

SL.No Time or Voltage Value
1 x1 250.3864 µs
2 y1 5.0000 V
3 x2 500.7728 µs
4 y2 5.0000061309 V
5 dx 250.3864 µs
6 dy 6.1309 µV
7 min x 0.0000 s
8 max x 1.0000 ms
9 min y 4.9968 V
10 min y 5.0951 V

Table 2: CDMFF transient analysis

REF.No ROM Supply Power
Organization Voltage(V) (mV)
[9] 1K ×16 Bits 1.8 −
[10] 128 ×1 Bit 0.7 0.0389
[11] 8K ×16 Bits 3.3 8.63
[12] 1K ×32 Bits 3.3 5.35
[13] 1K ×32 Bits 2.5 3.53
[14] 4K ×32 Bits 2.5 8.2
[1] 32 ×1 Bit 1.8 0.78
Proposed Work 32 ×1 Bit 5 137 × 10−6

4 Result and Analysis

The CATD Circuit is designed using CDMFF using Multisim schematic
editor and is simulated using Multisim simulator at 100 Hz, 50 %

4162
International Journal of Pure and Applied Mathematics Special Issue

duty cycle and Slew rate of 24.5 x 10-6 V/ms. Here the main
part of power dissipation is due to the switching activities that oc-
curred when the decoding is processed. But the redundant events
are avoided by using CDMFF and the power dissipation is reduced.
The Comparison Analysis and overview of the work of the work are
shown in the Table 2.

5 Conclusion
A novel CATD circuit has been proposed and designed using CDMFF
for the application of 32 bit low power ROM. It is observed that the
power is reduced by a huge amount during the decoding process in
CATD. The redundant events are avoided by the selectively gener-
ating the pulses and proper buffering also. The only disadvantage
will be increased in the size since it has higher number of transis-
tor. But all the transistors are not triggered at a time. They are
triggered selectively. Thus the power is reduced in this proposed
design.

References
[1] S. Kukrety, G. Singh, and V. Sulochana, A Low Power 32
Bit CMOS ROM Using a Novel ATD Circuit, International.
Journal of Electrical and. Computer Engineering, vol. 3, no. 4,
pp. 509-515, 2013.

[2] M. Akila, A Novel Analysis on Low-Power High- Performance

Flip-Flops, Int. J. Comput. Appl., vol. 90, no. 16, pp. 32-37,
2014.

[3] R. S. Dharshini, The Energy Efficient Dual Dynamic Node

Pulsed Hybrid Flip-Flop Featuring Dual Mode Logic And
Clock Gating, in National Conference on Information Process-
ing and Remote Computing, pp. 1-7, 2014.

[4] E. Kanniga, N. I. Singh, and K. S. R. Rathnam, Gated-

Demultiplexer Tree Buffer for Low, Int. J. Adv. Res. Electr.
Electron. Instrum. Eng., vol. 2, no. 10, pp. 4652-4659, 2013.

4163
International Journal of Pure and Applied Mathematics Special Issue

[5] R. Hossain, L. D. Wronski, A. Albicki, and R. Hossain, Low

Power Design Using Double Edge Wggered Flip-Flops, IEEE
Trans. very large scale Integr. Syst., vol. 2, no. 2, pp. 04, 1994.

[6] Ngangbam Phalguni Singh, Ndyetabura Y. Hamisi and

Hashimu Uledi Iddi, AC Analysis of Octree based Buffer Using
Various Data Conditioning Flip Flops, Int. J. Appl. Eng. Res.,
vol. 12, no. 19, pp. 8366-8370, 2017.

[7] Ngangbam Phalguni Singh, Ndyetabura Y Hamisi, and

Hashimu Uledi Iddi, DDFF based Low Power Dissipation in
Ring Counter using Octree, Int. J. Appl. Eng. Res., vol. 12,
no. 19, pp. 8346-8353, 2017.

[8] K. Jindal and V. K. Pandey, Design of Conditional Data Map-

ping Flip-Flop for Low Power Applications, Int. J. Sci. Mod.
Eng., vol. 1, no. 5, pp. 72-75, 2013.

[9] Wei Cui, Siliang Wu. Design of Small Area and Low Power
Consumption Mask ROM, Integrated Circuit Design and Tech-
nology, 2007. ICICDT ’07, IEEE International Conference on.
vol., no. pp.1,4, May 30 2007-June 1 2007

[10] Mustapa M, Mohd-yasin F, Khawi MK, Reaz MBI,Kordesch

A.,Low power ROM employing dynamic thresholdvoltage
MOSFET (DTMOS) technique, IEEE International Confer-
ence on Semiconductor Electronics,ICSE 2008. pp.103,107, 25-
27 Nov. 2008.

[11] BD Yang and LS Kim. ,A low power ROM using charge recy-
cling and charge-sharing techniques. IEEE J. Solid-State Cir-
cuits, vol. 38, no. 4, pp. 641-653, Apr. 2003.

[12] BD Yang and LS Kim. Low power charge-sharing ROM using

dummy bit lines. Electronic Letter vol. 39, no. 14, pp. 1041-
1042, Jul. 2003.

[13] BD Yang, and LS Kim. A low-power charge-recycling ROM

architecture. IEEE Symposium on Circuits and Systems. Vol.
11, No. 4, pp. 590-600, Aug. 2003.

4164
International Journal of Pure and Applied Mathematics Special Issue

[14] BD Yang and LS Kim. A Low-Power ROM using single charge-

sharing capacitor and hierarchical bit line. IEEE Transactions
on VLSI Systems. Vol. 14, No. 4, pp. 313-322, April 2006.

4165
4166