Example

- II
Answer: Compute the factorial of the variable num.

C
int prod = 1;

ISA-3 int idx;

for(idx = num; idx > 1; idx --) {
prod = prod * idx
}

Let us now try to convert this program to SimpleRisc .

SimpleRisc
mov r1, 1 /* prod = 1 */
mov r2, r0 /* idx = num */
.loop:
mul r1, r1, r2 /* prod = prod * idx */
sub r2, r2, 1 /* idx = idx - 1 */
cmp r2, 1 /* compare (idx, 1) */
bgt .loop /* if (idx > 1) goto .loop*/

Modifiers Mechanism
*  We can add the following modifiers to an instruc6on *  The processor internally converts a 16 bit immediate to a 32
that has an immediate operand bit number
*  Modifier : *  It uses this 32 bit number for all the computa6ons
*  default : mov → treat the 16 bit immediate as a signed number *  Valid only for arithme6c/logical insts
(automa6c sign extension)
*  (u) : movu → treat the 16 bit immediate as an unsigned number *  We can control the genera6on of this 32 bit number
*  (h) : movh → leA shiA the 16 bit immediate by 16 posi6ons *  sign extension (default)
*  treat the 16 bit number as unsigned (u suffix)
*  load the 16 bit number in the upper bytes (h suffix)

3 4

1
 More about Modifiers Examples
*  Move : 0x FF FF A3 2B in r0
*  default : mov r1, 0xAB 12
mov r0, 0xA32B
sign bit AB 12
*  Move : 0x 00 00 A3 2B in r0
*  unsigned : movu r1, 0xAB 12
movu r0, 0xA32B
00 00 AB 12
*  Move : 0x A3 2B 00 00 in r0
*  high: movh r1, 0xAB 12
movh r0, 0xA32B
AB 12 00 00

5 6

Example Implementing Functions

*  Set r0 ← 0x 12 AB A9 2D *  Func6ons are blocks of assembly instruc6ons that can be

repeatedly invoked to perform a certain ac6on
movh r0, 0x 12 AB
addu r0, 0x A9 2D *  Every func6on has a star6ng address in memory (e.g. foo
has a star6ng address A

function foo

7 8

2
 Implementing Functions - II Notion of the Return Address
callee
caller
*  To call a func6on, we need to set :
p function call
*  pc ← A
p+4 return address
*  We also need to store the loca6on of the pc that we need to
come to aAer the func6on returns
ret
*  This is known as the return address
*  PC of the call instruc6on → p
*  We can thus call any func6on, execute its instruc6ons, and
`then return to the saved return address *  PC of the return address → p + 4
because, every instruc6on takes 4 bytes

9 10

How do we pass arguments/ return Problems with this Mechanism

values
*  Space Problem
*  Solu6on : use registers
*  We have a limited number of registers
SimpleRisc
*  We cannot pass more than 16 arguments
.foo: *  Solu6on : Use memory also
add r2, r0, r1
ret
.main: *  Overwrite Problem
mov r0, 3
mov r1, 5 *  What if a func6on calls itself ? (recursive call)
call .foo
add r3, r2, 10 *  The callee can overwrite the registers of the caller
*  Solu6on : Spilling

11 12

3
 Register Spilling Spilling
*  The no6on of spilling
*  The caller can save the set of registers its needs Caller Caller

*  Call the func6on Save registers

Callee Callee
*  And then restore the set of registers aAer the func6on returns Save registers

*  Known as the caller saved scheme

*  callee saved scheme Restore registers

Restore registers
*  The callee saves, the registers, and later restores them
(a) Caller saved (b) Callee saved

13 14

Problems with our Approach Activation Block

Activation block
*  Using memory, and spilling int foo(int arg1) { Arguments
solves both the space problem and overwrite int a, b, c; Return address
a = 3; b = 4;
problem c = a + b + arg1;
Register spill area

*  However, there needs to be : return c;

} Local variables
*  a strict agreement between the caller and the callee
regarding the set of memory loca6ons that need to be used
*  Ac6va6on block → memory map of a func6on
*  Secondly, aAer a func6on has finished execu6on, all the space
that it uses needs to be reclaimed arguments, register spill area, local vars

15 16

4
 How to use activation blocks ? Using Activation Blocks - II
*  Assume caller saved spilling *  In the called func6on
*  Before calling a func6on : spill the registers *  Read the arguments and transfer to registers (if required)
*  Save the return address if the called func6on can call other
*  Allocate the ac6va6on block of the callee func6ons
*  Write the arguments to the ac6va6on block of the callee, if *  Allocate space for local variables
they do not fit in registers *  Execute the func6on
*  Call the func6on *  Once the func6on ends
*  Restore the value of the return address register (if required)
*  Write the return values to registers, or the ac6va6on block of the
caller
*  Destroy the ac6va6on block of the callee
17 18

Using Activation Blocks - III Organising Activation Blocks

*  Once the func6on ends (contd …) *  All the informa6on of an execu6ng func6on is stored in its
*  Call the ret instruc6on
ac6va6on block

*  and return to the caller *  These blocks need to be dynamically created and destroyed
– millions of 6mes
*  The caller :
*  What is the correct way of managing them, and ensuring
*  Retrieve the return values from the registers of its ac6va6on their fast crea6on and dele6on ?
block
*  Is there a paeern ?
*  Restore the spilled registers
*  con6nue ...

19 20

5
 Pattern of Function Calls Pattern of Function Calls
test test2
*  Last in First Out
main foo foobar foobarbar
*  Use a stack to store ac6va6on blocks
test2() {
main() {
test();
test() {
... ...
Stack
foo(); test2(); return; foo foo foo foo
} return; }
}
foobar foobar foobar
foo() { foobar() { foobarbar() {
... ... ...
foobar(); foobarbar(); foobarbar
return; return; return;
} } }

21 (a) (b) (c) (d) 22

Working with the Stack What has the Stack Solved ?

*  Allocate a part of the memory to save the stack
*  Space problem
*  Tradi6onally stacks are downward growing. *  Pass as many parameters as required in the ac6va6on block
*  The first ac6va6on block starts at the highest address
*  Overwrite problem
*  Subsequent ac6va6on blocks are allocated lower addresses
*  Solved by ac6va6on blocks
*  The stack pointer register (sp (r14)) points to the beginning of an
ac6va6on block *  Management of ac6va6on blocks
*  Alloca6ng an ac6va6on block : *  Solved by the no6on of the stack

*  sp ← sp - <constant> *  The stack needs to primarily be managed in soAware

*  De-alloca6ng an ac6va6on block :
*  sp ← sp + <constant>
23 24

6
 call and ret instructions Recursive Factorial Program

call .foo ra ← PC + 4 ; PC ← address(.foo);

C
ret PC ← ra
int factorial(int num) {
if (num <= 1) return 1;
return num * factorial(num - 1);
*  ra (or r15) ß return address register }
void main() {
*  call instruc6on }
int result = factorial(10);

*  Puts pc + 4 in ra, and jumps to the func6on

*  ret instruc6on
*  Puts ra in pc
25 26

Factorial in SimpleRisc nop instruction

.factorial:
cmp r0, 1 /* compare (1,num) */
beq .return
bgt .continue *  nop → does nothing
b .return
.continue:
sub sp, sp, 8 /* create space on the stack */ *  Example : nop
st r0, [sp] /* push r0 on the stack */
st ra, 4[sp] /* push the return address register */
sub r0, r0, 1 /* num = num - 1 */
call .factorial /* result will be in r1 */
ld r0, [sp] /* pop r0 from the stack */
ld ra, 4[sp] /* restore the return address */
mul r1, r0, r1 /* factorial(n) = n * factorial(n-1) */
add sp, sp, 8 /* delete the activation block */
ret
.return:
mov r1, 1
ret
.main:
mov r0, 10
call .factorial
27 28

7
 Encoding Instructions Basic Instruction Format
5 27
*  Encode the SimpleRisc ISA using 32 bits. opcode rest of the instruction
*  We have 21 instruc6ons. Let us allot each instruc6on an
unique code (opcode)

Inst. Code Format Inst. Code Format
add 00000 add rd, rs1, (rs2/imm) lsl 01010 lsl rd, rs1, (rs2/imm)
Instruction Code Instruction Code Instruction Code sub 00001 sub rd, rs1, (rs2/i mm) lsr 01011 lsr rd, rs1, (rs2/imm)
add 00000 not 01000 beq 10000 mul 00010 mul rd, rs1, (rs2/imm) asr 01100 asr rd, rs1, (rs2/imm)
sub 00001 mov 01001 bgt 10001 div 00011 div rd, rs1, (rs2/imm) nop 01101 nop
mod 00100 mod rd, rs1, (rs2/imm) ld 01110 ld rd.imm [rs1]
mul 00010 lsl 01010 b 10010
cmp 00101 cmp rs1, (rs2/imm) st 01111 st rd. imm[rs1]
div 00011 lsr 01011 call 10011 and 00110 and rd, rs1, (rs2/imm) beq 10000 beq offset
mod 00100 asr 01100 ret 10100 or 00111 or rd, rs1, (rs2/imm) bgt 10001 bgt offset
cmp 00101 nop 01101 not 01000 not rd, (rs2/imm) b 10010 b offset
and 00110 ld 01110 mov 01001 mov rd, (rs2/imm) call 10011 call offset
or 00111 st 01111 ret 10100 ret

29 30

0-Address Instructions 1-Address Instructions

32

*  nop and ret instruc6ons opcode

op
offset
offset

5 27

32 *  Instruc6ons – call, b, beq, bgt

*  Use the branch format
opcode
*  Fields :
5 *  5 bit opcode
*  27 bit offset (PC rela6ve addressing)
*  Since the offset points to a 4 byte word address
*  The actual address computed is : PC + offset * 4
31 32

8
 3-Address Instructions Register Format
32
*  Instruc6ons – add, sub, mul, div, mod, and, or, lsl, lsr, asr
opcode 0 dest reg src reg1 src reg2
*  Generic 3 address instruc6on op I rd rs1 rs2
*  <opcode> rd, rs1, <rs2/imm> 5 1 4 4 4
*  Let us use the I bit to specify if the second operand is an *  opcode → type of the instruc6on
immediate or a register.
*  I bit → 0 (second operand is a register)
*  I = 0 → second operand is a register
*  dest reg → rd
*  I = 1 → second operand is an immediate
*  source register 1 → rs1
*  Since we have 16 registers, we need 4 bits to specify a register
*  source register 2 → rs2

33 34

Immediate Format 2 Address Instructions

32

opcode 1 dest reg src reg1 immediate *  cmp, not, and mov
op I rd rs1 imm
2 *  Use the 3 address : immediate or register formats
5 1 4 4 modifier bits 18
*  Do not use one of the fields
*  opcode → type of the instruc6on
*  I bit → 1 (second operand is an immediate)
*  dest reg → rd
*  source register 1 → rs1
*  Immediate → imm
*  modifier bits → 00 (default), 01 (u), 10 (h)

35 36

9
 cmp, not, and mov Load and Store Instructions
32
*  ld rd, imm[rs1]
cmp 00101 I rs1 rs2 / imm

5 1 4 4 18 *  rs1 → base register

32 *  Use the immediate format.
mov 01001 I rd rs2 / imm

32
5 1 4 4 18
ld rd, imm[rs1] 01110 1 rd rs1 imm
32
5 1 4 4 18
not 01000 I rd rs2/ imm

5 1 4 4 18

37 38

Store Instruction Store Instruction

*  Strange case of the store inst. *  Let us make an excep6on and use the immediate format.
*  st reg1, imm[reg2] *  We use the rd field to save one of the source registers
*  has two register sources, no *  st rd, imm[rs1]
register des6na6on, 1 immediate
*  Cannot fit in the immediate format, because the second operand
can be either be a register OR an immediate (not both) 32

st rd, imm[rs1] 01111 1 rd rs1 imm

5 1 4 4 18

39 40

10
 Summary of Instruction Formats Source:

Format Definition
branch op (28-32) offset (1-27)
register op (28-32) I (27) rd (23-26) rs 1(19-22) rs 2(15-18)
immediate op (28-32) I (27) rd (23-26) rs 1(19-22) imm (1-18) Computer Organisation and Architecture
op → opcode, offset → branch offset, I → immediate bit, rd → destination register
rs1 → source register 1, rs2 → source register 2, imm → immediate operand Smruti Ranjan Sarangi,
IIT Delhi

*  branch format → nop, ret, call, b, beq, bgt

Chapter 1 Introduction to Computer
*  register format → ALU instruc6ons Architecture
*  immediate format → ALU, ld/st instruc6ons

PROPRIETARY MATERIAL. © 2014 The McGraw-Hill Companies, Inc. All rights reserved. No part of this PowerPoint slide may be displayed, reproduced or distributed in any form or by any means,
without the prior written permission of the publisher, or used beyond the limited distribution to teachers and educators permitted by McGraw-Hill for their individual course preparation. PowerPoint
Slides are being provided only to authorized professors and instructors for use in preparing for classes using the affiliated textbook. No other use or distribution of this PowerPoint slide is permitted.
41 The PowerPoint slide may not be sold and may not be distributed or be used by any student or any other third party. No part of the slide may be reproduced, displayed or distributed in any form or by
any means, electronic or otherwise, without the prior written permission of McGraw Hill Education (India) Private Limited.

Source:

Computer Organisation and Architecture

Smruti Ranjan Sarangi,
IIT Delhi

Chapter 3- Assembly Language

PROPRIETARY MATERIAL. © 2014 The McGraw-Hill Companies, Inc. All rights reserved. No part of this PowerPoint slide may be displayed, reproduced or distributed in any form or by any means,
without the prior written permission of the publisher, or used beyond the limited distribution to teachers and educators permitted by McGraw-Hill for their individual course preparation. PowerPoint
Slides are being provided only to authorized professors and instructors for use in preparing for classes using the affiliated textbook. No other use or distribution of this PowerPoint slide is permitted.
The PowerPoint slide may not be sold and may not be distributed or be used by any student or any other third party. No part of the slide may be reproduced, displayed or distributed in any form or by
any means, electronic or otherwise, without the prior written permission of McGraw Hill Education (India) Private Limited.

11