MPMC

ANSWER KEY UNIT TEST 4

Part A
1. Give the various modes and applications of 8254 timer?
Mode 0 Interrupt on Terminal Count - to control parking lot Signs around electronic factory.
Accurate time delay under software control
Mode 1 Programmable One Shot –To produce an interrupt sig nal if the ac power fails.
Mode 2 Rate Generator – to produce a 1 KHz signal for a r eal time clock from an 8 MHz
processor clock signal. Real time Clock interrupt
Mode 3 Square Wave Generator - Programmable audio tone generator
Mode 4 Software Triggered Strobe - Parallel Data Transfer and send out a strobe signal to let
the receiving system know that the data is available Mode 5 Hardware Triggered Strobe -
Parallel Data Transfer.
2.List the features of memory mapped I/O.
1. Memory-mapped I/O uses a section of memory for I/O. The idea is simple. Instead of having
"real" memory (i.e., RAM) at that address, place an I/O device.
2. Thus, communicating to an I/O device can be the same as reading and writing to memory
addresses devoted to the I/O device. The I/O device merely has to use the same protocol to
communicate with the CPU as memory uses.
3. Some ISAs use special I/O instructions. However, the signals generated by the CPU for I/O
instructions and for memory-mapped I/O are nearly the same. Usually, there's
just one special I/O pin that lets you know whether its a memory address or an I/O address. Other
than that, they behave nearly identically.
3.How memory interfacing is differentiated from I/O interfacing ?
Memory Interfacing chip select signal is needed but I/O interfacing it is not required. Also
memory interfacing MEMR and MEMW control signal are used but I/O interfacing IOR
and IOW control signal are used.
4. What is DMA? [Nov/Dec 2011]
Direct Memory Access. The device may transfer data directly to/from memory without
any interference from the CPU. The device requests the CPU (through a DMA controller)
to hold its data, address and control bus, so that the device may transfer data directly
to/from memory.
5. What are the advantages of Programmable Interval Timer/Counter IC?
 Compatible with All Intel and Most Other  Microprocessors
 Handles Inputs from DC to 10 MHz
 Status Read-Back Command
 Six Programmable Counter Modes
 Three Independent 16-Bit Counters
 Binary or BCD Counting
 Single +5V Supply
 Standard Temperature Range.
PART B

6. Explain the timer with block diagram and different modes of operation.(13)
INTEL 8254 programmable Timer/ counter is a specially designed chip for μC applications
which require timing and counting operation. Each counter has two inputs, clock and gate and
one output. The clock is signal that helps in counting by decrementing a preloaded value in the
respective counter register. The gate serves as an enable input. If the gate is maintained low the
counting is disabled.
Data Bus Buffer:
The data bus buffer is bidirectional, 8-bit buffer and is used to interface the 8253 to the system
data bus. Data is transmitted or received by the buffer. The data bus buffer has three basic
functions, (i) Programming the modes of 8253. (ii) Loading the count value in times (iii)
Reading the count value from timers. The data bus buffer is connected to μ Ρ which are
also bidirectional. The data transfer is through these pins.

It accepts inputs for the system control bus and in turn generate the control signals for overall
device operation.
CS : The chip select input is used to enable the communication between 8253 and the
microprocessor by means of data bus. A low on CS enables the data bus buffers, while a high
disables the buffer
RD &WR : The read (RD ) and write (WR) pins control the direction of data transfer on the 8-
bit bus. When the RD input pin is low. The CPU is inputting data from 8253 in the form of
counter value. When WR pins is low, then CPU is sending data to 8253 in the form of mode
information or loading counters. The RD &WR should not both be low simultaneously. When
RD & WR pins are HIGH, the data bus buffer is disabled.
A0 & A1: These two input lines are used for counter selection along with the CS pin

Programming the Chip

All operations are decided by the control word loaded into the control register. For each
counters, there is a count register which is 16 bits in size. A number is written into this register
and stored in counter block. The maximum size of the number is FFFF H. The operation of the
counter occurs by creating a delay by decrementing this number down to 0,
the rate at which this occurs depends on the input clock frequency.
Status Register
OUT NULL RW1 RW0 M2 M1 M0 BCD
OUT: The level of the OUT Pin M2,M1,M0 : Counter Mode
NULL = 1 if counter is 0 BCD : Logic 1 for BCD counter

Control Word Register:

It accepts information from the data bus buffer and stores it in a register. The information stored
in the egister controls the operation mode, selection of binary or BCD counting, Selection of
counter and loading the values in the count register.
SCI SCO RL1 RL0 M2 M1 M0 BCD

8253 OPERATING MODES

Mode 0 Interrupt on Terminal Count
Mode 1 Programmable One Shot
Mode 2 Rate Generator
Mode 3 Square Wave Generator
Mode 4 Software Triggered Strobe
Mode 5 Hardware Triggered Strobe
Mode 0 Interrupt on Terminal Count
The output goes high after the terminal count is reached. The counter stops if the Gate is low.
The timer count register is loaded with a count (say 6) when the WR line is made low by the
processor. The counter unit starts counting down with each clock pulse. The output goes high
when the register value reaches zero. In the meantime if the GATE is made low the count is
suspended at the value(3) till the GATE is enabled again.
Mode 1 Programmable One Shot
The output goes low with the Gate pulse for a predetermined period depending on the counter.
The counter is disabled if the GATE pulse goes momentarily low. The counter register is loaded
with a count value as in the previous case (say 5) The output responds to the GATE input and
goes low for period that equals the countdown period of the register (5 clock pulses in this
period). By changing the value of this count the duration of the output pulse can be changed. If
the GATE becomes low before the countdown is completed then the counter will be suspended
at that state as long as GATE is low.
Mode 2 Rate Generator
In this mode it operates as a rate generator. The output goes high for a period that equals the time
of countdown of the count register (3 in this case). The output goes low exactly for one clock
period before it becomes high again. This is a periodic operation.
Mode 3 Square Wave Generator
It is similar to Mode 2 but the output high and low period is symmetrical. The output goes high
after the count is loaded and it remains high for period which equals the countdown period of the
counter register. The output subsequently goes low for an equal period and hence generates a
symmetrical square wave unlike Mode 2. The GATE has no role here.
Mode 4 Software Triggered Strobe
In this mode after the count is loaded by the processor the countdown starts. The output goes low
for one clock period after the countdown is complete. The countdown can be suspended by
making the GATE low This is also called a software triggered strobe as the countdown is
initiated by a program.
Mode 5 Hardware Triggered Strobe
The count is loaded by the processor but the countdown is initiated by the GATE pulse. The
transition from low to high of the GATE pulse enables count down. The output goes low for one
clock period after the countdown is complete
7.Draw the block diagram of programmable interrupt controller and explain its
operations.(13)
Features of 8259:
1. It is programmed to work with either 8085 or 8086 processor.
2. It manages 8-interrupts according to the instructions written into its control registers.
3. In 8086 processor, it supplies the type number of the interrupt and the type number
is programmable.
4. The interrupts can be masked or unmasked individually.
5. The 8259s can be cascaded to accept a maximum of 64 interrupts.
It has eight functional blocks. They are:
1. Control logic
2. Read Write logic
3. Data bus buffer
4. Interrupt Request Register (IRR)
5. In-Service Register (ISR)
6. Interrupt Mask Register (IMR)
7. Priority Resolver (PR)
8. Cascade buffer.
The interrupt mask register (IMR) stores the masking bits of the interrupt lines to be masked.
The relevant information is send by the processor through OCW.
 The in-service register keeps track of which interrupt is currently being serviced.
 The priority resolver examines the interrupt request, mask and in-service registers and
determines whether INT signal should be sent to the processor or not.
 The cascade buffer/comparator is used to expand the interrupts of 8259.
 In cascade connection one 8259 will be directly interrupting 8086 and it is called master
8259.

Functional block diagram of 8259:

8. Explain in detail about KEYBOARD/DISPLAY CONTROLLER.

The INTEL 8279 is specially developed for interfacing keyboard and display devices to
8085/8086/8088 microprocessor based system. The important features of 8279 are,
o Simultaneous keyboard and display operations.
o Scanned keyboard mode.
o Scanned sensor mode.
o 8-character keyboard FIFO.
o 1 6-character display.
o Right or left entry 1 6-byte display RAM.
o Programmable scan timing.
The four major sections of 8279 are keyboard, scan, display and CPU interface.
Keyboard section:
 The keyboard section consists of eight return lines RL0 - RL7 that can be used to form
the columns of a keyboard matrix.
 It has two additional input : shift and control/strobe. The keys are automatically
debounced.
 The two operating modes of keyboard section are 2-key lockout and N-key rollover.
 In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is
recognized.
 In the N-key rollover mode simultaneous keys are recognized and their codes are stored
in FIFO.
 The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM.
  The FIFO can store eight key codes in the scan keyboard mode. The status of the shift
key and control key are also stored along with key code. The 8279 generate an interrupt
signal when there is an entry in FIFO. The format of key code entry in FIFO for scan
keyboard mode is,

Block diagram of 8279:

 The functional block diagram of 8279 is shown.

 In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in
FIFO RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as
high to interrupt the processor.
Display section:
 The display section has eight output lines divided into two groups A0-A3 and B0-B3.
 The output lines can be used either as a single group of eight lines or as two groups of
four lines, in conjunction with the scan lines for a multiplexed display.
 The output lines are connected to the anodes through driver transistor in case of common
cathode 7-segment LEDs.
 The cathodes are connected to scan lines through driver transistors.
 The display can be blanked by BD (low) line.
 The display section consists of 16 x 8 display RAM. The CPU can read from or write into
any location of the display RAM.
Scan section:
 The scan section has a scan counter and four scan lines, SL0 to SL3.
 In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.
 In encoded scan mode, the output of scan lines will be binary count, and so an external
decoder should be used to convert the binary count to decoded output.
 The scan lines are common for keyboard and display.
 The scan lines are used to form the rows of a matrix keyboard and also connected to digit
drivers of a multiplexed display, to turn ON/OFF.
CPU interface section:
 The CPU interface section takes care of data transfer between 8279 and the processor.
  This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279
and CPU.
 It requires two internal address A =0 for selecting data buffer and A = 1 for selecting
control register of8279.
 The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to
8279.
 It has an interrupt request line IRQ, for interrupt driven data transfer with processor.
 The 8279 require an internal clock frequency of 100 kHz. This can be obtained by
dividing the input clock by an internal prescaler.
 The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard
modes.
Part C
9. Explain in detail about Programmable Peripheral Interface.

Pins, Signals and internal block diagram of 8255:

 It has 40 pins and requires a single +5V supply.
 The INTEL 8255 is a device used to parallel data transfer between processor and slow
peripheral devices like ADC, DAC, keyboard, 7-segment display, LCD, etc.
 The 8255 has three ports: Port-A, Port-B and Port-C.
 Port-A can be programmed to work in any one of the three operating modes mode-0,
mode-1 and mode-2 as input or output port.
 Port-B can be programmed to work either in mode-0 or mode-1 as input or output port.
 Port-C (8-pins) has different assignments depending on the mode of port-A and port-B.
 If port-A and B are programmed in mode-0, then the port-C can perform any one of the
following functions.
 As 8-bit parallel port in mode-0 for input or output.
 As two numbers of 4-bit parallel ports in mode-0 for input or output.
 The individual pins of port-C can be set or reset for various control applications.
 If port-A is programmed in mode- 1/mode-2 and port-B is programmed in mode-1 then
some of the pins of port-C are used for handshake signals and the remaining pins can be
used as input/ output lines or individually set/reset for control applications.
 The read/write control logic control signals.
These signals are given below:
1. RD (low): This control signal enables the read operation. When this signal is low, the
microprocessor reads data from a selected I/O port of the 8255A.
2. WR (low): This control signal enables the write operation. When this signal goes low, the
microprocessor writes into a selected I/O port or the control register.
3. RESET: This is an active high signal. It clears the control register and set all ports in the input
mode.
4. CS (low), A0 and A1: These are device select signals. They are,
Block diagram of 8255:
 The internal block diagram of 8255 is shown in fig:
Or
9b. Explain in detail about Programmable DMA Controller - Intel 8257
 It is a device to transfer the data directly between IO device and memory without through
the CPU. So it performs a high-speed data transfer between memory and I/O device.
The features of 8257 are:
 The 8257 has four channels and so it can be used to provide DMA to four I/O devices
 Each channel can be independently programmable to transfer up to 64kb of data by
DMA.
 Each channel can be independently perform read transfer, write transfer and verify
transfer.
It is a 40 pin IC.

Functional Block Diagram of 8257:

 The functional blocks of 8257 are data bus buffer, read/write logic, control logic, priority
resolver and four numbers of DMA channels.
OPERATING MODES OF INTEL 8257
 Each channel of 8257 Block diagram has two programmable 16-bit registers named as
address register and count register.
 Address register is used to store the starting address of memory location for DMA data
transfer.
 The address in the address register is automatically incremented after every
read/write/verify transfer.
The functional block diagram of 8257 is shown in fig.

 The count register is used to count the number of byte or word transferred by DMA.
 14-bits B0-B13 is used to
count value and a 2-bits is
used for indicate the type
of DMA transfer
(Read/Write/Veri1
transfer).

 In read transfer the

data is transferred
from memory to
I/O device.

 In write transfer the data is transferred from I/O device to memory.

 Verification operations generate the DMA addresses without generating the DMA
memory and I/O control signals.
 The 8257 has two eight bit registers called mode set register and status register. The
format of mode set register is,

The use of mode set register is,

                       1. Enable/disable a channel.
                       2. Fixed/rotating priority
                       3. Stop DMA on terminal count.
                       4.Extended/normal write time.
                       5. Auto reloading of channel-2.