The 2018 International Power Electronics Conference
Implementation of a Miniaturized SiC Inverter
Hideaki Fujita and Cristian Andres Garces Guajardo
Tokyo Institute of Technology
hf@ieee.org
Abstract—This paper presents analysis, design, and implemen-
tation of a miniaturized inverters using SiC-MOSFETs. Theoret-
ical analysis and experimental verification in this paper reveals
the relationship between the time-domain switching properties
and the frequency-domain impedance characteristics. Based on
the analysis, damping resistors are inserted into the dc side of
the inverter. The damping resistors can effectively reduce the
impedance at resonant frequencies in frequency domain, and they
also enable to suppress the surge voltage and oscillation across the
switching devices in time domain. Moreover, it has theoretically
and experimentally been confirmed that the damping resistors
also have the capability of reducing the switching power losses
in the circuit.
I. I NTRODUCTION
Currently, SiC devices are available in the market, and it is
possible to reduce the power losses of inverters by replacing
an Si-IGBT module with an SiC-MOSFET module. The SiC-
MOSFETs have a low on-state resistance with a relatively
high voltage rating of more than 1200 V, which can be used
instead of 1200-V class IGBTs. Moreover, since the SiC-
MOSFETs have the fast switching capability, it is expected to
increases the switching frequency to a higher frequency than
IGBTs. In this case, the components used in the circuit has to
suffer a very high dv/dt and di/dt and to suppress the induced
electromagnetic interferences (EMI).
Various analysis and design methods are proposed to
reduce the EMI issue induced by a PWM inverters, such as
application of a common-mode chokes [4], active common
mode cancelers [5], and multilevel topologies [6]. They mainly
focuses on the common-mode leakage current because it
produces a relatively strong conduction EMI. The frequency
band of the conductive EMI is essentially in a range from 150
kHz to 30 MHz in a standard or regulation. The SiC-MOFET
has a very fast turn-on and turn-off times of a few tens nano
seconds or less at a relatively high dc-link voltage. This quick
switching operation would cause a serious EMI issues at a
higher frequency band.
For these reasons, it becomes attractive to improve the
layout of the switching devices and passive components on
printed circuit boards (PCBs)[7]-[9]. In these PCB design, it
is discussed various problems to make the circuit small, eg.,
crosstalk between the power lines, reduction of the radiated
EMI, temperature and thermal design, location of the cooling
devices, and so on. In the miniaturized design, it is very
important to pay attention to the size of components. Espe-
cially, the dc capacitors occupies a relatively large footprint
in the power circuit PCB. Recent polymer film capacitors
have a large current ripple ratings and are suitable as a dc
©2018 IEEJ
capacitor. However, they have a relatively large equivalent
series inductance (ESL), and thus, it is required to add a
capacitor having a better high-frequency response. Ceramic
capacitors seems to be suitable for this purpose although its
capacitance is relatively small. Therefore, the combination of
film and ceramic capacitors are often used in the dc side of
the power circuit PCB.
This paper presents analysis, design, and implementation
of a miniaturized inverters using SiC-MOSFETs. In this paper,
theoretical analysis and experimental verification has been
conducted to reveal the relationship between the time-domain
switching properties and the frequency-domain impedance
characteristics. Based on the analysis, an inverter was designed
and implemented to drive a 400-V, 15-kW induction motor
using 1200-V SiC-MOSFETs. The newly-designed inverter
circuit is equipped with damping resistors on its dc side to
suppress the resonance between the dc capacitors and stray
inductance. The added damping resistors make it possible to
reduce the impedance at resonant frequencies in frequency
domain successfully, and thus, they also make it possible to
suppress the surge voltage, overshoot, and oscillation across
the drain-to-source terminals of the switching devices in time
domain. Moreover, it has theoretically and experimentally been
confirmed that the damping resistors also have the capability
of reducing the switching power losses in the circuit.
II. C IRCUIT C ONFIGURATION
Fig. 1 shows circuit configuration of a traditional three-
phase voltage-source inverter, which consists of six switching
devices and a dc capacitor. In general, a three-phase inductive
load should be connected to the three-phase ac output of the
inverter. A practical inverter is usually would be connected
to a three-phase rectifier with a relatively-large electrolytic
capacitor as the power source. In this paper, the dc input is
assumed to be regulated at a constant voltage E instead of a
rectifier, as shown in Fig. 1 to make the following analysis
simple.
The experimental setup also employs the same circuit
configuration essentially. The main circuit is constructed on
a printed circuit board (PCB) as well as the gate drive circuit.
SiC-MOSFET (C2M0025120D: 1200 V, 90 A, Wolfspeed)
is used as the switching devices. Two SiC-MOSFETs are
connected in parallel and used as an arm of the inverter, and
thus, the inverter uses twelve MOSFETs totally. Six separated
heat sink are attached to the MOSFETs. No insulator is
inserted between the heat sink and the MOSFET because each
heat sink is isolated from the other arm. This makes it possible
to reduce the thermal resistance.
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i
dc
Zdc i
dc

 ∆vdc 
ia

ia
ib
E C vdc 
ib
E vdc

ic ic

Fig. 1. Circuit configuration of the developed inverter. Fig. 3. Equivalent Circuit of the inverter.

l4 l3 l2 l1 III. T RANSIENT A NALYSIS OF THE S WITCHING

Cd C4 C3 C2 C1
Fig. 2. Equivalent dc-link circuit of the inverter.
Fig. 2 shows the configuration of the dc-link capacitors,
and the circuit parameter of the dc-link components are shown
in TableI. The inverter is equipped with ceramic capacitors of
C1 = 20 nF, C2 = 33 nF, and C3 = 300 nF, and a film
capacitor of C4 = 1 µF. In general, it is better to attach the
dc capacitor to the inverter bridge as close as possible for
reduction of stray inductance in the connection. However, the
size of the film capacitor C4 is relatively larger than C1 through
C3 . Thus, the ceramic capacitors are required to be put closer
to the MOSFETs than the film capacitor C4 . In the following
experiment, an electrolytic capacitor of C4 = 3300 µF was
inserted between the film capacitor and a dc power supply to
eliminate the internal impedance of the power supply. Note
that l4 in Table I represents the equivalent series inductance
(ESL) in the electrolytic capacitor Cd . The stray inductance
between C4 and Cd are disregarded because the ESL in Cd is
much larger than the actual stray inductance between C4 and
Cd .
T RANSITION
Fig. 3 is the equivalent circuit of a three-phase voltage-
source inverter. At first, the the-phase load current can be
considered as a constant three-phase current source Ia , Ib ,
and Ic because the load should be inductive and its current
change can be negligible in a short switching duration. As
the Kirchhoff’s current laws, the following relation should be
considered in the load current:
Ia + I b + I c = 0 (1)
The dc side circuit of the inverter in Fig. 1 is replaced with
an equivalent series impedance Zdc in Fig. 3. The equivalent
series impedance Zdc is the dc-side impedance seen from the
terminals of the switching devices. Note that the equivalent
series impedance Zdc should be considered to include the
effect of all components, such as the capacitance, the series
equivalent resistance (ESR), and the series equivalent induc-
tance (ESL) of the dc capacitors, and stray inductance on the
PCB pattern. Assuming that no leak current flows through the
dc capacitor C in Fig. 1, the terminal voltage vdc is equal to
the dc supply voltage E when all the MOSFETs are turned
off. Thus, the dc supply voltage should be E also in Fig. 3
as the Thévenin’s theorem. Then, the voltage drop across the
equivalent series impedance, ∆vdc is given by
∆vdc = vdc − E, (2)
which represents the voltage ripples or the ac component
included in the terminal voltage vdc in time domain.

A. Time Domain Analysis

TABLE I. PARAMETERS OF THE DC LINK COMPONENTS
Fig. 4 shows two conduction states of the three-phase
C1 ceramic capacitor 10 × 2 = 20 nF
inverter assuming the switching states in the a-phase leg. In
ESL 1.1 nH
C2 ceramic capacitor 33 nF Fig. 4(a), the a-phase upper MOSFET is conducting, and the
ESL 1.6 nH lower MOSFETs are in on-state in the b- and c-phase legs. In
C3 ceramic capacitor 100 × 3 = 300 nF this state, the dc-side current is equal to the a-phase current
ESL 1.2 nH idc = ia . On the other hand, the lower MOSFETs are turned
C4 film capacitor 1 µF
on in all the three legs in Fig. 4(b). Then, the load current
ESL 73 nH
Cd electrolytic capacitor 3000 µF circulates the lower arms, an then no current flows through the
l1 stray inductance 1.3 nH dc side as idc = 0. Therefore, the initial and final value of the
l2 stray inductance 1.9 nH dc current can be considered as idc (0) = Ia and idc (∞) = 0 in
l3 stray inductance 10 nH a turn-on transition, respectively. And they need to be modified
l4 ESL in Cd 100 nH as idc (0) = 0 and idc (∞) = Ia for a turn-off transition.

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and/or a network analyzer. In addition, it is also required to

estimate the spectrum of the drain current Idc (ω).
Fig. 6(a) shows an equivalent circuit including two dc
capacitors and stray inductance between the capacitors. Here,
the capacitor Cd is assumed to be large enough to neglect
(a) (b) its impedance at the resonant frequency of the circuit. The
Fig. 4. Switching mode and current loop.
equivalent series resistance r is considered in the capacitor
C. It is usually small, and the the parallel resonant angular
frequency ωr is simply calculated by

idc
1
Coss  ωr = √ . (5)
iD lC
Zdc ∆vdc Zdc ∆vdc idc
The impedance seen from the current source is calculated
Coss Ia as follows:
( )
1
(a) (b) Zdc (ω) = jωl ∥ r +
jωC
Fig. 5. Simplified circuit for the dynamic analysis. = Rdc (ω) + jXdc (ω), (6)
where R(ω) is the transformed equivalent series resistance and
Fig. 5 is a simplified equivalent circuit paying attention X(ω) is the series reactance. The equivalent series resistance
to the switching transition in Fig. 4. The current sources Ia is given by
and iD represent the a-phase load current and the drain current
ω 4 l2 C 2 r
through the upper MOSFET. If the equivalent series impedance Rdc (ω) =
Zdc were expressed by a simple inductor Ldc , the applied (1 − ω 2 lC)2 + ω2 C 2 r2
( )4
voltage ∆vdc can also be expressed in time domain by ω
r
ωr
didc (t) = [ ( )2 ] 2 ( )2 ( )2 , (7)
∆vdc (t) = Ldc . (3) ω
dt 1 − ωr + ωωr r
Z0
This implies that the equivalent series impedance strongly
affects the voltage ripple in the dc side of the inverter. And and the series reactance is
thus, it is very important to reduce stray inductance existing 1 + ω 2 C(Cr2 − l)
Xdc (ω) = ωl
in the dc side of the inverter. However, the total impedance (1 − ω 2 lC)2 + ω 2 C 2 r2
Zdc has a complicated network consisting of capacitors and ( )2 ( )2 ( )2
stray inductance among them in a real circuit, for example as 1 − ωωr + ωωr r
Z0
shown in Fig. 2. = ωl [ ( )2 ] 2 ( )2 ( )2 . (8)
1 − ωωr + ωωr r
Z0
B. Frequency Domain Analysis
Fig. 5 (a) considers the effect of the output stray ca- As shown in (7), the transformed equivalent series resis-
pacitance Coss in both upper and lower MOSFETs. The tance and reactance Rdc (ω) and Xdc (ω) have a largest value
upper MOSFET is represented by the parallel connection of a around the parallel resonant angular frequency, ω ≈ ωr . Thus,
current source iD and Coss , and the body diode and Coss are the most significant surge voltage or oscillation would usually
only considered in the lower device as shown in Fig. 5 (a). be induced around the parallel resonant angular frequency ωr .
Moreover, the dc power supply E in Fig. 4 is removed from The transformed equivalent series resistance and reactance is
Fig. 5 (a), and thus, this equivalent circuit is only effective for simply obtained at ωr as
ac analysis to derive the surge and/or oscillating component l Z2
∆. It can also be expressed in frequency domain by using the Rdc (ωr ) = = 0, (9)
Cr r
Fourier transform as, √
l
∆Vdc (ω) = Zdc (ω)Idc (ω). (4) Xdc (ωr ) = = Z0 , (10)
C
where Zdc (ω), ∆Vdc (ω), and Idc (ω) are frequency responses where Z0 is the characteristic impedance between the stray
of the impedance, surge component, and drain current, respec- inductance l and capacitor C, given by
tively. In this case, the frequency response of the impedance, √
Zdc (ω) is require to evaluate the surge voltage. Although l
Z0 = . (11)
the equivalent series impedance Zdc has complicated char- C
acteristics due to the dc capacitors and stray inductance, it Equation (9) implies that it is possible to reduce the trans-
can fortunately be measured by using an impedance analyzer formed equivalent series resistance Rdc (ωr ) by suppressing

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l Rdc l4 l3 l2 l1

r R4 R3
Cd Idc Xdc Idc Cd C2 C1
C C4 C3

(a) (b)
Fig. 6. Simplified equivalent impedance. Fig. 7. Equivalent dc-link circuit of the inverter with damping resistors.

TABLE II. DAMPING RESISTORS

the stray inductance l. This well agrees with the result of R3 chip resistors 1 ∥ 3 = 0.3 Ω
the transient analysis. On the other hand, the transformed R4 carbon resistor 0.6 Ω
equivalent series resistance Rdc (ωr ) is inversely proportional
to the real equivalent series resistance (ESR) r. Thus, a non-
negligible surge voltage would be induced when the capacitor across the dc link can be reduced as
C has a very small ESR r. The estimated voltage ripple or
∆V̇dc (ωr ) = Z0 (1 + j)Idc (ωr ). (15)
oscillation across the dc link can be calculated as
Assuming that the damping resistor is much higher than the
∆V̇dc (ωr ) = [R (ω) + jXdc (ω)] ESR in the capacitor, the power loss in the damping resistance
( dc2 )
Z0 Rdc (ω) is also estimated as
= + jZ0 Idc (ωr ). (12)
r 2
Pdc (ωr ) = Z0 Idc (ωr ). (16)
The total power loss in the transformed equivalent series The total power loss in the damping capacitor and the ESR
resistance Rdc (ω) can be obtained by seems to be reduced because the ESR r is usually lower than
∫ ∞ ∫ ∞ the characteristic impedance Z0 .
2
P = P (ω)dω = R(ω)Idc (ω)dω. (13)
0 0
V. E XPERIMENTAL RESULTS
In fact, this calculated power loss in the transformed equivalent
series resistance Rdc (ω) occurs in the ESR of the capacitor C Fig. 8 shows the measured impedance of the dc link seen
because no other lossy element is considered in the equivalent from one of the three inverter legs. Four difference conditions
circuit in Fig. 6(a). are examined in Fig. 8. In case of no damping resistor,
the impedance plot has three large peaks in the measured
As mentioned above, the most significant oscillation ap- impedance at frequencies of 300 kHz, 1.2 MHz, and 20 MHz.
pears around ωr . Therefore, the dominant power lose is also The peak value of impedance reaches 6 Ω at 1.2 MHz which is
assumed to be caused by the resonant frequency component caused by the parallel resonance between the ceramic capacitor
in the equivalent current source, Idc (ωr ). The power loss can C3 = 300 nF and the film capacitor C4 = 1 µF. And the
be estimated by resonance at 20 MHz is induced between ceramic capacitors
Z02 2 of C2 = 33 nF and C3 = 300 nF. The damping resistor
2
P (ωr ) = R(ωr )Idc I (ωr ).
(ωr ) = (14) R3 is required to eliminate the The resonance at 1.2 MHz is
r dc
damped by the resistor R3 inserted in series with either film or
As shown in (14), the expected power loss is essentially in ceramic capacitor. The better impedance plot is obtained when
inverse proportion to the capacitor ESR r. Thus, relatively both damping resistors are inserted to both film or ceramic
large power loss would occur and cause a non-negligible heat capacitors.
in the capacitor if the circuit uses dc capacitors with a low
equivalent series resistance r. Fig. 9 shows experimental waveforms of the experimental
setup. The input dc voltage was 600 V, the switching frequency
IV. E FFECT OF DAMPING RESISTORS was set to 20 kHz. The practical dead time was 300 ns,
no dead time compensation was implemented. A inductive
Fig. 7 shows the circuit configuration of the dc link where load was connected to the inverter. The output line-to-line
damping resistors are applied to the capacitors. Two damping was modulated properly, and the line current has a sinusoidal
resistors R3 and R4 are connected in parallel with ceramic waveform. Moreover, almost no overshoot was observed in
capacitor C3 and the film capacitor C4 . The aim of the the voltage waveform, irrespective of phase angle of the line
damping resistors are mainly to suppress the peak of the current.
impedance Zdc . Thus, these resistance values R3 and√R4 are
designed based Figs. 10-13 show experimental turn-on and off waveforms
√ on the characteristic impedance Z3 = l3 /C3 measure with/without the damping resisters. In this measure-
and Z4 = l4 /C4 , respectively.
ment, the source current iS was measured instead of the drain
It is assumed to connect a damping resistor R = Z0 to current because of the pin arrangement of the MOSFETs.
the circuit Fig. 5 (a). The induced voltage ripple or oscillation Although iS included the gate current iG , which would be

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10 700

vDS [V]

1 0
Measured impedance [Ω]

30

0.1 iS [A]

Without resistor 30
0.01
With R3
With R4 ∆vdc [V] 0
With R3 and R4

0.001 -30  
10 k 100 k 1M 10 M 100 M
Frequency [Hz] 200 ns

Fig. 8. Measured impedance of the dc link seen from one of the inverter Fig. 11. Turn-off waveforms without damping resistor.
legs.
700

vDS [V]
600
0
vuv [V] 0
30
-600
30 iS [A]

iu [A] 0 0

-30   30

Fig. 9. Experimental Waveforms of 10 ms

∆vdc [V] 0

-30  
negligible. Figs. 10 and Figs. 11 included a continuous oscil- 200 ns
lation in ∆vdc , while it was well damped in Figs. 12 and Figs.
13. Fig. 12. Turn-on waveforms with damping resistors.

Fig. 14 shows the measured power loss with/without the

damping resisters. In this measurement, one of the three-
phase leg was only used as a buck converter to improved the
measurement accuracy. The input dc voltage was E = 600
V, and the switching frequency was set to 20 kHz. As shown
700
in Fig. 14, the damping resister reduced the power loss by 2
W. Although the difference is not so large, it is consumed in
the small capacitors in case of the circuit without damping
resistors. For this reason, the capacitor may causes undesired
heat and make its lifetime short if no damping resistor is
connected.

vDS [V]
VI. C ONCLUSION
0
This paper have discussed the analysis, design, and imple-
30 mentation of a miniaturized inverters using SiC-MOSFETs. An
inverter was designed and implemented to drive a 400-V, 15-
iS [A]
kW induction motor using 1200-V SiC-MOSFETs based on
0 the analysis. The newly-designed inverter circuit is equipped
with damping resistors on its dc link capacitors to suppress
30
the resonance between the dc capacitors and stray inductance.
∆vdc [V] 0 The effect of the damping resistor has been evaluated in
theoretical analysis and experimental verification. As a result,
-30   it has been clarified that the added damping resistor makes it
200 ns possible to reduce the impedance at the resonant frequency.
and to suppress the surge voltage, overshoot, and oscillation
Fig. 10. Turn-on waveforms without damping resistor. across the drain-to-source terminals. Moreover, it has also been

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700
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Measured power loss Ploss [W]

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0 5 10 15 20 25
Load current iL [A]

Fig. 14. Measured power loss.

confirmed that the damping resistor can reduce the power

losses.

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