Haswell ULT 15W: Vram Ddr3L-Sodimm Cha

5 4 3 2 1
BOM
ZYW ULT SYSTEM BLOCK DIAGRAM IV@ : iGPU
EV@ : Optimus
01
eDP@ : no stuff when use LVDS
Dual Channel DDR III VRAM LVD@: stuff when use LVDS
DDR3L-SODIMM CHA 1333/1600 MHZ Haswell ULT 15W GPU DDR3 TPM@ : TPM
N15S-GT (GeForce 840M)
P14 PCIE-5 N15V-GM (GeForce 820M)
P21,P22 8M@ :8M FLASH ROM
MCP 1168pins PCI-E x4 RD@ : Re-driver SATA
D X'TAL 27MHz D
TX/RX
P16~P20 NF@ : NGFF card
DDR3L-SODIMM CHB IMC
DC+GT3
P15
40 mm X 24 mm
RTD2136N
LVDS Conn. P25
SATA - HDD1 SATA0 P24
P28 SATA
eDP EDP
SATA ODD SATA1 eDP Conn. P25
P28
SATA2/PCIE6_L1 DDI2 ITE6513

U19 VGA Conn. P26
NGFF P23
DIS: SLG3NB3454 AL003454000
UMA: SLG3NB3455 AL003455002 SATA3/PCIE6_L0 DP
X'TAL 27MHz
P27 DDI1
HDMI Conn. P26
Integrated PCH
USB3.0-port1,2
I/O board (card reader+LED)
Cardreader USB2.0-port7 USB3.0/2.0
GL834L USB2.0-port0,1 USB3 Port X2
CONN. 2in 1
(cardreader) P30 MB side
P29 P30
C
USB2.0 C
USB2.0-port6 CLK
CCD(Camera)
P25
PCI-E x1 PCIE-port4 USB2.0-port4
USB2.0-port5
Touch Screen(option) MINI CARD
P25 WLAN+BT
X'TAL P27
32.768KHz
PCIE-port3
RTL8111GS-CG RJ45
P29
I/O board X'TAL 24MHz
USB2.0-port2,3 P2~P13 10/100/1G P29
USB2 IO*2 I/O Board Conn. CLK
P30 P8 BATTERY RTC
X'TAL 25MHz
Azalia IHDA
SPI SPI ROM
8M P8
I2C
LPC I2C
EC
B Int. D-MIC ALC283 B
D-MIC
AUDIO CODEC IT8587
P30 P31 P33
PWM PS2
Global Jack Speaker*2 HALL SENSOR FAN Touch PAD

P30 P30
K/B Con.
P31 P23 P32 P32
A A
Quanta Computer Inc.

PROJECT : ZYW
Size Document Number Rev
3A
Block Diagram
Date: Tuesday, April 29, 2014 Sheet 1 of 46
5 4 3 2 1
5 4 3 2 1
Haswell ULT (DISPLAY,eDP)

U33A HSW_ULT_DDR3L
02
eDP Panel
C54 C45 EDP_TXN0
26 INT_HDMITX2N DDI1_TXN0 EDP_TXN0 EDP_TXN0 24
D 26 INT_HDMITX2P C55 B46 EDP_TXP0 EDP_TXP0 24 D
B58 DDI1_TXP0 EDP_TXP0 A47 EDP_TXN1
HDMI
26 INT_HDMITX1N DDI1_TXN1 EDP_TXN1 EDP_TXN1 24

26 INT_HDMITX1P C58 B47 EDP_TXP1 EDP_TXP1 24
B55 DDI1_TXP1 EDP_TXP1
26 INT_HDMITX0N DDI1_TXN2
A55 C47
26 INT_HDMITX0P DDI1_TXP2 EDP_TXN2
26 INT_HDMICLK- A57 C46
B57 DDI1_TXN3 EDP_TXP2 A49
26 INT_HDMICLK+ DDI1_TXP3 EDP_TXN3
DDI EDP B49
C51 EDP_TXP3
23 CRT_TXN0 DDI2_TXN0
C50 A45 EDP_AUXN
CRT
23 CRT_TXP0 DDI2_TXP0 EDP_AUXN EDP_AUXN 24

23 CRT_TXN1 C53 B45 EDP_AUXP EDP_AUXP 24
B54 DDI2_TXN1 EDP_AUXP
23 CRT_TXP1 DDI2_TXP1
C49 D20 EDP_RCOMP R269 24.9/F_4 +VCCIOA_OUT
B50 DDI2_TXN2 EDP_RCOMP A43 DP_UTIL R630 *0_4 PCH_BRIGHT
A53 DDI2_TXP2 EDP_DISP_UTIL
B53 DDI2_TXN3
DDI2_TXP3
eDP_RCOMP
R631 *0_4
Trace length < 100 mils
Trace width = 20 mils
1 OF 19 Trace spacing = 25 mils
C C
+3V
HSW_ULT_DDR3L
U33I
PCI_PIRQA# R185 10K_4
PCI_PIRQB# R562 10K_4
PCI_PIRQC# R183 10K_4
PCI_PIRQD# R198 10K_4
24,25 PCH_BRIGHT PCH_BRIGHT B8 B9 HDMI_DDCCLK_SW 26 DGPU_SELECT# R559 10K_4
PCH_BLON A9 EDP_BKLCTL DDPB_CTRLCLK C9 CRT_CLK R195 2.2K_4
25,33 PCH_BLON EDP_BKLEN DDPB_CTRLDATA HDMI_DDCDATA_SW 26
PCH_VDDEN C6 eDP SIDEBAND D9 CRT_CLK CRT_DATA R196 2.2K_4
25 EDP_VDD_EN EDP_VDDEN DDPC_CTRLCLK D11 CRT_DATA TPD_INT#_D R171 100K_4
DDPC_CTRLDATA
PCI_PIRQA# U6 +3V
PCI_PIRQB# P4 PIRQA/GPIO77 C5
PIRQB/GPIO78 +3V DDPB_AUXN
PCI_PIRQC# N4 +3V B6 CRT_AUX#_C C551 *short_4 CRT_AUXN 23
PCI_PIRQD# N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5
PIRQD/GPIO80 +3V DDPB_AUXP +3V
PCI_PME# AD4 +3V_S5 A6 CRT_AUX_C C549 *short_4 CRT_AUXP 23
TP95 PME PCIE DDPC_AUXP
TPD_INT#_D U7 +3V
DGPU_SELECT# L1 GPIO55 CRT_AUXN R582 *100K_4
GPIO52 +3V
BOARD_ID4 L3 +3V C8 INT_HDMI_HPD 26
10 BOARD_ID4 GPIO54 DDPB_HPD
BOARD_ID1 R5 +3V A8 CRT_HPD 23 CRT_AUXP R579 *100K_4
10 BOARD_ID1 GPIO51 DDPC_HPD
BOARD_ID2 L4 +3V D6
10 BOARD_ID2 GPIO53 EDP_HPD EDP_HPD 24,25
B B
R194 R244
4.7K_4
9 OF 19 100K_4
+3V
2
3 1 TPD_INT#_D
32,33 TPD_INT#
Q26
2N7002K
A A

PROJECT :ZYW
3A
Haswell 3/5 (DDI/eDP)
5 4 3 2 1
5 4 3 2 1
Haswell ULT
U33C HSW_ULT_DDR3L
(DDR3L)
U33D
Haswell Processor (DDR3)
HSW_ULT_DDR3L
03
14 M_A_DQ0 M_A_DQ0 AH63 AU37 M_A_CLK0# 14
M_A_DQ1 AH62 SA_DQ0 SA_CLK#0 AV37 M_A_DQ32 AY31 AM38
14 M_A_DQ1 SA_DQ1 SA_CLK0 M_A_CLK0 14 14 M_A_DQ32 SB_DQ0 SB_CK#0 M_B_CLK0# 15
14 M_A_DQ2 M_A_DQ2 AK63 AW36 M_A_CLK1# 14 14 M_A_DQ33 M_A_DQ33 AW31 AN38 M_B_CLK0 15
M_A_DQ3 AK62 SA_DQ2 SA_CLK#1 AY36 M_A_DQ34 AY29 SB_DQ1 SB_CK0 AK38
14 M_A_DQ3 SA_DQ3 SA_CLK1 M_A_CLK1 14 14 M_A_DQ34 SB_DQ2 SB_CK#1 M_B_CLK1# 15
14 M_A_DQ4 M_A_DQ4 AH61 14 M_A_DQ35 M_A_DQ35 AW29 AL38 M_B_CLK1 15
M_A_DQ5 AH60 SA_DQ4 AU43 M_A_DQ36 AV31 SB_DQ3 SB_CK1
D
14 M_A_DQ5 SA_DQ5 SA_CKE0 M_A_CKE0 14 14 M_A_DQ36 SB_DQ4 D
14 M_A_DQ6 M_A_DQ6 AK61 AW43 M_A_CKE1 14 14 M_A_DQ37 M_A_DQ37 AU31 AY49 M_B_CKE0 15
M_A_DQ7 AK60 SA_DQ6 SA_CKE1 AY42 M_A_DQ38 AV29 SB_DQ5 SB_CKE0 AU50
14 M_A_DQ7 SA_DQ7 SA_CKE2 14 M_A_DQ38 SB_DQ6 SB_CKE1 M_B_CKE1 15
14 M_A_DQ8 M_A_DQ8 AM63 AY43 14 M_A_DQ39 M_A_DQ39 AU29 AW49
M_A_DQ9 AM62 SA_DQ8 SA_CKE3 M_A_DQ40 AY27 SB_DQ7 SB_CKE2 AV50
14 M_A_DQ9 SA_DQ9 14 M_A_DQ40 SB_DQ8 SB_CKE3
14 M_A_DQ10 M_A_DQ10 AP63 AP33 M_A_CS#0 14 14 M_A_DQ41 M_A_DQ41 AW27
M_A_DQ11 AP62 SA_DQ10 SA_CS#0 AR32 M_A_DQ42 AY25 SB_DQ9 AM32
14 M_A_DQ11 SA_DQ11 SA_CS#1 M_A_CS#1 14 14 M_A_DQ42 SB_DQ10 SB_CS#0 M_B_CS#0 15
14 M_A_DQ12 M_A_DQ12 AM61 14 M_A_DQ43 M_A_DQ43 AW25 AK32 M_B_CS#1 15
M_A_DQ13 AM60 SA_DQ12 AP32 M_A_DQ44 AV27 SB_DQ11 SB_CS#1
14 M_A_DQ13 SA_DQ13 SA_ODT0 TP38 14 M_A_DQ44 SB_DQ12
14 M_A_DQ14 M_A_DQ14 AP61 14 M_A_DQ45 M_A_DQ45 AU27 AL32 M_B_ODT0
SA_DQ14 SB_DQ13 SB_ODT0 TP39
14 M_A_DQ15 M_A_DQ15 AP60 AY34 M_A_RAS# 14 14 M_A_DQ46 M_A_DQ46 AV25
M_B_DQ0 AP58 SA_DQ15 SA_RAS AW34 M_A_DQ47 AU25 SB_DQ14 AM35
15 M_B_DQ0 SA_DQ16 SA_WE M_A_WE# 14 14 M_A_DQ47 SB_DQ15 SB_RAS M_B_RAS# 15
15 M_B_DQ1 M_B_DQ1 AR58 AU34 M_A_CAS# 14 15 M_B_DQ32 M_B_DQ32 AM29 AK35 M_B_WE# 15
M_B_DQ2 AM57 SA_DQ17 SA_CAS M_B_DQ33 AK29 SB_DQ16 SB_WE AM33
15 M_B_DQ2 SA_DQ18 15 M_B_DQ33 SB_DQ17 SB_CAS M_B_CAS# 15
15 M_B_DQ3 M_B_DQ3 AK57 AU35 M_A_BS#0 14 15 M_B_DQ34 M_B_DQ34 AL28
M_B_DQ4 AL58 SA_DQ19 SA_BA0 AV35 M_B_DQ35 AK28 SB_DQ18 AL35
15 M_B_DQ4 SA_DQ20 SA_BA1 M_A_BS#1 14 15 M_B_DQ35 SB_DQ19 SB_BA0 M_B_BS#0 15
15 M_B_DQ5 M_B_DQ5 AK58 AY41 M_A_BS#2 14 15 M_B_DQ36 M_B_DQ36 AR29 AM36 M_B_BS#1 15
M_B_DQ6 AR57 SA_DQ21 SA_BA2 M_B_DQ37 AN29 SB_DQ20 SB_BA1 AU49
15 M_B_DQ6 SA_DQ22 M_A_A[15:0] 14 15 M_B_DQ37 SB_DQ21 SB_BA2 M_B_BS#2 15
15 M_B_DQ7 M_B_DQ7 AN57 AU36 M_A_A0 15 M_B_DQ38 M_B_DQ38 AR28 M_B_A[15:0] 15
M_B_DQ8 AP55 SA_DQ23 SA_MA0 AY37 M_A_A1 M_B_DQ39 AP28 SB_DQ22 AP40 M_B_A0
15 M_B_DQ8 SA_DQ24 SA_MA1 15 M_B_DQ39 SB_DQ23 SB_MA0
15 M_B_DQ9 M_B_DQ9 AR55 AR38 M_A_A2 15 M_B_DQ40 M_B_DQ40 AN26 AR40 M_B_A1
M_B_DQ10 AM54 SA_DQ25 SA_MA2 AP36 M_A_A3 M_B_DQ41 AR26 SB_DQ24 SB_MA1 AP42 M_B_A2
15 M_B_DQ11 M_B_DQ11 AK54 AU39 M_A_A4 15 M_B_DQ42 M_B_DQ42 AR25 AR42 M_B_A3
M_B_DQ12 AL55 SA_DQ27 SA_MA4 AR36 M_A_A5 M_B_DQ43 AP25 SB_DQ26 SB_MA3 AR45 M_B_A4
15 M_B_DQ13 M_B_DQ13 AK55 AV40 M_A_A6 15 M_B_DQ44 M_B_DQ44 AK26 AP45 M_B_A5
M_B_DQ14 AR54 SA_DQ29 SA_MA6 AW39M_A_A7 M_B_DQ45 AM26 SB_DQ28 SB_MA5 AW46M_B_A6
15 M_B_DQ15 M_B_DQ15 AN54 DDR CHANNEL A AY39 M_A_A8 15 M_B_DQ46 M_B_DQ46 AK25 AY46 M_B_A7
M_A_DQ16 AY58 SA_DQ31 SA_MA8 AU40 M_A_A9 M_B_DQ47 AL25 SB_DQ30 SB_MA7 AY47 M_B_A8
14 M_A_DQ16 SA_DQ32 SA_MA9 15 M_B_DQ47 SB_DQ31 SB_MA8
14 M_A_DQ17 M_A_DQ17 AW58 AP35 M_A_A10 14 M_A_DQ48 M_A_DQ48 AY23 DDR CHANNEL B AU46 M_B_A9
M_A_DQ18 AY56 SA_DQ33 SA_MA10 AW41M_A_A11 M_A_DQ49 AW23 SB_DQ32 SB_MA9 AK36 M_B_A10
14 M_A_DQ18 SA_DQ34 SA_MA11 14 M_A_DQ49 SB_DQ33 SB_MA10
14 M_A_DQ19 M_A_DQ19 AW56 AU41 M_A_A12 14 M_A_DQ50 M_A_DQ50 AY21 AV47 M_B_A11
M_A_DQ20 AV58 SA_DQ35 SA_MA12 AR35 M_A_A13 M_A_DQ51 AW21 SB_DQ34 SB_MA11 AU47 M_B_A12
14 M_A_DQ21 M_A_DQ21 AU58 AV42 M_A_A14 14 M_A_DQ52 M_A_DQ52 AV23 AK33 M_B_A13
C M_A_DQ22 AV56 SA_DQ37 SA_MA14 AU42 M_A_A15 M_A_DQ53 AU23 SB_DQ36 SB_MA13 AR46 M_B_A14 C
14 M_A_DQ23 M_A_DQ23 AU56 14 M_A_DQ54 M_A_DQ54 AV21 AP46 M_B_A15
M_A_DQ24 AY54 SA_DQ39 AJ61 M_A_DQS#0 M_A_DQ55 AU21 SB_DQ38 SB_MA15
14 M_A_DQ24 SA_DQ40 SA_DQSN0 M_A_DQS#0 14 14 M_A_DQ55 SB_DQ39
14 M_A_DQ25 M_A_DQ25 AW54 AN62 M_A_DQS#1 M_A_DQS#1 14 14 M_A_DQ56 M_A_DQ56 AY19 AW30 M_A_DQS#4 M_A_DQS#4 14
M_A_DQ26 AY52 SA_DQ41 SA_DQSN1 AM58 M_B_DQS#0 M_A_DQ57 AW19 SB_DQ40 SB_DQSN0 AV26 M_A_DQS#5
14 M_A_DQ26 SA_DQ42 SA_DQSN2 M_B_DQS#0 15 14 M_A_DQ57 SB_DQ41 SB_DQSN1 M_A_DQS#5 14
14 M_A_DQ27 M_A_DQ27 AW52 AM55 M_B_DQS#1 M_B_DQS#1 15 14 M_A_DQ58 M_A_DQ58 AY17 AN28 M_B_DQS#4 M_B_DQS#4 15
M_A_DQ28 AV54 SA_DQ43 SA_DQSN3 AV57 M_A_DQS#2 M_A_DQ59 AW17 SB_DQ42 SB_DQSN2 AN25 M_B_DQS#5
14 M_A_DQ28 SA_DQ44 SA_DQSN4 M_A_DQS#2 14 14 M_A_DQ59 SB_DQ43 SB_DQSN3 M_B_DQS#5 15
14 M_A_DQ29 M_A_DQ29 AU54 AV53 M_A_DQS#3 M_A_DQS#3 14 14 M_A_DQ60 M_A_DQ60 AV19 AW22 M_A_DQS#6 M_A_DQS#6 14
M_A_DQ30 AV52 SA_DQ45 SA_DQSN5 AL43 M_B_DQS#2 M_A_DQ61 AU19 SB_DQ44 SB_DQSN4 AV18 M_A_DQS#7
14 M_A_DQ30 SA_DQ46 SA_DQSN6 M_B_DQS#2 15 14 M_A_DQ61 SB_DQ45 SB_DQSN5 M_A_DQS#7 14
14 M_A_DQ31 M_A_DQ31 AU52 AL48 M_B_DQS#3 M_B_DQS#3 15 14 M_A_DQ62 M_A_DQ62 AV17 AN21 M_B_DQS#6 M_B_DQS#6 15
M_B_DQ16 AK40 SA_DQ47 SA_DQSN7 M_A_DQ63 AU17 SB_DQ46 SB_DQSN6 AN18 M_B_DQS#7
15 M_B_DQ16 SA_DQ48 14 M_A_DQ63 SB_DQ47 SB_DQSN7 M_B_DQS#7 15
15 M_B_DQ17 M_B_DQ17 AK42 AJ62 M_A_DQS0 M_A_DQS0 14 15 M_B_DQ48 M_B_DQ48 AR21
M_B_DQ18 AM43 SA_DQ49 SA_DQSP0 AN61 M_A_DQS1 M_B_DQ49 AR22 SB_DQ48 AV30 M_A_DQS4
15 M_B_DQ18 SA_DQ50 SA_DQSP1 M_A_DQS1 14 15 M_B_DQ49 SB_DQ49 SB_DQSP0 M_A_DQS4 14
15 M_B_DQ19 M_B_DQ19 AM45 AN58 M_B_DQS0 M_B_DQS0 15 15 M_B_DQ50 M_B_DQ50 AL21 AW26 M_A_DQS5 M_A_DQS5 14
M_B_DQ20 AK45 SA_DQ51 SA_DQSP2 AN55 M_B_DQS1 M_B_DQ51 AM22 SB_DQ50 SB_DQSP1 AM28 M_B_DQS4
15 M_B_DQ20 SA_DQ52 SA_DQSP3 M_B_DQS1 15 15 M_B_DQ51 SB_DQ51 SB_DQSP2 M_B_DQS4 15
15 M_B_DQ21 M_B_DQ21 AK43 AW57 M_A_DQS2 M_A_DQS2 14 15 M_B_DQ52 M_B_DQ52 AN22 AM25 M_B_DQS5 M_B_DQS5 15
M_B_DQ22 AM40 SA_DQ53 SA_DQSP4 AW53 M_A_DQS3 M_B_DQ53 AP21 SB_DQ52 SB_DQSP3 AV22 M_A_DQS6
15 M_B_DQ22 SA_DQ54 SA_DQSP5 M_A_DQS3 14 15 M_B_DQ53 SB_DQ53 SB_DQSP4 M_A_DQS6 14
15 M_B_DQ23 M_B_DQ23 AM42 AL42 M_B_DQS2 M_B_DQS2 15 15 M_B_DQ54 M_B_DQ54 AK21 AW18 M_A_DQS7 M_A_DQS7 14
M_B_DQ24 AM46 SA_DQ55 SA_DQSP6 AL49 M_B_DQS3 M_B_DQ55 AK22 SB_DQ54 SB_DQSP5 AM21 M_B_DQS6
15 M_B_DQ24 SA_DQ56 SA_DQSP7 M_B_DQS3 15 15 M_B_DQ55 SB_DQ55 SB_DQSP6 M_B_DQS6 15
15 M_B_DQ25 M_B_DQ25 AK46 15 M_B_DQ56 M_B_DQ56 AN20 AM18 M_B_DQS7 M_B_DQS7 15
M_B_DQ26 AM49 SA_DQ57 AP49 M_B_DQ57 AR20 SB_DQ56 SB_DQSP7
15 M_B_DQ26 SA_DQ58 SM_VREF_CA +VREF_CA_CPU 15 M_B_DQ57 SB_DQ57
15 M_B_DQ27 M_B_DQ27 AK49 AR51 +VREFDQ_SA_M3 15 M_B_DQ58 M_B_DQ58 AK18
M_B_DQ28 AM48 SA_DQ59 SM_VREF_DQ0 AP51 M_B_DQ59 AL18 SB_DQ58
15 M_B_DQ28 SA_DQ60 SM_VREF_DQ1 +VREFDQ_SB_M3 15 M_B_DQ59 SB_DQ59
15 M_B_DQ29 M_B_DQ29 AK48 15 M_B_DQ60 M_B_DQ60 AK20
M_B_DQ30 AM51 SA_DQ61 M_B_DQ61 AM20 SB_DQ60
15 M_B_DQ30 SA_DQ62 15 M_B_DQ61 SB_DQ61
15 M_B_DQ31 M_B_DQ31 AK51 15 M_B_DQ62 M_B_DQ62 AR18
SA_DQ63 M_B_DQ63 AP18 SB_DQ62
15 M_B_DQ63 SB_DQ63
B B
3 OF 19 4 OF 19
A A

PROJECT : ZYW
3A
Haswell 2/5 (DDR3 I/F)
5 4 3 2 1
5 4 3 2 1
04
H_PECI (50ohm)
Haswell ULT (SIDEBAND)
Route on microstrip only
D
Spacing >18 mils D
Trace Length: 0.4~6.125 iches
H_PWRGOOD (50ohm)
Trace Length: 1~11.25 inches HSW_ULT_DDR3L
U33B
CPU_PLTRST# (50ohm)
Trace Length: 10~17 inches PROC_DETECT D61
TP111 PROC_DETECT
CATERR# K61 MISC
TP118 N62 CATERR J62
33 H_PECI H_PECI XDP_PRDY#
PECI PRDY K62 TP151
XDP_PREQ#
PREQ TP152
E60 XDP_TCK0 TCK,TMS
PROC_TCK E61 XDP_TCK0 8,13
XDP_TMS_CPU Trace Length < 9000mils
JTAG PROC_TMS TP157
33,34,38 H_PROCHOT# H_PROCHOT# R670 56_4 H_PROCHOT#_R K63 E59 XDP_TRST#
PROCHOT THERMAL
PROC_TRST F63 XDP_TDI_CPU XDP_TRST# 8,13
PROC_TDI F62 TP156
XDP_TDO_CPU
PROC_TDO XDP_TDO_CPU 13
H_PWRGOOD_R C61
PROCPWRGD PWR
J60 XDP_BPM#0
BPM#0 H60 TP149
XDP_BPM#1
BPM#1 TP150
SM_RCOMP[0:2] H61 XDP_BPM#2 BPM#[0:7]
BPM#2 H62 TP122
Trace length < 500 mils XDP_BPM#3 Trace Length 1~6 inches
BPM#3 TP129
SM_RCOMP_0 AU60 K59 XDP_BPM#4
Trace width = 12~15 mils SM_RCOMP_1 AV60 SM_RCOMP0 DDR3L BPM#4 H63 XDP_BPM#5
TP54 Length match < 300 mils
C
Trace spacing = 20 mils SM_RCOMP_2 AU61 SM_RCOMP1 BPM#5 K60 XDP_BPM#6
TP117
C
SM_RCOMP2 BPM#6 TP113
CPU_DRAMRST# AV15 DSW J61 XDP_BPM#7
AV61 SM_DRAMRST BPM#7 TP60
DDR_PG_CTRL
SM_PG_CNTL1
2 OF 19
B B
DRAM COMP XDP PU/PD DDR3L ODT GENERATION +1.35V_SUS

+1.05V_VCCST
R295 200/F_4 SM_RCOMP_0 +5V_S5 +3VSUS U12
XDP_TDO_CPU R657 51_4
5 1
VCC NC
1
R296 120/F_4 SM_RCOMP_1
1
XDP_TCK0 R312 51_4 R273 R777 C268
XDP_TRST# R680 *51_4 2 R267 *short_4 DDR_PG_CTRL
R297 100/F_4 SM_RCOMP_2 220K/F_4 *220K/F_4 0.1u/10V_4 A
2
2
2
4 3
37 DDR_VTTT_PG_CTRL Y GND
+1.35V_SUS 74AUP1G07GW
PU/PD of CPU DRAMRST
3
+1.35V_SUS R286 66.5/F_4
+VCCIO_OUT M_A_ODT0_DIMM 14
2 Q24
2N7002K R284 66.5/F_4 M_A_ODT1_DIMM 14
1
H_PROCHOT# R671 *62_4

R251 R626 66.5/F_4 M_B_ODT0_DIMM 15
+1.05V_VCCST 470_4
1
A R621 66.5/F_4 A
M_B_ODT1_DIMM 15
R672 62_4
CPU DRAM
2
CPU_DRAMRST# R252 *short_4 DDR3_DRAMRST# 14,15

1
H_PWRGOOD_R R647 10K_4 C249

*0.1u/10V_4
PROJECT : ZYW
2

3A
Haswell 1/5 (PEG/DMI/FDI)
5 4 3 2 1
5 4 3 2 1
VCCST PWRGD
+1.05V_VCCST
CRB is via +1.05V PG
+3V_S5
5
U16
1
05
VCC NC
C367
R342 0.1u/10V_4 2 VCCST_PWRGD_EN
10K_4 A
D
+1.35V_SUS R292 *short_8 Haswell ULT (POWER) VCCST_PWRGD R338 VCCST_PWRGD_R
*short_4 4
Y GND
3 D
C383 74AUP1G07GW
R294 *short_8 *0.1u/10V_4
+ C588
*470u/2V_7343 R337 *0_4 HWPG_1.05V_EC
3
HSW_ULT_DDR3L
U33L
+1.35V_CPU 1.4A +VCCIN 32A Q32 Reserve from EC
TP120 ULT_RVSD_61 L59 C36 74AUP1G07GW
RSVD VCC +VCC_CORE
+1.35V_CPU TP44 ULT_RVSD_62 J58 C40 B-stage DNP 2 HWPG_1.05V_EC# 33
RSVD VCC C44
VCC A Y
AH26 C48 C287 C297 C336 C340 C330 C315
C304 C305 C320 C303 C325 C284 AJ31 VDDQ VCC C52 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 *2N7002K
VDDQ VCC L L
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 AJ33 C56
1
AJ37 VDDQ VCC E23
VDDQ VCC H Z
AN33 E25
AP43 VDDQ VCC E27
AR48 VDDQ VCC E29 R356 *short_4
VDDQ VCC PCH_PWROK 7,33
+ AY35 E31 VCCST_PWRGD_EN R355 *0_4
VDDQ VCC EC_PWROK 7,33
C293 C301 C312 C306 C292 AY40 E33 C317 C314 C288 C327 C342 C341
*470u/2V_7343 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 AY44 VDDQ VCC E35 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 1A-6 2013/10/21 Del APWORK.
AY50 VDDQ VCC E37
VDDQ VCC E39
F59 VCC E41
ZYW +VCC_CORE
TP63 ULT_RVSD_63 N58 VCC VCC E43
R666 100/F_4 ULT_RVSD_64 AC58 RSVD VCC E45
+VCC_CORE TP45 RSVD VCC
C E47 C
R674 *short_4 VCC_SENSE_R E63 VCC E49 C289 C279 C299 C329 C592 C278
38 VCC_SENSE VCC_SENSE VCC
TP33 ULT_RVSD_65 AB23 E51 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8
A59 RSVD VCC E53
300mA +VCCIO_OUT VCCIO_OUT VCC
300mA E20 E55 +1.05V +VCCIO_OUT
+VCCIOA_OUT VCCIOA_OUT VCC
TP32 ULT_RVSD_66 AD23 E57
ULT_RVSD_67 AA23 RSVD VCC F24 R318 *0_8
TP35 RSVD VCC
TP69 ULT_RVSD_68 AE59 F28
R645 *10K_4 RSVD VCC F32
+1.05V_VCCST VCC
H_CPU_SVIDART# L62 F36 C339 C298 C345 C280 C328 C286 C359
VRON_CPU R646 10K_4 IMVP_PWRGD H_CPU_SVIDCLK N63 VIDALERT HSW ULT POWER VCC F40 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 *4.7u/6.3V_6
H_CPU_SVIDDAT L63 VIDSCLK VCC F44
VCCST_PWRGD B59 VIDSOUT VCC F48
13 VCCST_PWRGD F60 VCCST_PWRGD VCC F52
VRON_CPU
38 VRON_CPU IMVP_PWRGD C59 VR_EN VCC F56
10,38 IMVP_PWRGD VR_READY VCC G23
D63 VCC G25
PWR_DEBUG_R H59 VSS VCC G27 C333 C338 C316 C331 C324 C296
P62 PWR_DEBUG VCC G29 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8
R313 150_6 ULT_RVSD_69 P60 VSS VCC G31
+1.05V_VCCST TP50 RSVD_TP VCC
ULT_RVSD_70 P61 G33
TP51
ULT_RVSD_71 N59 RSVD_TP VCC G35 SVID Layout note: need routing together
TP52
TP57 ULT_RVSD_72 N61 RSVD_TP VCC G37 ZYW and ALERT need between CLK and DATA.
ULT_RVSD_73 T59 RSVD_TP VCC G39
TP64 RSVD VCC
TP67 ULT_RVSD_74 AD60 G41
ULT_RVSD_75 AD59 RSVD VCC G43 +VCCIO_OUT +1.05V_VCCST
TP43 RSVD VCC VCC Output Decoupling Recommendations
TP53 ULT_RVSD_76 AA59 G45
ULT_RVSD_77 AE60 RSVD VCC G47
TP68 RSVD VCC 470uFx4 7343 TOP socket side
B TP61 ULT_RVSD_78 AC59 G49 B
ULT_RVSD_79 AG58 RSVD VCC G51
TP47 RSVD VCC 22uFx8 0805 4 on TOP, 4 on BOT near socket edge
TP59 ULT_RVSD_80 U59 G53 R682 R681
ULT_RVSD_81 V59 RSVD VCC G55 *130/F_4 130/F_4
TP49 RSVD VCC 22uFx11 0805 TOP, inside socket cavity
G57
AC22 VCC H23 H_CPU_SVIDDAT R683 *short_4
VCCST VCC 10uFx11 0805 BOT, inside socket cavity VR_SVID_DATA 38
+1.05V +1.05V_VCCST AE22 J23
AE23 VCCST VCC K23
+1.05V_VCCST VCCST VCC Place PU resistor
R265 *short_8 K57 close to CPU
AB57 VCC L22 +1.05V_VCCST +VCCIO_OUT
AD57 VCC VCC M23
C272 AG57 VCC VCC M57
*4.7u/6.3V_6 C24 VCC VCC P57
C28 VCC VCC U57
VCC VCC Place PU resistor
C32 W57 close to CPU R689 R684
+VCC_CORE VCC VCC 75_4 *75_4
12 OF 19
H_CPU_SVIDART# R673 43_4 VR_SVID_ALERT# 38
+3V
HWPG_1.05V for DDR=1.5V
H_CPU_SVIDCLK R685 *short_4 VR_SVID_CLK 38
+3V
R320
*4.7K_4
A A
R328
HWPG_1.05V 33
*4.7K_4
3
3
R321
R340 *4.7K_4 2 2 *100K/F_4
+1.05V
Q34
1
C378 *MMBT3904-7-F C369 Q30

PROJECT : ZYW
1
*1000p/50V_4 *1000p/50V_4 *DTC144EU

10/30 reserve Size Document Number Rev
DDR=1.5V ,This block POP Haswell 4/5 (POWER) 3A

5 4 3 2 1
5 4 3 2 1
Haswell ULT (CFG,RSVD)

U33S HSW_ULT_DDR3L
06
D CFG0 AC60 AV63 D
13 CFG0 CFG0 RSVD_TP
CFG1 AC62 AU63
AC63
CFG3 AA63 CFG2
13 CFG3 CFG3
CFG4 AA60 C63
8,13 CFG4 CFG4 RSVD_TP
Y62 C62
Y61 CFG5 RSVD_TP B43
Y60 CFG6 RSVD
CFG8 V62 CFG7 A51
CFG9 V61 B51
13 CFG10 CFG10 V60
U60 CFG10 L60
T63 CFG11 RSVD_TP
T62 CFG12 RESERVED N60
T61 CFG13 RSVD
T60 CFG14 W23
CFG15 RSVD Y22
AA62 RSVD AY15 OPI_COMP1 R599 49.9/F_4
U63 CFG16 PROC_OPI_RCOMP
AA61 CFG18 AV62
U62 CFG17 RSVD D58
CFG19 RSVD
R660 49.9/F_4 CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
C VSS C
REFPKG_OCC A5
TP97 RSVD P20
E1 RSVD R20
D1 RSVD RSVD
J20 RSVD
H18 RSVD
R597 8.2K_4 TD_IREF B12 RSVD
TD_IREF
19 OF 19
Processor Strapping
1 0
CFG0 CFG0
(DEFAULT) NORMAL OPERATION; NO STALL STALL R306 *1K_4
EAR-STALL/NOT STALL RESET SEQUENCE
AFTER PCU PLL IS LOCKED
CFG1 CFG1
(DEFAULT) NORMAL OPERATION PCH-LESS MODE R688 *1K_4
PCH/ PCH LESS MODE SELECTION
B B
CFG3 DISABLED ENABLED CFG3 R687 *1K_4

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY) NO PHYSICAL DISPLAY PORT ATTACHED AN EXTERNAL DISPLAY PORT DEVICE IS
TO CONNECTED
EMBEDDED DISPLAY PORT TO THE EMBEDDED DISPLAY PORT
CFG 8 DISABLED(DEFAULT); IN THIS CASE, NOA ENABLED; NOA WILL BE AVAILABLE

ALLOW THE USE OF NOA ON LOCKED UNITS WILL BE DISABLED IN LOCKED UNITS AND REGARDLESS OF THE LOCKING OF THE UNIT CFG8 R686 *1K_4
ENABLED IN UN-LOCKED UNITS
CFG9 NO VR SUPPORTING SVID IS PRESENT. THE CFG9

VRS SUPPORTING SVID PROTOCOL ARE R676 *1K_4
NO SVID PROTOCOL CAPABLE VR CHIP WILL NOT GENERATE (OR RESPOND TO)
CONNECTED PRESENT SVID ACTIVITY
A A
CFG10 POWER FEATURES ACTIVATED POWER FEATURES (ESPECIALLY CLOCK
CFG10 R307 *1K_4
SAFE MODE BOOT DURING RESET GATINE ARE NOT ACTIVATED
PROJECT : ZYW
3A
Haswell 5/5 (CFG/GND)
5 4 3 2 1
5 4 3 2 1
Haswell ULT PCH (PM)

33
13
PCH_SUSACK#
SYS_RESET#
PCH_SUSPWRACK R513
R514 *0_4
*0_4 SUSACK#_R
SYS_RESET#
AK2
U33H HSW_ULT_DDR3L
SYSTEM POWER MANAGEMENT
AW7 DSWVREN
Deep Sx
DSWVREN 8
07
C545 *1u/6.3V_4 AC3 SUSACK DSWVRMEN AV5 DPWROK_R R207 *0_4
SYS_RESET DPWROK DPWROK 33
SYS_PWROK R516 *short_4 SYS_PWROK_R AG2 DSW AJ5 PCIE_LAN_WAKE# PCIE_LAN_WAKE# 27,29
R508 *0_4 R498 *0_4 EC_PWROK_R AY7 SYS_PWROK WAKE
D D
EC_PWROK R517 *0_4 R497 *0_4 APWROK_R AB5 PCH_PWROK
PCI_PLTRST# AG7 APWROK V5 CLKRUN#
PLTRST +3V_S5 +3V CLKRUN/GPIO32 AG4 LPCPD#
CLKRUN# 23,33
+3V_S5 SUS_STAT/GPIO61 LPCPD# 23
+3V_S5 AE6 PCH_SUSCLK PCH_SUSCLK 27
SUSCLK/GPIO62 AP5
DSW SLP_S5/GPIO63
33 RSMRST# R209 *short_4 PCH_RSMRST# AW6
R499 *short_4 PCH_SUSPWRACK AV4 RSMRST
33 PCH_SUSPWARN# SUSWARN/SUSPWRDNACK/GPIO30 +3V_S5
33 DNBSWON# R139 *short_4 PCH_PWRBTN# AL7 DSW DSW AJ6 SUSC# SUSC# 13,33
R175 *short_4 PCH_ACPRESENT AJ8 PWRBTN SLP_S4 AT4 SUSB#
34 ACPRESENT
PCH_BATLOW# AN4 ACPRESENT/GPIO31 DSW DSW SLP_S3 AL5
SUSB# 13,33
BATLOW/GPIO72 DSW DSW SLP_A
PCH_SLP_S0#_R AF3 +3V_S5 DSW AP4 PCH_SLP_SUS#
TP93 SLP_S0 SLP_SUS PCH_SLP_SUS# 33
PCH_SLP_WLAN# AM5 DSW DSW AJ7 PCH_SLP_LAN#
TP91 SLP_WLAN/GPIO29 SLP_LAN TP25
+3V_S5
8 OF 19
LPCPD# R553 *10K_4
C C
Power Sequence R486 *short_4 APWROK_R
33 APWORK
5,33 PCH_PWROK R217 *short_4 EC_PWROK_R
EC_PWROK R537 *0_4 SYS_PWROK_R

R211 Speed up 250ms to boot up R489
100K_4
RSMRST# R205 0_4 DPWROK_R for EC power on 250 ms 10K_4
Non Deep Sx
PCH PM PU/PD PLTRST# Buffer Deep Sx Circuit Non Deep Sx

+3V +3V
R335 0_6
C185 0.1u/10V_4
CLKRUN# R172 8.2K_4 +3V_S5 +3VCC_S5
5
SYS_RESET# R533 10K_4

2 1 3
4 PLTRST# 13,16,23,27,29,30,33
B PCI_PLTRST# 1 R330 Q33 B
PCH_RSMRST# R210 10K_4 C375 *100K_4 *AO3413
2
SYS_PWROK R509 *10K_4 U9 *0.33u/10V_6
3
DPWROK_R R204 100K/F_4 TC7SH08FU R130

100K_4
R327
*0_6
+3V_S5
3
PCH_SUSPWRACK R490 *10K_4
SYSPWOK
+3V_S5 PCH_SLP_SUS# 2
+3V_S5 C381 *0.1u/10V_4 Q31

*2N7002K
PCH_ACPRESENT R191 10K_4
1
5
PCH_BATLOW# R536 8.2K_4

PCIE_LAN_WAKE# R133 1K_4 2 EC_PWROK EC_PWROK 5,33
PCH_PWRBTN# R142 *10K_4 DSW PU 13 SYS_PWROK SYS_PWROK 4
1 IMVP_PWRGD_3V 10
A +3VPCU A
U18
3
R176 *10K_4 TC7SH08FU R350

R520
R156
*8.2K_4
*1K_4 R345 *0_4
10K_4 Quanta Computer Inc.
R143 *10K_4
PROJECT : ZYW
3A
LPT 1/6 (DMI/FDI/VGA)
5 4 3 2 1
5 4 3 2 1
RTC Clock 32.768KHz (RTC)
08
C196 15p/50V_4 RTC_X1
Haswell ULT PCH (RTC/HDA/SATA/SPI)
1
Y8 R197
Haswell ULT PCH(LPC,SPI,SMBUS,C-LINK,THERMAL)
32.768KHZ 10M_4
U33E HSW_ULT_DDR3L
C195 15p/50V_4 RTC_X2
2
RTC_X1 AW5
RTC_X2 AY5 RTCX1
R218 1M_4 SM_INTRUDER# AU6 RTCX2 J5 SATA_RXN_1ST_HDD# U33G HSW_ULT_DDR3L
RTC Circuitry (RTC) +3V_RTC
+3V_RTC
PCH_INTVRMEN AV7 INTRUDER SATA_RN0/PERN6_L3 H5 SATA_RXP_1ST_HDD
SATA_RXN_1ST_HDD# 28
28 HDD1
D INTVRMEN SATA_RP0/PERP6_L3 SATA_RXP_1ST_HDD D
SRTC_RST# AV6 RTC B15 SATA_TXN_1ST_HDD# AU14 +3V_S5 SMBALERT/GPIO11 AN2 SMBALERT#
D10 +3V_RTC
Trace width = 30 mils RTC_RST# AU7 SRTCRST SATA_TN0/PETN6_L3 A15 SATA_TXP_1ST_HDD
SATA_TXN_1ST_HDD# 28 23,27,33 LPC_LAD0
AW12 LAD0 AP2 SMB_PCH_CLK
13 RTC_RST# RTCRST SATA_TP0/PETP6_L3 SATA_TXP_1ST_HDD 28 23,27,33 LPC_LAD1 LAD1 +3V_S5 SMBCLK
+3VPCU R182 *short_6 +3V_RTC_2 R165 23,27,33 LPC_LAD2
AY12 LPC +3V_S5 AH1 SMB_PCH_DAT
RTC_RST# J8 SATA_RXN_ODD# AW11 LAD2 SMBUS SMBDATA AL2 SMB0ALERT#
SATA_RN1/PERN6_L2 SATA_RXN_ODD# 28 23,27,33 LPC_LAD3 LAD3 +3V_S5SML0ALERT/GPIO60
R181 1K_4 +3V_RTC_1 H8 SATA_RXP_ODD AV12 +3V_S5 AN1 VGA_MBCLK
VCCRTC_2 SATA_RXP_ODD 28 23,27,33 LPC_LFRAME#
1
20K/F_4 SATA_RP1/PERP6_L2 A17 SATA_TXN_ODD# LFRAME SML0CLK AK1 VGA_MBDATA
SATA_TN1/PETN6_L2 SATA_TXN_ODD# 28 ODD +3V_S5 SML0DATA
BAT54C B17 SATA_TXP_ODD 28 +3V_S5 AU4 SMB1ALERT#
SATA_TP1/PETP6_L2 SATA_TXP_ODD SML1ALERT/PCHHOT/GPIO73
C193 J7 +3V_S5 AU3 SMB_ME1_CLK
1u/6.3V_4 *JUMP HDA_BCLK_R AW8 J6 SATA_RXN_PERN6_L1# SML1CLK/GPIO75 AH3 SMB_ME1_DAT
+3V_RTC_[0:2] 27 +3V_S5
2
HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 SATA_RXN_PERN6_L1# SML1DATA/GPIO74
HDA_SYNC_R AV11 SATA2 PCIE6_L1 H6 SATA_RXP_PERP6_L1 PCH_SPI_CLK AA3
Trace width = 20 mils SATA_RXP_PERP6_L1 27
1
R164 HDA_RST#_R AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14 SATA_TXN_PETN6_L1# PCH_SPI_CS0# Y7 SPI_CLK AF2 CL_CLK
HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 SATA_TXN_PETN6_L1# 27 NGFF PCIE6_L1 SPI_CS0 CL_CLK TP86
BT6 SRTC_RST# 31 PCH_AZ_CODEC_SDIN0 AY10 AUDIO SATA C15 SATA_TXP_PETP6_L1 27 PCH_SPI_CS1# Y4 AD2 CL_DAT
HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1 SATA_TXP_PETP6_L1 SPI_CS1 CL_DATA TP89
BAT_CONN AU12 AC2 SPI C-LINK AF4 CL_RST#
TP26
1
20K/F_4 HDA_SDO_R AU11 HDA_SDI1/I2S1_RXD F5 SATA_RXN_1ST_SSD# PCH_SPI_SI AA2 SPI_CS2 CL_RST
27
2
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 SATA_RXN_1ST_SSD# SPI_MOSI

RTC CR2032 Coin Battery AW10 E5 SATA_RXP_1ST_SSD 27 PCH_SPI_SO AA4
HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 SATA_RXP_1ST_SSD SPI_MISO
C188 C187 J6 AV10 SATA3 PCIE6_L0 C17 SATA_TXN_1ST_SSD# PCH_SPI_IO2 Y6
DBV: AHL03003057 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 SATA_TXN_1ST_SSD# 27 SSD/NGFF PCIE6_L0 SPI_IO2
VDE: AHL03003003 1u/6.3V_4 1u/6.3V_4 *JUMP AY8 D17 SATA_TXP_1ST_SSD 27 PCH_SPI_IO3 AF1
SATA_TXP_1ST_SSD
2
I2S1_SCLK SATA_TP3/PETP6_L0 SPI_IO3
+3V V1 VGPU_EN 7 OF 19
SATA0GP/GPIO34 VGPU_EN 40
+3V U1 ODD_PRSNT# ODD_PRSNT# 28
SATA1GP/GPIO35 V6 SSD_SATA2GP SSD_SATA2GP
HDA31 +3V SATA2GP/GPIO36
R245 33_4 HDA_RST#_R +3V AC1 SSD_SATA3GP SSD_SATA3GP R534 NF@0_4
PCH_AZ_CODEC_RST# SATA3GP/GPIO37 SSD_SATA3GP 27
AU62
4,13 XDP_TRST# PCH_TRST
31 PCH_AZ_CODEC_SDOUT R234 33_4 HDA_SDO_R 13 XDP_TCK1 XDP_TCK1 AE62 A12 SATA_IREF R595 *short_4 +V1.05S_ASATA3PLL +3V
XDP_TDI AD61 PCH_TCK SATA_IREF L11
31 PCH_AZ_CODEC_BITCLK R231 33_4 HDA_BCLK_R
13 XDP_TDI
TP153
PCH_JTAG_TDOAE61 PCH_TDI RSVD K10 R199 *10K_4 SSD_SATA2GP R186 *10K_4 SMBus +3V_S5
AD62 PCH_TDO JTAG
RSVD C12 SATA_RCOMP R596 3.01K/F_4 R566 *10K_4 SSD_SATA3GP R552 *10K_4
13 XDP_TMS PCH_TMS SATA_RCOMP +V1.05S_ASATA3PLL
AL11 U3 SATA_LED# R563 10K_4 R530 IV@10K_4 VGPU_EN R529 EV@10K_4
RSVD SATALED +3V
C C227 AC4 R569 10K_4 SMB0ALERT# C
*10p/50V_4 R695 *short_4 PCH_JTAGX AE63 RSVD R161 10K_4 SMB1ALERT#
4,13 XDP_TCK0 JTAGX SATA2GP= H ; HSIO12= SATA2
PCH_EDM AV2 SATA_RCOMP R144 10K_4 SMBALERT#
TP87 RSVD SATA2GP= L ; HSIO12= PCIE6 L1
Impedance = 50 ohm
R247 33_4 HDA_SYNC_R Trace length < 500 mils SATA3GP= H ; HSIO11= SATA3
31 PCH_AZ_CODEC_SYNC
Trace spacing = 15 mils SATA3GP= L ; HSIO11= PCIE6 L0 R121 2.2K_4 SMB_PCH_CLK
C242 *10p/50V_4 5 OF 19 R114 2.2K_4 SMB_PCH_DAT
R556 2.2K_4 VGA_MBDATA
8M@ 15ohm CS01502JB12 R538 2.2K_4 VGA_MBCLK
PCH SPI ROM(8M) 4M@ 33ohm CS03302JB29
8M@4M@ 15ohm (when one SPI device)
PCH JTAG 8M@4M@ 33ohm (when two SPI device)
JTAG_TCK,JTAG_TMS MP remove(Intel) +3V_S5 R157 *short_6 +3V_PCH_ME +3V_PCH_ME +3V
Trace Length < 9000mils
+1.05V_S5 U32 C190 0.1u/10V_4
PCH_SPI_CS0# 1 8
XDP_TMS R691 51_4 CS# VCC
XDP_TDI R677 51_4
AKE3EFP0N07 Winbond W25Q64FVSSIQ PCH_SPI_SO R507 8M@4M@15_4 2 7 SPI_HOLD_IO3_ME R510 1K_4 R123 R113
PCH_JTAG_TDO
PCH_JTAGX
R679
R678
51_4
*1K_4
PCH_SPI_SO_EC R518 8M@4M@15_4 IO1/DO IO3/HOLD#
6 R491 8M@4M@15_4 PCH_SPI_CLK
SMBus(PCH) Q18
4.7K_4 4.7K_4
AKE3EZN0Q01 EON EN25QH64-104HIP R492 1K_4 SPI_WP_IO2_ME 3 CLK 5
+3V_PCH_ME IO2/WP#
XDP_TCK1 R693 *51_4 5 R478 8M@4M@15_4 PCH_SPI_SI
4 IO0/DI SMB_PCH_DAT 3 4
AKE3EGN0Q01 GD GD25B64BSIGR GND CLK_SDATA 13,14,15,27
W25Q64FW -- 8MB C535 2

PCH_SPI_CLK_EC R496 8M@4M@15_4 *22p/50V_4
B B
PCH_SPI_SI_EC R463 8M@4M@15_4 SMB_PCH_CLK 6 1
ULT Strapping Table CLK_SCLK 13,14,15,27
Pin Name Strap description Sampled Configuration note PCH/S5 2N7002DW DDR_TP_XDP_WL/S0
0 = Default enable (iPD 20K) PCH_SPI_IO2 R483 8M@4M@15_4 SPI_WP_IO2_ME
GPIO81(SPKR) No reboot on TCO Timer PWROK +3V R549 *1K_4 SPKR SPKR 10,31 3.3K is original and for no R482 *4M@33_4 SPI_WP_IO2_EC
expiration 1 =Disable No-Reboot mode support fast read function PCH_SPI_IO3 R511 8M@4M@15_4 SPI_HOLD_IO3_ME
reserve for SPI fast read
0 = Default can program ME (iPD 20K) R477 *4M@33_4 SPI_HOLD_IO3_EC
+3V_PCH_ME
SMBus(EC) +3V_S5
HDA_SDO Flash Descriptor Security PWROK HDA_SDO_R R233 *short_4
ME_WR# 33
Override / Intel ME Debug Mode 1 =can't program ME U30
PCH_SPI_CS1# 1 8
PCH_SPI_CLK R468 *4M@33_4 6 CE# VDD
R228 330K_4 PCH_INTVRMEN R227 *330K_4 PCH_SPI_SI R464 *4M@33_4 5 SCK R119 R129
INTVRMEN Integrated 1.05V VRM enable ALWAYS 1=Should be always pull-up +3V_RTC
PCH_SPI_SO R467 *4M@33_4 2 SI 7SPI_HOLD_IO3_EC R474 *1K_4 *2.2K_4 *2.2K_4
SO HOLD# Q19
C531 *22p/50V_4 3 4 5
0 = Default disable (iPD 20K) 10 GPIO66
PCH_SPI_CLK_R WP# VSS C532
GPIO66 Top-Block Swap override R147 *1K_4 GPIO66 R162 *1K_4 PCH_SPI_SI_R *4M@ROM-4M_EC *4M@0.1u/10V_4 3 4 SMB_ME1_CLK
1 = Enable TBS function +3V
PCH_SPI_SO_R
19,24,33 2ND_MBCLK
0 = Default SPI (iPD 20K) 10 GPIO86

2
GPIO86 Boot BIOS Strap Bit R128 *1K_4 GPIO86 R136 *1K_4 R480 *1K_4 SPI_WP_IO2_EC
1 =LPC +3V +3V_PCH_ME
6 1 SMB_ME1_DAT
19,24,33 2ND_MBDATA
0 = Default enable w/o
1A-3 2013/10/16 Add U34 flash 4M ROM reserve for ZQ0D.
confidentiality(iPD 20K)
10 GPIO15
EC/S5 *2N7002DW PCH/S5
GPIO15 TLS(Transport layer security) R188 8.2K_4 GPIO15 R202 *1K_4 R465 *4M@33_4 PCH_SPI_CLK_R
A 1 =Default enable with +3V_S5 33 PCH_SPI_CLK_EC
R462 *4M@33_4 PCH_SPI_SI_R 2ND_MBCLK R125 *short_4 SMB_ME1_CLK
A
confidentiality 33 PCH_SPI_SI_EC
R469 *4M@33_4 PCH_SPI_SO_R 2ND_MBDATA R122 *short_4 SMB_ME1_DAT
33 PCH_SPI_SO_EC
0 = Enable an external display

CFG4 port is connected to the eDP CFG4 R690 1K_4 R473 8M@0_4 PCH_SPI_CS0#
DP presence strap
1 =disable
6,13 CFG4 33 SPI_CS0#_UR_ME
R476 *4M@0_4 PCH_SPI_CS1# Quanta Computer Inc.
only 0ohm option PROJECT : ZYW
7 DSWVREN
DSWVREN Deep Sx well on die VR enable 1=Should be always pull-up +3V_PCH_ME Size Document Number Rev
R226 330K_4 DSWVREN R225 *330K_4 3A
+3V_RTC
R475 10K_4 SPI_CS0#_UR_ME
LPT 2/6 (SATA/HDA/SPI)
5 4 3 2 1
5 4 3 2 1
Haswell ULT PCH (PCIE,USB3.0,USB2.0) Haswell ULT PCH (CLOCK) XTAL24_IN C570 12p/50V_4
09
3
4
U33K HSW_ULT_DDR3L R605 Y11
1M_4 24MHz
16 PEG_RX#0
F10 DSW AN8 USBP0- 30
1
2
E10 PERN5_L0 USB2N0 AM8 USBP0-
16 PEG_RX0 DSW USBP0+ 30 M/B side
PERP5_L0 USB2P0 USBP0+
D XTAL24_OUT D
16 PEG_TX#0 C567 EV@0.22u/10V_4 C_PEG_TX#3 C23 DSW AR7 USBP1- 30 C574 12p/50V_4
PETN5_L0 USB2N1 USBP1- HSW_ULT_DDR3L
16 PEG_TX0 C566 EV@0.22u/10V_4 C_PEG_TX3 C22 DSW AT7 USBP1+ 30 M/B side U33F
PETP5_L0 USB2P1 USBP1+
16 PEG_RX#1
F8 DSW AR8 USBP6- 30
PERN5_L1 USB2N2 USBP6-
16 PEG_RX1 E8 DSW AP8 USBP6 30 D/B side
PERP5_L1 USB2P2 USBP6
PEG x4
16 PEG_TX#1 C569 EV@0.22u/10V_4 C_PEG_TX#2 B23 DSW AR10 USBP7- 30 TP104 CLK_PCIE_N0 C43 A25 XTAL24_IN
PETN5_L1 USB2N3 USBP7- CLKOUT_PCIE_N0 XTAL24_IN
16 PEG_TX1 C568 EV@0.22u/10V_4 C_PEG_TX2 A23 DSW AT10 USBP7 30 D/B side TP105 CLK_PCIE_P0 C42 B25 XTAL24_OUT
PETP5_L1 USB2P3 USBP7 CLKOUT_PCIE_P0 XTAL24_OUT
TP90 CLK_PCIE_REQ0# U2 +3V
H10 AM15 USBP10_WLAN# PCIECLKRQ0/GPIO18 K21
16 PEG_RX#2 PERN5_L2 DSW USB2N4 USBP10_WLAN# 27 RSVD
16 PEG_RX2 G10 DSW AL15 USBP10_WLAN mini card B41 M21
PERP5_L2 USB2P4 USBP10_WLAN 27 CLKOUT_PCIE_N1 RSVD
A41 C26 ICLK_BIAS R278 3.01K/F_4 +V1.05S_AXCK_LCPLL
C563 EV@0.22u/10V_4 C_PEG_TX#1 B21 AM13 USB_TOUCH# CLK_PCIE_REQ1# Y5 CLKOUT_PCIE_P1 DIFFCLK_BIASREF
16 PEG_TX#2 PETN5_L2 DSW USB2N5 USB_TOUCH# 25 TP24 PCIECLKRQ1/GPIO19 +3V
16 PEG_TX2 C562 EV@0.22u/10V_4 C_PEG_TX1 C21 DSW AN13 USB_TOUCH 25 T/S C35 TESTLOW_C35
PETP5_L2 USB2P5 USB_TOUCH C41 CLOCK TESTLOW_C35 C34
CLK_PCIE_LAN#_R TESTLOW_C34
NGFF VGA WLAN LAN

29 CLK_PCIE_LAN# CLKOUT_PCIE_N2 TESTLOW_C34
16 PEG_RX#3 E6 DSW AP11 USB_CCD# 25 29 CLK_PCIE_LAN_R B42 AK8 TESTLOW_AK8
PERN5_L3 USB2N6 USB_CCD# CLK_PCIE_LAN CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8
16 PEG_RX3 F6 DSW AN11 USB_CCD 25 CCD 29 PCIE_REQ_LAN# AD1 +3V AL8 TESTLOW_AL8
PERP5_L3 USB2P6 USB_CCD PCIE_REQ_LAN# PCIECLKRQ2/GPIO20 TESTLOW_AL8 TPM@22_4 R208 PCLK_TPM 23
16 PEG_TX#3 C565 EV@0.22u/10V_4 C_PEG_TX#0 B22 DSW AR13 USBP4# CLK_PCIE_WLAN#_R B38 AN15 CLK_PCH_PCI3 22_4 R215
A21 PETN5_L3 USB2N7 AP13 USBP4# 30 27 CLK_PCIE_WLAN#
C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLK_PCH_PCI4
PCLK_DEBUG 27
16 PEG_TX3 C564 EV@0.22u/10V_4 C_PEG_TX0 DSW USBP4 Card reader CLK_PCIE_WLAN_R 22_4 R224
PETP5_L3 USB2P7 USBP4 30 27 CLK_PCIE_WLAN CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_EC 33
27 PCIE_CLK_WLAN_REQ# PCIE_CLK_WLAN_REQ#_R N1 +3V
G11 PCIECLKRQ3/GPIO21 B35 CLK_PCIE_XDPN TP154
29 PCIE_RXN_LAN# PERN3 CLKOUT_ITPXDP
29 F11 G20 USB3_RXN1 30 16 CLK_PCIE_VGAN A39 A35 CLK_PCIE_XDPP TP155
PCIE_RXP_LAN PERP3 USB3RN1 USB3_RXN1 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
H20 USB3_RXP1 B39
LAN
USB3RP1 USB3_RXP1 30 16 CLK_PCIE_VGAP CLKOUT_PCIE_P4

29 PCIE_TXN_LAN# C576 0.1u/10V_4PCIE_TXN_LAN#_C C29 16 CLK_PEGA_REQ# CLK_PEGA_REQ# U5 +3V
C581 0.1u/10V_4PCIE_TXP_LAN_C B30 PETN3 PCIE USB C33 USB3_TXN1 PCIECLKRQ4/GPIO22
29 PCIE_TXP_LAN PETP3 +3V_S5 USB3TN1 USB3_TXN1 30 USB3.0
C +3V_S5 B34 USB3_TXP1 30 27 CLK_PCIE_NGFFN
B37 C
USB3TP1 USB3_TXP1 CLKOUT_PCIE_N5
F13 A37
WLAN
27 PCIE_RXN_WLAN# PERN4 27 CLK_PCIE_NGFFP CLKOUT_PCIE_P5

27
G13 E18 USB3_RXN2 30 27 CLK_PCIE_NGFF# CLK_PCIE_NGFF# T2 +3V
PCIE_RXP_WLAN PERP4 USB3RN2 USB3_RXN2 PCIECLKRQ5/GPIO23
F18 USB3_RXP2 30
USB3RP2 USB3_RXP2
27 PCIE_TXN_WLAN# C575 0.1u/10V_4PCIE_TXN_WLAN#_C B29 USB3.0
C578 0.1u/10V_4PCIE_TXP_WLAN_C A29 PETN4 B33 USB3_TXN2 6 OF 19
27 PCIE_TXP_WLAN PETP4 +3V_S5 USB3TN2 USB3_TXN2 30
+3V_S5 A33 USB3_TXP2 30
G17 USB3TP2 USB3_TXP2
TP28 PCIE_RXN1
PCIE_RXP1 F17 PERN1/USB3RN3
TP29 PERP1/USB3RP3
USBCOMP +3V
PCIE_TXN1 C30
TP100
PCIE_TXP1 C31 PETN1/USB3TN3 +3V_S5 AJ10 USBCOMP R248 22.6/F_4
Impedance = 50 ohm
TP101 PETP1/USB3TP3 +3V_S5 USBRBIAS AJ11 Trace length < 500 mils CLK_PCIE_REQ0# R548 10K_4
F15 USBRBIAS AN10 Trace spacing = 15 mils CLK_PCIE_REQ1# R200 10K_4
G15 PERN2/USB3RN4 RSVD AM10 PCIE_CLK_WLAN_REQ#_R R560 10K_4
PERP2/USB3RP4 RSVD USB Overcurrent PCIE_REQ_LAN# R535 10K_4 CLK_PCI_EC PCLK_DEBUG
B31 CLK_PCIE_NGFF# R547 10K_4
A31 PETN2/USB3TN4 +3V_S5 +3V_S5
PETP2/USB3TP4 +3V_S5 AL3 USB_OC0# RP6
+3V_S5 OC0/GPIO40 AT1 USB_OC1#
USB_OC0# 30 DB U2 10 1 TESTLOW_C35 R619 10K_4 C218 C212
+3V_S5 OC1/GPIO41 AH2 USB_OC2#
USB_OC1# 30 MB U3 USB_OC0# 9 2 TESTLOW_C34 R614 10K_4 *18p/50V_4 *18p/50V_4
+3V_S5 OC2/GPIO42
E15 +3V_S5 AV3 USB_OC3# USB_OC1# 8 3 TESTLOW_AK8 R241 10K_4
E13 RSVD OC3/GPIO43 USB_OC2# 7 4 TESTLOW_AL8 R237 10K_4
R271 3.01K/F_4 PCIE_RCOMP A27 RSVD USB_OC3# 6 5
R274 *short_4 PCIE_IREF B27 PCIE_RCOMP
+V1.05S_AUSB3PLL PCIE_IREF 10K_10P8R
+3V
B B
11 OF 19
CLK_PEGA_REQ# R131 10K_4
R132 *1K_4
A A

PROJECT : ZYW
3A
LPT 3/6 (PCIE/USB/CLK)
5 4 3 2 1
5 4 3 2 1
PCH GPIO PU/PD
High Low
Haswell ULT PCH (GPIO,CPU/MISC,NCTF)
U33J HSW_ULT_DDR3L
10
+3V
GPIO8 Touch panel No touch panel IRQ_SERIRQ R485 10K_4
DEVSLP0 R528 *10K_4
BOARD_ID0 P1 +3V D60 THRMTRIP# DEVSLP1 R544 *10K_4
D GPIO8 AU2 BMBUSY/GPIO76 THRMTRIP V4 SIO_RCIN# SIO_RCIN# R506 10K_4 D
25 GPIO8 GPIO8 +3V_S5 +3V RCIN/GPIO82 SIO_RCIN# 33
LAN_DISABLE# AM7 DSW T4 IRQ_SERIRQ IRQ_SERIRQ 23,33 SIO_EXT_SMI# R503 10K_4
GPIO15 AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 OPI_COMP2 R598 49.9/F_4 SIO_EXT_SCI# R573 10K_4
8 GPIO15
SKU_ID0 Y1 GPIO15 +3V_S5 MISC PCH_OPI_RCOMP AF20
DGPU_PWROK T3 GPIO16 +3V RSVD AB21 DGPU_HOLD_RST# R201 10K_4
20 DGPU_PWROK
GPIO24 AD5 GPIO17 +3V RSVD GPIO85 R168 10K_4
WK_GPIO27 AN5 GPIO24 +3V_S5 GPIO87 R155 10K_4
GPIO28 AD7 GPIO27 DSW GPIO88 R127 10K_4
GPIO26 AN3 GPIO28 +3V_S5 GPIO89 R169 10K_4
GPIO26 +3V_S5 R6 GPIO83 GPIO90 R525 10K_4
+3V GSPI0_CS/GPIO83
GPIO56 AG6 L6 GPIO84 GPIO91 R502 10K_4
TP21
GPIO57 AP1 GPIO56 +3V_S5 +3V GSPI0_CLK/GPIO84 N6 GPIO85 GPIO92 R153 10K_4
TP92
GPIO58 AL4 GPIO57 +3V_S5 +3V GSPI0_MISO/GPIO85 L8 GPIO86 GPIO93 R524 10K_4
GPIO59 AT5 GPIO58 +3V_S5 +3V GSPI0_MOSI/GPIO86 R7 GPIO87
GPIO86 8
GPIO94 R568 10K_4
TP27
GPIO44 AK4 GPIO59 +3V_S5 GPIO
+3V GSPI1_CS/GPIO87 L5 GPIO88 GPIO65 R148 10K_4
GPIO47 AB6 GPIO44 +3V_S5 +3V GSPI1_CLK/GPIO88 N7 GPIO89 DGPU_EVENT# R543 *10K_4
DGPU_HOLD_RST# U4 GPIO47 +3V_S5 +3V GSPI1_MISO/GPIO89 K2 GPIO90 GPIO83 R138 10K_4
16 DGPU_HOLD_RST#
DGPU_PWR_EN Y3 GPIO48 +3V +3V GSPI_MOSI/GPIO90 J1 GPIO91 GPIO84 R126 10K_4
41 DGPU_PWR_EN
DGPU_PW_CTRL# P3 GPIO49 +3V +3V UART0_RXD/GPIO91 K3 GPIO92 I2C0_SDA_GPIO6 R551 2.2K_4
MODPHY_EN Y2 GPIO50 +3V +3V UART0_TXD/GPIO92 J2 GPIO93
Reserve GPIO68,69 for board ID
I2C0_SCL_GPIO7 R501 2.2K_4
36 MODPHY_EN
GPIO13 AT3 HSIOPC/GPIO71 +3V +3V
SERIAL IO UART0_RTS/GPIO93 G1 GPIO94 GPIO67 R519 10K_4
GPIO14 AH4 GPIO13 +3V_S5 +3V UART0_CTS/GPIO94 K4 SIO_EXT_SMI# R532 *10K_4 GPIO68 R539 10K_4
GPIO25 AM4 GPIO14 +3V_S5 +3V UART1_RXD/GPIO0 G2 SIO_EXT_SCI#
SIO_EXT_SMI# 33
R542 *10K_4 GPIO69 R523 10K_4
GPIO45 AG5 GPIO25 DSW +3V UART1_TXD/GPIO1 J3 DGPU_EVENT#
SIO_EXT_SCI# 33
R550 *100K_4 DGPU_PWR_EN R531 10K_4
TP20
GPIO46 AG3 GPIO45 +3V_S5 +3V UART1_RST/GPIO2 J4 GC6_FB_EN
DGPU_EVENT# 19
1A-3
GPIO46 +3V_S5 +3V UART1_CTS/GPIO3 F2 GPIO4
GC6_FB_EN 19,20
C +3V I2C0_SDA/GPIO4 C
GPIO9 AM3 +3V_S5 +3V F3 GPIO5 R558 10K_4 GC6_FB_EN R752 *10K_4
GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 I2C0_SDA_GPIO6 R151 *10K_4 PCH_ODD_EN R134 *10K_4
DEVSLP0 P2 GPIO10 +3V_S5 +3V I2C1_SDA/GPIO6 F1 I2C0_SCL_GPIO7
I2C0_SDA_GPIO6 32
27 DEVSLP0 DEVSLP0/GPIO33 +3V +3V I2C1_SCL/GPIO7 I2C0_SCL_GPIO7 32
BOARD_ID3 C4 +3V +3V E3 PCH_ODD_EN
SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 PCH_ODD_EN 28
DEVSLP1 L2 +3V +3V F4 GPIO65
SKU_ID1 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 GPIO66
DEVSLP2/GPIO39 +3V +3V SDIO_D0/GPIO66 GPIO66 8
8,31 SPKR SPKR V2 +3V +3V E4 GPIO67 GPIO4 R152 *10K_4
SPKR/GPIO81 SDIO_D1/GPIO67 C3 GPIO68 GPIO5 R135 *10K_4
+3V SDIO_D2/GPIO68
+3V E2 GPIO69
SDIO_D3/GPIO69
10 OF 19
high UMA Only
Board ID CPU thermal trip GPU power is control by PCH

low GPIO (Discrete, SG or Optimize) +3V
+1.05V_VCCST
+3V
R505 EV@100K_4 DGPU_PW_CTRL#R484 IV@1K_4
3
DGPU_PWROK R751 *10K_4
R561 *10K_4 BOARD_ID0 R546 10K_4 DGPU_PWROK PD on GPU side +3V_S5
2 BOARD_ID1 IMVP_PWRGD_3V 2 Q35
LAN_DISABLE# R238 10K_4
B R184 10K_4 BOARD_ID1 R170 *10K_4 FDV301N B
2 BOARD_ID2 GPIO8 R149 10K_4
GPIO46 R174 *10K_4
1
GPIO24 R187 10K_4
R527 10K_4 BOARD_ID2 R545 *10K_4 +1.05V_VCCST GPIO28 R495 10K_4
R700 GPIO47 R179 10K_4
R578 10K_4 BOARD_ID3 R577 *10K_4 1K_4 GPIO57 R521 10K_4
GPIO58 R158 10K_4
2 BOARD_ID4 R699 GPIO59 R235 10K_4
GPIO26 R145 10K_4
2
R504 10K_4 BOARD_ID4 R526 *10K_4 1K_4 GPIO45 R189 10K_4
GPIO44 R572 10K_4
THRMTRIP# 1 3 GPIO13 R522 10K_4
SYS_SHDN# 33,35,39
Q49 MMBT3904-7-F GPIO14 R190 10K_4
+3V GPIO9 R570 10K_4
SKU ID GPIO10 R555 10K_4
GPIO56 R177 10K_4
Low High R565 IV@10K_4 SKU_ID0 R564 EV@10K_4 GPIO25 R772 10K_4
U36 +1.05V_VCCST +3V WK_GPIO27 R773 10K_4
N15V-GM-B R137 IV@10K_4 SKU_ID1 R154 EV@10K_4 non-DS3, stuff R772,R773
1 5 DS3, stuff R159,R160 +3VPCU
BOARD_ID0 N15V-GL-B (Default) NC VCC GPIO25 R159 *10K_4
1
R696 R160 *10K_4
2 C626 WK_GPIO27 R166 *10K_4
BOARD_ID1 Reserved SKU_ID1 SKU_ID0 VGA H/W Setup 5,38 IMVP_PWRGD A 0.1u/10V_4
10K_4
(Default) Reserved
2
Signal Menu
A 3 4 IMVP_PWRGD_3V 7 GPIO27 : If not used then use A
UMA Only 0 0 UMA Hidden UMA boot GND Y
8.2-kΩ to 10-kΩ pull-down to GND.
BOARD_ID2 Reserve for Touch pad, default(low) 74AUP1G07GW
dGPU Only 0 1 GPU Hidden GPU boot
WO/dTPM Switchable
1 0 UMA+GPU dGPU/SG UMA boot
BOARD_ID3 (Default) W/dTPM (Mux) PROJECT :ZYW
w/VGA Optimize Size Document Number Rev
1 1 UMA UMA/SG UMA boot 3A
BOARD_ID4 (Default) wo/VGA (Muxless) LPT 4/6 (GPIO/MISC)
5 4 3 2 1
5 4 3 2 1
C230
C215
C234
*1u/6.3V_4
1u/6.3V_4
1u/6.3V_4 U33M
Haswell ULT PCH (Power)
HSW_ULT_DDR3L
C267
1u/6.3V_4
+3VCC_S5
11
1.838A K9
+1.05V +1.05V_MODPHY VCCHSIO
L10
VCCHSIO +3V_RTC
1.741A M9
R257 *short_8 +V1.05S_AIDLE N8 VCCHSIO HSIO RTC AH11
P9 VCC1_05 VCCSUS3_3 AG10 C224 C226 C225
D B18 VCC1_05 VCCRTC AE7 +VCCRTCEXT 0.1u/10V_4 0.1u/10V_4 1u/6.3V_4 D
+V1.05S_AUSB3PLL VCCUSB3PLL DCPRTC
C238 B11
+V1.05S_ASATA3PLL VCCSATA3PLL
*1u/6.3V_4
18mA C239
Y20 SPI Y8 +V3.3M_PSPI 0.1u/10V_4
AA21 RSVD VCCSPI R141 *short_6
R242 *0_6
10mA +V1.05S_APLLOPI
W21 VCCAPLL
OPI
+3V_S5
+1.05V_S5 VCCAPLL AG14 R140 *0_6 +3V
VCCASW AG13 PCH_VCC_1_1_21
C241 C237 VCCASW
10u/6.3V_6 1u/6.3V_4 +1.05V_DCPSUS3 J13 USB3 C189
DCPSUS3 +1.05V
J11 +V1.05S_CORE_PCH R254 *short_6 0.1u/10V_4
VCC1_05 +1.05V
H11
AH14 HDA VCC1_05 H15
R117 *0_6
25mA +1.05V_DCPSUS2
+V3.3DX_1.5DX_1.8DX_AUDIO VCCHDA VCC1_05 AE8 R253 *short_8
+1.05V_S5 VCC1_05 +1.05V
AF22
AH13 VRM VCC1_05 AG19
Deep Sx 0.114A DCPSUS2 CORE DCPSUSBYP
C183 +3VPCU R494 *0_6 AG20 C245 C266 C243
1u/6.3V_4 C273 22u/6.3V_8 DCPSUSBYP AE9 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6
R512 0_6 VCCASW AF9
+3V_S5 VCCASW
+3VCC_S5 AC9 AG8
AA9 VCCSUS3_3 VCCASW AD10 +1.05V_DCPSUS1 +PCH_VCCDSW
Non Deep Sx VCCSUS3_3
GPIO/LPC
DCPSUS1
C235 +VCCPDSW AH10 AD8
1u/6.3V_4 +V3.3S_VCCPCORE V8 VCCDSW3_3 DCPSUS1
W9 VCC3_3 C544
VCC3_3 J15 1u/6.3V_4
R118 *short_8
41mA THERMAL SENSOR VCCTS1_5 K14
+3V VCC3_3 +V1.05M_VCCASW
K16
VCC3_3
C176 +V1.05M_VCCASW
0.658A R258 *short_6 +1.05V
C 22u/6.3V_8 +V1.05S_AXCK_DCB J18 0.109A C
K19 VCCCLK SERIAL IO U8
A20 VCCCLK VCCSDIO T9 R116 *0_6 C244 C246
+V1.05S_AXCK_LCPLL VCCACLKPLL VCCSDIO
J17 1u/6.3V_4 22u/6.3V_8
+1.05V VCCCLK +1.05V_S5
R21
+1.05V VCCCLK
C255 1u/6.3V_4 T21 LPT LP POWER C182
C257 1u/6.3V_4 K18 VCCCLK SUS OSCILLATOR AB8 1u/6.3V_4
M20 RSVD DCPSUS4
WW15 4/10 Intel VCCDSW3 RSVD
63mA V21 3mA
G3 can't boot issue. AE20 RSVD AC20 +V1.5S_VCCATS R266 *short_6
C541 +3VCC_S5 VCCSUS3_3 RSVD +1.5V
AE21 AG16 1mA
+VCCPDSW +PCH_VCCDSW VCCSUS3_3 USB2 VCC1_05 AG17 +V3.3S_VCCPTS R249 *short_6
VCC1_05 +3V
0.47u/25V_6 C253
13 OF 19 1u/6.3V_4
+V3.3S_VCCSDIO
17mA R250 *short_6 +3V
PCH VCCHSIO Power +1.05V_DCPSUS4 R115 *0_6 +1.05V_S5
C240
1u/6.3V_4
C181
1u/6.3V_4
+V1.05S_VCCUSBCORE R270 *short_8 +1.05V

B B
C260
1u/6.3V_4
VCCAPLL power +1.05V +V1.05S_AXCK_DCB
+1.05V +V1.05S_APLLOPI L18 2.2uH/210mA_8

0.2A
L17 2.2uH/210mA_8
57mA
C248 C247 C254
47u/6.3V_8 47u/6.3V_8 1u/6.3V_4
C233 C232 C263

*47u/6.3V_8 *47u/6.3V_8 1u/6.3V_4
+1.05V +V1.05S_AXCK_LCPLL
PCH HDA Power L20 2.2uH/210mA_8

31mA
+1.05V_MODPHY +V1.05S_AUSB3PLL +1.05V_MODPHY +V1.05S_ASATA3PLL
11mA
A L16 2.2uH/210mA_8
41mA L15 2.2uH/210mA_8
42mA C270 C269 C275 A
+1.5V +V3.3DX_1.5DX_1.8DX_AUDIO 47u/6.3V_8 47u/6.3V_8 1u/6.3V_4
R150 *short_6
C262 C261 C264 C228 C223 C560
47u/6.3V_8 47u/6.3V_8 1u/6.3V_4 47u/6.3V_8 47u/6.3V_8 1u/6.3V_4
C256
0.1u/10V_4 Quanta Computer Inc.
Place close to ball PROJECT :ZYW
3A
LPT 5/6 (POWER)
5 4 3 2 1
5 4 3 2 1
Haswell ULT (GND) 12

HSW_ULT_DDR3L HSW_ULT_DDR3L HSW_ULT_DDR3L HSW_ULT_DDR3L
U33N U33O U33P U33R
D H17 D
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10 N23
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22 RSVD R23
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59 RSVD T23
VSS VSS VSS VSS VSS VSS AT2 RSVD
A28 AJ45 AP3 AW33 D38 J63 RSVD U10
VSS VSS VSS VSS VSS VSS AU44 RSVD
A32 AJ47 AP31 AW35 D39 K1 RSVD
VSS VSS VSS VSS VSS VSS AV44
A36 AJ50 AP38 AW37 D41 K12 RSVD
VSS VSS VSS VSS VSS VSS D15
A40 AJ52 AP39 AW4 D42 L13 RSVD AL1
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15 RSVD AM11
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17 RSVD AP7
VSS VSS VSS VSS VSS VSS F22 RSVD
A52 AJ58 AP54 AW44 D46 L18 RSVD AU10
VSS VSS VSS VSS VSS VSS H22 RSVD
A56 AJ60 AP57 AW47 D47 L20 RSVD AU15
VSS VSS VSS VSS VSS VSS J21 RSVD
AA1 AJ63 AR11 AW50 D49 L58 RSVD AW14
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61 RSVD AY14
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7 RSVD
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10 18 OF 19
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
C AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9 C
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62 VSS_SENSE_R R675 *short_4
VSS VSS VSS VSS VSS VSS_SENSE VSS_SENSE 38
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 VSS R667 100/F_4
AH30 VSS VSS AN32 AU53 VSS VSS C18
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH44 VSS VSS AN45 AV24 VSS VSS D12
B AH57 VSS VSS AN52 AV39 VSS VSS D23 B
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ25 VSS VSS AP10 AV49 VSS VSS D29
VSS VSS VSS 15 OF 19 VSS
14 OF 19
HSW_ULT_DDR3L
U33Q
DC_TEST_AY2_AW 2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW 3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 TP_DC_TEST_A4
DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 TP96
TP107 TP_DC_TEST_AY60 AY60
DC_TEST_AY61_AW 61 AY61 DAISY_CHAIN_NCTF_AY60 A60 TP_DC_TEST_A60
DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 TP106
DC_TEST_AY62_AW 62 AY62 A61 DC_TEST_A61_B61
TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 TP_DC_TEST_A62
A TP88 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 TP109 A
DC_TEST_A3_B3 B3 AV1 TP_DC_TEST_AV1 TP84
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 TP_DC_TEST_AW 1
DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 TP94
DC_TEST_B62_B63 B62 AW2 DC_TEST_AY2_AW 2
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW 3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW 61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW 62
DAISY_CHAIN_NCTF_C2
17 OF 19
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
AW63 TP_DC_TEST_AW 63 TP108 Quanta Computer Inc.
PROJECT : ZYW
3A
LPT 6/6 (GND)
5 4 3 2 1
5 4 3 2 1
13
D D
C C
B B
A A

PROJECT :ZYW
3A
CPU/PCH XDP
5 4 3 2 1
1 2 3 4 5 6 7 8
+1.35V_SUS
14
3 M_A_A[15:0] JDIM6A JDIM6B
M_A_A0 98 5 75 44
A0 DQ0 M_A_DQ6 3 VDD1 VSS16
M_A_A1 97 7 M_A_DQ2 3 76 48
M_A_A2 96 A1 DQ1 15 81 VDD2 VSS17 49
M_A_A3 95 17 M_A_DQ7 3 82 54
M_A_A4 92 A3 DQ3 4 87 VDD4 VSS19 55
M_A_A5 91 6 88 60
M_A_A6 90 16 M_A_DQ5 3 93 61
M_A_A7 86 A6 DQ6 18 94 VDD7 VSS22 65
M_A_A8 89 21 99 66
M_A_A9 85 A8 DQ8 23
M_A_DQ9 3 2.48A 100 VDD9 VSS24 71
M_A_A10 107 33 105 72
A10/AP DQ10 M_A_DQ11 3 VDD11 VSS26
PC2100 DDR3 SDRAM SO-DIMM

A M_A_A11 84 35 M_A_DQ15 3 106 127 A
M_A_A12 83 A11 DQ11 22 111 VDD12 VSS27 128
A12/BC# DQ12 M_A_DQ12 3 VDD13 VSS28
M_A_A13 119 24 112 133
M_A_A14 80 34 M_A_DQ14 3 117 134
M_A_A15 78 A14 DQ14 36 118 VDD15 VSS30 138
39 123 139

DQ16 M_A_DQ17 3 VDD17 VSS32
109 41 M_A_DQ16 3 124 144
3 M_A_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_A_DQ19 3 145
3 M_A_BS#1 BA1 DQ18 VSS34
79 53 M_A_DQ18 3 199 150
3 M_A_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_A_DQ21 3 151
3 M_A_CS#0 S0# DQ20 VSS36
121 42 M_A_DQ20 3 77 155
3 M_A_CS#1 S1# DQ21 NC1 VSS37
101 50 M_A_DQ23 3 122 156
3 M_A_CLK0 CK0 DQ22 NC2 VSS38
103 52 R219 *10K_4 125 161
3 M_A_CLK0# CK0# DQ23 M_A_DQ22 3 +3V NCTEST VSS39
102 57 M_A_DQ25 3 162
3 M_A_CLK1 CK1 DQ24 VSS40
104 59 M_A_DQ24 3 PM_EXTTS#1A 198 167
3 M_A_CLK1# CK1# DQ25 EVENT# VSS41
73 67 M_A_DQ26 3 30 168
3 M_A_CKE0 CKE0 DQ26 4,15 DDR3_DRAMRST# RESET# VSS42
74 69 M_A_DQ31 3 C360 *0.1u/10V_4 172
3 M_A_CKE1 CKE1 DQ27 VSS43
115 56 M_A_DQ28 3 173
3 M_A_CAS# CAS# DQ28 VSS44
110 58 M_A_DQ29 3 +SMDDR_VREF_DQ0 +SMDDR_VREF_DQ0 1 178
3 M_A_RAS# 113 RAS# DQ29 68 126 VREF_DQ VSS45 179
3 M_A_WE# WE# DQ30 M_A_DQ27 3 +SMDDR_VREF_DIMM VREF_CA VSS46
R213 10K_4 DIMM1_SA0 197 70 M_A_DQ30 3 184
R212 10K_4 DIMM1_SA1 201 SA0 DQ31 129 VSS47 185
SA1 DQ32 M_A_DQ33 3 VSS48
202 131 2 189
8,13,15,27 CLK_SCLK SCL DQ33 M_A_DQ32 3 VSS1 VSS49
200 141 M_A_DQ35 3 3 190
8,13,15,27 CLK_SDATA SDA DQ34 143 8 VSS2 VSS50 195
(204P)
DQ35 M_A_DQ34 3 VSS3 VSS51
116 130 M_A_DQ36 3 9 196
4 M_A_ODT0_DIMM ODT0 DQ36 VSS4 VSS52
120 132 M_A_DQ37 3 13
4 M_A_ODT1_DIMM ODT1 DQ37 VSS5
140 14
DQ38 M_A_DQ39 3 VSS6
B 11 142 M_A_DQ38 3 19 B
28 DM0 DQ39 147 20 VSS7
DM1 DQ40 M_A_DQ41 3 VSS8
46 149 M_A_DQ44 3 25
(204P)
63 DM2 DQ41 157 26 VSS9 203
DM3 DQ42 M_A_DQ42 3 VSS10 VTT1 +DDR_VTT_RUN
136 159 31 204
DM4 DQ43 M_A_DQ46 3 VSS11 VTT2
153 146 M_A_DQ40 3 32
170 DM5 DQ44 148 37 VSS12 205
DM6 DQ45 M_A_DQ45 3 VSS13 GND
187 158 M_A_DQ43 3 38 206
DM7 DQ46 160 43 VSS14 GND
DQ47 M_A_DQ47 3 VSS15
M_A_DQS0 12 163 M_A_DQ49 3
M_A_DQS1 29 DQS0 DQ48 165
DQS1 DQ49 M_A_DQ52 3
M_A_DQS2 47 175 DDR3-DIMM1_H=5.2_RVS
M_A_DQS3 64 177 M_A_DQ54 3
M_A_DQS4 137 DQS3 DQ51 164
M_A_DQS5 154 166 M_A_DQ55 3
M_A_DQS6 171 DQS5 DQ53 174
M_A_DQS7 188 176
3 M_A_DQS[7:0]
M_A_DQS#0 10 DQS7 DQ55 181
M_A_DQ51 3 M1 solution
DQS#0 DQ56 M_A_DQ56 3 +1.35V_SUS
M_A_DQS#1 27 183 M_A_DQ61 3
M_A_DQS#2 45 DQS#1 DQ57 191
DQS#2 DQ58 M_A_DQ63 3
M_A_DQS#3 62 193 M_A_DQ59 3
M_A_DQS#4 135 DQS#3 DQ59 180
M_A_DQS#5 152 DQS#4
DQS#5
DQ60
DQ61
182
M_A_DQ57
M_A_DQ60
3
3 R285 Vref_CA
M_A_DQS#6 169 192 M_A_DQ58 3 1.8K/F_4
M_A_DQS#7 186 DQS#6 DQ62 194 +SMDDR_VREF_DIMM
3 M_A_DQS#[7:0] DQS#7 DQ63 M_A_DQ62 3
+VREF_CA_CPU R272 *short_6 R279 2/F_6

1A-2 2013/10/16 Chage net name M_B_DQS#[7:0] to DDR3-DIMM1_H=5.2_RVS
2
M_A_DQS#[7:0].
C M3 solution C271 R280 C282
C
0.022u/16V_4 1.8K/F_4 470p/50V_4
1
+1.35V_SUS Place these Caps near SO-DIMM R275
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0 24.9/F_4
C322 C308 C326 C310 C337
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4
C291 + C300 C281 C277 C384 C382

330u/2V_7343
10u/6.3V_6 0.1u/10V_4 0.1u/10V_4
C344 C347 C321 C348 C313 2.2u/6.3V_6 2.2u/6.3V_6

M1 solution
10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 +1.35V_SUS
+3V +DDR_VTT_RUN
R344 Vref_DQ
1.8K/F_4
+SMDDR_VREF_DQ0
C210 C207 C211 C208 C198 C199 C209
C220 C219 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 +VREFDQ_SA_M3 R332 *short_6 R336 2/F_6
2.2u/6.3V_6 0.1u/10V_4 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6
2
M3 solution C379 R334 C380
0.022u/16V_4 1.8K/F_4 470p/50V_4
1
D D
R339
24.9/F_4
SA1 SA0 Quanta Computer Inc.

CHA 0 0
PROJECT : ZYW
CHB 1 0 3A
DDR3 MEMORY SO-DIMM A
1 2 3 4 5 6 7 8
5 4 3 2 1
3 M_B_A[15:0]
M_B_A0
M_B_A1
M_B_A2
M_B_A3
98
97
96
95
JDIM7A
A0
A1
A2
DQ0
DQ1
DQ2
5
7
15
17
M_B_DQ23
M_B_DQ22
M_B_DQ20
M_B_DQ19
3
3
3
3
+1.35V_SUS
75
76
81
82
JDIM7B
VDD1
VDD2
VDD3
VSS16
VSS17
VSS18
44
48
49
54
15
M_B_A4 92 A3 DQ3 4 87 VDD4 VSS19 55
A4 DQ4 M_B_DQ17 3 VDD5 VSS20
M_B_A5 91 6 M_B_DQ16 3 88 60
M_B_A6 90 A5 DQ5 16 93 VDD6 VSS21 61
M_B_A7 86 18 M_B_DQ21 3 94 65
M_B_A8 89 A7 DQ7 21 99 VDD8 VSS23 66
D
M_B_A9 85 A8 DQ8 23
M_B_DQ2 3 2.48A 100 VDD9 VSS24 71
D
M_B_A10 107 33 M_B_DQ7 3 105 72
M_B_A11 84 A10/AP DQ10 35 106 VDD11 VSS26 127

M_B_A12 83 22 M_B_DQ3 3 111 128
M_B_A13 119 A12/BC# DQ12 24 112 VDD13 VSS28 133
M_B_A14 80 34 M_B_DQ0 3 117 134
M_B_A15 78 A14 DQ14 36 118 VDD15 VSS30 138
39 123 139

DQ16 M_B_DQ8 3 VDD17 VSS32
109 41 M_B_DQ9 3 124 144
3 M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ10 3 145
3 M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ11 3 199 150
3 M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ12 3 151
3 M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ13 3 77 155
3 M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ15 3 122 156
3 M_B_CLK0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ14 3 R214 *10K_4 125 161
3 M_B_CLK0# CK0# DQ23 +3V NCTEST VSS39
102 57 M_B_DQ27 3 162
3 M_B_CLK1 CK1 DQ24 VSS40
104 59 M_B_DQ26 3 PM_EXTTS#1B 198 167
3 M_B_CLK1# CK1# DQ25 EVENT# VSS41
73 67 M_B_DQ24 3 30 168
3 M_B_CKE0 CKE0 DQ26 4,14 DDR3_DRAMRST# RESET# VSS42
74 69 M_B_DQ25 3 C361 *0.1u/10V_4 172
3 M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ30 3 173
3 M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ31 3 +SMDDR_VREF_DQ1 +SMDDR_VREF_DQ1 1 178
3 M_B_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_B_DQ29 3 126 179
3 M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R229 10K_4 DIMM2_SA0 197 70 M_B_DQ28 3 184
R216 10K_4 DIMM2_SA1 201 SA0 DQ31 129 VSS47 185
+3V SA1 DQ32 M_B_DQ33 3 VSS48
202 131 M_B_DQ32 3 2 189
8,13,14,27 CLK_SCLK 200 SCL DQ33 141 3 VSS1 VSS49 190
8,13,14,27 CLK_SDATA SDA DQ34 M_B_DQ38 3 VSS2 VSS50
143 M_B_DQ39 3 8 195
(204P)
C DQ35 VSS3 VSS51 C
116 130 M_B_DQ36 3 9 196
4 M_B_ODT0_DIMM ODT0 DQ36 VSS4 VSS52
120 132 M_B_DQ37 3 13
4 M_B_ODT1_DIMM ODT1 DQ37 VSS5
140 M_B_DQ34 3 14
11 DQ38 142 19 VSS6
DM0 DQ39 M_B_DQ35 3 VSS7
28 147 M_B_DQ40 3 20
46 DM1 DQ40 149 25 VSS8
DM2 (204P) DQ41 M_B_DQ41 3 VSS9
63 157 M_B_DQ45 3 26 203 +DDR_VTT_RUN
136 DM3 DQ42 159 31 VSS10 VTT1 204
DM4 DQ43 M_B_DQ47 3 VSS11 VTT2
153 146 M_B_DQ43 3 32
170 DM5 DQ44 148 37 VSS12 205
DM6 DQ45 M_B_DQ42 3 VSS13 GND
187 158 M_B_DQ46 3 38 206
DM7 DQ46 160 43 VSS14 GND
DQ47 M_B_DQ44 3 VSS15
M_B_DQS2 12 163 M_B_DQ55 3
M_B_DQS0 29 DQS0 DQ48 165
DQS1 DQ49 M_B_DQ49 3
M_B_DQS1 47 175 M_B_DQ50 3 DDR3-DIMM1_H=5.2_STD
M_B_DQS3 64 DQS2 DQ50 177
M_B_DQS4 137 164 M_B_DQ52 3
M_B_DQS5 154 DQS4 DQ52 166
M_B_DQS6 171 174 M_B_DQ54 3
M_B_DQS7 188 DQS6 DQ54 176
3 M_B_DQS[7:0] DQS7 DQ55 M_B_DQ48 3
M_B_DQS#2 10 181 M_B_DQ56 3
M_B_DQS#0 27 DQS#0 DQ56 183
DQS#1 DQ57 M_B_DQ57 3
M_B_DQS#1 45 191 M_B_DQ59 3
M_B_DQS#3 62 DQS#2 DQ58 193
M_B_DQS#4 135 180 M_B_DQ61 3
M_B_DQS#5 152 DQS#4 DQ60 182
B M_B_DQS#6 169 192 M_B_DQ60 3 B
M_B_DQS#7 186 DQS#6 DQ62 194
3 M_B_DQS#[7:0] DQS#7 DQ63 M_B_DQ58 3
M1 solution
1A-22013/10/16 Swap M_B_DQS2/M_B_DQS3 and swap DDR3-DIMM1_H=5.2_STD +1.35V_SUS
M_B_DQS#2/M_B_DQS#3.
R346 Vref_DQ
1.8K/F_4
+1.35V_SUS Place these Caps near SO-DIMM +SMDDR_VREF_DQ1
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1
C302 C349 C311 C332 C334 +VREFDQ_SB_M3 R343 *short_6 R341 2/F_6
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4
2
C335 + C354 C283 C276 C391 C394
M3 solution C389 R347 C392
330u/2V_7343 0.022u/16V_4 1.8K/F_4 470p/50V_4
1
10u/6.3V_6 0.1u/10V_4 0.1u/10V_4
C343 C319 C350 C309 C294 2.2u/6.3V_6 2.2u/6.3V_6 R348

10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 24.9/F_4
+3V +DDR_VTT_RUN
A C203 C205 C204 C206 C200 C202 C201 A

C221 C222 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
2.2u/6.3V_6 0.1u/10V_4 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6
SA1 SA0
CHA 0 0 Quanta Computer Inc.
PROJECT : ZYW
CHB 1 0 Size Document Number Rev
3A
DDRIII Memory SO-DIMM B
5 4 3 2 1
5 4 3 2 1
<VGA>
16
+3V_GFX +3V_GFX
+VGPU_CORE PLACE UNDER GPU BALLS

U39A R103 U39E
+1.05V_GFX
1000mA EV@10K/F_4 11/14 NVVDD
2
1/14 PCI_EXPRESS K10
VDD
VDD K12
PEX_WAKE AB6 PEX_CLKREQ# 1 3 CLK_PEGA_REQ# 9 VDD K14
To be placed no further from the GPUC169 EV@22u/6.3V_8 VDD K16
than bewteen BGA and Power supply C174 EV@22u/6.3V_8 AA22 PEX_IOVDD Q17 PU at page 9 VDD K18
C144 EV@10u/6.3V_6 AB23 PEX_IOVDD PEX_RST AC7 PEGX_RST# EV@2N7002K VDD L11
C140 EV@10u/6.3V_6 AC24 PEX_IOVDD VDD L13 C119 C88 C80 C107 C112 C109 C124 C126
place near balls C143 EV@4.7u/6.3V_6 AD25 PEX_IOVDD PEX_CLKREQ AC6 PEX_CLKREQ# R99 *EV@0_4 VDD L15
D C141 EV@1u/6.3V_4 AE26 PEX_IOVDD VDD L17 D
place under BGA C139 EV@1u/6.3V_4 AE27 PEX_IOVDD PEX_REFCLK AE8 CLK_PCIE_VGAP 9 VDD M10 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6
PEX_REFCLK AD8 CLK_PCIE_VGAN 9 VDD M12 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6
VDD M14
PEX_TX0 AC9 C_PEG_RX0 C526 EV@0.22u/10V_4 VDD M16
PEG_RX0 9
PEX_TX0 AB9 C_PEG_RX#0 C525 EV@0.22u/10V_4 VDD M18 4.7uF x 15 population x10
PEG_RX#0 9
PLACE CLOSE TO BGA VDD N11
AG6 PEG_TX0 +3V_GFX J8/K8 N13
PEX_RX0 PEG_TX0 9 VDD
+1.05V_GFX
AA10 PEX_IOVDDQ PEX_RX0 AG7 PEG_TX#0 PEG_TX#0 9 VDD N15
C175 EV@22u/6.3V_8 AA12 PEX_IOVDDQ C152 EV@4.7u/6.3V_6 VDD N17 C103 C114 C111 C129 C94 C106 C131
To be placed no further from the GPUC168 EV@22u/6.3V_8 AA13 PEX_IOVDDQ PEX_TX1 AB10 C_PEG_RX1 C524 EV@0.22u/10V_4 PEG_RX1 9 VDD P10
than bewteen BGA and Power supply C136 EV@10u/6.3V_6 AA16 PEX_IOVDDQ PEX_TX1 AC10 C_PEG_RX#1 C523 EV@0.22u/10V_4 PEG_RX#1 9 C515 EV@1u/6.3V_4 VDD P12
C142 EV@10u/6.3V_6 AA18 PEX_IOVDDQ VDD P14 EV@4.7u/6.3V_6 *EV@4.7u/6.3V_6 *EV@4.7u/6.3V_6 *EV@4.7u/6.3V_6
place near balls C134 EV@4.7u/6.3V_6 AA19 PEX_IOVDDQ PEX_RX1 AF7 PEG_TX1 PEG_TX1 9 VDD P16 EV@4.7u/6.3V_6 *EV@4.7u/6.3V_6 *EV@4.7u/6.3V_6
C148 EV@1u/6.3V_4 AA20 PEX_IOVDDQ PEX_RX1 AE7 PEG_TX#1 PEG_TX#1 9 C146 EV@0.1u/10V_4 VDD P18
place under BGA C159 EV@1u/6.3V_4 AA21 PEX_IOVDDQ VDD R11
AB22 PEX_IOVDDQ PEX_TX2 AD11 C_PEG_RX2 C520 EV@0.22u/10V_4 VDD R13
PEG_RX2 9
AC23 PEX_IOVDDQ PEX_TX2 AC11 C_PEG_RX#2 C519 EV@0.22u/10V_4 PLACE CLOSE TO GPU BALLS L8/M8 VDD R15
PEG_RX#2 9
AD24 R17
2500mA AE25
PEX_IOVDDQ
PEX_IOVDDQ PEX_RX2 AE9 PEG_TX2 PEG_TX2 9
VDD
VDD T10 PLACE NEAR GPU
AF26 PEX_IOVDDQ PEX_RX2 AF9 PEG_TX#2 VDD T12
PEG_TX#2 9 +VGPU_CORE
AF27 PEX_IOVDDQ not GC6 2.0 unstuff resistor VDD T14 47u x1 22u x7 4.7u x6 330u x1
PEX_TX3 AC12 C_PEG_RX3 C522 EV@0.22u/10V_4 PEG_RX3 9 VDD T16 stuff x 1 stuff x 5 RSVD by DG
PEX_TX3 AB12 C_PEG_RX#3 C521 EV@0.22u/10V_4 PEG_RX#3 9 VDD T18
VDD U11
PEX_RX3 AG9 PEG_TX3 PEG_TX3 9
PLACE CLOSE TO BGA VDD U13
AG10 PEG_TX#3 +3V_MAIN L8/M8 U15 + C507 C91 C508 C128 C81 C101 C506
PEX_RX3 PEG_TX#3 9 VDD
VDD U17
PEX_TX4 AB13 C74 EV@4.7u/6.3V_6 VDD V10 C496 EV@47u/6.3V_8 EV@4.7u/25V_8 EV@4.7u/25V_8 EV@4.7u/25V_8
PEX_TX4 AC13 VDD V12 EV@330u/2V_7343 EV@22u/6.3V_8 EV@4.7u/25V_8 EV@4.7u/25V_8
C73 EV@1u/6.3V_4 VDD V14
PEX_RX4 AF10 VDD V16
PEX_RX4 AE10 VDD V18 0817 RSVD more NVVDD caps by NV DG
C 210mA of +3V_GFX C93 EV@0.1u/10V_4 C
PEX_TX5 AD14 C92 EV@0.1u/10V_4
+3V_GFX
PLACE NEAR BGA AA8 PEX_PLL_HVDD PEX_TX5 AC14 bga595-nvidia-n13p-gv2-s-a2
EV@0.1u/10V_4 C90 AA9 PEX_PLL_HVDD PLACE CLOSE TO GPU BALLS L8/M8 COMMON C491 C84 C490 C116 C99 C127 C492
EV@4.7u/6.3V_6 C162 PEX_RX5 AE12 U39C
EV@4.7u/6.3V_6 C157 PEX_RX5 AF12 14/14 XVDD/VDD33 *EV@22u/6.3V_8 *EV@22u/6.3V_8 *EV@22u/6.3V_8 *EV@22u/6.3V_8
AB8 PEX_SVDD_3V3 0.4MM = 16mils *EV@22u/6.3V_8 *EV@22u/6.3V_8 *EV@4.7u/25V_8
PEX_TX6 AC15 AD10 NC VDD33 G10
AB15 AD7 G12
PEX_TX6
B19
NC
NC
VDD33
VDD33 G8
+3V_GFX for meet Power down sequence
PEX_RX6 AG12
AG13
VDD33 G9
+3V_MAIN for +3V_GFX +VGPU_CORE
PEX_RX6 0.1uF x 8 population x 4
F11 3V3AUX_NC 0.4MM = 16mils D9 *EV@RB500V-40
+VGPU_CORE
PEX_TX7 AB16
PEX_TX7 AC16 V5 FERMI_RSVD1_NC C89 EV@0.1u/10V_4
+3V_GFX
V6 FERMI_RSVD2_NC C117 EV@0.1u/10V_4
PEX_RX7 AF13 D8 *EV@820@RB500V-40 C118 EV@0.1u/10V_4
+1.5V_GFX
PEX_RX7 AE13 C113 EV@0.1u/10V_4
C104 *EV@0.1u/10V_4
NC PEX_TX8 AD17 No stuff D8 when GC6 support. C98 *EV@0.1u/10V_4
PEX_TX8 AC17 CONFIGURABLE C105 *EV@0.1u/10V_4
NC +3V_GFX
POWER CHANNELS C115 *EV@0.1u/10V_4
PEX_RX8 AE15 * nc on substrate
NC
NC PEX_RX8 AF15 SYS_PEX_RST_MON# R454 *EV@10K_4
G1 XPWR_G1 GPU_PEX_RST_HOLD# R450 10K_4
F2 VDD_SENSE PEX_TX9 AC18 G2 XPWR_G2
40 VGA_VCCSENSE NC
AB18 G3
NC PEX_TX9 XPWR_G3
G4 XPWR_G4
F1 AG15 G5 +3V VDD33
40 VGA_VSSSENSE GND_SENSE NC PEX_RX9
AG16 G6
XPWR_G5 GC6 2.0 PEGX_RST#
NC PEX_RX9
G7
XPWR_G6 +3V_GFX/
XPWR_G7
PEX_TX10 AB19 +3V_MAIN
NC
PEX_TX10 AC19 C513 t>0
B NC B
V1 XPWR_V1 *EV@0.1u/10V_4 NVDD
AF16 V2
8mils width NC PEX_RX10 XPWR_V2 +VGPU_CORE
5
PEX_RX10 AE16
NC
(0.2MM) SYS_PEX_RST_MON# 2
PEX_TX11 AD20 4PEGX_RST# PXE_VDD
NC
AC20 PEGX_RST# 19
R451 *EVG@0_4 1
NC PEX_TX11
W1
19 GPU_PEX_RST_HOLD# +1.05V_GFX
XPWR_W1 t>0
PEX_RX11 AE18 W2 XPWR_W2 U28 R449 FBVDDQ
3
NC
AF18 W3 *EV@TC7SH08FU
NC PEX_RX11
W4
XPWR_W3
EV@100K_4
+1.35_GFX
XPWR_W4
PEX_TX12 AC21 N15x Power on sequance
NC
PEX_TX12 AB21
NC bga595-nvidia-n13p-gv2-s-a2 COMMON
*EV@200/F_4 R97 PEX_TSTCLK AF22 AG18 +3V

PEX_TSTCLK_OUT NC PEX_RX12
PEX_TSTCLK#AE22 PEX_TSTCLK_OUT PEX_RX12 AG19
NC
PEX_PLLVDD : 0.3MM = 12mils (150mA) R448
RSVD R1 and C1 for GV2 co-layout sDDR3R1 PEX_TX13 AD23 C516 EVG@0_4
NC
*short_6 R104 PEX_PLLVDD AE23 EV@0.1u/10V_4
+1.05V_GFX NC PEX_TX13
PEX_RST timing
EV@4.7u/6.3V_6 C153 AA14 PEX_PLLVDD PEX_RX13 AF19
NC
C1 C137 AA15 PEX_PLLVDD NC PEX_RX13 AE19
5
EV@1u/6.3V_4 C133
EV@1u/6.3V_4 place near BGA PEX_TX14 AF24 2
NC 7,13,23,27,29,30,33 PLTRST#
EV@0.1u/10V_4 C154 PEX_TX14 AE24 4 I/O 3.3V
place near ball
NC
1 SYS_PEX_RST_MON# 19
10 DGPU_HOLD_RST#
PEX_RX14 AE21
NC
PEX_RX14 AF21 U29 PEX_RST
3
EV@10K/F_4 NC
R98 TESTMODE AD9 TESTMODE EV@TC7SH08FU
PEX_TX15 AG24
NC
NC PEX_TX15 AG25
R457 *EV@0_4
PEX_RX15 AG21 Trise >= 1uS Tfail <=500nS
NC
AG22
A NC PEX_RX15 PCH control PEGX_RST# A
GF117 GF119
EV@2.49K/F_4 R460 PEX_TERMP AF25 PEX_TERMP
bga595-nvidia-n13p-gv2-s-a2 COMMON

PROJECT : ZYW
3A
DGPU 1/5 (PEG)
5 4 3 2 1
5 4 3 2 1
<VGA>
U39B
2/14 FBA
17
19,20,33 EC_FB_CLAMP *EVG@0_4 R413 FB_CLAMP F3 FBA_D0 E18 VMA_DQ0
NC GF119
FBA_D1 F18 VMA_DQ1
EV@10K_4 R414 FB_CLAMP FBA_D2 E16 VMA_DQ2
GF117
FBA_D3 F17 VMA_DQ3 VMA_DQ[63:0]
VMA_DQ[63:0] 21
FBA_D4 D20 VMA_DQ4
FBA_D5 D21 VMA_DQ5
FBA_D6 F20 VMA_DQ6 U39F
D FBA_D7 E21 VMA_DQ7 13/14 GND D
FBA_D8 E15 VMA_DQ8 M13 GND GND A2
FBA_D9 D15 VMA_DQ9 M15 GND GND AB17
FBA_D10 F15 VMA_DQ10 U39D M17 GND GND AB20
FBA_D11 F13 VMA_DQ11
C13 VMA_DQ12
For Fermi 12/14 FBVDDQ N10
N12
GND GND AB24
AC2
FBA_D12 GND GND
FBA_D13 B13 VMA_DQ13 FBVDDQ B26 +1.5V_GFX N14 GND GND AC22
FBA_CMD2 R57 EV@10K/F_4
FBA_D14 E13 VMA_DQ14 FBVDDQ C25 N16 GND GND AC26
FBA_D15 D13 VMA_DQ15 FBVDDQ E23 N18 GND GND AC5
FBA_D16 B15 VMA_DQ16 FBVDDQ E26 P11 GND GND AC8
FBA_D17 C16 VMA_DQ17 FBVDDQ F14 P13 GND GND AD12
FBA_D18 A13 VMA_DQ18 FBVDDQ F21 P15 GND GND AD13
FBA_D19 A15 VMA_DQ19 FBVDDQ G13 P17 GND GND A26
FBA_D20 B18 VMA_DQ20 FBVDDQ G14 P2 GND GND AD15
FBA_D21 A18 VMA_DQ21 FBVDDQ G15 P23 GND GND AD16
FBA_D22 A19 VMA_DQ22 FBVDDQ G16 P26 GND GND AD18
FBA_D23 C19 VMA_DQ23 FBVDDQ G18 P5 GND GND AD19
FBA_D24 B24 VMA_DQ24 FBVDDQ G19 R10 GND GND AD21
FBA_D25 C23 VMA_DQ25 FBVDDQ G20 R12 GND GND AD22
FBA_D26 A25 VMA_DQ26 FBVDDQ G21 R14 GND GND AE11
FBA_D27 A24 VMA_DQ27 FBVDDQ H24 R16 GND GND AE14
FBA_D28 A21 VMA_DQ28 FBVDDQ H26 R18 GND GND AE17
FBA_D29 B21 VMA_DQ29 FBVDDQ J21 T11 GND GND AE20
FBA_D30 C20 VMA_DQ30 FBVDDQ K21 T13 GND GND AB11
FBA_D31 C21 VMA_DQ31 FBVDDQ L22 T15 GND GND AF1
FBA_D32 R22 VMA_DQ32 FBVDDQ L24 T17 GND GND AF11
FBA_CMD0 C27 FBA_CMD0 FBA_D33 R24 VMA_DQ33 FBVDDQ L26 U10 GND GND AF14
21 FBA_CMD[30:0]
FBA_CMD1 C26 FBA_CMD1 FBA_D34 T22 VMA_DQ34 FBVDDQ M21 U12 GND GND AF17
FBA_CMD2 E24 FBA_CMD2 FBA_D35 R23 VMA_DQ35 FBVDDQ N21 U14 GND GND AF20
FBA_CMD3 F24 FBA_CMD3 FBA_D36 N25 VMA_DQ36 FBVDDQ R21 U16 GND GND AF23
FBA_CMD4 D27 FBA_CMD4 FBA_D37 N26 VMA_DQ37 FBVDDQ T21 U18 GND GND AF5
FBA_CMD5 D26 FBA_CMD5 FBA_D38 N23 VMA_DQ38 FBVDDQ V21 U2 GND GND AF8
FBA_CMD6 F25 FBA_CMD6 FBA_D39 N24 VMA_DQ39 FBVDDQ W21 U23 GND GND AG2
C FBA_CMD7 F26 FBA_CMD7 FBA_D40 V23 VMA_DQ40 U26 GND GND AG26 C
FBA_CMD8 F23 FBA_CMD8 FBA_D41 V22 VMA_DQ41 U5 GND GND AB14
FBA_CMD9 G22 FBA_CMD9 FBA_D42 T23 VMA_DQ42 V11 GND GND B1
FBA_CMD10 G23 FBA_CMD10 FBA_D43 U22 VMA_DQ43 V13 GND GND B11
FBA_CMD11 G24 FBA_CMD11 FBA_D44 Y24 VMA_DQ44 V15 GND GND B14
FBA_CMD12 F27 FBA_CMD12 FBA_D45 AA24 VMA_DQ45 V17 GND GND B17
FBA_CMD13 G25 FBA_CMD13 FBA_D46 Y22 VMA_DQ46 +1.5V_GFX Y2 GND GND B20
FBA_CMD14 G27 FBA_CMD14 FBA_D47 AA23 VMA_DQ47 Y23 GND GND B23
FBA_CMD15 G26 FBA_CMD15 FBA_D48 AD27 VMA_DQ48 Y26 GND GND B27
FBA_CMD16 M24 FBA_CMD16 FBA_D49 AB25 VMA_DQ49 Y5 GND GND B5
FBA_CMD17 M23 FBA_CMD17 FBA_D50 AD26 VMA_DQ50 PLACE CLOSE TO GPU BALLS GND B8
FBA_CMD18 K24 FBA_CMD18 FBA_D51 AC25 VMA_DQ51 GND E11
FBA_CMD19 K23 FBA_CMD19 FBA_D52 AA27 VMA_DQ52 C120 EV@0.1u/10V_4 GND E14
FBA_CMD20 M27 FBA_CMD20 FBA_D53 AA26 VMA_DQ53 C79 EV@0.1u/10V_4 GND E17
FBA_CMD21 M26 FBA_CMD21 FBA_D54 W26 VMA_DQ54 C77 *EV@0.1u/10V_4 GND E2
FBA_CMD22 M25 FBA_CMD22 FBA_D55 Y25 VMA_DQ55 C71 *EV@0.1u/10V_4 GND E20
FBA_CMD23 K26 FBA_CMD23 FBA_D56 R26 VMA_DQ56 GND E22
FBA_CMD24 K22 FBA_CMD24 FBA_D57 T25 VMA_DQ57 GND E25
FBA_CMD25 J23 FBA_CMD25 FBA_D58 N27 VMA_DQ58 GND E5
FBA_CMD26 J25 FBA_CMD26 FBA_D59 R27 VMA_DQ59 C78 EV@1u/6.3V_4 GND E8
FBA_CMD27 J24 FBA_CMD27 FBA_D60 V26 VMA_DQ60 GND H2
FBA_CMD28 K27 FBA_CMD28 FBA_D61 V27 VMA_DQ61 C70 EV@1u/6.3V_4 GND H23
FBA_CMD29 K25 FBA_CMD29 FBA_D62 W27 VMA_DQ62 GND H25
FBA_CMD30 J27 FBA_CMD30 FBA_D63 W25 VMA_DQ63 C76 *EV@1u/6.3V_4 GND H5
TP14 J26 FBA_CMD31 GND K11
+1.5V_GFX EV@40.2/F_4 R62 FB_CAL_PD_VDDQ D22 FB_CAL_PD_VDDQ C65 *EV@1u/6.3V_4 GND K13
FBA_DQM0 D19 VMA_DM0 VMA_DM[7..0] 21 GND K15
FBA_DQM1 D14 VMA_DM1 GND K17
FBA_DQM2 C17 VMA_DM2 EV@42.2/F_4 R47 FB_CAL_PU_GND C24 FB_CAL_PU_GND GND L10
FBA_DQM3 C22 VMA_DM3 GND L12
FBA_DQM4 P24 VMA_DM4 GND L14
FBA_DQM5 W24 VMA_DM5 EV@51.1/F_4 R50 FB_CAL_TERM_GND B25 FB_CALTERM_GND GND L16
FBA_DQM6 AA25 VMA_DM6 C58 EV@4.7u/6.3V_6 GND L18
B *EV@60.4/F_4 R67 FBA_DEBUG0 F22 U25 VMA_DM7 PLACE CLOSE TO GPU BALLS C171 EV@4.7u/6.3V_6 L2 B
+1.5V_GFX FBA_DEBUG0 FBA_DQM7 GND
*EV@60.4/F_4 R92 FBA_DEBUG1 J22 bga595-nvidia-n13p-gv2-s-a2 C97 *EV@4.7u/6.3V_6 L23
FBA_DEBUG1 GND
COMMON L25
sDDR3 C24 *EV@4.7u/6.3V_6 GND
FBA_DQS_WP0 E19 VMA_WDQS0 VMA_WDQS[7..0] 21 R47=42.2/F AA7 GND GND L5
FBA_DQS_WP1 C15 VMA_WDQS1 R50=51.1/F AB7 GND GND M11
21 VMA_CLK0 VMA_CLK0 D24 FBA_CLK0 FBA_DQS_WP2 B16 VMA_WDQS2
21 VMA_CLK0# VMA_CLK0# D25 FBA_CLK0 FBA_DQS_WP3 B22 VMA_WDQS3 C26 EV@10u/6.3V_6
21 VMA_CLK1 VMA_CLK1 N22 FBA_CLK1 FBA_DQS_WP4 R25 VMA_WDQS4 C25 *EV@10u/6.3V_6
M22 W23 C53 *EV@10u/6.3V_6 COMMON bga595-nvidia-n13p-gv2-s-a2
21 VMA_CLK1# VMA_CLK1# FBA_CLK1 FBA_DQS_WP5 VMA_WDQS5
FBA_DQS_WP6 AB26 VMA_WDQS6 C66 *EV@10u/6.3V_6
FBA_DQS_WP7 T26 VMA_WDQS7
D18 FBA_WCK01 FBA_DQS_RN0 F19 VMA_RDQS0 VMA_RDQS[7..0] 21 C23 EV@22u/6.3V_8

C18 FBA_WCK01 FBA_DQS_RN1 C14 VMA_RDQS1
D17 FBA_WCK23 FBA_DQS_RN2 A16 VMA_RDQS2 C424 EV@22u/6.3V_8
D16 FBA_WCK23 FBA_DQS_RN3 A22 VMA_RDQS3
T24 FBA_WCK45 FBA_DQS_RN4 P25 VMA_RDQS4 C426 *EV@22u/6.3V_8
U24 FBA_WCK45 FBA_DQS_RN5 W22 VMA_RDQS5
V24 FBA_WCK67 FBA_DQS_RN6 AB27 VMA_RDQS6 C425 EV@22u/6.3V_8
V25 FBA_WCK67 FBA_DQS_RN7 T27 VMA_RDQS7
EV@HCB1608KF/1A/30ohm_6 PLACE CLOSE TO BGA
+1.05V_GFX L13
EV@22u/6.3V_8 C167
F16 FB_PLLAVDD
+
EV@0.1u/10V_4 C108 *EV@330u/2V_7343 C41
EV@0.1u/10V_4 C160 +FB_PLLAVDD P22 FB_PLLAVDD
+
EV@330u/2V_7343 C446
EV@0.1u/10V_4 C87 +FB_PLLAVDD H22 FB_DLLAVDD GF119
C87 close ball H22 35mA FB_PLLAVDD GF117
A A
FB_VREF_PROBE D23

PROJECT : ZYW
3A
DGPU 2/5 (Memory)
5 4 3 2 1
5 4 3 2 1
<VGA> <HDM> <CRT>

U39G
4/14 IFPAB
GF117
NC
GF119
IFPA_TXC AC4
W5
U39K
3/14 DACA
GF119
DACA_VDD
GF117
NC
GF117
NC
NC
GF119
I2CA_SCL
I2CA_SDA
B7
A7
EV_CRTDCLK
EV_CRTDDAT
R75
R74
EV@2.2K_4
EV@2.2K_4
18
IFPA_TXC AC3 AE2 DACA_VREF
GF119 GF117 NC TSEN_VREF
AA6 IFPAB_RSET AF2 DACA_RSET DACA_HSYNC AE3
NC NC NC
IFPA_TXD0 Y3 DACA_VSYNC AE4
NC NC
IFPA_TXD0 Y4
NC
V7 IFPAB_PLLVDD NC DACA_RED AG3
NC
D IFPA_TXD1 AA2 D
NC
W7 IFPAB_PLLVDD IFPA_TXD1 AA3 DACA_GREEN AF4
NC NC NC
DACA_BLUE AF3
NC
NC IFPA_TXD2 AA1
IFPA_TXD2 AB1
NC
AA5 bga595-nvidia-n13p-gv2-s-a2 COMMON

NC IFPA_TXD3
NC IFPA_TXD3 AA4
U39I
6/14 IFPD
IFPB_TXC AB4
NC GF119 GF117
IFPB_TXC AB5
NC GF117 GF119
U6 IFPD_RSET NC
GF119 GF117
W6 AB2 DVI/HDMI DP
IFPA_IOVDD NC NC IFPB_TXD4
IFPB_TXD4 AB3
NC
Y6 IFPB_IOVDD T7 IFPD_PLLVDD I2CX_SDA IFPD_AUX P4
NC NC NC
NC I2CX_SCL IFPD_AUX P3
IFPB_TXD5 AD2 R7 IFPD_PLLVDD
NC NC
IFPB_TXD5 AD3
NC
IFPD_L3 R5
NC TXC
IFPD_L3 R4
NC TXC
NC IFPB_TXD6 AD1
IFPB_TXD6 AE1 IFPD_L2 T5
NC NC TXD0
IFPD_L2 T4
NC TXD0
IFPB_TXD7 AD5 TXD1 IFPD_L1 U4

NC NC
NC IFPB_TXD7 AD4 IFPD NC TXD1 IFPD_L1 U3
IFPD_L0 V4
NC TXD2
IFPD_L0 V3
NC TXD2
C C
NC GPIO14 B3
IFPAB R6 IFPD_IOVDD GF119 NC GPIO17 D4
NC GF117
U39H
5/14 IFPC
IFPC
GF119 GF117 U39J
T6 IFPC_RSET GF117 GF119
NC 7/14 IFPEF
DVI/HDMI DP GF119
GF117
M7 N5 DVI-DL DVI-SL/HDMI DP
IFPC_PLLVDD NC NC I2CW_SDA IFPC_AUX
N7 IFPC_PLLVDD NC I2CW_SCL IFPC_AUX N4 NC I2CY_SDA I2CY_SDA IFPE_AUX J3
NC GF119 GF117
NC I2CY_SCL I2CY_SCL IFPE_AUX J2
J7 IFPEF_PLLVDD NC
IFPC_L3 N3
NC TXC
NC IFPC_L3 N2 IFPE_L3 J1
TXC NC TXC TXC
IFPE_L3 K1
NC TXC TXC
IFPC_L2 R3 K7 IFPEF_PLLVDD NC
NC TXD0
IFPC_L2 R2 IFPE_L2 K3
NC TXD0 NC TXD0 TXD0
IFPE_L2 K2
NC TXD0 TXD0
TXD1 IFPC_L1 R1
NC
NC TXD1 IFPC_L1 T1 K6 IFPEF_RSET IFPE_L1 M3
NC NC TXD1 TXD1
IFPE_L1 M2
NC TXD1 TXD1
IFPC_L0 T3
B NC TXD2 B
IFPC_L0 T2 IFPE_L0 M1
NC TXD2 NC TXD2 TXD2
IFPE_L0 N1
NC TXD2 TXD2
P6 IFPC_IOVDD NC NC GPIO15 C3 IFPE
bga595-nvidia-n13p-gv2-s-a2 COMMON GPIO18 C2

NC HPD_E HPD_E
GF119 GF117
H6 IFPE_IOVDD NC
GF119
U39M J6 IFPF_IOVDD GF117
NC DVI-DL DVI-SL/HDMI DP
NV_PLLVDD 0.3MM=12mils 78mA 9/14 XTAL_PLL
NC IFPF_AUX H4
I2CZ_SDA
+1.05V_GFX L11 EV@HCB1608KF/1A/30ohm_6 NV_PLLVDD L6 PLLVDD NC I2CZ_SCL IFPF_AUX H3
M6 SP_PLLVDD
C125 C132
EV@22u/6.3V_8 EV@0.1u/10V_4 SP_VID_PLLVDD N6 VID_PLLVDD NC TXC IFPF_L3 J5
GF119
Near GPU Under GPU NC TXC IFPF_L3 J4
NC GF117
GPU_SP_PLLVDD 0.3MM=12mils NC TXD3 TXD0 IFPF_L2 K5
+1.05V_GFX L12 EV@BLM15PX181SN1D(180,1.5A)_4 NC IFPF_L2 K4
TXD3 TXD0
R415 EV@10K/F_4 R416 EV@10K/F_4
C147 C145 A10 XTALSSIN XTALOUTBUFF C10 NC TXD4 TXD1 IFPF_L1 L4
C135 C138 IFPF NC TXD4 TXD1 IFPF_L1 L3
EV@22u/6.3V_8 EV@4.7u/6.3V_6 EV@0.1u/10V_4 CLK_27M_VGA_2 C11 XTALIN XTALOUT B10 XTALOUT IFPF_L0 M5
NC TXD5 TXD2
EV@0.1u/10V_4 IFPF_L0 M4
bga595-nvidia-n13p-gv2-s-a2 COMMON NC TXD5 TXD2
A close to balls one by one ball A
NC HPD_F GPIO19 F7
CLK_27M_VGA_2
XTALOUT Y6
1 3
2 4
C64 EV@27MHZ C60

EV@10p/50V_4 EV@10p/50V_4
PROJECT : ZYW
3A
DGPU 3/5 (Display)
5 4 3 2 1
5 4 3 2 1
<VGA> Logical Logical Logical Logical

Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
19
U39L
10/14 MISC2 ROM_SO DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE 1000
ROM_SCLK SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED 0010
E10 VMON_IN0 ROM_SI RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0] XXXX
F10 VMON_IN1 ROM_CS D12 R56 EV@10K_4 +3V_GFX
STRAP0 USER[3] USER[2] USER[1] USER[0] 1111
ROM_SI B12 ROM_SI
ROM_SO A12 ROM_SO STRAP1 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0] 0000
STRAP0 D1 STRAP0 ROM_SCLK C12 ROM_SCLK
STRAP1 D2 STRAP1 STRAP2 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] 0100
D STRAP2 E4 STRAP2 D
STRAP3 E3 STRAP3 STRAP3 SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED 0000
STRAP4 D3 STRAP4
STRAP4 RESERVED PCIE_SPEED_CHANGE_GEN3 PCIE_MAX SPEED DP_PLL_VDD33 0111
GF119 GF117
C1 STRAP5_NC +3V_GFX
NC
D11 R425 *EV@10K_4 +3V_MAIN
R3 BUFRST
R418 EV@840@40.2K/F_4 F6 MULTISTRAP_REF0_GND PGOOD D10

N15V-GM NC N15S-GT Stuff 50K
N15P-GT Stuff GF119 GF117
R58 R52 N15P-GT Stuff 50K R419 STRAP1~4: Reserve footprint for pull-up to 3V3_AON and pull-down to forward.
N15S-GT Stuff R66 R55 R61 R421 N15P-GT: NC
R747 *EV@40.2K F4 MULTISTRAP_REF1_GND NC R59 EV@840@49.9K/F_4_820@10K-check N15S-GT: NC
CEC E9 EV@820@10K/F_4-check *EV@10K/F_4
F5 SYS_PEX_RST_MON# 16 STRAP0
R748 *EV@40.2K MULTISTRAP_REF2_GND NC *EV@4.99K/F_4 *EV@4.99K/F_4 *EV@4.99K/F_4 EV@820@10K/F_4-check STRAP0~3:
ROM_SI STRAP1 EV@820@10K/F_4-check N15V-GM: Memory strap setting Please follow N15x latest RVL "RVL-06891-001".
ROM_SO STRAP2
ROM_SCLK STRAP3
bga595-nvidia-n13p-gv2-s-a2 COMMON STRAP4
U39N R49 R53

8/14 MISC1 I2CS Slave Address= 0x9E (default) R420 R65 R54 R60 R422
I2CS_SCL D9 GFX_SCL EV@840@820-10k@4.99K/F_4
I2CS_SDA D8 GFX_SDA R64 EV@840@820-10k@4.99K/F_4 EV@820@10K/F_4-check EV@820@10K/F_4-check EV@820@10K/F_4
EV@820@10K/F_4-check EV@820@10K/F_4-check N15V-GM Stuff 10K
I2CC_SCL A9 DGPU_EDIDCLK EV@2.2K_4 R438 N15S-GT Stuff 4.99K
I2CC_SDA B9 DGPU_EDIDDATA EV@2.2K_4 R434 N15P-GT Stuff 4.99K
EV@840@HY@SA-15k@820-10k@4.99K/F_4 N15V-GM Stuff 10K
E12 THERMDN GF117 GF119
C9 N13P_SCL EV@2.2K_4 R79
F12 THERMDP
NC
NC
I2CB_SCL
I2CB_SDA C8 N13P_SDA EV@2.2K_4 R77 Mutil-level mode strapping: Logical Strap Bit Mapping
C ROM_SI: C
R76 EVG@0_4 N15P-GT: For N15P-GT & N15S-GT : PU-VDD PD
JTAG_TCK AE5 JTAG_TCK N15S-GT:
JTAG_TMS AD6 Please follow N15x latest RVL
JTAG_TDI AE6
JTAG_TMS
JTAG_TDI FB_CLAMP_MON 1 3 R84 EVG@0_4
EC_FB_CLAMP17,20,33 N15V-GM: R3=40.3k pull down. 4.99K 1000 0000
JTAG_TDO AF6 R83 *EVG@0_4
TP82 JTAG_TRST#AG4
JTAG_TDO
JTAG_TRST GPIO0 C6 Q14
GC6_FB_EN 10,20 Stuff 10K pull down 1.ROM_SCLK =4.99K pull down 10K 1001 0001
GPIO1 B2 *EVG@2N7002K +3V_GFX 2.ROM_SO = 4.99K pull down 15K 1010 0010
2
D6 R70 *EVG@0_4
+3V_GFX
GPIO2
C7 *EV@10K/F_4 3.ROM_SI= Memory strap setting
GPIO3
GPIO4 F9 +3V_GFX 3.STRAP0 = 50k Pull pu. 20K 1011 0011
GPIO9_ALERT R774 EV@10K/F_4 A3 3V_MAIN_EN R69
GPIO5
GPIO6 A4
3V_MAIN_EN 20
FB_CLAMP_REQ#_R 1 3 4.Strap4~1 = reserve Pull up 24.9K 1100 0100
DGPU_PSI R423 *EV@10K/F_4 B6
GPIO7
GPIO8 A6 GPIO8_OVERT# R78 Q15 and Pull down 30.1K 1101 0101
GPIO8_OVERT#R427 EV@10K/F_4 F8 GPIO9_ALERT *EVG@2N7002K
GPIO9
34.8K 1110 0110
2
GPIO10 C5
JTAG_TMS R110 *EV@10K/F_4 E7 EVG@10K/F_4 R71 *EVG@0_4
GPIO11
GPIO12 D7 GPIO12_ACIN
PWM-VID 40 FB_CLAMP_REQ# 33 Binary mode strapping: 45.3K 1111 0111
JTAG_TDI R109 *EV@10K/F_4 B4 VGPU_PSI R72 *EVG@0_4
GPIO13 DGPU_PSI 40 DGPU_EVENT# 10 For N15V-GM-B sku:
GPIO12_ACIN R432 EV@10K/F_4
GF117 GF119
+3V_GFX Board_ID0= STRAP3
GPU_PEX_RST_HOLD#R437 EV@10K/F_4 GPIO16 D5 H=N15V-GM,L=N15V-GL Optimus ---> 4.99k PD
NC
E6
JTAG_TCK R112 *EV@10K/F_4
NC GPIO20
GPIO21 C4 GPU_PEX_RST_HOLD# SMBus(VGA) Device ID=0x1140
NC GPU_PEX_RST_HOLD# 16
JTAG_TRST#
GPIO21 N15x for GC6
+3V_GFX
R3= N.C. Resistor P/N
R111 EV@10K/F_4 +3V_MAIN
1.ROM_SCLK =10K pull down. 4.99K---> CS24992FB26
EC_FB_CLAMP R85 EV@10K/F_4 2.ROM_SI= 10k pull down 10K ---> CS31002FB26
3.ROM_SO= 10k pull down 15K ---> CS31502FB24

R439 R442 20K ---> CS32002FB29
B
GPIO8 VGA thrmtrip# => inform EC EV@10K/F_4 4.Strap3~0 = RVL memory 24.9K---> CS32492FB16 B
over temperature protect dGPU_OPP# = EC control EV@10K/F_4 Q40

5
binary mode setting. 49.9K--> CS34992FB10
GPIO12_ACIN 1 3
dGPU_OPP# 33
5.Strap4 =10k pull down 30.1K---> CS33012FB18
GPIO8_OVERT# 1 3
dGPU_OTP# 33
GFX_SCL 4 3
2ND_MBCLK 8,24,33 34.8K---> CS33482FB22
Q39 GPIO12 AC detect 45.3K---> CS34532FB18
+3V_GFX Q38 EV@2N7002K EV@2N7002K AC high
2
DC low 2 N15P-GT/ N15S-GT VRAM Configuration Table

2
dGPU_OTP# = EC control
GFX_SDA 1 6
2ND_MBDATA 8,24,33
R428 *EV@0_4 R433 *short_EV@0_4 ROM_SI DESCRIPTION Vendor Vendor P/N QCI P/N
PEGX_RST# 16
+3V_GFX VGA/VGA EC/S5
EV@2N7002DW 0000 (0x0) DDR3 256MBx16,1000MHz HYNIX H5TC4G63AFR-11C AKD5PGWTW13
4Gb 0001 (0x1) DDR3 256MBx16,1000MHz MICRON MT41J256M16HA-093G:E
0010 (0x2) DDR3 256MBx16,1000MHz SAMSUNG K4W4G1646D-BC1A
0110 (0x6) DDR3 128MBx16,1000MHz HYNIX H5TC2G63FFR-11C AKD5MZDTW05
2Gb 0111 (0x7) DDR3 128MBx16,1000MHz MICRON MT41J128M16JT-093G:K
1000 (0x8) DDR3 128MBx16,1000MHz SAMSUNG K4W2G1646Q-BC1A
N15V-GM VRAM Configuration Table:

Strap
[3:0] DESCRIPTION Vendor Vendor P/N QCI P/N
0100 (0x4) DDR3 256MBx16,1000MHz HYNIX H5TC4G63AFR-11C
4Gb 1101 (0xD) DDR3 256MBx16,1000MHz MICRON MT41J256M16HA-093G:E
1001 (0x9) DDR3 256MBx16,1000MHz SAMSUNG K4W4G1646D-BC1A
1110 (0xE) DDR3 128MBx16,1000MHz SAMSUNG K4W2G1646Q-BC1A
0001 (0x1) DDR3 128MBx16,1000MHz MICRON MT41J128M16JT-093G:K
A 2Gb 0101 (0x5) DDR3 128MBx16,1000MHz SAMSUNG K4W2G1646E-BC1A A
1100 (0xC) DDR3 128MBx16,1000MHz HYNIX H5TC2G63FFR-11C
Brand Name DevID
N15P-GT-A2 GeForce GTX 850M 0x1391

Vendor P/N QCI P/N
N15S-GT-B-A2 GeForce 840M 0x1341 Quanta Computer Inc.
840M N15S-GT-B-A2 AJ0N15S0T04
820M N15V-GM-B-A2 AJ0N15V0T03 N15V-GM-B-A2 GeForce 820M 0x1140
PROJECT : ZYW
3A
DGPU 4/5 (MIO/GPIO)
5 4 3 2 1
5 4 3 2 1
20
3V MAIN POWER
+3V_GFX +3V_GFX
D D
+3V_GFX R44 C62 60mil

*EV@10K_4
1
*EV@0.022U/25V_4
R73
EV@NGC6@0_8
R39 R46 *EV@200K_4 2
EV@10K_4
3
*EV@AO3413 60mil
Q12 Q13 +3V_MAIN
3
C69
19 3V_MAIN_EN 2
*EV@0.022U/25V_4
N15V stuff not support GC6.
*EV@2N7002E 1A-7 2013/10/21 add R5331 for not GC6 support.
1
+3V_GFX
+3V
R40
EV@4.7K_4
C C
R36 3V_MAIN_PWGD
3V_MAIN_PWGD 40,41
EV@4.7K_4
3
R41
2 EV@100K/F_4
3
+3V_MAIN R51 EV@4.7K_4 2

C56 Q10
1
Q9 EV@1000p/50V_4 EV@DTC144EU
1
C61 EV@MMBT3904-7-F
*EV@1000p/50V_4 +1.05V_GFX and GPU core power EN
+3V
+3V
C164
EV@0.1u/10V_4
C155
B B
GC6 need system 3V to control FBVDDQ
EV@0.1u/10V_4
5
U8 2 R108 *short_4
HWPG_1.5VGFX 41
5
DGPU_PWROK 4 R100 *EV@0_4
10 DGPU_PWROK GC6_FB_EN 10,19
1 GPU_PWR_GD GPU_PWR_GD 40
2 R102 EV@0_4 EC_FB_CLAMP 17,19,33
4
41 FBVDDQ_EN
3
EV@MC74VHC1G08DFT2G 1 GPU_PWR_GD_R R106 *Short_EV@0_4 GPU_PWR_GD
R107 R101 PD at GPU power side

EV@100K_4 EV@100K_4 U7 EV@SN74AHC1G32DCKR
3
C158 *EV@0.1u/10V_4
*EV@0_4 R105
A A

PROJECT : ZYW
3A
DGPU 5/5 (Power/Ground)
5 4 3 2 1
5 4 3 2 1
17
17
17
17
VMA_DQ[63..0]
VMA_DM[7..0]
VMA_WDQS[7..0]
VMA_RDQS[7..0] CHANNEL A: 1024MB DDR3X16
21
VRAM8 VRAM12 VRAM9 VRAM13
VREFC_VMA1 M8 E3 VMA_DQ12 VREFC_VMA1 M8 E3 VMA_DQ21 VREFC_VMA3 M8 E3 VMA_DQ40 VREFC_VMA3 M8 E3 VMA_DQ62

VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ9 VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ19 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ45 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ58
VREFDQ DQL1 F2 VMA_DQ13 VREFDQ DQL1 F2 VMA_DQ20 VREFDQ DQL1 F2 VMA_DQ41 VREFDQ DQL1 F2 VMA_DQ63
FBA_CMD9 N3 DQL2 F8 VMA_DQ11 FBA_CMD9 N3 DQL2 F8 VMA_DQ18 FBA_CMD9 N3 DQL2 F8 VMA_DQ47 FBA_CMD9 N3 DQL2 F8 VMA_DQ56
D 17 FBA_CMD9 P7 A0 DQL3 H3 P7 A0 DQL3 H3 P7 A0 DQL3 H3 P7 A0 DQL3 H3 D
FBA_CMD11 VMA_DQ14 FBA_CMD11 VMA_DQ23 FBA_CMD11 VMA_DQ43 FBA_CMD11 VMA_DQ61
17 FBA_CMD11 P3 A1 DQL4 H8 P3 A1 DQL4 H8 P3 A1 DQL4 H8 P3 A1 DQL4 H8
17 FBA_CMD8 A2 DQL5 A2 DQL5 A2 DQL5 A2 DQL5
FBA_CMD25 N2 G2 VMA_DQ15 FBA_CMD25 N2 G2 VMA_DQ22 FBA_CMD25 N2 G2 VMA_DQ42 FBA_CMD25 N2 G2 VMA_DQ60
17 FBA_CMD25 P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7
17 FBA_CMD10 P2 A4 DQL7 P2 A4 DQL7 P2 A4 DQL7 P2 A4 DQL7
FBA_CMD24 FBA_CMD24 FBA_CMD24 FBA_CMD24
17 FBA_CMD24 R8 A5 R8 A5 R8 A5 R8 A5
17 FBA_CMD22 R2 A6 D7 R2 A6 D7 R2 A6 D7 R2 A6 D7
17 FBA_CMD7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
FBA_CMD21 T8 C3 VMA_DQ0 FBA_CMD21 T8 C3 VMA_DQ24 FBA_CMD21 T8 C3 VMA_DQ39 FBA_CMD21 T8 C3 VMA_DQ48
17 FBA_CMD21 R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8 R3 A8 DQU1 C8
FBA_CMD29 L7 C2 VMA_DQ3 FBA_CMD29 L7 C2 VMA_DQ26 FBA_CMD29 L7 C2 VMA_DQ37 FBA_CMD29 L7 C2 VMA_DQ50
17 FBA_CMD29 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7 R7 A10/AP DQU3 A7
FBA_CMD28 N7 A2 VMA_DQ2 FBA_CMD28 N7 A2 VMA_DQ27 FBA_CMD28 N7 A2 VMA_DQ36 FBA_CMD28 N7 A2 VMA_DQ51
17 FBA_CMD28 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
FBA_CMD20 T3 B8 VMA_DQ6 FBA_CMD20 T3 B8 VMA_DQ29 FBA_CMD20 T3 B8 VMA_DQ32 FBA_CMD20 T3 B8 VMA_DQ52
17 FBA_CMD20 T7 A13 DQU6 A3 T7 A13 DQU6 A3 T7 A13 DQU6 A3 T7 A13 DQU6 A3
17 FBA_CMD4 M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7 M7 A14 DQU7
17 FBA_CMD14 A15 A15 A15 A15
FBA_CMD12 M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2

17 FBA_CMD12 N8 BA0 VDD#B2 D9 +1.5V_GFX N8 BA0 VDD#B2 D9 N8 BA0 VDD#B2 D9 +1.5V_GFX N8 BA0 VDD#B2 D9
17 FBA_CMD27 M3 BA1 VDD#D9 G7 M3 BA1 VDD#D9 G7 M3 BA1 VDD#D9 G7 M3 BA1 VDD#D9 G7
17 FBA_CMD26 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
VMA_CLK0 J7 VDD#N1 N9 VMA_CLK0 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9
17 VMA_CLK0 CK VDD#N9 CK VDD#N9 17 VMA_CLK1 CK VDD#N9 CK VDD#N9
17 VMA_CLK0# VMA_CLK0# K7 R1 VMA_CLK0# K7 R1
17 VMA_CLK1# VMA_CLK1# K7 R1 VMA_CLK1# K7 R1
FBA_CMD3 K9 CK VDD#R1 R9 FBA_CMD3 K9 CK VDD#R1 R9 FBA_CMD19 K9 CK VDD#R1 R9 FBA_CMD19 K9 CK VDD#R1 R9 +1.5V_GFX
17 FBA_CMD3 CKE VDD#R9 CKE VDD#R9 +1.5V_GFX 17 FBA_CMD19 CKE VDD#R9 CKE VDD#R9
FBA_CMD2 K1 A1 FBA_CMD2 K1 A1 FBA_CMD18 K1 A1 FBA_CMD18 K1 A1

17 FBA_CMD2 ODT VDDQ#A1 ODT VDDQ#A1 17 FBA_CMD18 ODT VDDQ#A1 ODT VDDQ#A1
C FBA_CMD0 L2 A8 FBA_CMD0 L2 A8 FBA_CMD16 L2 A8 FBA_CMD16 L2 A8 C
17 FBA_CMD0 J3 CS VDDQ#A8 C1 J3 CS VDDQ#A8 C1 17 FBA_CMD16 J3 CS VDDQ#A8 C1 J3 CS VDDQ#A8 C1
17 FBA_CMD30 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
FBA_CMD15 K3 C9 FBA_CMD15 K3 C9 FBA_CMD15 K3 C9 FBA_CMD15 K3 C9
17 FBA_CMD15 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9
FBA_CMD13 L3 D2 FBA_CMD13 L3 D2 FBA_CMD13 L3 D2 FBA_CMD13 L3 D2
17 FBA_CMD13 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
VMA_WDQS1 F3 VDDQ#F1 H2 VMA_WDQS2 F3 VDDQ#F1 H2 VMA_WDQS5 F3 VDDQ#F1 H2 VMA_WDQS7 F3 VDDQ#F1 H2
VMA_RDQS1 G3 DQSL VDDQ#H2 H9 VMA_RDQS2 G3 DQSL VDDQ#H2 H9 VMA_RDQS5 G3 DQSL VDDQ#H2 H9 VMA_RDQS7 G3 DQSL VDDQ#H2 H9
DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9
VMA_DM1 E7 A9 VMA_DM2 E7 A9 VMA_DM5 E7 A9 VMA_DM7 E7 A9

VMA_DM0 D3 DML VSS#A9 B3 VMA_DM3 D3 DML VSS#A9 B3 VMA_DM4 D3 DML VSS#A9 B3 VMA_DM6 D3 DML VSS#A9 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
VMA_WDQS0 C7 VSS#G8 J2 VMA_WDQS3 C7 VSS#G8 J2 VMA_WDQS4 C7 VSS#G8 J2 VMA_WDQS6 C7 VSS#G8 J2
VMA_RDQS0 B7 DQSU VSS#J2 J8 VMA_RDQS3 B7 DQSU VSS#J2 J8 VMA_RDQS4 B7 DQSU VSS#J2 J8 VMA_RDQS6 B7 DQSU VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9
17 FBA_CMD5 RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1
VMA_ZQ1 L8 VSS#T1 T9 VMA_ZQ2 L8 VSS#T1 T9 VMA_ZQ3 L8 VSS#T1 T9 VMA_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R63 VSSQ#B9 D1 R426 VSSQ#B9 D1 R94 VSSQ#B9 D1 R446 VSSQ#B9 D1
VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8
EV@243/F_4 VSSQ#D8 EV@243/F_4 VSSQ#D8 EV@243/F_4 VSSQ#D8 EV@243/F_4 VSSQ#D8
E2 E2 E2 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
B
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 B
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
EV@VRAM _DDR3_HYNIX_256MX16 EV@VRAM _DDR3_HYNIX_256MX16 EV@VRAM _DDR3_HYNIX_256MX16 EV@VRAM _DDR3_HYNIX_256MX16
+1.5V_GFX +1.5V_GFX FBA_CMD17 TP12 +1.5V_GFX +1.5V_GFX

17 FBA_CMD17
FBA_CMD1 TP10
17 FBA_CMD1
10/14 modify
VMA_CLK0 R429 R38 R93 R453
EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4
R45 VMA_CLK1
EV@162/F_4
VREFC_VMA1 VREFD_VMA1 R96 VREFC_VMA3 VREFD_VMA3
VMA_CLK0# EV@162/F_4
Fermi : Change to 160 ohm C473 VMA_CLK1# C130 C512

R430 R43 C59 R90 EV@0.1u/10V_4 R452 EV@0.1u/10V_4
1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402) EV@0.1u/10V_4 EV@0.1u/10V_4
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402) Fermi : Change to 160 ohm
EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4
1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402)
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)
+1.5V_GFX
A +1.5V_GFX A
C458 EV@10u/6.3V_6 C518 EV@10u/6.3V_6 +1.5V_GFX
+1.5V_GFX C466 EV@1u/10V_4 C166 EV@10u/6.3V_6 C51 EV@10u/6.3V_6

C514 EV@1u/10V_4
+1.5V_GFX C75 EV@10u/6.3V_6 C163 EV@1u/10V_4 C465 EV@0.1u/10V_4 C457 EV@10u/6.3V_6
C170 EV@1u/10V_4
C528
C471
EV@1u/10V_4
EV@1u/10V_4 C83 EV@1u/10V_4
C470
C527
EV@0.1u/10V_4
EV@0.1u/10V_4
C517 EV@1u/10V_4 C505 EV@1u/10V_4 C149 EV@1u/10V_4 C509 EV@0.1u/10V_4
C161 EV@1u/10V_4 C467 EV@1u/10V_4 C55 EV@1u/10V_4 C469 EV@0.1u/10V_4 C156 EV@0.1u/10V_4 PROJECT : ZYW
C510 EV@1u/10V_4 C54 EV@1u/10V_4 C468 EV@1u/10V_4 C151 EV@0.1u/10V_4 C57 EV@0.1u/10V_4 Size Document Number Rev
3A
N15P- DDR3 VRAM 1/2
5 4 3 2 1
5 4 3 2 1
22
D D
C C
B B
A A

PROJECT : ZYW
3A
N13P DDR3 VRAM 2/2
5 4 3 2 1
5 4 3 2 1
DP TO VGA
23
30mils
+3V
L8 80ohm@100MHz
C482 C96
C100
1u/6.3V_4 0.1u/10V_4 0.1u/10V_4
D L33 80ohm@100MHz D
link L5031 to +3V directly

(meet IVDDO vs OVDD sequence) 20mils
C504
10u/6.3V_6 RX_DVDD18
C110
C102 0.1u/10V_4 C483
0.1u/10V_4 0.1u/10V_4
ISPSCL
IVDDO
ISPSDA
13
48
35
36
38
39
12
14
44
46
U27
1
2
20mils
IVDDO
IVDDO
OVDD
OVDD
IVDD
IVDD
IVDD
IVDD
DDCSCL
IVDD33
IVDD33
DDCSDA
2 CRT_HPD CRT_HPD 40 MCUVDDH +5V
HPD
45 MCUVDDH 80ohm@100MHz L10
C503 0.1u/10V_4 CRT_TXP0_C 26 MCUVDDH
2 CRT_TXP0 RX0P
C502 0.1u/10V_4 CRT_TXN0_C 27
2 CRT_TXN0 RX0N
C501 0.1u/10V_4 CRT_TXP1_C 29 47
2 CRT_TXP1 RX1P MCURSTN
C500 0.1u/10V_4 CRT_TXN1_C 30
2 CRT_TXN1 RX1N
28 URDBG
URDBG TP13
+3V
15 ISPSCL R440 22/J_4 DDCCLK DDCCLK 26
ISPSCL 16 ISPSDA R443 22/J_4 DDCDAT
ISPSDA DDCDAT 26
*1M_4 R89 CRT_AUXP CRT_AUXP C489 0.1u/10V_4 CRT_AUXP_C 20
2 CRT_AUXP RXAUXP
CRT_AUXN C487 0.1u/10V_4 CRT_AUXN_C 19 23 R81 22/J_4 DDCCLK
2 CRT_AUXN RXAUXN VGADDCCLK
*1M_4 R87 CRT_AUXN 21 R82 22/J_4 DDCDAT
VGADDCSDA
18 3 VSYNC VSYNC 26
17 DCAUXP VSYNC 4 HSYNC
DCAUXN HSYNC HSYNC 26 20mils
DAC_VDDC 80ohm@100MHz L9 IVDDO_18
C478 C479
C C
IVDDO 30mils C477
20mils 10mils 25 10 0.1u/10V_4 0.1u/10V_4
L31 80ohm@100MHz IVDDO_18 31 AVCC VDDC 0.1u/10V_4
0.1u/10V_4 C123 AVCC
C493
10u/6.3V_6 C122
10mils
22
PVCC
IT6513FN
1u/6.3V_4 0.1u/10V_4 C499 11 CRT_RED CRT_RED 26
IORP
9 CRT_GRE CRT_GRE 26
IOGP
L32 80ohm@100MHz RX_DVDD18 24
0.1u/10V_4 C494 DVDD18 8 CRT_BLU
IOBP CRT_BLU 26
C495
10mils 41
4.7u/6.3V_6 NC/VGADETECT
10mils 5 VGA_RST R435 100/F_4
32 RSET
0.1u/10V_4 C121 ASPVCC
7 DAC_VDDC
VDDA C475 C476
20mils
6 VGA_COMP 0.1u/10V_4 0.1u/10V_4
2.2K_4 R86 43 COMP
MCUVDDH PCSDA
2.2K_4 R444 42
PCSCL 34 27M_CRT_IN
XTALIN 33 27M_CRT_OUT Y10
change power net name from +5V to MCUVDDH XTALOUT
PWDNB
1 3
2 4
GND
C498 *27MHZ C497
IT6513N-QFN-48 *10p/50V_4 *10p/50V_4
37
49
MCUVDDH R88 10K_4

FAE: the current firmware we built in iT6513
Add R5501 by FAE syggestion were all enabled embedded crystal function.
B B
TPM (TPM)
NPCT650AA0WX infromation:
R761 TPM_I@0_4 TPM_VDD

TPM_VDD R760 TPM_N@0_4 NOTE:
TPM_VSB
1) The PP is an input signal with configurable polarity.
2) By default the PP functionality is disabled.
NOTE:
GPX signal is connected to the TCS_EN signal
of the PCI Express Root Complex of chipset.
24
19
10
U11
5
NOTE:
VDD3
VDD2
VDD1
VSB
GPIO_IF[0..3], GPX and PP are optional.

Leave them open if not used.
R763 TPM_I@4.7K_4
17 7 R762 *TPM_I@4.7K_4 TPM Power Sequence
8,27,33 LPC_LAD3 LAD3 PP
20 6 R764 *TPM_I@20K_4 TPM_VDD
8,27,33 LPC_LAD2 LAD2/SPI_IRQ GPX/GPIO2 5 ms < t
23 2 TP147
8,27,33 LPC_LAD1 LAD1/MOSI GPIO1
26
8,27,33 LPC_LAD0 LAD0/MISO
22 1 TP148 SLB9665 PIN9 NC
8,27,33 LPC_LFRAME# LFRAME/SCS GPIO0/XOR_OUT VSB 0 < t
10,33 IRQ_SERIRQ R757 TPM@0_4 27 9 R765 TPM_I@0_4 PLTRST#
R756 TPM@0_4 21 SERIRQ GPIO3/BADD 8 R766 *TPM_N@10K_4
9 PCLK_TPM LCLK/SCLK TEST
C673 *TPM@10p/50V_4
15 3 VDD 0 ms < t
16 CLKRUN/GPIO04 NC1 12
R758 TPM_N@0_4 28 LRESET/SPI_RST NC2 13
7,33 CLKRUN# LPCPD NC3 LRESET#
14
PLTRST# NC4
7,13,16,27,29,30,33 PLTRST#
GND1
GND2
GND3
GND4
NOTE:
1) It is recommended to connect the TPM to the system's
7 LPCPD# standby voltage to improve performance.
D35 TPM_N@RB500V-40 TPM@NPCT620/650_TSSOP28
4
11
18
25
2) If only one power plane is available in the system,

connect both VSB and VDD to that power source.
AL000650K00 : NPCT650AA0WX 3) LRESET# must be asserted for at least 5 msec after
AL009655K01 : SNI SLB9655TT1.2 VSB power-up.
A
4) VSB may come up anytime before VDD power-up, A
but not after VDD power-up.
GPIO_IF3
BADD SELECTION
0 EEh - EFh
TPM_VSB 1 7Eh - 7Fh
TPM_VDD R768 *TPM_N@0_4
+3VSUS
+3V_S5 R769 TPM_N@0_4 '1' - pin is left open.
R767 TPM@2.2_6 '0' - pin is pulled down.
+3V
C704 C709
C674 C706 C708 C707 C705 TPM_N@10u/6.3V_6 TPM_N@0.1U/10V_4
TPM@10u/6.3V_6 TPM@0.1U/10V_4 TPM@0.1U/10V_4 TPM@0.1U/10V_4 TPM@0.1U/10V_4
PROJECT : ZYW
3A
Mini DP/HD3SS2521
5 4 3 2 1
5 4 3 2 1
R396 LVD@0_4
24
INT_LVDS_EDIDCLK 25
R392 LVD@0_4
0912 Need to PU 4.7K to +3V on IC or conn side
INT_LVDS_EDIDDATA 25
INT_TXLOUT0- 25
INT_TXLOUT0+ 25
INT_TXLOUT1- 25
INT_LVDS_BL_EN
D INT_TXLOUT1+ 25 D
2136_CFG1
2136_CFG0
VCCK_V12
MIICSDA
MIICSCL
INT_TXLOUT2- 25
INT_TXLOUT2+ 25 INT_LVDS_BL_EN INT_LVDS_BL_EN 25

R393 *LVD@100K_4
49
48
47
46
45
44
43
42
41
40
39
38
37
U22
LVDS_PWM_2136
MODE_CFG1
MODE_CFG0
MIICSCL
EPAD_GND
BL_EN
TXO0+
TXO1+
TXO2+
TXO0-
TXO1-
TXO2-
MIICSDA
VCCK
LVDS_PWM_2136 25
R391 LVD@100K_4
2,25 EDP_HPD R405 LVD@1K_4 DP_HPD 1 36 INT_TXLCLKOUT- 25

DP_HPD TXOC- INT_LCDVCC_EN INT_LCDVCC_EN 25
R412 LVD@100K_4 TEST_MODE 2 35
TEST_MODE TXOC+ INT_TXLCLKOUT+ 25
C464 LVD@0.1U/10V_4 IV_EDP_AUXN 3 34
2 EDP_AUXN AUX_CH_N TXO3-
C463 LVD@0.1U/10V_4 IV_EDP_AUXP 4 33
2 EDP_AUXP AUX_CH_P TXO3+
AVCC33 5 32 INT_TXUOUT0- 25
R410 EDP@0_4 DP_V33 TXE0-
25 INT_eDP_AUXP
25 INT_eDP_AUXN R411 EDP@0_4 6 31 INT_TXUOUT0+ 25
2 EDP_TXP0 C462 LVD@0.1U/10V_4 IV_EDP_TXP0 7

DP_GND
LANE0_P
RTD2136N TXE0+
TXE1-
30
INT_TXUOUT1- 25
C461 LVD@0.1U/10V_4 IV_EDP_TXN0 8 29
2 EDP_TXN0 LANE0_N TXE1+ INT_TXUOUT1+ 25
C460 LVD@0.1U/10V_4 IV_EDP_TXP1 9 28
2 EDP_TXP1 LANE1_P TXE2- INT_TXUOUT2- 25
2 EDP_TXN1 C459 LVD@0.1U/10V_4 IV_EDP_TXN1 10 27 INT_TXUOUT2+ 25

LANE1_N TXE2+
VCCK_V12 11 26
SWR_VCCK/LDO_VCCK
DP_V12 TXEC- INT_TXUCLKOUT- 25
SWR_VDD/LDO_VDD
DP_REXT 12 25
DP_REXT TXEC+ INT_TXUCLKOUT+ 25
SWR_LX/LDO_FB
C 25 INT_eDP_TXN1 R406 EDP@0_4 C
PANEL_VCC
25 INT_eDP_TXP1 R407 EDP@0_4 C48 R404
PWMOUT
CIICSDA
CIICSCL
R408 EDP@0_4 LVD@0.1U/10V_4 LVD@12K/F_4
PWMIN
25 INT_eDP_TXN0
TXE3+
TXE3-
PVCC
GND
25 INT_eDP_TXP0 R409 EDP@0_4
LVD@RTD2136N
13
14
VCCK_V12 15
16
17
18
19
20
21
22
23
24
LVDS_PWM_2136
INT_LCDVCC_EN
CIICSDA
PWM_IN
CIICSCL
DVCC33
DVCC33
PIN17
+3V Close to chip
L7 LVD@HCB1608KF-221T20_2A AVCC33 Note: R388 LVD@0_4 2,25
PCH_BRIGHT
1. C1,C4,C7,C8,C9,C16 should be closed to chip
C49 C50 C52
2. C9 should be X5R material
LVD@10U/6.3V_6 LVD@0.1U/10V_4
LVD@0.1U/10V_4 3. R8 should be 12K olm with +/- 1% R387
20mil For PIN15 LVD@100K_4
4 Entire trace of Panel VCC should be wider than 80-mil
+3V
L27 LVD@HCB1608KF-221T20_2A DVCC33
30mil For PIN18 W/O Panel_VCC Output
C455 C456 C453 C454 C450
LVD@10U/6.3V_6 LVD@0.1U/10V_4 LVD@0.1U/10V_4

LVD@0.1U/10V_4 LVD@22U/6.3V_6
B B
Mode Configure Table(Power On Latch)

Dual Mode Regulator Configuration
CFG0
EEPROM Mode EP Mode 2.2-uH(L6) 0 Olm(R31)
0 1 In EEPROM mode, an additional EEPROM is needed. External device connect to DP2LVDS by SWR Connect NC
EEPROM should configure with following condition. Pin13/Pin14, I2C protocol is used LDO NC Connect
0 X EP MODE
CFG1
1- EEPROM with a size 8K-Byte Address=0x94&96x6A
1 ROM ONLY MODE EEPROM MODE SWR MODE
2- EEPROM device should be 2-byte addressing device To EC PIN17 L6 *LVD@TLPC3010C-4R7M VCCK_V12
ROM ONLY Mode : CFG0 4.7K pull low, CFG1 4.7K pull high 3- Slave address should configure as 0xA8
EP Mode : CFG0 4.7K pull high, CFG1 4.7K pull low CIICSCL 1 6
2ND_MBCLK 8,19,33
Q8A LVD@2N7002KDW_115MA R32 LVD@0_4 VCCK_V12 LDO MODE
EEPROM Mode : CFG0 4.7K pull high, CFG1 4.7K pull high +3V R37
2
*LVD@0.1U/10V_4 LVD@4.7K_4
+3V +3V C47
0918 FAE suggest
+3V SMbus connect to EC
8
U6
7
1. C18 10-uF capacitor should be X5R material
MIICSDA R31 *LVD@0_4 5 VCC WP 3 R42
A 2. Inductor should be withstand current >600-mA A
5
R399 R401 MIICSCL R33 *LVD@0_4 6 SDA A2 2 LVD@4.7K_4

4 SCL A1 1
GND A0 4 3
3. Capacitors should be closed to PIN17
*LVD@4.7K_4 LVD@4.7K_4 2136_CFG0 R397 *LVD@0_4 CIICSDA
2ND_MBDATA 8,19,33
2136_CFG1 R402 *LVD@0_4 *LVD@M24C64 Q8B LVD@2N7002KDW_115MA
2136_CFG0 2136_CFG1
VCCK_V12
R398 R400 I2C address=0xA8 C43 C46 C45

LVD@4.7K_4 *LVD@4.7K_4
LVD@22U/6.3V_6
LVD@0.1U/10V_4
LVD@0.1U/10V_4 Quanta Computer Inc.
PROJECT : ZYW
3A
eDP to LVDS
5 4 3 2 1
1 2 3 4 5 6 7 8
R390 LVD@0_8
LCD Power HALL IC
+3V
Backlight Control +3VPCU
+3VPCU +3V +3V R34

C445 U21 *100K_4 +3VPCU
1u/6.3V_4 5 1 LCDVCC LID#

IN OUT LID# 33
R749 R16 R30
4 C447 C451 C449 C448 C452 LID591#,EC intrnal PU AL009247000 -- BCD
IN 10K_4 *10K_4 10K_4 C10 1u/10V_4 AL009132001 -- ANC Main source
R389 LVD@0_8 3 *0.1u/10V_4 *2.2u/10V_6 0.1u/10V_4 0.01u/25V_4 22u/6.3V_8 D7 AL008251000 -- YBT 2nd
24 INT_LCDVCC_EN
1
ON/OFF 2
GND 1N4148WS
A A
EDP@G5243AT11U 2 LID#
R383 EDP@0_4 EDP_VDD_EN_R BL_ON
2 EDP_VDD_EN
2
R385 R395 EDP@0_4 PCH_BLON_R BL# HE6
2,33 PCH_BLON
APX9132H AI D21
3
5
3
*VPORT_6
100K_4
R394 LVD@0_4 2
24 INT_LVDS_BL_EN EC_FPBACK# 33
1
R29 Q7
DTC144EUA
1
100K_4 Q6
1
2N7002DW
eDP CONN CCD_PWR V_BLIGHT LVDS CONN CCD_PWR

VIN TP_PWR
C40 C22 C13 C8 C11 C6

C19 C9 C18 C17
0.1u/10V_4_X7R LVD@4.7u/25V_8 LVD@1000p/50V_4 LVD@0.1u/10V_4_X7R
4.7u/25V_8 1000p/50V_4 0.1u/10V_4_X7R 1000p/50V_4 LVD@1000p/50V_4
1000p/50V_4
B B
+3V
VIN +3V
V_BLIGHT
R11 *100K_4 EDP_AUX_C R14 *100K_4 CN8
R12 *100K_4 EDP_AUX#_C R15 *100K_4 MAX 1.5A R9 *short_6 R379 *LVD@10K_4 EDP_HPD CN7
G_5
R10 *short_6 V_BLIGHT
G_5
40 V_BLIGHT
39 R8 LVD@4.7K_4 INT_LVDS_EDIDCLK 40
38 +3V 39
C440 C12 37 R7 LVD@4.7K_4 INT_LVDS_EDIDDATA 38
*1u/6.3V_4 *1u/6.3V_4 36 C14 C15 37
LCDVCC 35 *LVD@1u/6.3V_4 *LVD@1u/6.3V_4 36
R28 *short_6 CCD_PWR 34 LCDVCC 35
+3V 33 34
CCD_PWR
32 33
R13 *short_6 TP_PWR 31 G_4 BL_ON 32
+5V 30 31 G_4
LVDS_PWM_2136
29 24 LVDS_PWM_2136 30
C16 *0.1u/10V_4_X7R 24 INT_LVDS_EDIDCLK INT_LVDS_EDIDCLK
PCH_BRIGHT 28 INT_LVDS_EDIDDATA 29
2,24 PCH_BRIGHT 27 24 INT_LVDS_EDIDDATA 28
BL_ON USB_CCD#_R
EDP_HPD 26 USB_CCD_R 27
2,24 EDP_HPD 25 26
INT_EDP_AUXP C20 .1U/16V_4 EDP_AUX_C 24 USB_EDP_CCD_R R382 LVD@0_4 USB_CCD_R INT_TXLOUT0- 25
24 INT_EDP_AUXP 23 24 INT_TXLOUT0- 24
INT_EDP_AUXN C21 .1U/16V_4 EDP_AUX#_C USB_EDP_CCD#_R R381 LVD@0_4 USB_CCD#_R 24 INT_TXLOUT0+ INT_TXLOUT0+
24 INT_EDP_AUXN 22 23
C444 .1U/16V_4 EDP_TX1_C 21 INT_TXLOUT1- 22
24 INT_EDP_TXP1 20 24 INT_TXLOUT1- 21
eDP 24 INT_EDP_TXN1 C443 .1U/16V_4 EDP_TX1#_C 24 INT_TXLOUT1+ INT_TXLOUT1+
19 20
R384 *short_4 INT_EDP_TXP0 C442 .1U/16V_4 EDP_TX0_C 18 INT_TXLOUT2- 19
24 INT_EDP_TXP0 17 24 INT_TXLOUT2- 18
CCD (FCM) INT_EDP_TXN0 C441 .1U/16V_4 EDP_TX0#_C 24 INT_TXLOUT2+ INT_TXLOUT2+
24 INT_EDP_TXN0 16 17
USB_EDP_CCD_R USB_EDP_CCD_R 15 INT_TXLCLKOUT- 16
9 USB_CCD 14 24 INT_TXLCLKOUT- 15
9 USB_EDP_CCD#_R CCD-USB USB_EDP_CCD#_R 24 INT_TXLCLKOUT+ INT_TXLCLKOUT+
C USB_CCD# 13 14 C
USB_TOUCH_R 12 INT_TXUOUT0- 13
11 24 INT_TXUOUT0- 12
Touch Panel USB_TOUCH#_R 24 INT_TXUOUT0+ INT_TXUOUT0+
R386 *short_4 10 G_1 11
TP77 I2C1_SDA_GPIO6_CONN 9 INT_TXUOUT1- 10 G_1
8 24 INT_TXUOUT1- 9
TP75 I2C1_SCL_GPIO7_CONN 24 INT_TXUOUT1+ INT_TXUOUT1+
7 8
TS_EN R369 *short_4 6 INT_TXUOUT2- 7
33 TS_EN 5 24 INT_TXUOUT2- 6
TP_RST# 24 INT_TXUOUT2+ INT_TXUOUT2+
R380 *short_4 TP76 4 5
Touch Panel (TSN) 3 INT_TXUCLKOUT- 4
10 GPIO8 2 24 INT_TXUCLKOUT- 3
24 INT_TXUCLKOUT+ INT_TXUCLKOUT+
1 2
G_0
9 USB_TOUCH_R
USB_TOUCH 1
G_0
9 USB_TOUCH#_R EDP@50398-04071-001
USB_TOUCH#
LVD@50398-04071-001
R378 *short_4
D D

PROJECT : ZYW
1A
LVDS/CAMERA/LID
1 2 3 4 5 6 7 8
5 4 3 2 1
HDMI
From PCH
C552 0.1u/10V_4 INT_HDMITX2N_C
2 INT_HDMITX2N
C553 0.1u/10V_4 INT_HDMITX2P_C
2 INT_HDMITX2P
2
2
INT_HDMITX1N
INT_HDMITX1P
C550 0.1u/10V_4 INT_HDMITX1P_C HDMI connector
2 INT_HDMITX0N
C561 0.1u/10V_4 INT_HDMITX0P_C
2 INT_HDMITX0P
C547 0.1u/10V_4 INT_HDMICLK+_C
2 INT_HDMICLK+
C546 0.1u/10V_4 INT_HDMICLK-_C
2 INT_HDMICLK-
CN12
D D
20
1
INT_HDMITX2P_C 1 SHELL1
R574 R576 R246 R243 R232 R230 R239 R236 2 D2+
INT_HDMITX2N_C 3 D2 Shield
470_4 470_4 470_4 470_4 470_4 470_4 470_4 470_4 INT_HDMITX1P_C 4 D2-
5 D1+
2
INT_HDMITX1N_C 6 D1 Shield
INT_HDMITX0P_C 7 D1-
8 D0+
INT_HDMITX0N_C 9 D0 Shield 23
EMI INT_HDMICLK+_C 10
11
D0-
CK+
GND
22
INT_HDMICLK-_C 12 CK Shield GND
3
INT_HDMITX2P_C 13 CK-
14 CE Remote
R583 *120/F_4 Q45 HDMI_DDCCLK_MB 15 NC
2 HDMI_DDCDATA_MB 16 DDC CLK
+3V +5V DDC DATA
INT_HDMITX2N_C Q22 17
3 1 HDMI_5V 18 GND
INT_HDMITX1P_C 2N7002K IN OUT 2 19 +5V
R581 GND HDMI_MB_HPD R192 *short_4 HP_DET_CN HP DET 21
1
R580 *120/F_4 *100K/F_4 AP2331SA-7 C213 SHELL2
1
*220p/50V_4 D13 HDMI connector
INT_HDMITX1N_C *EGA_4 D24 D25 D23
R178
INT_HDMITX0P_C 20K_4
*EGA_4 *EGA_4 *EGA_4
2
R594 *120/F_4
INT_HDMITX0N_C
INT_HDMICLK+_C +3V +5V
R575 *120/F_4
2
INT_HDMICLK-_C D11
RB501V-40 +3V +3V
C +3V HDMI-detect C
1
R557 R554 R203
2
2
2.2K_4 2.2K_4 1M_4
I2C 1
Q43
3 1 3
HDMI_DDCCLK_MB 2 INT_HDMI_HPD HDMI_MB_HPD
2N7002K Q20
2N7002K
+3V
+5V
2
D12
Power trace tracking
RB501V-40
+3V
From PCH 2,5,7,8,9,10,11,13,14,15,16,20,23,24,25,26,27,28,29,30,31,32,33,35,36,37,38,39,40,41 +3V

1
23,25,26,28,31,32,35,39 +5V
R571 R567
2 HDMI_DDCCLK_SW
2
2.2K_4 2.2K_4
Q44
1 3 HDMI_DDCDATA_MB
2 HDMI_DDCDATA_SW
2N7002K
B B
Q16 C95 *0.1u/10V_4

+5V 3 1
IN OUT 2
GND CRTVDD5 CN9
16
AP2331SA-7
6
L30 BLM18BB470_6 CRT_R1 1 11 CRT_11
23 CRT_RED TP11
7
+5V L29 BLM18BB470_6 CRT_G1 2 12 DDCDAT
23 CRT_GRE DDCDAT 23
8
L28 BLM18BB470_6 CRT_B1 3 13 CRTHSYNC
23 CRT_BLU 9
C85 4 14 CRTVSYNC
C488 C485 C480 C481 C484 C486 10
U40 0.1u/10V_4 R445 R441 R436 5 15 DDCCLK DDCCLK 23
75/F_4 75/F_4 75/F_4 5.6p/16V_4 5.6p/16V_4 5.6p/16V_4 5.6p/16V_4 5.6p/16V_4 5.6p/16V_4
1 5
OE# VCC CRT CONN
17
HSYNC 2 4 CRTHSYNC
23 HSYNC A Y
DDCDAT 2.2K_4 R424 CRTVDD5
3 DDCCLK 2.2K_4 R431
GND +5V
M74VHC1GT125DF2G C68 0.22u/6.3V_4
C668 C72 *220p/50V_4
U41 0.1u/10V_4 C82 0.1u/10V_4 CRTVDD5

A 2,5,7,8,9,10,11,13,14,15,16,20,23,24,25,26,27,28,29,30,31,32,33,35,36,37,38,39,40,41 +3V A
1 5 C63 10p/50V_4 CRTVSYNC
OE# VCC 23,25,26,28,31,32,35,39 +5V
C86 10p/50V_4 CRTHSYNC
VSYNC 2 4 CRTVSYNC
23 VSYNC A Y C474 *10p/50V_4 DDCCLK
3 C472 *10p/50V_4 DDCDAT

GND
M74VHC1GT125DF2G
PROJECT : ZYW
1A
HDMI (PS8101)
5 4 3 2 1
5 4 3 2 1
+WL_VDD +1.5V_WLAN
Mini Card 1 (MNC)
33 BT_POWERON
R608 *short_4
TP99
BT_PWRON_R
CL_RST1#_WLAN
51
49
CN13
Reserved +3.3V
52
50 +WL_VDD
500mA for +1.5V
+1.5V
26
PLTRST# R609 *DBG@0_4 CL_DATA1_WLAN 47 Reserved GND 48
7,13,16,23,27,29,30,33 PLTRST# Reserved +1.5V
9 R610 *DBG@0_4 CL_CLK1_WLAN 45 46 +3V R611 *short_8 +WL_VDD +1.5V_WLAN R240 *0_6
PCLK_DEBUG Reserved LED_WPAN#
no-stuff in ZYW B-stage 43 44
41 GND LED_WLAN# 42 C231
Debug +WL_VDD
39 +3.3Vaux LED_WWAN# 40
TP98
C580 C555 C558 C557 C554 C556
37 +3.3Vaux GND 38 USBP10_WLAN_L R584 *short_4 10u/6.3V_6 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *1000p/50V_4 *0.1u/10V_4 *10u/6.3V_8
GND USB_D+ USBP10_WLAN 9
35 36 USBP10_WLAN#_L R585 *short_4 9
GND USB_D- USBP10_WLAN#
D 9 33 34 D
PCIE_TXP_WLAN PETp0 GND
9 31 32 WLAN_CLK_SDATA *0_4 R586 CLK_SDATA 8,13,14,15
PCIE_TXN_WLAN# PETn0 SMB_DATA
29 30 WLAN_CLK_SCLK *0_4 R587 CLK_SCLK 8,13,14,15
27 GND SMB_CLK 28
25 GND +1.5V 26 +WL_VDD +WL_VDD
9 PCIE_RXP_WLAN PERp0 GND
9 23 24
PCIE_RXN_WLAN# PERn0 +3.3Vaux
21 22 R588 *short_4 PLTRST#
GND PERST# PLTRST# 7,13,16,23,27,29,30,33
19 20 RF_EN
UIM_C4 W_DISABLE# RF_EN 33
17 18 R283 R607
UIM_C8 GND Q46 4.7K_4 4.7K_4
CLK_PCIE_WLAN_C
15
13 GND UIM_VPP
16
14
A_LFRAME#_R
A_LAD3_R
R589
R590
*short_4
*short_4
LPC_LFRAME# 8,23,33 S0 5
9 CLK_PCIE_WLAN REFCLK+ UIM_RESET LPC_LAD3 8,23,33
9 CLK_PCIE_WLAN#_C 11 12 A_LAD2_R R591 *short_4 9 4 3 PCIE_CLKREQ_WLAN#_R
CLK_PCIE_WLAN# REFCLK- UIM_CLK LPC_LAD2 8,23,33 PCIE_CLK_WLAN_REQ#
9 10 A_LAD1_R R592 *short_4
GND UIM_DATA LPC_LAD1 8,23,33
PCIE_CLKREQ_WLAN#_R 7 8 A_LAD0_R R593 *short_4
CLKREQ# UIM_PWR LPC_LAD0 8,23,33
5 6 2
3 Reserved +1.5V 4 Debug DSW
GND
GND
PCIE_WAKE#_R 1 Reserved GND 2 1 6 PCIE_WAKE#_R
WAKE# +3.3V 7,27,29 PCIE_LAN_WAKE#
MINI-CARD1
53
54
2N7002DW
R612 *0_4
R282 *0_4
C C
NGFF (NGF)
6/25 Add R580/R581 by Kingston SSD. CN6
+3V_SATA
NGFF pin Type Description
R366 NF@0_4 SSD_PRESENCE 1 2
3 PRESERVE 3.3Vaux 4
5 GND 3.3Vaux 6
7 N/A N/A 8
9 N/A N/A 10 DAS
11 N/A DAS# 12 TP74
ZYW: N/A Key
This pin is grounded on the SSD. May be used by host to
13 14 determine if slot is empty or populated
For port auto-configuration implementations, 15 Key Key 16 1 PRESENCE
17 Key Key 18
follow the routing guidelines for SATA 19 Key
Key
Key
N/A
20
21 22
but use 100 nF AC coupling capacitors 23 WWAN/SSDIND_N N/A 24
25 N/A N/A 26
27 N/A N/A 28
C656 NF@0_4 SATA_RXN_PERN6_L1#_C 29 GND N/A 30 10 DAS# Device Activity Signal
8 SATA_RXN_PERN6_L1# PERN1 N/A
C655 NF@0_4 SATA_RXP_PERP6_L1_C 31 32 R362 NF@0_4 10
8 SATA_RXP_PERP6_L1 PERP1 N/A DEVSLP0
33 34
C654 NF@0.1U/10V_4 SATA_TXN_PETN6_L1#_C 35 GND N/A 36
8 SATA_TXN_PETN6_L1# PETN1 N/A
C653 NF@0.1U/10V_4 SATA_TXP_PETP6_L1_C 37 38 DEVSLP R365 *NF@100K_4
8 SATA_TXP_PETP6_L1 PETP1 Device sleep
39 40
C652 NF@0_4 SATA_RXP_1ST_SSD_C 41 GND N/A 42
8 SATA_RXP_1ST_SSD
C651 NF@0_4 SATA_RXN_1ST_SSD#_C 43 SATA RX+ N/A 44 21 WWAN/SSDIND_N This pin connect to Ground
8 SATA_RXN_1ST_SSD# SATA RX- N/A
45 46
C650 NF@0.1U/10V_4 SATA_TXN_1ST_SSD#_C 47 GND N/A 48
8 SATA_TXN_1ST_SSD# SATA TX- N/A
C649 NF@0.1U/10V_4 SATA_TXP_1ST_SSD_C 49 50 R724 NF@0_4 PLTRST#
8 SATA_TXP_1ST_SSD SATA TX+ PERST PLTRST# 7,13,16,23,27,29,30,33
51 52 CLK_PCIE_NGFF#_R If system didn't support DEVSLP, set DEVSLP Sleep Signal pin
CLK_PCIE_NGFFN 53 GND CLKREQ 54 PCIE_NGFF_WAKE#_R
9 CLK_PCIE_NGFFN REFCLKN PEWAKE
power high and keep (from power on), device will ignore.
9 CLK_PCIE_NGFFP 55 56 If system support DEVSLP, set DEVSLP Sleep Signal pin power low
CLK_PCIE_NGFFP REFCLKP MFG1
B
57 58 Device Sleep Signal (from power on) device, device will support DEVSLP function. B
GND MFG2
+3V 38 Device Sleep Signal H: SSD enter sleep model.
Device Sleep Signal L: SSD exit sleep model.
+3V_SATA 59 60
R359 61 KEY
KEY
KEY B KEY
KEY
62
63 PLATFORM PIN OUT 64 REFCLKN no connect on SSD
R363 65 KEY KEY 66
NF@10K_4 KEY KEY 53
8 SSD_SATA3GP NF@1M_4
SSD_SATA3GP
PLTRST# R723 *0_4 RESET_C 67
RESET
3
SSD_PEDET_R 69 68 R361 NF@0_4 PCH_SUSCLK REFCLKP no connect on SSD

71 IFDET SUSCLK 70
PCH_SUSCLK 7 55
73 GND 3.3Vaux 72
2 75 GND 3.3Vaux 74 Manufacturing pin. Use determined by vendor. Must be a noconnect on the host board
56 MFG1
GND
GND
R364 GND 3.3Vaux

Q37 *NF@0_4
NF@2N7002 NF@SSD_NGFF_CONN MFG2 Manufacturing pin. Use determined by vendor. Must be a noconnect on the host board
58
76
77
NGFF-80149-2121-75P-KB
1
Card pin69 = Ground (SATA card) SUSCLK no connect on SSD

68
+3V
69 IFDET This pin connect to Ground

1.5A +3V_SATA
R360 *short_8 +3V_SATA Close mSATA conn.

+3V_SATA
+3V_SATA +3V_SATA
C399
C400
C414 C413 C416 C412 C418
A
*NF@0.1u/10V_4 NF@10u/6.3V_4 NF@0.1U/10V_4 NF@0.1U/10V_4 R719 R718 A
*NF@10U/6.3V_8 NF@0.1U/10V_4 NF@0.1U/10V_4 Q51
S0 5
NF@4.7K_4
NF@4.7K_4
9
4 3 CLK_PCIE_NGFF#_R
CLK_PCIE_NGFF#
rating = 1000mA @ 128G 2

DSW 1 6 PCIE_NGFF_WAKE#_R
7,27,29 PCIE_LAN_WAKE#
NF@2N7002DW
R709 *0_4 PROJECT : ZYW
R726 *0_4 1A
Mini-Card/NGFF
5 4 3 2 1
5 4 3 2 1
HDD1 SATA Re-driver

SATA
HDD1 27
HDD1
Reference design "DNI" RD_POWER
D D
CN22 A_EQ1 R664 *RD@4.7K/J_4 Equalization level setting for Channel x(x=A/B),internally
10 A_EQ2 R663 *RD@4.7K/J_4 pulled down
9 SATA_TXP_1ST_HDD_C C629 0.01U/25V_4 SATA_TXP_1ST_HDD_C_RD [x_EQ2, x_EQ1] ==
8 SATA_TXN_1ST_HDD#_C C630 0.01U/25V_4 SATA_TXN_1ST_HDD#_C_RD EN C602 *RD@0.1u/10V_4 R662 *RD@4.7K/J_4 B_EQ1 R661 *RD@4.7K/J_4 L/L: for channel loss up to 7.4dB
7 B_EQ2 R665 *RD@4.7K/J_4 L/H: for channel loss up to 14.4dB
H/L: for channel loss up to 11.2dB
6 SATA_RXN_1ST_HDD#_C C627 0.01U/25V_4 SATA_RXN_1ST_HDD#_C_RD H/H: for channel loss up to 5dB
5 SATA_RXP_1ST_HDD_C C625 0.01U/25V_4 SATA_RXP_1ST_HDD_C_RD
4
3 +5V_HDD1 120mil R658 *short_8 +5V
12 2 C619 De-emphasis level setting for Channel x(x=A/B), internally
11 1 + C372 C366 C370 A_DE R637 *RD@4.7K/J_4 pulled down
*100u/6.3V_3528 B_DE R636 *RD@4.7K/J_4 [x_DE] ==
SATA_CONN 10u/6.3V_6 0.1U/16V_4 0.1U/16V_4 L: -3.5 dB
H: -1.5dB
RD_POWER
R635 *short_RD@0/J_4 RD_POWER

+1.5V
B_EQ1
A_EQ2
A_EQ1
B_EQ2
C599 C601
RD@10u/6.3V_6 RD@0.1u/10V_4 C615
RD@0.1u/10V_4
21
20
19
18
17
16
U35
B_EQ1
A_EQ2
A_EQ1
B_EQ2
VDD
GND
22 25
GND GND
8 SATA_TXP_1ST_HDD C611 RD@0.01u/25V_4 SATA_TXP_1ST_HDD_IC 1 15 SATA_TXP_1ST_HDD_C_RD
C C608 RD@0.01u/25V_4 SATA_TXN_1ST_HDD#_IC 2 A_INp A_OUTp 14 SATA_TXN_1ST_HDD#_C_RD C
8 SATA_TXN_1ST_HDD# A_INn A_OUTn
3 13
4 GND GND 12 SATA_RXN_1ST_HDD#_C_RD
C605 RD@0.01u/25V_4 SATA_RXN_1ST_HDD#_IC 5 B_OUTn B_INn 11 SATA_RXP_1ST_HDD_C_RD
8 SATA_RXN_1ST_HDD# B_OUTp B_INp
8 SATA_RXP_1ST_HDD C603 RD@0.01u/25V_4 SATA_RXP_1ST_HDD_IC
REXT
B_DE
A_DE
23
VDD
GND 24
EN
GND
RD_POWER
RD@PS8527A
6
7
8
9
10
B_DE
A_DE
C600
EN
RD@0.1u/10V_4
R638
RD@4.99K/F_4
B B
ODD
CN14
14
GND14
1
GND1 2 SATA_TXP_ODD_C C597 0.01U/25V_4X
RXP SATA_TXP_ODD 8
3 SATA_TXN_ODD#_C C596 0.01U/25V_4X SATA_TXN_ODD# 8
RXN 4
GND2 5 SATA_RXN_ODD#_C C591 0.01U/25V_4X
TXN SATA_RXN_ODD# 8
6 SATA_RXP_ODD_C C589 0.01U/25V_4X 8
TXP 7 SATA_RXP_ODD
GND3
ODD_PRSNT# 8
R616 10K_4 +3V
8 C583 *15p/50V_4 +5V_ODD +5V
DP 9
+5V 10 +5V_ODD R618 *short_8
+5V 11
MD 12
GND 13 C571 C572 + C573
GND
15 *0.1U/16V_4Y 10U/6.3V_6X *100U/6.3V_3528P_E45b
GND15
6030D-13G20
A A
EC_ODD_EJ 33
R600 10K_4 +3V

PROJECT : ZYW
1A
SATA HDD/LED/SW
5 4 3 2 1
5 4 3 2 1
LAN
XTAL2 C177 10P/50V_4
1
2
Y7
25MHZ +-30PPM
VDD10
3
4
XTAL1
C178 10P/50V_4
R124 2.49K/F_4 RSET
10 mils TP19
TP17
TP18 +3V
LANVCC
D D
R540 *10K/J_4
2
32
31
30
29
28
27
26
25
U10
3 1 PCIE_REQ_LAN#_R
AVDD33
AVDD10
CKXTAL2
CKXTAL1
LED0
RSET
LED1/GPO
LED2(LED1)
9 PCIE_REQ_LAN#
33 Q42
GND *2N7002K
+3V
R541 *short_4
MDI_0+ 1 24 REGOUT R163

MDI_0- 2 MDIP0 REGOUT 23 1K_4 +3V_S5
MDIN0 VDDREG(VDD33) VDDREG/VDD33
VDD10 3 22 VDD10
MDI_1+ 4 AVDD10(NC) DVDD10(NC) 21 PCIE_LAN_WAKE#_R
MDI_1- 5 MDIP1 LANWAKEB 20 ISOLATEB R487 10K/J_4
MDI_2+ 6 MDIN1 ISOLATEB 19
MDI_2- 7 MDIP2(NC) RTL8111GS-CG PERSTB 18 GPP_RX2N_LAN C540 0.1U/10V_4
PLTRST# 7,13,16,23,27,30,33
MDIN2(NC) HSON PCIE_RXN_LAN# 9
2
VDD10 8 17 GPP_RX2P_LAN C543 0.1U/10V_4 9 R146
AVDD10 HSOP PCIE_RXP_LAN
*15K_4
3 1 PCIE_LAN_WAKE#_R
7,27 PCIE_LAN_WAKE#
AVDD33(NC)
REFCLK_N
MDIN3(NC)
MDIP3(NC)
REFCLK_P
CLKREQB
Q41 2N7002K
LANVCC
+3V_S5 LANVCC Consider VCC33 may be connected to Main R488 *0_4
HSIN
HSIP
Power or chipset/bios's GPO, the pull-low
resistor R14 can be NC only when Main Power
40 mils (Iout=1A) 40 mils (Iout=1A) or chipset/bios's GPO can ensure to drive the
9
10
11
12
13
14
15
16
R471 *short_8 ISOLATEB pin to a voltage level < 0.8V at the
system state S1~S5.
MDI_3+ If the ISOLATEB pin can not be well-controlled to

C529 C530 MDI_3- a voltage level < 0.8V at S1~S5, the pull-low
0.1U/10V_4 10U/6.3V_6 LANVCC resistor R14 is needed to make sure the LAN
chip is well isolated.
C 9 C
CLK_PCIE_LAN#
CLK_PCIE_LAN 9
PCIE_TXN_LAN# 9
PCIE_TXP_LAN 9
PCIE_REQ_LAN#_R
5,7,8,9,10,11,13,23,32,33,35,38,40 +3V_S5
2,5,7,8,9,10,11,13,14,15,16,20,23,24,25,26,27,28,30,31,32,33,35,36,37,38,39,40,41 +3V
LANVCC
For RTL8111G(S) For RTL8111G(S)
VDDREG/VDD33 RTL8111GS * Place 0.1uF CAP close to each * Place 1uF CAP close to each VDD10 pin-- 22 (reserve)
40 mils (Iout=1A) REGOUT (SWR mode) support VDD10 pin-- 3, 8, 22, 30 VDD10
R120 *short_8
40 mils (Iout=1A) 40 mils (Iout=1A)
C192 C180 C194 C179 40 mils (Iout=1A) C186 C184 L14 4.7uH
0.1U/10V_4 0.1U/10V_4 4.7U/6.3V_6 4.7U/6.3V_6 0.1U/10V_4 4.7U/6.3V_6
C172 C173 C542 C538 C533 C534 C537 C539

4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 1U/6.3V_4 0.1U/10V_4
For RTL8111GS
* Place 0.1uF CAP close to each Remove For Not Using SWR mode
VDD33 pin-- 11, 32 close to Pin23.
B
Tramsformer B
RJ45 Connector
U31
Layout:All termination CN10

MDI_0+ R458 *short_4 MDI_0+_C 1 TD1+ MX1+ 24 LAN_MX0+
signal should have 30
MDI_0- R459 *short_4 MDI_0-_C 2 TD1- MX1- 23 LAN_MX0- mil trace
3 TCT1 MCT1 22 LAN_MCT
4 21 LAN_MX0+ 1
TCT2 MCT2 LAN_MX0- 2
MDI_1+ R466 *short_4 MDI_1+_C 5 20 LAN_MX1+ LAN_MX1+ 3
TD2+ MX2+ LAN_MX2+ 4
MDI_1- R470 *short_4 MDI_1-_C 6 19 LAN_MX1- LAN_MX2- 5
TD2- MX2- LAN_MX1- 6
LAN_MX3+ 7 9
LAN_MX3- 8 10
MDI_2+ R472 *short_4 MDI_2+_C 7 18 LAN_MX2+
TD3+ MX3+
MDI_2- R479 *short_4 MDI_2-_C 8 17 LAN_MX2-
TD3- MX3-
9 16
TCT3 MCT3
LAN_RJ45
10 15
TCT4 MCT4
MDI_3+ R500 *short_4 MDI_3+_C 11 14 LAN_MX3+
TD4+ MX4+
MDI_3- R515 *short_4 MDI_3-_C 12 13 LAN_MX3- R456
TD4- MX4-
A 75/F_8 A
C536
0.01U/50V/X7R_4 D22
*BS4200N-C_1812
NS692417
R455
C511
*1M_8
220p/3KV_1808
PROJECT : ZYW
F3A
LAN
5 4 3 2 1
5 4 3 2 1
USBP0-_R RV101 2 *EGA_4

USB3.0 (UB3)
9
9
USBP0-
USBP0+
USBP0-
USBP0+
C595 *1.6P/50V_4
R628
R629
*short_4
*short_4
USBP0-_R
USBP0+_R
USBPWR0
1
2
3
4
CN15
USB3.0 CONN
1
2
3
VBUS
D-
D+
USBP0+_R
USB3_RXP1_R
RV111
USB3_RXN1_R RV131
RV121
2 *EGA_4
2 *EGA_4
2 *EGA_4
29
+5V_S5 USB3_RXN1 R634 *short_4 USB3_RXN1_R 5 4 GND USB3_TXN1_R RV9 1 2 *EGA_4
9 USB3_RXN1 5 SSRX-
9 USB3_RXP1 R633 *short_4 USB3_RXP1_R 6
USB3_RXP1 7 6 SSRX+ USB3_TXP1_R RV8 1 2 *EGA_4
C593 *1.6P/50V_4 C584 0.1u/10V_4 USB3_TXN1_C R615 *short_4 USB3_TXN1_R 8 7 GND
C670 C604 U34 USBPWR0 C582 0.1u/10V_4 USB3_TXP1_C R613 *short_4 USB3_TXP1_R 9 8 SSTX-
9 SSTX+
Close USB3.0
13
12
11
10
*10U/6.3V_8 1u/6.3V_4 5 1
IN OUT USB3_TXN1 C585 C579
9 USB3_TXN1
13
12
11
10
2 C351 C352 C598 C669 9 USB3_TXP1 *1.6P/50V_4 *1.6P/50V_4
D GND USB3_TXP1 D
USBON# 4 3
33 USBON# EN /OC 0.1u/10V_4 10U/6.3V_8
G524B2T11U 470P/50V_4 100U/6.3V_1206
9 USB_OC1#
USB_OC1#
G524B2T11U: Enable: Low Active /2.5A
USBPWR0
9 USBP1- CN16
USBP1-
9 USBP1+ USB3.0 CONN
USBP1+ 1
1 VBUS
R656 *short_4 USBP1-_R 2 USBP1-_R RV141 2 *EGA_4
2 D-
C618 *1.6P/50V_4 R659 *short_4 USBP1+_R 3
4 3 D+ USBP1+_R RV151 2 *EGA_4
USB3_RXN2 R669 *short_4 USB3_RXN2_R 5 4 GND
9 USB3_RXN2 5 SSRX-
USB3_RXP2 R668 *short_4 USB3_RXP2_R 6 USB3_RXN2_R RV171 2 *EGA_4
9 USB3_RXP2 6 SSRX+
7
C616 *1.6P/50V_4 C610 0.1u/10V_4 USB3_TXN2_C R652 *short_4 USB3_TXN2_R 8 7 GND USB3_RXP2_R RV161 2 *EGA_4
C607 0.1u/10V_4 USB3_TXP2_C R648 *short_4 USB3_TXP2_R 9 8 SSTX-
9 SSTX+
13
12
11
10
USB3_TXN2_R RV7 1 2 *EGA_4
9 USB3_TXN2 C609 C606
USB3_TXN2
13
12
11
10
9 USB3_TXP2 *1.6P/50V_4 *1.6P/50V_4 USB3_TXP2_R RV6 1 2 *EGA_4
USB3_TXP2
C C
Card Reader+ LED/B Connector
+3V
CN18
+3VPCU 1 13
+3V 2 14
for
ESD C710
3 39P/50V_4
33 PWRLED# 4
33 SUSLED# 5
33 BATLED0# 6
USB D/B (UB2) 7,13,16,23,27,29,33 PLTRST#

33 BATLED1#
R780
R781
0_4
*0_4
7
8
9
USBPWR2 9 USBP4# 10 +3VPCU
9 USBP4 11
CN21
12
1
2 13 Card reader+LED/B CONN
3
for
ESD
4 C711
5 39P/50V_4
6
9 USBP6- 7
9 USBP6 8
B 9 B
9 USBP7- 10
9 USBP7 11 14
12
USB daughter board 196033-12011-3
+5V_S5
1u/6.3V_4 USBPWR2
C357 U14 Close USB3.0
5 1
IN OUT
2 C622 C623 C624
GND
USBON# 4 3
EN /OC
G524B2T11U 470P/50V_4 0.1u/10V_4 *100U/6.3V_1206
9 USB_OC0#
USB_OC0#
G524B2T11U: Enable: Low Active /2.5A
A A

PROJECT : ZYW
F3A
USB3(S&C)
5 4 3 2 1
5 4 3 2 1
Codec(ADO) Grounding circuit(ADO)

HP-R2
+3VPCU
HP-L2
LINE1-VREFO-L PIN1, PIN4, PIN3, PIN6 are ANALOG R710
LINE1-VREFO-R +1.5V
Q50
MIC2-VREFO 100K_4
1 6 SLEEVE
CODEC_VREF C385 2.2U/6.3V_4 ADOGND R715
2
INT_AMIC-VREFO C377 10u/6.3V_4 ADOGND +5VA
3
C396
C398
R333 100K_4 4 3 RING2 *100K_4
D D
C639 5
1u/10V_4
2
10u/6.3V_4
R722 10K_4 PCH_AZ_CODEC_RST#
1u/10V_4 C368 ADOGND
placed close to codec C371 2N7002DW Q52
0.1u/10V_4 10u/6.3V_4 PJA138K C648
*1u/10V_4
1
+AZA_VDD
Place next to pin 26
36
35
34
33
32
31
30
29
28
27
26
25
+1.5VA
U17
ADOGND
CPVEE
HP-OUT-L
LINE1-VREFO-L
MIC2-VREFO
LDO1-CAP
AVDD1
AVSS1
CPVDD
CBN
HP-OUT-R
LINE1-VREFO-R
VREF
C407
10u/6.3V_4
C401
0.1u/10V_4
D-Mic +3V
ADOGND 37 24 LINE2-L +3V
CBP LINE2-L TP70
38 23 LINE2-R C662 10u/6.3V_4
AVSS2 LINE2-R TP71
ADOGND C663 0.1u/10V_4 R746
Place next to pin 40 C402 10u/6.3V_4 39 22 LINE1-L *0_4
LDO2-CAP LINE1-L U20
Analog 40 21 LINE1-R 6 1
AVDD2 LINE1-R VDD GND
Digital L23 +5V_PVDD 41 20 DMIC_DAT_L *short_4 R368 DMIC_DAT_C 5 2
+5V
PBY160808T-600Y-N(60,3A) PVDD1 NC close to codec DATA CS
L_SPK+ 42 19 C364 10u/6.3V_4 ADOGND DMIC_CLK_L *short_4 R367 DMIC_CLK_C 4 3
C405 C404 SPK-L+ MIC1-CAP CLK GND R745
L_SPK- 43
SPK-L-
ALC283 MIC2-R/SLEEVE
18 SLEEVE trace width of SLEEVE & RING2 D-MIC *short_4
1
10u/6.3V_4 0.1u/10V_4
R_SPK- 44 17 RING2 are required at least 40mil and D38 D39
SPK-R- MIC2-L/RING2 its length should be asshort as possible
near Codec R_SPK+ 45 16 *TVS/6pF_4 *TVS/6pF_4
2
SPK-R+ MONO-OUT
46 15 CODEC_JDREF R324 20K/F_4
PVDD2 JDREF ADOGND
Low is power down
amplifier output PD# 47 GPIO0/DMIC-DATA 14
GPIO1/DMIC-CLK
C403 PDB Sense B
C 48 13 SENSEA R325 39.2K/F_4 HP_JD# C
SDATA-OUT
TP72 SPDIFO/GPIO2 Sense A
LDO3-CAP
0.1u/10V_4
SDATA-IN
DVDD-IO
PCBEEP
RESETB
BIT-CLK
Placement near Audio Codec
DVDD
SYNC
DVSS
49
DGND
Analog
near Codec
Digital
1
10
11
12
DMIC_CLK
close to codec
C386 1.6Vrms
R352 *short_6 +AZA_VDD
+3V
10u/6.3V_4 PCBEEP C634 1u/10V_4 BEEP_1 R702 47K_4 D27 1N4148WS 8,10
SPKR
C641 C633 R701 D29 1N4148WS 33
PCBEEP_EC
C640 4.7K_4
0.1u/10V_4 10u/6.3V_4 100p/50V_4
+3V +1.5V
Place next to pin 1

PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_RST# 8
R331 *0_4
DMIC_DAT_L
PCH_AZ_CODEC_SYNC 8 HEADPHONE/MIC/LINE combo (AMP)
Tied at one point only under DMIC_CLK_L R707 22_4 DVDD_IO R329 *short_4
the codec or near the codec
C420 C419 MIC2-VREFO R697 2.2K/J_4 FB1/FB2(SLEEVE/RING2) should choose DC resistance (Rdc) < 30m-ohm
R326 *short_4 ACZ_SDIN R704 33_4 C373 C374
R319 *0_4 *10p/50V_4 10p/50V_4
PCH_AZ_CODEC_SDIN0 8
R698 2.2K/J_4 to get the best audio performance for HP crosstalk
R316 *0_4 PCH_AZ_CODEC_BITCLK 8 0.1u/10V_4 10u/6.3V_4 Combo Jack
R315 *0_4 SLEEVE L43 BLM15AG121SN1D/120/500MA_4
R314 *0_4 C638 *22p/50V_4 CN23
R357 *0_4
need check with RING2 L46 BLM15AG121SN1D/120/500MA_4 4
C631 *1000p/50V_4 DMIC vender PCH_AZ_CODEC_SDOUT 8 Place next to pin 9 3
C632 *1000p/50V_4 HP-L2 R708 56/F_4 HP-L3 L45 BLM15AG121SN1D/120/500MA_4 HP-L4 1
HP-R2 R703 56/F_4 HP-R3 L44 BLM15AG121SN1D/120/500MA_4 HP-R4 2

5
B B
ADOGND HP_JD# 6 7
1
Cap need near AVDD1 and AVDD2 SIT_2SJ3052-005111F
D30
power source input LINE1-L C637 4.7U/6.3V_6 C628 C645 C642 C635
*14V/38V/100P_4
LINE1-VREFO-L
2
D28 R706 4.7K_4 100p/50V_4
1
PCH_AZ_CODEC_RST# 2 1 100p/50V_4 100p/50V_4 100p/50V_4 D36 D37 ADOGND
LINE1-VREFO-R R705 4.7K_4
*5.5V/25V/410P_4
LINE1-R C636 4.7U/6.3V_6 ADOGND *14V/38V/100P_4 *14V/38V/100P_4 ADOGND
2
Level shift
Codec PWR 5V(ADO) Mute(ADO) +3V +1.5V
Codec PWR 1.5V(ADO)
+AZA_VDD
R353
*10K_4
R351
*1K_4
2
PD# PD# D33 *RB500V-40 PD#_R 3 1 PCH_AZ_CODEC_RST# +1.5VA
DIGITAL ANALOG
R354 DIGITAL ANALOG
L42 HCB2012KF220T60/6A/22ohm_8 *10K/J_4 Q36
+5V +5VA *PJA138K
U15 +1.5V L24 HCB1608KF-121T30_3A_6
3 4 D20 RB500V-40 33
IN OUT AMP_MUTE#
C417
2
GND C363 C365 1U/6.3V_4
1 5 R322 *29.4K/F_4
SHDN SET *10u/6.3V_6 *0.1u/10V_4
A
C356 C355
*G923-330T1UF
R323 Internal Speaker Need Check P/N and F/P A
*10K/F_4
*0.1u/10V_4 *10u/6.3V_6 ADOGND
R358 *0_4 40mil for each signal CN26

R_SPK+ R742 *short_6 R_SPK+_1
R_SPK- R_SPK-_1 1
close pin3 R741 *short_6
2
ADOGND L_SPK- R740 *short_6 L_SPK-_1
L_SPK+ R739 *short_6 L_SPK+_1 3 5
4 6
C661 C660 C659 C666

SPK_CONN_4P Quanta Computer Inc.
1000P/50V_4 1000P/50V_4 1000P/50V_4 1000P/50V_4 PROJECT : ZYW
F3A
Place these EMI components next to codec
Audio
5 4 3 2 1
5 4 3 2 1
+3VPCU
KEYBOARD (KBC) TOUCHPAD BOARD CONN (TPD I2C/PS2 co-lay) +3V_S5 R771 0_6 R776 *0_6
CN19
1
2
3
MX0
MX1
MX2
MX0
MX1
33
33
MX4
MX5
MX6
MX7
10
9
8
7
6
RP7
1
2
3
4
5
MX3
MX2
MX1
MX0
+TPVDD
R301
2.2K_4
R298
2.2K_4
+3VSUS
+3V
L22
L21
*0_6
*0_6
1
Q53
AO3413
+TPVDD
32
MX2 33
4 MX3 I2C_TP_SDA_R C614 + C714
MX3 33
2
5 MX4 *10K_10P8R 0.1u/10V_4 C712 0.1u/10V_4
MX4 33
6 MX5 <EMI> I2C_TP_SCL_R 0.22u/25V_6
MX5 33
7 MX6 R775
MX6 33
8 MX7 MX4 1 2
MX7 33 33 PTP_PWR_EN#
9 MY17 MX5 3 4 CP10
MY17 33
10 MY16 MX6 5 6 *220P_8P4R R300 *TDI@0_4 10K/J_4
MY16 33
D 11 MY15 MX7 7 8 C713 D
MY15 33 Q48
12 MY14 MY3 1 2 +TPVDD *1000p/50V_4
MY14 33
13 MY13 MY2 3 4 CP6
MY13 33
14 MY12 MY1 5 6 *220P_8P4R 1 6 R308 R309
MY12 33 +TPVDD
15 MY11 MY0 7 8
MY11 33
16 MY10 MY7 1 2 2 I2C_TP_SDA_R 10K_4 10K_4
MY10 33 10 I2C0_SDA_GPIO6
17 MY9 MY6 3 4 CP7 10 I2C0_SCL_GPIO7 I2C_TP_SCL_R CN17 +TPVDD
MY9 33 50mil
18 MY8 MY5 5 6 *220P_8P4R +TPVDD 1
MY8 33
19 MY7 MY4 7 8 4 3 R304 *short_4 TPCLK_R 2 R302
MY7 33 33 TPCLK
20 MY6 MY11 1 2 R303 *short_4 TPDATA_R 3
MY6 33 33 TPDATA
21 MY5 MY10 3 4 CP8 5 4 10K/J_4
MY5 33
22 MY4 MY9 5 6 *220P_8P4R I2C_TP_SDA_R 5 TPD_INT#
MY4 33
23 MY3 MY8 7 8 I2C_TP_SCL_R 6
MY3 33 2N7002DW
24 MY2 MY15 1 2 TPD_INT# 7 9
MY2 33 2,33 TPD_INT#
25 MY1 MY14 3 4 CP9 R299 *TDI@0_4 8 10
MY1 33 33 TPD_EN
26 MY0 MY13 5 6 *220P_8P4R C715
MY0 33
MY12 7 8 +3V *10p/50V_4
TP CN
MX0 1 2 C613 C612 TP CONN pin7: Interrupt#/Wake#
27 MX1 3 4 CP11 *0.1u/10V_4 *0.1u/10V_4 TP CONN pin8: LID close, Function off
28 MX2 5 6 *220P_8P4R
MX3 7 8
KB CONN
+3V VIN +TPVDD

FAN1 For CPU (THM) Stitch Caps (EMC)
+3V +3V +5V +5V +5V +5V +5V
R784 R783
+3V +5V +3V +5V R782 *1M_6 *22_8
*10K_4
C214 C236 C408 C415 C421 C358 C664
3
R206 R167 R193 R173
3
C C
1K/J_4 0.1u/25V_4 0.1u/25V_4 0.1u/25V_4 0.1u/25V_4 0.1u/25V_4 0.1u/25V_4 0.1u/25V_4
10K/J_4 10K/J_4
*short_8 PTP_PWR_EN# 2 2 2
33 CN11
FANSIG1
+5V_FAN1 R785 Q56
4 6
2
*1M_6 *2N7002K +5V_S5 +5V_S5 +5V_S5 +5V_S5 +5V_S5
1
3 5 Q54 Q55
1
1 3 FAN_PWM_CN1 2 *DTC144EU *DTC144EU +3V +3V +3V +3V +3V
33 CPUFAN1 1 +3V +3V +3V +3V
Q21 30mil FAN1
MMBT3904-7-F_200MA
C409 C410 C353 C376 C665

C165 C150 C229 C290
0.1u/25V_4 0.1u/25V_4 0.1u/25V_4 0.1u/25V_4 0.1u/25V_4
For EMI C197 C191 0.1u/25V_4 0.1u/25V_4 0.1u/25V_4 0.1u/25V_4
*220p/50V_4 *220p/50V_4
+5V_S5 +5V_S5 +5V_S5 +5V_S5 +5V_S5

VIN VIN VIN VIN
KB_BL LED (KBL) +5V

+5V
NUT (OTH)
C362 *KBL@2.2u/6.3V_6 HOLE9 HOLE22 HOLE24 HOLE19 HOLE15 HOLE8 HOLE11
R317 *HG-C315D110P2 *HG-C315D110P2 *hg-tc315bc236d110p2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2-V5 *HG-C315D110P2
1
7 6 7 6 7 6 7 6 7 6 6 7 6
KBL@10K_4 Q28 8 5 8 5 8 5 8 5 8 5 5 8 5
B KBL@AO3413 9 4 9 4 9 4 9 4 9 4 4 9 4 B
2
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
3
2 +5V_KB
33 KB_BL_LED
HOLE13 HOLE17 HOLE18 HOLE20
Q29 C621 C620 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2
KBL@DTC144EU CN20 7 6 7 6 7 6 7 6
1
KBL@4.7u/6.3V_6 *KBL@0.01u/16V_4 8 5 8 5 8 5 8 5
4 9 4 9 4 9 4 9 4
3 6
2 5
1
2
3
1
2
3
1
2
3
1
2
3
1
C620 -> EOD KBL@KB_backlight GPU nuts Mini card nuts
HOLE10 HOLE14 HOLE6 HOLE12 HOLE16
*H-C110D110N EV@H-C236D138P2 EV@H-C236D138P2 EV@H-TC236I138BC236D138P2 H-C217D61P2
HOLE21 HOLE23
*HG-C315D110P2 *hg-tc315i236bc315d110p2
7 6 7 6
8 5 8 5
9 4 9 4
1
Power Switch. (FSW)
1
2
3
1
2
3
+3VPCU
A A
R6
10K_4 HOLE7
*CPU-BKT
SW6
POWER_SW
13,33 NBSWON# NBSWON# 1 3
2 4
1
2
3
4
1
C7 D6
5
0.1u/10V_4 *VPORT_6
PROJECT : ZYW
2

KB/TP/FAN 3A

5 4 3 2 1
5 4 3 2 1
L37 +A3VPCU +3VPCU

EC(KBC)
33
BLM15AG121SN1D/0.5A/120ohm_4 +3VPCU_ECPLL L19 +3VPCU_EC
C590 BLM15AG121SN1D/0.5A/120ohm_4
0.1u/10V_4 C265 (For PLL Power) S5_ON R261 10K_4
ECAGND 0.1u/10V_4 +3VPCU_EC +3V +3V_EC

12 mils
+3V_RTC
R293 2.2_6 12 mils HWPG
+3VPCU 1 2 +3VPCU_EC C274
SUSC# 7,13
D40 D41 D42
SUSB# 7,13
C716 C323 C346 C318 C577 C259 C258 0.1u/10V_4 *EGA_4 *EGA_4 *EGA_4
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 +3V_GFX

EC_ODD_EJ 28
PTP_PWR_EN# 32
D R281 *short_6 +3V_EC dGPU_OTP# R778 *10K_4 D
+3V
+3VPCU_EC and +3V_RTC
C285 dGPU_OPP# R627 *10K_4
minimum trace width 12mils. CLKRUN# 7,23
0.1u/10V_4
114
121
127
MAINON R625 100K_4
11
26
50
92
74
84
83
82
19
20
99
98
97
96
93
3
U13
10 110 MBCLK SUSON R262 100K_4
VBAT
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VCC
AVCC
EGCLK/WUI27/GPE3(Dn)
EGCS#/WUI26/GPE2(Dn)
EGAD/WUI25/GPE1(Dn)
L80HLAT/BAO/WUI24/GPE0(Dn)
L80LLAT/WUI7/GPE7(Up)
WUI42/GPH6/ID6(Dn)
WUI41/GPH5/ID5(Dn)
WUI40/GPH4/ID4(Dn)
WUI19/GPH3/ID3(Dn)
CLKRUN#/WUI16/GPH0/ID0(Dn)
8,23,27 LPC_LAD0 LAD0/GPM0(X) SMCLK0/GPB3(X) MBCLK 34
9 111 MBDATA
8,23,27 LPC_LAD1 LAD1/GPM1(X) SMDAT0/GPB4(X) MBDATA 34
8 115 2ND_MBCLK 2ND_MBCLK 8,19,24 VRON R632 100K_4
8,23,27 LPC_LAD2 LAD2/GPM2(X) SMCLK1/GPC1(X)
7 116 2ND_MBDATA 2ND_MBDATA 8,19,24
8,23,27 LPC_LAD3 LAD3/GPM3(X) SMDAT1/GPC2(X)
PLTRST# 22 117 EC_PECR_R R263 43_4 H_PECI 4 PCH_SPI_SI_EC R260 *10K_4
7,13,16,23,27,29,30 PLTRST# LPCRST#/WUI4/GPD2(Up) PECI/SMCLK2/WUI22/GPF6(Up)
SM BUS
+3VPCU 13 118
9 CLK_PCI_EC LPCCLK/GPM4(X) SMDAT2/WUI23/GPF7(Up) EC_FPBACK# 25
6 PCH_SPI_SO_EC R259 *10K_4
8,23,27 LPC_LFRAME# LFRAME#/GPM5(X) 85 TP37
PROCHOT_EC 17 PS2CLK0/TMB0/CEC/GPF0(Up) 86
LPCPD#/WUI6/GPE6(Dn) PS2DAT0/TMB1/GPF1(Up) LID# 25
2
89
PS2CLK2/WUI20/GPF4(Up) TPCLK 32
D19 TP30 SIO_A20GATE 126 90
GA20/GPB5(X) PS2DAT2/WUI21/GPF5(Up) TPDATA 32
PS/2
R287 SDMK0340L-7-F 5
100K_4
10,23
10
IRQ_SERIRQ
SIO_EXT_SMI#
15
23
SERIRQ/GPM6(X)
ECSMI#/GPD4(Up)
SM BUS PU(KBC)
10 SIO_EXT_SCI# ECSCI#/GPD3(Up) LPC
1
WRST# 14 GPIO
4 WRST#
10 SIO_RCIN# KBRST#/GPB6(X)
16
5 HWPG_1.05V_EC# PWUREQ#/BBO/SMCLK2ALT/GPC7(Up)/SMCLK2ALT
C307
1u/6.3V_4 24 30 +3VPCU
PWM0/GPA0(Up) PWRLED#
25 30
2,25
35,37
PCH_BLON
SUSON
R779 0_4 119
123 CRX0/GPC0(Dn)
CTX0/TMA0/GPB2(Dn) CIR
IT8587 PWM1/GPA1(Up)
PWM2/GPA2(Up)
PWM3/GPA3(Up)
PWM4/GPA4(Up)
28
29
30
SUSLED#
BATLED1#
SUSLED#
BATLED0#
APWORK
30
30
7
MBCLK
MBDATA
R264
R604
4.7K_4
4.7K_4
31 CPUFAN2 TP41
PWM5/GPA5(Up) +3V_S5
PWM
CLK_PCI_EC 80 2ND_MBCLK R603 4.7K_4
C 37,39 MAINON DAC4/DCD0#/GPJ4(X) C
BT_POWERON 104 47 2ND_MBDATA R602 4.7K_4
27 BT_POWERON DSR0#/GPG6(X) TACH0A/GPD6(Dn) FANSIG1 32
33 48 FANSIG2 TP42
5,7 EC_PWROK GINT/CTS0#/GPD5(Up) TACH1A/TMA1/GPD7(Dn)
88
32 KB_BL_LED PS2DAT1/RTS0#/GPF3(Up)
R622 TP40 81 120
DAC5/RIG0#/GPJ5(X) TMRI0/WUI2/GPC4(Dn) DNBSWON# 7
87 124
32 TPD_EN PS2CLK1/DTR0#/GPF2(Up) TMRI1/WUI3/GPC6(Dn) DPWROK 7
*22_4 TP31 E51_TXD 109
108 TXD/SOUT0/GPB1(Up)
31 AMP_MUTE# RXD/SIN0/GPB0(Up) H_PROCHOT# 4,34,38
3
71 125 NBSWON#
7 PCH_SLP_SUS# ADC5/DCD1#/WUI29/GPI5(X) PWRSW/GPE4(Up) NBSWON# 13,32
C587 72 18 dGPU_OPP# Q27
34 ACIN
73 ADC6/DSR1#/WUI30/GPI6(X) UART port RI1#/WUI0/GPD0(Up) 21
dGPU_OPP# 19
*10p/50V_4 34 TEMP_MBAT SB_ACDC 34
35 ADC7/CTS1#/WUI31/GPI7(X) RI2#/WUI1/GPD1(Up) PROCHOT_EC 2
25 TS_EN RTS1#/WUI5/GPE5(Dn) WAKE UP
34
31 PCBEEP_EC PWM7/RIG1#/GPA7(Up)
107 112
34 D/C# DTR1#/SBUSY/GPG1/ID7(Dn) RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7(Dn) RSMRST# 7
1A-5 2013/10/18 change U27.87 for Touch pad ID
TP34 95 R289 2N7002K
for I2C/PS2 solution switch. 94 CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2(Dn)
TP36
1
CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1(Dn) 100K_4
105
8 PCH_SPI_CLK_EC FSCK/GPG7
101
8 SPI_CS0#_UR_ME FSCE#/GPG3 RF_EN 27
102 EXTERNAL SERIAL FLASH ICMNT
8 PCH_SPI_SI_EC FMOSI/GPG4 ICMNT 34
103 66
8 PCH_SPI_SO_EC FMISO/GPG5 ADC0/GPI0(X) 67 C594 10u/6.3V_6 ECAGND
56 ADC1/GPI1(X) 68
32 MY16 KSO16/SMOSI/GPC3(Dn) ADC2/GPI2(X) TPD_INT# 2,32
57 69
32 MY17 KSO17/SMISO/GPC5(Dn) ADC3/GPI3(X) VRON 38
32 70 FB_CLAMP_REQ#
32 CPUFAN1 PWM6/SSCK/GPA6(Up) ADC4/WUI28/GPI4(X) FB_CLAMP_REQ# 19
Please do not place any
S5_ON 100 A/D D/A
pull-up resistor 35,36,39 S5_ON
106 SSCE0#/GPG2(X)
on GPG0, GPG2, and GPG6 8 ME_WR# SSCE1#/GPG0(X) SPI ENABLE
76
TACH2/GPJ0(X) dGPU_OTP# 19
(Reserved 32 MY0
36
KSO0/PD0 GPJ1(X)
77 EC_FB_CLAMP
EC_FB_CLAMP 17,19,20
hardware strapping). 37 78
32 MY1 KSO1/PD1 DAC2/TACH0B/GPJ2(X) PCH_PWROK 5,7
38 79
32 MY2 KSO2/PD2 DAC3/TACH1B/GPJ3(X) USBON# 30
39
32 MY3 KSO3/PD3
B 40 KBMX B
32 MY4 KSO4/PD4
41
32 MY5 KSO5/PD5
42
32 MY6 KSO6/PD6
43
32 MY7 KSO7/PD7
44
32 MY8 KSO8/ACK#
45
32 MY9 KSO9/BUSY
46
32
32
MY10
MY11
51 KSO10/PE
KSO11/ERR# CK32KE/GPJ7
2
PCH_SUSACK# 7
HWPG(KBC)
KSI3/SLIN#
KSI1/AFD#
KSI0/STB#
KSI2/INIT#
52 128 +3V
32 MY12 KSO12/SLCT CK32K/GPJ6 PCH_SUSPWARN# 7
53
VCORE
32 MY13 KSO13
AVSS
54 CLOCK R268 *0_4 DDR=1.5V, D1 DNP and D2 POP

KSI4
KSI5
KSI6
KSI7
32 MY14
VSS
VSS
VSS
VSS
VSS
VSS
55 KSO14 ZYW use internal crystal,

32 MY15 KSO15
so if CK32K(Pin 128) N/A should be connect GND.
DDR=1.35V, D1 POP and D2 DNP R623
IT8587E/FX 10K_4
SM BUS ARRANGEMENT TABLE
58
59
60
61
62
63
64
65
27
49
91
113
122
75
12
D1
D18 RB500V-40 HWPG
39 HWPG_1.5V
32 MX0 SM Bus 1 Battery D2
C295 D17 *RB500V-40
32 MX1 5 HWPG_1.05V
ECAGND
32 MX2
0.1u/10V_4 SM Bus 2 PCH/VGA D16 *RB500V-40
32 MX3 37 HWPG_VDDR
32 MX4
D15 *RB500V-40
32 MX5 13,36 HWPG_1.05V_S5
32 MX6 SM Bus 3
L36 D14 *RB500V-40
32 MX7 35 SYS_HWPG
BLM15AG121SN1D/0.5A/120ohm_4
SM Bus 4
3/5VPCU reset switch (FSW)

A A
SW7
3/5V_SW
1 3 SYS_SHDN# 10,35,39
2 4
1
C617 D26
5
0.1u/16V_4 *14V/38V/100P_4
2
PROJECT : ZYW
3A
KBC IT8587
5 4 3 2 1
5 4 3 2 1
PJ6
1
2
VA1
1
2
3
PQ38
AOL1413
5
VA2
PD10
SBR1045SP5-13
1
2
3 1
PR170
0.02/F_0612
2
VIN
1
2
3
PQ60
AOL1413 34
5
3 PR173
1
PC11 PC10 *short 0_4
0.1u/50V_6 2200p/50V_6 PC12 PC13 PR22 24737_ACN PC131 PC137 PR82
7
6
5
4
4
0.1u/50V_6 0.1u/50V_6 220K_4 0.1u/50V_6 2200p/50V_6 33K/F_4
PD9
SMAJ20A 24737_ACP
2
D dcjk-2dc2003-000111-3p-v D
POWER_JACK PR172
1 6 *short 0_4
PD6 PR20 2 5 PR81

D/C# 33
1N4148WS 220K_4 10K_4
recommend 200mA at least. 3 4 PR21
*short 0_4
PQ6
3
IMD2AT108
2
24737_ACP
PQ25
2N7002K
24737_ACN
1
PR63
*short 0_6 PC126 PC128 PC127
0.1u/50V_6 0.1u/50V_6 0.1u/50V_6
PR69
+3VPCU 63.4K/F_4
1
VIN
PR193 PC143
ACP
ACN
10K/F_4 1u/16V_6
C 24737_ACDET 6 16 24737_REGN C
ACDET REGN
PR51 PR62 PR50 PC120
*10K_4 100K_4 100K_4 0.1u/25V_4 PD11
24737_VCC 20 RB500V-40
VCC PR196 PC140 PC133
PR76 PC132 *short 0_6 2200p/50V_6 4.7u/25V_8
20_1206 0.47u/25V_6 17 24737_BST
33 ACIN BTST
5
PC138
47n/50V_6
7 ACPRESENT
PQ55
PR182 18 24737_DH 4 MDV1528
HIDRV
6
*0_4 5
33 SB_ACDC ACOK#
PR185 19 24707_LX
3
2
1
*short 0_4 PHASE PR211
0.01/F_0612
MBDATA 8 PU15 PL13
PQ54 SDA BQ24737RGRR 6.8uH_7X7X3
2N7002DW PR195 15 24737_DL 1 2 BAT-V
1
*short 0_4 LCDRV

PC51 MBCLK 9
SCL
5
0.1u/50V_6
+3VPCU PR197
PR209 *short 0_4 14 PR99
PC53 10K_4 PGND *4.7_6
*100p/50V_4 24737_BM# 11 4 PR215 PR219
BM# PQ59 *short 0_4
B *short 0_4 B
PR186 PC152 MDV1528
*10K_4 24737_CMPOUT 3 PR207 10_6 0.1u/25V_4
3
2
1
BAT-V CMPOUT 13 24737_SRP 24737_SRP PC40 PC142 PC160
SRP PC41 2200p/50V_6 10U/25V_8 10U/25V_8
24737_ILIM 10 PC157 *680p/50V_6 24737_SRN
PJ7 ILIM 0.1u/25V_4
PR119 *short 0_4 PR204 PR208 7.5_6
50458-00801-v02-8p-l
9 8 316K/F_4 24737_CMPIN 4 12 24737_SRN

7 CMPIN SRN
6 PR116 100_4 TEMP_MBAT
IOUT
GND
GND
GND
GND
GND
5 TEMP_MBAT 33
PC153
4 0.1u/25V_4
3 PR90 PR187
+3VPCU
21
22
23
24
25
2 PR117 1M_4
10 1 *100K_4
*100K_4
PC55 PC54
*47p/50V_4 *47p/50V_4 +1.05V
PR203 PC141
100K/F_4 0.01u/25V_4
REGN MAX voltage 6.5V
3
PR47
PR118 PR115
100_4 100_4 PR75
*100K_4 V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
24737_BM# 2 PR74
MBCLK 33
*1.62K/F_4
*0_4
=0.793V for 3.965A current limit
H_PROCHOT# 4,33,38
PQ26
3
*2N7002K
A MBDATA 33
33 ICMNT Pin10 ILIM=0.793V A
1
Rsr = 0.01ohm
PU10 24737_CMPOUT 2
*IP4223-CZ6
1 6 MBDATA PC136 PQ19
CH1 CH4 100p/50V_4 *2N7002K
2 5
+3VPCU Quanta Computer Inc.
1
VN VP
TEMP_MBAT 3 4 MBCLK
CH2 CH3 PROJECT : ZYW
Add ESD diode base on EC FAE suggestion Limit set on 60W/3.16A 2A
Charger(BQ24737RGRR)
5 4 3 2 1
5 4 3 2 1
MAIND
MAIND 36,39
SYS_SHDN#
SYS_SHDN# 10,33,39
35
PR97
*short 0_6
JP15 JP13
*short 0.001/F_3720 +3VPCU VL 3V_LDO *short 0.001/F_3720
PR194
D D
10K/F_4
33 SYS_HWPG
1 2 +5VPCU_VIN +3VPCU_VIN 1 2 VIN
VIN
SYS_SHDN#
10u/6.3V_6
0.1u/25V_4
4.7u/6.3V_6
1
+
PR78 PR71
2
PC104 PC147 PC144 *100K/F_4
PC46
PC45
33U/25V_6x4.5 4.7u/25V_8 2200p/50V_6 *short 0_4 PR77 PC146 PC145
51225_VIN
PC33
2200p/50V_6 4.7u/25V_8
*short 0_4
+5VPCU +5VPCU
5
+3VPCU
5 Volt +/- 5%
5
TDC : 7.2A PQ56 +3VPCU
PEAK : 9.6A MDV1528 3.3 Volt +/- 5%
13
12
1
3
4
TDC : 3.7A
1
OCP : 12A PQ57 4
VREG5
VREG3
VIN
MDV1528
Width : 300mil 7 6 SYS_SHDN#
PEAK : 5A
3
2
1
PGOOD EN2
OCP : 7A
1
2
3
JP17 51225_EN1 20 10 51225_DH2
Width : 160mil
2
*short 0.001/F_3720 EN1 DRVH2 PR83 PC36 JP16
2
PL15 51225_DH1 16 9 51225_VBST2 PL14 *short 0.001/F_3720
2.2uH_7X7X3 PC37 PR89 DRVH1 VBST2 3.3uH_7X7X3
+5V_SRC 51225_VBST1 17 8 51225_SW2 1/F_6 0.1u/50V_6 +3V_SRC
VBST1 PU8 SW2
0.1u/50V_6 1/F_6 51225_SW1 18 TPS51225RUKR 11 51225_DL2
5
C
SW1 DRVL2 C
PR192 51225_DL1 15 4 51225_FB2 PR189
15.4K/F_4 DRVL1 VFB2 PQ61 6.81K/F_4
PQ63 51225_FB1 2 21 MDV1595S PR101
+ PR110 MDV1595S 4 VFB1 GND 4 *4.7_6 +
*4.7_6 14 22
VO1 GND
VCLK
PC139 PC161 PC44 PC155
GND
GND
GND
GND
CS1
CS2
220u/6.3V_6X4.2 0.1u/50V_6 0.1u/50V_6 220u/6.3V_6X4.2
1
2
3
3
2
1
PC48
PR191 *680p/50V_6 PR190
19
26
25
24
23
10K/F_4 PC50 10K/F_4
*680p/50V_6
51225_CS1
51225_CS2
51225_VCLK
OCP:7A
118K/F_4
69.8K/F_4
PC154
L(ripple current)
2 0.1u/50V_6 =(9-3.3)*3.3/(3.3u*0.355M*9)
PD8 ~1.784A
OCP:12A 1PS302 3
Iocp=7-(1.784/2)=6.108A
L(ripple current) PR199
1 *short 0_6 1/13 Adding +3VSUS power for touch pad Vth=6.108A*14mOhm+1mV=86.5117mV
=(9-5)*5/(2.2u*0.3M*9) (By acer request) R(Ilim)=(86.5117mV*8)/10uA
PR66
PR65
PC52
=3.367A 0.1u/50V_6 PC150 ~69.21K
Iocp=12-(3.367/2)=10.3165A 0.1u/50V_6 PR67
2 *short 0_6
B Vth=9.316A*14mOhm+1mV=145.431mV PD12
B
R(Ilim)=(145.431mV*8)/10uA 1PS302 3 VIN +3VSUS +15V VIN +3VPCU

=116.35K 1
+15V_ALWP PR231 PR229 PR232 PR233

+15V
*1M_6 *22_8 *1M_6 *1M_6
3
PR217
22_8 PC158
0.1u/50V_6
SUSD 2
3
PQ67
2 *AO3404
33,37 SUSON
1
2 2
+3VSUS
PR230 PQ65 PQ64
1
PQ66 *1M_6 *2N7002K *2N7002K
VIN +3V_S5 +5V_S5 +15V VIN +5VPCU +5VPCU +3VPCU +3VPCU *DTC144EU PC172
TDC : 0.038A
1
*2.2n/50V_4
PEAK : 0.05A
PR45 PR32 PR100 PR57 PR56 Width : 20mil
5
5
1M_6 22_8 22_8 1M_6 *1M_6
3
S5D 4 MAIND 4 MAIND 4 S5D 2
A PQ62 PQ58 PQ53 PQ52 A
3
MDV1528Q MDV1528Q MDV1528Q AO3404

33,36,39
3
2
1
3
2
1
3
2
1
2
S5_ON
1
2 2 2
+5V_S5 +5V +3V +3V_S5
PR41 PQ14 PQ27 PQ17
1
PQ16 1M_6 2N7002K 2N7002K 2N7002K

DTC144EU PC28
TDC : 3A TDC : 4.16A TDC : 2.15A TDC : 0.89A
1
*2.2n/50V_4
PEAK : 4A PEAK : 5.54A PEAK : 2.86A PEAK : 1.18A PROJECT : ZYW
Width : 120mil Width : 180mil Width : 100mil Width : 40mil SYSTEM 5V/3V (TPS51225) 2A

5 4 3 2 1
5 4 3 2 1
JP8
*short 0.001/F_3720
36
1 2 VIN
D D
+5VPCU
+3V
PC31 PC111 PC110

1u/10V_4 2200p/50V_6 4.7u/25V_8
5
PR87
100K/F_4
7
PQ49
MDV1528
V5IN
51211V_DRVH 4
1 9 PR61 PC30 +1.05V_S5
13,33 HWPG_1.05V_S5 PGOOD DRVH
PR200 *short 0_6 0.1u/50V_6
51211V_EN 3 10 51211V_VBST
33,35,39 S5_ON
3
2
1
*short 0_4 EN VBST PL9
51211V_TRIP 2 PU7 8 51211V_SW +1V_SRC 1 2
PR88 93.1K/F_4 TRIP TPS51211DSCR SW
51211V_TST 5 6 51211V_DRVL 2.2uH_7X7X3
PR84 464K/F_4 TST DRVL
5
12 11 JP11
C PR85 GND GND PR43 PR198 *short 0.001/F_3720 C
GND
GND
GND
GND
*100K/F_4 *4.7_6 5.1K/F_4
FB
+
4 +1.05V
13
14
15
16
4
51211V_FB
PC114
0.1u/50V_6
PC115
330u/2.5V_6X4.2
1.05 Volt +/- 5%
PQ51 PC26 TDC : 4.85A
3
2
1
MDV1595S *680p/50V_6 PR86
OCP=9A
10K/F_4 PEAK : 6.47A
L ripple current OCP : 9A
=(19-1.05)*1.05/(2.2u*290k*19)
=1.555A Width : 320mil
Vtrip=10-(1.555/2)*14mohm
=115.12mV
Rlimit=115.12mV/10uA*8=92.09Kohm VFB=0.7V
+1.05V_S5
20131225 Modify power circuit for VCCSATA3PLL timing,
(add PR228 , no stuff PR26)
B B
5
+3V VIN +1.05V_MODPHY +15V +1.05V_S5
MAIND 4
35,39 MAIND
PR28 PR34 PR31 PQ46
1
2
3
1
3
*1M_4 *22_8 *1M_4 AON6756
PR228 +1.05V_MODPHY +1.05V

*100K_4 MODPHY_D 2
+1.05V
2
R750 *short_8
3
PR27 PQ48 connect +1.05V power to VCCHSIO,VCCUSB3PLL

*0_4 PR29 *AO3404
and VCCSATAPLL directly TDC : 4.85A
1
2 *1M_4 2 2
10 MODPHY_EN PC23 +1.05V_MODPHY
PEAK : 6.47A
1
PQ13 PQ12 *2.2n/50V_4

PQ9 *2N7002K *2N7002K Width : 200mil
1
PC22 PR26 *PDTC143TT

1
*1u/10V_4 *100K_4
A A
+1.05V_MODPHY
2
TDC : 1.43A Quanta Computer Inc.

PEAK : 1.9A
Width : 80mil PROJECT : ZYW
+1.05V_S5 (TPS51211) 2A

5 4 3 2 1
5 4 3 2 1
TDC : 0.75A
PEAK : 1A
Width : 40mil
+DDR_VTT_RUN
37
PC105 PC112
10u/6.3V_6 10u/6.3V_6
D TDC : 0.38A D
PEAK : 0.5A DDR_VTTREF
Width : 20mil
Close to IC
Greater than or equal 40mil
PC118
0.22u/10V_4
+5VPCU
+3V JP9
*short 0.001/F_3720
PC24 PC117
22
21
10u/6.3V_6 1u/10V_4
2
PR178 51216_VIN 1 2
VIN
100K/F_4
PAD
PAD
VTTGND
VLDOIN
VTTSNS
VTTREF
VTT
PQ47
MDV1528 +1.35VSUS
1.35 Volt +/- 5%
5
20 12
C
33 HWPG_VDDR PGOOD V5IN PC103 PC102 TDC : 5.3A C
PR177 51216_S3 17 14 51216_DRVH

2200p/50V_4 4.7u/25V_8
PEAK : 7A
33,39 MAINON S3 DRVH
*0_4 PR179 PC106 4 OCP : 9A
2/F_6 0.1u/50V_6 JP10
33,35 SUSON
PR176 51216_S5 16 15 51216_VBST *short 0.001/F_3720 Width : 220mil
*short 0_4 S5 PU13 VBST PL11
3
2
1
TPS51216RUKR 2.2uH_7X7X3
PR39 51216_MODE 19 13 51216_SW +1.35VSUS_SRC 1 2 +1.35V_SUS
200K/F_4 MODE SW
5
PR38 51216_TRIP 18 11 51216_DRVL
TRIP DRVL +1.35V_SUS 4,5,14,15
93.1K/F_4
VDDQSNS
PR42
26 10 *4.7_6
PAD PGND
REFIN
GND
PAD
PAD
PAD
REF
+
PC121 PC101
VREF=1.8V PC25 0.1u/50V_6 330u/2.5V_6X4.2
6
25
24
23
3
2
1
*680p/50V_6
51216_REF
51216_REFIN
PQ50
MDV1595S
PC122 PR46
B 0.1u/10V_4 *short 0_6 B
RDSon=2.2mohm
PR184
51216_S3 PR36 51216_S5 10K/F_4 Close to output cap
*0_4
PR49 PC123
30.1K/F_4 0.01u/25V_4 Mode Frequency Discharge mode
PR35
*short 0_4
51216_S3 200K 400K Tracking Discharge
4 DDR_VTTT_PG_CTRL
100K 300K Tracking Discharge

OCP=9A
L ripple current
=(19-1.35)*1.35/(2.2u*400k*19)
A =1.425A DDR=1.35V S3 S5 +1.35VSUS REF VTT A
Vtrip=9-(1.425/2)*14mohm OCP=9A
=116.024mV PR84=10K/F_4
Rlimit=116.024mV/10uA*8=92.82Kohm S0 1 1 ON ON ON Quanta Computer Inc.
PR86=30.1K/F_4
S3 (mainon off) 0 1 ON ON OFF PROJECT : ZYW
2A
S4/S5 0 0 OFF OFF OFF DDR 1.35V(TPS51216)
5 4 3 2 1
5 4 3 2 1
JP6
*short 0.001/F_3720
38
+VIN_VCCIN
IMON offset
Place NTC close to the 1 2 VIN
+VIN_VCCIN +3V_S5 51624_VREF
VCORE Hot-Spot. +5V_S5 +5V_S5
2200p/50V_4
33U/25V_6x4.5
1
0.1u/50V_6
4.7u/25V_8
4.7u/25V_8
PC43
PC148
PC64
PC171
PC149
PC130 +
100K/F_4_4250NTC
1u/10V_4
PR111
2M/F_4
D D
2
665K/F_4
20/F_6
36.5K/F_4
*90.9K/F_4
*39.2K/F_4
2
PR95
PR93
PR213
PR130
PR94
PR220
PR224
10K/F_4
1_6
PR113
VDD
51624_SKIP# 1 5 PL12
PR216 SKIP# VIN 0.15uH_7X7X4
51624_OCP-I 51624_VRON 51624_PWM1 8 4 CS_SW1 1 2
DCR= 1mOhm
PWM VSW +VCC_CORE
2M/F_4 CS_BSTR1 6 3
4
BOOT_R PGND
PC62
PR72
1n/50V_4
100K/F_4
150K/F_4
30K/F_4
20K/F_4
39K/F_4
PC68
1u/6.3V_4
2.26K/F_4
0.33u/6.3V_4
PR105
PR104
PR102
PR103
CS_BST1 7 9
1000p/50V_6 2.2_6
PR112 2.2u/10V_6 +
9.09K/F_4
BOOT PAD
PR214
PC67
PR106
PC49
*330u/2V_7343
100K/F_4
22u/6.3V_8
0.1u/10V_4
22u/6.3V_8
PR80 *short 0_4
PC35
PC60
PC151
PC169
PR210 PC156 PU16
PC34
2.2/F_6 0.22u/25V_6 CSD97374CQ4M
Add 11 GND VIAs
for thermal pad
PR79
51624_CSP1
2.94K/F_4
+1.05V
PR201
51624_B-RAMP
51624_SLEWA
51624_F-IMAX
51624_O-USR
Close to VR 51624_THERM PC162
51624_VREF
51624_VDD
*0.1u/25V_4
0.12u/10V_4
PC56
51624_V5A
16.9K/F_4
10K/F_4_3435KNTC
PR122
51624_VBAT
0.1u/10V_4
BW-U 15W(1 phase) BW-U 28W(1 phase)

56_4
PC69
PR141
PR140
PR139
PR225
*56_4
130/F_4
*75/F_4
PR202
51624_CSN1
27
10
11
15
14
28
16
2
9
PC164
Icc TDC PL2：14A *0.1u/25V_4 Icc TDC PL2：19A
VDD
O-USR
VREF
VBAT
F-IMAX
B-RAMP
SLEWA
V5A
THERM
C 4,33,34 H_PROCHOT#
30
VR_HOT PWM1
6 51624_PWM1 Icc Max：32A Icc Max：40A C
VR_SVID_CLK PR134 *short 0_4 51624_CLK 31 5 51624_PWM2 Close to the Close with
5 VR_SVID_CLK VCLK PWM2 OCP：37A VR side. phase1 inductor OCP：47A
5 VR_SVID_ALERT# VR_SVID_ALERT# PR135 *short 0_4 51624_ALERT# 32 4 51624_MODE
ALERT MODE
5 VR_SVID_DATA VR_SVID_DATA 51624_DATA 1
VDIO CSP1
17 51624_CSP1 Fsw：1.2MHz Fsw：1.2MHz
PR136 *short 0_4
3 PU9 18 51624_CSN1
PGOOD TPS51624RSM CSN1
+3V +3V +3V 51624_SKIP# 7
SKIP CSN2
19 51624_CSN2 ：
VCORE L/L： PS3 OSR ：
VCORE L/L：
51624_VRON 8 20 51624_CSP2
VR_ON CSP2 R_DC_LL：- 2.0mV/A 100K Ohm ON ON R_DC_LL：- 2.0mV/A
51624_VFB 24 21 Rmode
100K/F_4
*100K/F_4
*100K/F_4
VFB NC
PR120
PR222
PR114
51624_GFB 23 22 PR125
GFB N/C 150K/F_4 R_AC_LL：- 7.0mV/A R_AC_LL：- 7.0mV/A
DROOP
150K Ohm ON OFF

COMP
OCP-I
IMON
GND
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
51624_VREF
26
25
12
13
29
33
34
35
36
37
38
39
40
41
42
5,10 IMVP_PWRGD
PR128 *short 0_4
51624_DROOP
51624_OCP-I
51624_IMON
For BW-U 28W 2 phase

51624_COMP
4.7K/F_4
33 VRON
PR218 *0_4 PR226
*short 0_8 +VIN_VCCIN
*short 0_4
*short 0_4
5 VRON_CPU
PR221 *short 0_4
+VCC_CORE
+5V_S5
PR109
PC63
PR137
365K/F_4
20131014 add
10K/F_4
*100p/50V_4
*2200p/50V_4
*0.1u/50V_6
*4.7u/25V_8
*4.7u/25V_8
PC65
PC167
PC168
PC42
PC163
4700p/25V_4
B PC66 *1u/10V_4 B
PR223
PR131
PR129
PC47
PR133 *330p/50V_4
*10_4
2
1500p/50V_4
VDD
PR138
PR98
51624_SKIP# 1 5
39K/F_4
PL16
4.75K/F_4
5 VCC_SENSE SKIP# VIN

PC70
*0.24uH_7X7X4 DCR= 1mOhm

51624_PWM2 8 4 CS_SW2 1 2
12 VSS_SENSE +3V_S5 PWM VSW +VCC_CORE
CS_BSTR2 6 3
4
BOOT_R PGND
PR121
*1.82K/F_4
CS_BST2 7 9
*1000p/50V_6 *2.2_6
PR132
PC61 BOOT PAD
Parallel *10_4
*0_4
*0.01u/50V_4
*0.1u/10V_4
*22u/6.3V_8
*22u/6.3V_8
PC58
PC134
PC38
PR127 PC170 PU17
PC57
Close to the 0_4 PR227 *0.22u/25V_6 *CSD97374CQ4M
CPU side. *2.2/F_6 Add 11 GND VIAs
for thermal pad
PR107
PR108
51624_CSP2 51624_CSP2
*10K/F_4_3435KNTC *2.67K/F_4
BW-U 28W 1 phase BW-U 28W 2 phase
PR205
51624_PWM2 PC166
*0.1u/25V_4
*0.15u/10V_4
PC59
Location Value Location Value Location Value 51624_CSN2
*22.6K/F_4
PR126
PR79 CS22212FB11 、PL16
PL12、 0.24uH_7X7X4 PR105 56.2K/F_4
PR206
51624_CSN2
PR124 PC165
PR122 CS32262FB15 PR79 1.82K/F_4 PR223 2.37K/F_4
A PR94 CS45232FB00 、PR126
PR122、 *22.6K/F_4 PR138 10K/F_4
PR123
0_4
*0_4
Block 1. *0.1u/25V_4
PR223 CS24752FB12 PR201 2.67K/F_4 PR109 150K/F_4 Close to the Close with
VR side. phase1 inductor
PR98 CS35622FB10 PC144 0.15u/10V_4 、PR127
PR123、 *0_4
、PC164
PC162、
PR109 CS44122FB00 PR94 294K/F_4 、PC166 *0.1u/25V_4
PC165、 Quanta Computer Inc.
Block 1. Stuff PROJECT : ZYW
2A
+VCCIN(TPS51624)
5 4 3 2 1
1 2 3 4 5
+3VPCU
1 2
+1.5V
1.5Volt +/- 5%
+1.5V
39
+3V
JP14 PC135 PC129 TDC : 0.6A
1
*short 0.001/F_3720 10u/6.3V_6 0.1u/25V_6
PU14 TPS54318RTER
PEAK : 0.8A JP12
PR181 16
VIN PH
10 Width : 40mil *short 0.001/F_3720
A
100K/F_4 A
1 11 PL10
VIN PH 1uH_7X7X3
2
2 12
VIN PH
14 13 PR180 *short 0_6
33 HWPG_1.5V PW RGD BOOT
MAINON 15 6 PC113
EN VSNS 0.1u/50V_6 PR188
7 3
R1
PR55 100K/F_4
*short 0_4 COMP GND PC107 PC109 PC108
8 4 0.1u/10V_4 10u/6.3V_6 10u/6.3V_6
RT/CLK GND 1.5V_VSNS
PAD
PAD
PAD
PAD
PAD
PAD
PC124 9 5
1000p/50V_4 PR183 PR48 SS AGND
8.06K/F_4 121K/F_4 VFB=0.8V R2 PR54
22
21
20
19
18
17
113K/F_4
PC119 PC125 PC116

*100p/50V_4 1500p/50V_4 0.01u/25V_4
V0=0.8*(R1+R2)/R2
B B
VIN
Thermal protection
PD7
DA2J10100L
Need fine tune
for thermal protect point VIN +3V +5V +1.05V +15V
Note placement position
TEMP=70C(3/27modify)
PR25 PR68 PR44 PR73 PR30 PR91
1M_6 1M_4 22_8 22_8 22_8 1M_4
1
PQ8
AO3409 MAINON_ON_G MAIND
2 MAIND 35,36
3
3
3
PR60
2 PQ21 1M_4 2 2 2 2
3
S5_ON 2 33,37 MAINON DTC144EU PC39

33,35,36 S5_ON
PQ15 PQ22 PQ11 PQ23 *2200p/50V_4
2N7002K 2N7002K 2N7002K 2N7002K
1
PQ7 PR174 PR70
1
1
DTC144EU *short 0_6 *100K/F_6
C C
VL VL
SYS_SHDN# 10,33,35
PR167 PC92 PR171

PR148 200K/F_4 0.1u/50V_6 200K_6
3
2.2K/F_4
8
PR168
10K/F_4_3435NTC 2.469V 3
+ 1 2
LM393_PIN2 2
- PQ42
3
PU12A 2N7002K
4
AS393MTR-E1 PC91
1
0.1u/50V_6
S5_ON 2
PR169
PQ39 200K/F_4
2N7002K
1
D 5 D
+ 7
6
-
PU12B
AS393MTR-E1

For EC control thermal protection (output 3.3V) PROJECT : ZYW
2A
+1.5V/Thermal Protect
1 2 3 4 5
5 4 3 2 1
+5V_S5
40
JP7
PR19 +VIN_GPU_CORE *short EV@0.001/F_3720
*short EV@0_6
1 2 VIN
D D
EV@2200p/50V_4
EV@0.1u/50V_6
EV@4.7u/25V_8
EV@4.7u/25V_8
EV@33U/25V_6x4.5
1
PR166
18 1658R-PVCC
PC88
PC89
PC18
PC16
PC83
PR155 EV@6.81K/F_4 PR16 EV@12.4K/F_4 EV@2.2/F_6 PQ37 +
1
3V_MAIN_PWGD 1658R-VREF 1658R-BOOT1
PC86 EV@AON6414AL
2
EV@1U/10V_4
2
PC75 *EV@0.01U/25V_4 PC85
5
PR163 1 2 EV@0.22u/25V_6
EV@100K/F_4 PU11
PR149 1 1658R-BOOT1
PVCC
+VIN_GPU_CORE 1658R-OCS/CB 9 BOOT1 1658R-UGATE1 4 4 PQ36
PR143 *EV@1/F_4 OCS/CB 2 1658R-UGATE1 *EV@AON6414AL
PR17 *EV@0_4 *EV@499K/F_4 UGATE1
8 VGPU_EN
1
2
3
1
2
3
20 1658R-PHASE1 PL8
3V_MAIN_PWGD PR162 *short EV@0_4 1658R-EN 3 PHASE1 EV@0.36uh_LDCR
20,41 3V_MAIN_PWGD EN 19 1658R-LGATE1 1658R-PHASE1
DCR=1.1m ohm
LGATE1 +VGPU_CORE
DGPU_PSI PR161 *short EV@0_4 1658R-PSI 4
19 DGPU_PSI
5
PSI PR24
EV@UP1658RQKF EV@2.2/F_6
PWM-VID PR157 *short EV@0_4 1658R-VID 5 15 1658R-BOOT2 +
EV@330u/2V_7343
19 PWM-VID VID BOOT2 1658R-LGATE1 4 4
EV@0.1u/10V_4
EV@10u/6.3V_8
14
PC99
PC100
PC98
1658R-UGATE2
1 2 1658R-VREF 8 UGATE2
1
2
3
1
2
3
PC79 EV@1U/10V_4 VREF 16 1658R-PHASE2 PQ44 PC21
PHASE2 EV@AON6752 EV@1000p/50V_6
1658R-REFADJ 6 17 1658R-LGATE2 PR18 EV@10K_4
REFADJ LGATE2 1 2 +3V
C C
7 PQ41
+3V_S5 +3VPCU R1 PR14 REFIN 13 1658R-PG PR164 *short EV@0_4
PR13 EV_S@20K/F_4
R2 PGOOD GPU_PWR_GD 20 *EV@AON6752
1658R-REFIN
*E@0.01U/25V_4
PC78
EV_S@20K/F_4 12 1658R-COMP
COMP
EV@4700P/25V_4
GND
PR159 PR158 10
FB
1
FBRTN +VIN_GPU_CORE
PC82
EV@10K_4 *EV@10K_4
1
PR165
11
21
DGPU_PSI PR144 EV@2.2/F_6
EV@22P/50V_4
C R3
2
1658R-FBRTN
PC77 EV_S@2K/F_4 1658R-BOOT2
EV@2200p/50V_4
EV@0.1u/50V_6
EV@4.7u/25V_8
EV@4.7u/25V_8
EV@4.7u/25V_8
EV@4.7u/25V_8
2
PC81
EV_S@2700P/50V_4
EV@16K/F_6
1658R-FB
PC87
PC90
PC19
PC17
PC15
PC14
PR160
PR15 PC84
5
*EV@0_4 EV@0.22u/25V_6
1658R-UGATE2 4 4
PR145 PQ34
EV_S@18.2K/F_4
R4 *EV@AON6414AL
1
2
3
1
2
3
Phase Number of Operation *EV@22P/50V_4 PQ35 PL7
1
EV@AON6414AL EV@0.36uh_LDCR
DCR=1.1m ohm
*short EV@0_4
*short EV@0_4
PC80
PR156
PR154
PR147 1658R-PHASE2 +VGPU_CORE
*EV@5.1K/F_4
2
5
PR146
EV_S@0_4
R5 PR23 +
EV@330u/2.5V_6X4.2
EV@330u/2.5V_6X4.2
+ +
EV@330u/2V_7343
EV@2.2/F_6
3
1658R-LGATE2 4 4
EV@0.1u/10V_4
EV@10u/6.3V_8
PC94
PC95
PC93
PC96
PC97
B B
20131018 no need standby function
N15S-GT N15P-GX
1
2
3
1
2
3
2 PQ43 PQ40
PQ33 EV@AON6752 *EV@AON6752 PC20
*EV@2N7002K EV@1000p/50V_6
1
Standby PC76
Location Value Value
1
Function *EV@1U/10V_4
2
PR155 CS26812FB13 CS32002FB29

+VGPU_CORE
PR16 CS31242FB13 CS33302FB14
PR153
、PQ36 *BAM64140000 BAM64140000
PQ34、
Parallel *short EV@0_4 N15S-GT/N15V-GM N15P-GX
、PQ41 *BAM67520000 BAM67520000
PQ40、
PR152 *short EV@0_4
+VGPU_CORE +VGPU_CORE
16 VGA_VCCSENSE
N15S-GT(840M) N15V-GM(820M) Countinue current:26A Countinue current:49A
16 VGA_VSSSENSE
PR151 *short EV@0_4 Peak current:60A Peak current:76A
Location QCI P/N Value QCI P/N Value
PR150 OCP:75A OCP:100A
*short EV@0_4 PR13 CS32002FB29 20K CS32702FB16 27K FSW:300KHz FSW:300KHz
L/L=0mV/A L/L=0mV/A
A
PR14 CS32002FB29 20K CS27502FB11 7.5K A
PR144 CS22002FB19 2K CS00002JB38 0

PR145 CS31822FB16 18K CS26202FB17 6.2K Quanta Computer Inc.
PR146 CS00002JB38 0 CS21742FB00 1.74K PROJECT : ZYW
2A
PC77 CH22706KB14 2.7N CH25604KB18 5.6N +VGPU_CORE(UP1642PQAG)
5 4 3 2 1
5 4 3 2 1
16,17,18
16,17,21
16,19,20,33
+1.05V_GFX
+1.5V_GFX
+3V_GFX 41
D D
VIN +1.05V_GFX +15V +1.05V_S5
5
PR58 PR175 PR40
EV@1M_4 EV@22_8 EV@1M_4
dGPU_D1 4 PQ45
EV@MDV1528Q
3
3
PR64
+1.05V_GFX
3
2
1
*short EV@0_4 PR59
20,40 3V_MAIN_PWGD
2 EV@1M_4 2 2
+1.05V_GFX
TDC : 2.7A
PC27
PEAK : 3.6A
1
PQ10 PQ18 *EV@2.2n/50V_4
PQ20 EV@2N7002K EV@2N7002K
Width : 120mil
1
PC29 PR52 EV@PDTC143TT
1
*EV@1u/10V_4 EV@100K_4
2 VIN +3V_GFX +15V +3VPCU

C C
PR37 PR92 PR53
3
EV@1M_4 EV@22_8 EV@1M_4
dGPU_D 2
3
3
PR212 PQ24
*short EV@0_4 PR33 EV@AO3404 +3V_GFX
1
10 DGPU_PWR_EN
2 EV@1M_4 2 2
PC32
+3V_GFX TDC : 0.23A
PEAK : 0.3A
1
PQ29 PQ30 *EV@2.2n/50V_4

PQ28 EV@2N7002K EV@2N7002K
Width : 40mil
1
PC159 PR96 EV@PDTC143TT
1
*EV@1u/10V_4 EV@100K_4
2
VIN
+5V_S5
+3V
B PC8 PC7 PC74 ZYW B-SMT: B
EV@1u/10V_4 EV@2200p/50V_6 EV@4.7u/25V_8 +1.5V_GFX = 1.35V (EMI issue)
5
PR7
EV@100K/F_4
7
PQ31
EV@MDV1528
V5IN
1.5GFX_DRVH 4
HWPG_1.5VGFX 1 9 PR6 +1.5V_GFX
20 HWPG_1.5VGFX PGOOD DRVH *EV@SHORT_6 PC6
FBVDDQ_EN 1.5GFX_EN 3 10 1.5GFX_VBST PL6
3
2
1
20 FBVDDQ_EN PR9 *short EV@0_4 EN VBST EV@2.2uH_7X7X3
1.5GFX_TRIP 2 PU6 8 1.5GFX_SW EV@0.1u/50V_6
PR8 EV@78.7K/F_4 TRIP EV@TPS51211DSCR
SW
1.5GFX_TST 5 6 1.5GFX_DRVL
PC72 PR12 EV@464K/F_4 TST DRVL
5
*EV@1u/10V_4 12 11
GND GND PR11 PR142 +1.5V_GFX
GND
GND
GND
GND
*EV@4.7_6 EV@11.5K/F_4 1.5 Volt +/- 5%

FB
+
4 TDC : 4.5A
13
14
15
16
PC71 PC73
OCP=8A 1.5GFX_FB EV@0.1u/50V_6 EV@330u/2V_7343
PEAK : 6A
L ripple current PC9 OCP : 8A
3
2
1
PQ32 *EV@680p/50V_6 PR10

=(19-1.5)*1.5/(2.2u*290k*19) EV@MDV1595S EV@12K/F_4 Width : 200mil
=2.165A
Vtrip=8-(2.165/2)*14mohm
=96.84mV
Rlimit=96.84mV/10uA*8=77.47Kohm
A A
ZYW B-SMT:
change PR10 from 10k to 12k

PROJECT : ZYW
2A
+1.5V_GFX/+1.05V_GFX/+3V_GFX
5 4 3 2 1
1 2 3 4 5 6 7 8
VGA power up sequence

42
+3VPCU
+3V_MAIN
PCH MOSFET +3V_GFX
DGPU_PWR_EN
GPIO49 MOSFET
A A
3V_MAIN_EN (GPU GPIO5)
3V_MAIN_PWGD
PG All 3.3V
t>0
NVVDD
PXE_VDD
+1.05V
+1.05V_S5 t>0
FBVDDQ
MOSFET +1.05V_GFX N15x Power on sequance

3V_MAIN_PWGD Notes: -All 3.3V includes all rails powered at 3.3V
-PEX_VDD 1.05V inculdes all rails that are shared
PWM-VID (GPU GPIO11)
VIN
B
+VGPU_CORE B
3V_MAIN_PWGD VIN +1.5V_GFX

PWM
PWM
VGPU_PWRGD
OR FBVDDQ_EN HWPG_1.5VGFX
Gate DGPU_PWROK
VGPU_PWRGD
EC_FB_CLAMP(EC)
GC6_FB_EN (GPU GPIO0 )
C C
GPIO17
VGA Reset
PLTRST#
PEGX_RST#
PCH DGPU_HOLD_RST#
PEX_RST timing
D D
I/O 3.3V
PEX_RST
Trise >= 1uS Tfail <=500nS Quanta Computer Inc.

PROJECT : ZYW
3A
GPU PWR CRL
1 2 3 4 5 6 7 8
5 4 3 2 1
Battery Mode
Support Deep Sx
3
+3VPCU
VIN 1
+5VPCU
VL
3 3
+3VPCU
5b
+3.3V_DSW
1
VIN BAT-V
43
3V_LDO 3V/5V 2
11 2 VR depend on A measure +3.3V_DSW
3 +5VPCU +5V_S5
+15V
result to implement EN CHARGER Battery
EN2
EN1
D
+3VPCU S5 PWR +3V_S5 10 4 for B test D
3
3
S5_ON 8 NBSWON# 5a DSW_ON +3VPCU or +3.3V_DSW
1 VIN Delay DSW power well 10ms DSW PWR

+3VCC_S5
PWR 6 DPWROK DPWROK
SUS PWR
DDR VDDQ +1.35V_SUS 18 BTN 13 RSMRST# +1.05V
RSMRST#
VR 7 14 SB_ACDC ASW PWR
DDR_VTTREF 19 EC ACPRESENT +3V_S5
30 DNBSWON#
15 PWRBTN#
HWPG SUSC# 16 SPI PWR
+DDR_VTT_RUN 23 SLP_S4# +V1.05DX_MODPHY
SUSB# 20 SLP_S3#
HSIO PWR
PCH_SUSACK# SUSACK +1.05V
HWPG_VDDR 24
PG PCH_SUSPWARN# SUSWRAN
PLL PWR
S5
S3
PCH_SLP_SUS# SLP_SUS# +1.05V
31a
APWROK PCH
DDR_PG_CTRL APWROK CORE PWR
C
22 31b PCH_PWROK
+3V C
MAINON
21 31C EC_PWROK PCH_PWROK SDIO PWR
+3V_S5
PCH_CLK
35
PLTRST# HDA PWR
VRON
SUSON
S5_ON
MAINON
EC_PWROK
HWPG_1.05V_EC#
SUSON PLTRST#
17 38
+3VPCU 24 HWPG_VDDR IMVP_PWRGD
3 36 SYS_PWROK
34 SYS_PWROK
26 HWPG_1.05V_S5 EC_PWROK
+1.5V 12 31C
1.5V 38
HWPG_1.5V 30a 31C 32b 21 17 8
VR
PLTRST#
29 29
HWPG_1.5V
PG
EN
+VCCIN
MAINON CORE PWR

21 +1.35V_SUS
RESET#
CPU
VDDQ PWR
+1.05V_VCCST
RUN PWR +1.05V
+1.05V_VCCST PROCPWRGD
B
3 +5VPCU +5V 28 VCCST PWR B
MOS1
SM_PG_CNTL1
VCCST_PWRGD
0 ohm
3 +3VPCU +3V 27
VR_READY
MOS2
VR_EN
EC_PWROK 10K ohm
SVID
+1.05V_S5 +1.05V 31C
9 25
MOS3
G
HWPG_1.05V
1 VIN 12
MAINON
VRON_CPU
DDR_PG_CTRL
21
IMVP_PWRGD
VCCST_PWRGD_EN
SVID
33
+VCC_CORE PCH_PWROK VCCST_PWRGD_EN
VIN IMVP 31b
1 9 VR
SYS_PWROK
+1.05V_S5 36
+1.05V_S5
VR 34
12 IMVP_PWRGD HWPG_1.05V_EC# 37 22 34 32a
HWPG_1.05V_S5 PG 30a
EN
PG
EN
A A
8 SVID VRON_CPU 32a HWPG+1ms

S5_ON
37 VRON 32b
PCH MAINON 21
CPU Quanta Computer Inc.
PROJECT : ZYW
3A
Power Sequence
5 4 3 2 1
1 2 3 4 5 6 7 8
+3V_S5 +3V 44
SDRAM
2.2K 2.2K 4.7K 4.7K
+3V
AP2 SMB_PCH_CLK CLK_SCLK
A 2N7002DW A
AH1 SMB_PCH_DAT Level shift CLK_SDATA Mini Card-WLAN
XDP
Haswell
ULT
+3V_S5
2.2K 2.2K
B B
AN1 VGA_MBCLK
AK1 VGA_MBDATA
+3V_S5
*2.2K *2.2K
+3V_S5
AU3 SMB_ME1_CLK
*2N7002DW
AH3 SMB_ME1_DAT Level shift
+3V_S5 +3V_GFX
C 0 0 C
4.7K 4.7K 4.7K 4.7K
+3V_MAIN
115 2ND_MBCLK
2N7002DW GFX_SCL
Level shift VGA
116 2ND_MBDATA GFX_SDA
+3V
CIICSCL CIICSCL
2N7002DW RTD2136R
EC Level shift CIICSDA CIICSDA
+3VPCU
IT8587 4.7K 4.7K
D D
4.7K 4.7K
110 MBCLK
+3V
111 MBDATA CHARGER
PROJECT : ZYW
3A
Block Diagram
1 2 3 4 5 6 7 8
5 4 3 2 1
實實實defult
虛實實reserve
SYS_HWPG S5D
MDV1528Q +5V_S5 45
VGPU_PWRGD
3V_LDO PWRGD
+5VPCU MDV1528Q +5V
D
PWR EN1 PWRGD
D
S5_Vout
3V/5V MAIND
VIN Vin
VGPU Core Vout
+VGPU_CORE
up1658
TPS51225
3V_LDO EN
EN2 3V_MAIN_PWGD
Vin S3_Vout +3VPCU AO3404 +3V_S5
VIN
S5D
HWPG_1.5VGFX
MDV1528Q +3V
MAIND PWRGD
VIN Vin
+1.5V_GFX Vout
TPS51211
+1.5V_GFX
EN
AO3404 +3V_GFX FBVDDQ_EN
C C
dGPU_PWR_EN
PCH
HWPG_1.05V
AON6756 +1.05V
PWRGD
VIN +1.05V_S5 MAIND

Vin Vout +1.05V_S5
TPS51211
IMVP_PWRGD
EN
S5_ON MDV1528Q +1.05V_GFX
EC PWRGD
3V_MAIN_PWGD VIN +VCC_CORE Vout +VCC_CORE
B B
Vin
MAINON TPS51624RSMR
EC EN
AO3404 +1.05V_MODPHY VRON_CPU
VRON
MODPHY_EN
PCH
HWPG_VDDR
HWPG_1.5V
SUSON PWRGD
+1.35V_SUS PWRGD
EC S5 EN
S5_Vout +3VPCU +1.5V
+1.35V_SUS DDR_VTTREF Vin Vout +1.5V
TPS54318
TPS51216 EN
DDR_VTTT_PG_CTRL
MAINON
A
PCH S3 EN
A
Vin S3_Vout +DDR_VTT_RUN
MAINON

VIN
PROJECT : ZYW
3A
ULT PWR CONTROL
5 4 3 2 1

Haswell ULT 15W: Vram Ddr3L-Sodimm Cha

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Haswell ULT 15W: Vram Ddr3L-Sodimm Cha

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5 4 3 2 1

SATA2/PCIE6_L1 DDI2 ITE6513

Global Jack Speaker*2 HALL SENSOR FAN Touch PAD

Quanta Computer Inc.

Haswell ULT (DISPLAY,eDP)

26 INT_HDMITX1N DDI1_TXN1 EDP_TXN1 EDP_TXN1 24

23 CRT_TXP0 DDI2_TXP0 EDP_AUXN EDP_AUXN 24

Quanta Computer Inc.

Quanta Computer Inc.

DRAM COMP XDP PU/PD DDR3L ODT GENERATION +1.35V_SUS

PU/PD of CPU DRAMRST

H_PROCHOT# R671 *62_4

CPU_DRAMRST# R252 *short_4 DDR3_DRAMRST# 14,15

H_PWRGOOD_R R647 10K_4 C249

Size Document Number Rev

C378 *MMBT3904-7-F C369 Q30

*1000p/50V_4 *1000p/50V_4 *DTC144EU

Date: Tuesday, April 29, 2014 Sheet 5 of 46

Haswell ULT (CFG,RSVD)

CFG3 DISABLED ENABLED CFG3 R687 *1K_4

CFG 8 DISABLED(DEFAULT); IN THIS CASE, NOA ENABLED; NOA WILL BE AVAILABLE

CFG9 NO VR SUPPORTING SVID IS PRESENT. THE CFG9

Haswell ULT PCH (PM)

SYSTEM POWER MANAGEMENT

EC_PWROK R537 *0_4 SYS_PWROK_R

PCH PM PU/PD PLTRST# Buffer Deep Sx Circuit Non Deep Sx

SYS_RESET# R533 10K_4

DPWROK_R R204 100K/F_4 TC7SH08FU R130

+3V_S5 C381 *0.1u/10V_4 Q31

PCH_BATLOW# R536 8.2K_4

R176 *10K_4 TC7SH08FU R350

RTC Clock 32.768KHz (RTC)

HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 SATA_RXN_1ST_SSD# SPI_MOSI

W25Q64FW -- 8MB C535 2

0 = Default SPI (iPD 20K) 10 GPIO86

0 = Enable an external display

NGFF VGA WLAN LAN

USB3RP1 USB3_RXP1 30 16 CLK_PCIE_VGAP CLKOUT_PCIE_P4

27 PCIE_RXN_WLAN# PERN4 27 CLK_PCIE_NGFFP CLKOUT_PCIE_P5

Quanta Computer Inc.

PCH GPIO PU/PD

high UMA Only

Board ID CPU thermal trip GPU power is control by PCH

+V1.05S_VCCUSBCORE R270 *short_8 +1.05V

VCCAPLL power +1.05V +V1.05S_AXCK_DCB

+1.05V +V1.05S_APLLOPI L18 2.2uH/210mA_8

C233 C232 C263

PCH HDA Power L20 2.2uH/210mA_8

Haswell ULT (GND) 12

DC_TEST_AY2_AW 2 AY2 A3 DC_TEST_A3_B3

Quanta Computer Inc.

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

+VREF_CA_CPU R272 *short_6 R279 2/F_6

0.022u/16V_4 1.8K/F_4 470p/50V_4

C291 + C300 C281 C277 C384 C382

C344 C347 C321 C348 C313 2.2u/6.3V_6 2.2u/6.3V_6

SA1 SA0 Quanta Computer Inc.

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

C343 C319 C350 C309 C294 2.2u/6.3V_6 2.2u/6.3V_6 R348

A C203 C205 C204 C206 C200 C202 C201 A

+VGPU_CORE PLACE UNDER GPU BALLS

1000p/50V_4 1000p/50V_4 *DTC144EU