CMEN722

TUTORIAL ON LECTURE 2 & 3

DIGITAL SYSTEM DESIGN WITH VHDL
Q1
What is VHSIC Hardware Description Language (VHDL)?
Solution
VHDL is an industry standard language used to describe hardware from the abstract to concrete
level.
Q2
List the basic features of VHDL and explain any three?
Solution
i. Concurrency
ii. Supports sequential statements
iii. Supports for test & simulation
iv. Strongly typed language
v. Supports hierarchies
vi. Supports for vendor defined libraries
vii. Supports multivalued logic

Q3
Why Use VHDL?
Solution
Quick Time-to-Market
i. Allows designers to quickly develop designs requiring tens of thousands of
logic gates
ii. Provides powerful high-level constructs for describing complex logic
iii. Supports modular design methodology and multiple levels of hierarchy
One language for design and simulation

Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
 Allows creation of device-independent designs that are portable to multiple vendors. Good
for ASIC Migration
Allows user to pick any synthesis tool, vendor, or device

Concurrency:
i. VHDL is a concurrent language.
ii. HDL differs with Software languages with respect to Concurrency only.
iii. VHDL executes statements at the same time in parallel, as in Hardware.

Supports sequential statements:

i. VHDL supports sequential statements also, it executes one statement at a time in sequence
only.
ii. As the case with any conventional languages.
Example:
if a=‘1’ then y<=‘0’;
else y<=‘1’;
end if ;

Supports for test & simulation:

i. To ensure that design is correct as per the specifications, the designer has to write another
program known as “TEST BENCH”. ii. It generates a set of test vectors and sends them to
the design under test (DUT).
iii. Also gives the responses made by the DUT against a specification for correct results to
ensure the functionality.

Strongly typed language:

i. VHDL allows LHS & RHS operators of same type. ii.
Different types in LHS & RHS are illegal in VHDL.
iii. Allows different type assignment by conversion.
Example:
A : in std_logic_vector (3 down to 0).
B : out std_logic_vector (3 down to 0).
Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
C : in bit_vector (3 down to 0).
B <= A; --perfect.
B <= C; --type miss match, syntax error.
Supports hierarchies:
i. Hierarchy can be represented using VHDL.
ii. Consider example of a Full-adder which is the top-level module, being composed of three
lower level modules i.e. Half-Adder and OR gate.

Example :

Levels of abstraction:
i. Data Flow level o In this style of modeling the flow of data through the entity is expressed
using concurrent signal assignment statements.
ii. Structural level o In this style of modeling the entity is described as a set of interconnected
statements.
iii. Behavioral level. o This style of modeling specifies the behavior of an entity as a set of
statements that are executed sequentially in the specified order.
Q4
Mention the VHDL identifiers you know?
Solution
i. Identifiers are used to name items in a VHDL model.
ii. A basic identifier may contain only capital ‘A’ - ’Z’ , ‘a’ - ’z’, ‘0’ - ’9’, underscore character
‘_’
iii. Must start with an alphabet. iv. May not end with an underscore character.
v. Must not include two successive underscore characters.
vi. Reserved word cannot be used as identifiers. vii. VHDL is not
case sensitive.
Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
Q5
What are the basic objects of VHDL?
Solution
i. There are three basic object types in VHDL
• Signal: represents interconnections that connect components and ports.
• Variable: used for local storage within a process.
• Constant: a fixed value. ii. The object type could be a scalar or an array.
Q6
Distinguish between variables and signals?
Solution
Signals vs. Variables:
i. Variables can only be used inside processes; signals can be used inside or outside
processes.
ii. Any variable that is created in one process cannot be used in another process; signals can
be used in multiple processes though they can only be assigned in a single process.
iii. Variables need to be defined after the keyword process but before the keyword begin.
Signals are defined in the architecture before the begin statement.
iv. Variables are assigned using the := assignment symbol. Signals are assigned using the <=
assignment symbol.
v. Variables that are assigned immediately take the value of the assignment. Signals depend
on if it's combinational or sequential code to know when the signal takes the value of the
assignment.
Q7
What is programmable logical array? List suitable user programmable logic families you know.
Solution
A programmable logic array (PLA) is a type of logic device that can be programmed to implement
various kinds of combinational logic circuits. The device has a number of AND and OR gates
which are linked together to give output or further combined with more gates or logic circuits.
a. PLA (Programmable array logic)
b. PAL (Programmable logic array)
c. GAL (gate array logic )
Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
 d. CPLD (Complex programmable logic device)
e. FPGA (Field-programmable gate array)
f. SOC (system on chip)
Q8
Write short note on the following:
FPGA
CPLD
Operator overloading
Packet switching
Solution FPGA:
A field-programmable gate array (FPGA) is an integrated circuit that can be programmed or
reprogrammed to the required functionality or application after manufacturing. Important
characteristics of field-programmable gate arrays include lower complexity, higher speed, volume
designs and programmable functions. With more technological advances, field-programmable gate
arrays are a convenient proposition for most designs and markets.
CPLD:
A complex programmable logic device (CPLD) is a logic device with completely programmable
AND/OR arrays and macrocells. Macrocells are the main building blocks of a CPLD, which
contain complex logic operations and logic for implementing disjunctive normal form expressions.
AND/OR arrays are completely reprogrammable and responsible for performing various logic
functions. Macrocells can also be defined as functional blocks responsible for performing
sequential or combinatorial logic.
Operator overloading is a technique by which operators used in a programming language are
implemented in user-defined types with customized logic that is based on the types of arguments
passed.

Operator overloading:
Operator overloading facilitates the specification of user-defined implementation for operations
wherein one or both operands are of user-defined class or structure type. This helps user-defined
types to behave much like the fundamental primitive data types. Operator overloading is helpful
Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
in cases where the operators used for certain types provide semantics related to the domain context
and syntactic support as found in the programming language. It is used for syntactical convenience,
readability and maintainability.

Packet switching:
Packet switching is a digital network transmission process in which data is broken into
suitablysized pieces or blocks for fast and efficient transfer via different network devices. When a
computer attempts to send a file to another computer, the file is broken into packets so that it can
be sent across the network in the most efficient way. These packets are then routed by network
devices to the destination.

Q9
Distinguish between inertial delay and transport delay?
Solution
Inertial delay of a system is the time required by that system to recognize the changes in its input.
So input changes will be reflected at the output if and only if the input remains stable more than
inertial delay. Transportation delay is the time required by the system to pass its input changes to
output.
Q10
Write a VHDL program to model a 4-bit comparator

Solution entity Exercise is port ( A : in

std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
Ag : out std_logic;
Bg : out std_logic;
AeqB: out std_logic
);
end Exercise;

architecture Comparator of Exercise is

begin
Ag <= '1'when (A>B) else '0';
Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
 Bg <= '1' when (B>A) else '0'; --Problem: Here if i sumulate B="ZZZZ", Bg is 1, asi if B>A
AeqB<= '1' when (A=B) else '0';
end Comparator;
or

Solution
ENTITY compare IS
PORT ( A, B : IN SIGNED(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END compare ;
ARCHITECTURE Behavior OF compare IS BEGIN
AeqB <= ‘1’ WHEN A = B ELSE ‘0’ ;
AgtB <= ‘1’ WHEN A > B ELSE ‘0’ ;
AltB <= ‘1’ WHEN A < B ELSE ‘0’ ;
END Behavior ;

Q11
List the merits and demerits of FPGAs?
Solution
Merits of FPGAs:
a. Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA
design.
b. No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design.
For FPGA this is not there. FPGA tools are cheap.
c. Simpler design cycle: This is due to software that handles much of the routing, placement,
and timing. Manual intervention is less.
d. More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer
capacities, etc of the project since the design logic is already synthesized and verified in
FPGA device.
e. Field Re-programability: A new bit stream ( i.e. your program) can be uploaded remotely,
instantly.

f. Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be
implemented on FPGA which could be verified for almost accurate results so that it can be
implemented on an ASIC.
Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
Demerits of FPGAs:
a. Power consumption in FPGA is more. You don’t have any control over the power
optimization. This is where ASIC wins the race!
b. You have to use the resources available in the FPGA. Thus FPGA limits the design size.
c. Good for low quantity production. As quantity increases cost per product increases
compared to the ASIC implementation.
Q12
Why VLSI ?
Solution
a. Building complex electronic circuit using discrete components are difficult and expensive
- Cost depends on quantity of devices.
b. Integrated circuits solved much of the problems
c. Print many tiny circuits on
d. Cost depends on die size.
Q13
List the advantages of VLSI?
Solution
a. Reduction in size, power, design, cycle time.
b. Design security.
c. Easy up-gradation.
d. Low cost.
e. Remote Programmability.
f. Long time in market.

Q14
Write down the Boolean expression for the circuit output Z as shown in Figure 1?

Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
 Figure 1
Solution
A•C=B

B•C=E
A•B=F
Z=B+E+F

Z =A•C+B•C+A•B

Q15
Provide the Boolean expression from the given true table of Z output and write the equivalent
VHDL code that represent the derived Boolean expression.

Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
Solution

Q16
Write a behavioral VHDL description for a 4-bit shift register. The shift register is to be negative
edge triggered. Sin is a serial input to the most significant bit of the shift register. Sout is a serial
output from the least significant bit of the shift register. En_n is an active low enable. sreg is the
4-bit register. Write only the VHDL ARCHITECTURE construct. The VHDL ENTITY construct
is given below.

Solution

Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
Q17
Draw a diagram for typical output circuitry in a PLA. Describe each component. Solution

Figure 2 Description:
The D flip-flop provides storage capability for the PLA block, allowing sequential circuits to be
implemented. The multiplexer selects either registered or non-registered outputs from the PLA.
The tri-state gate allows the output to have tri-state capabilities. Feedback into the programmable
AND plane is provided as well.

Q18
What is the purpose of a sensitivity list in a VHDL PROCESS block?

Solution
The list contains all signals that can be used to activate the process.

Q19
Give the VHDL statement to implement the logic function in Figure 2 using a selected assignment
statement. Define any signals used in the statement.

Solution
SIGNAL xyz : STD_LOGIC_VECTOR(2 DOWNTO 0);
xyz <= x & y & z; WITH xyz SELECT
f <= ‘1’ WHEN “000”, ‘1’
WHEN “001”,
Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
‘1’ WHEN “010”,
‘1’ WHEN “101”,
‘1’ WHEN “111”,
‘0’ WHEN OTHERS;

Q20
Write a behavioral VHDL description for a 2-to-1 multiplexer. Model the multiplexer as a
process block Write only the VHDL ARCHITECTURE construct. The VHDL ENTITY
construct is given below:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux2to1 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s : IN STD_LOGIC; f : OUT STD_LOGIC );
END mux2to1;

Solution
ARCHITECTURE Behavior OF mux2to1 IS
BEGIN
PROCESS (w,s)
BEGIN
IF s = '0' THEN
f <= w(0); ELSE
f <= w(1);
END IF;
END PROCESS;
END Behavior;

Q21
Write down the expression for the final output f from the given Figure 3, show all steps involve.

Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
 Figure 3
Solution
The functions realized at each point are:

Q22
Write down the expression for the final output f from the given Figure 4. Show all functions at
each point.

Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!
 Figure 4
Solution

Lecturer: Engr. Dr. M. J. Musa (𝑴𝑪𝑶𝑹𝑬𝑵, 𝑴𝑵𝑰𝑨𝑬, 𝑴𝑨𝑪𝑬, 𝑴𝑰𝑨𝑬𝑵𝑮) Good luck!