ALPHA COLLEGE OF ENGINEERING

Approved by AICTE & affiliated to Anna University & ISO Certified

Thirumazhisai, Chennai-600 124

QUESTION BANK

SUBJECT : CS6801MULTICORE ARCHITECTURE AND PROGRAMMING

SEM/YEAR : VIII/IV
UNIT I MULTI-CORE PROCESSORS
Single core to Multi-core architectures – SIMD and MIMD systems – Interconnection networks - Symmetric
and Distributed Shared Memory Architectures – Cache coherence - Performance Issues –
Parallel program design.
PART-A
Q.No Questions MARKS Appeared in
Month/Year
1 Express the term latency and throughput.
2 Analyze the agglomeration /Aggregation.
3 Define SIMD and MIMD.
4 List the different types of interconnect.
5 Discuss symmetric shared memory. 2 N/D-‘18
6 Interpret foster’s Methodology.
7 Differentiate symmetric memory Architecture and distributed memory
Architecture.
8 Give the pros and cons of distributed memory.
9 What is the purpose of multi-core integrated circuits?
10 Demonstrate directory based coherence.
11 Draw UMA and NUMA architecture.
12 Explain false sharing.
13 Formulate how multicore processor superior to single core processor?
14 State Amdhal’s law. 2 N/D-‘18
15 Show the Flynn’s Classification taxonomy.
16 Define vector instructions. 2 A/M-‘17
17 What do you mean by snooping cache coherence? 2 A/M-‘17
18 Analyze the formula for speed up and efficiency of parallel program.
19 Illustrate the cache coherence with example.
20 Summarize the protocols used in cache coherence.

21 Define speedup.

22 Write down the performance metrices 2 A/M-18

23 List the steps in designing a parallel program.

24 Define efficiency.

25 Define the terms latency and throughput.

 ALPHA COLLEGE OF ENGINEERING
Approved by AICTE & affiliated to Anna University & ISO Certified
Thirumazhisai, Chennai-600 124

PART B
1 i) Explain parallel program design with example. 7 A/M-‘17
ii) Write Short notes about MIMD system. 6
2 Describe in detail about interconnection network with neat diagram. 13 A/M-‘17
3 i) Define cache coherence problem. What are the two main approaches 7
to cache coherence?
ii) Describe the working of snooping cache coherence and directory 6
based coherence.
i)Describe the developments from single core to multi core 7 A/M-‘19
4. architecture. N/D-‘18
ii) Compare single core and multi core processor. 6
5 i) Explain in detail about SIMD and MIMD systems. 8 A/M-‘17
ii) Discuss briefly the performance issues of multicore processors. 5
6 Explain in detail about distributed shared memory architecture 13 N/D-‘18
highlighting the directory based cache coherence protocol. Substantiate
your explanation with suitable examples and statediagrams.
7 Illustrate Flynn’s classification in detail with neat diagram. 13
8 Describe the foster’s methodology in detail with suitable examples. 13
9 i)Formulate Amdhal’s law and its limitations in detail. 5
ii) Outline the steps in Designing and building parallel programs. Give
example. 8
10 Illustrate symmetric shared memory architecture in detail with neat 13
diagram.
11 Describe the following in detail 7
i)UMA systems.
ii) NUMA systems. 6
12 Analyze and elaborate about parallel program design? 13 A/M-‘17
13 Explain the following in detail 6 A/M-‘19
i)Shared memory interconnect. 7
ii)Distributed memory interconnect
1 Discuss in detail about the performance issues in the parallel 13
4 programming.
15 What is Amdahl’s Law? Pointout the Kinds of Problems we Solve with 13
Amdahl’s Law?
16 Explain how a queue, implemented in hardware in the CPU, could be 15
used to improve the performance of a write-through cache.
17 In our discussion of parallel hardware, we used Flynn’s taxonomy to identify 15
three types of parallel systems: SISD, SIMD, and MIMD. None of our
systems were identified as multiple instruction, single data, or MISD. Assess
how would an MISD system work? Give an example.
18 Generalize your view about why the performance of a hardware
multithreaded processing core might degrade if it had large caches and
 ALPHA COLLEGE OF ENGINEERING
Approved by AICTE & affiliated to Anna University & ISO Certified
Thirumazhisai, Chennai-600 124

it ran many threads. 15

UNIT II - PARALLEL PROGRAM CHALLENGES

Performance – Scalability – Synchronization and data sharing – Data races – Synchronization primitives
(mutexes, locks, semaphores, barriers) – deadlocks and livelocks – communication between threads
(condition variables, signals, message queues and pipes).
PART-A
Q.No Questions MARKS Appeared in
Month/Year
1 Show the two common metrics for performance. 2 A/M-‘19
2 Analyze about scalability.
3 Examine what is data sharing?
4 Define critical region. 2 A/M-‘19
5 Define region of code.
6 Discuss about data race. 2 A/M-‘19
7 Illustrate the conditions to avoid data race.
8 Classify the synchronization primitives. 2 N/D-‘18
9 Give definition for mutex lock and spin lock. 2 A/M-‘18
10 Generalize on semaphore and barrier.
11 Tabulate the difference between deadlock and livelock. 2 N/D-’18,
A/M-‘17
12 Formulate the condition under which a deadlock situation may arise.
13 What is thread? Assess the use of swapping.
14 List out the different ways of communication between thread.
15 Differentiate condition variables and signals.
16 What is data sharing? 2 A/M-‘17
17 Summarize message queue.
18 Point out the difference between message queues and pipes.
19 Define signals and events.
20 Explain Livelock.
21 Define Synchronization.
22 Define semaphores.
23 Define Readers-Writer Locks.
24 Define signals and events.
25 Define von neuman architecture 2 A/M-‘19
PART-B
1 i)Discuss in detail about the hardware constraints applicable to improve 6 A/M-‘18
scalability.
ii)Describe the various approaches in parallel programming. 7
2 Illustrate the following in parallel program
i)Performance. 7
ii) Scalability. 6
3 Describe in detail about the synchronization primitives in parallel 13 A/M-‘18
program challenges.
4 i)Generalize on what is data race? What are the tools used for detecting 7 A/M-‘18
data race?
ii)How to avoid data race? Explain in detail. 6
5 i) Examine the necessity of structure reflects in performance. 7
ii) Identify and explain data race detection with suitable example. 6
 ALPHA COLLEGE OF ENGINEERING
Approved by AICTE & affiliated to Anna University & ISO Certified
Thirumazhisai, Chennai-600 124

6 With suitable example describe the following. 9 N/D-‘18

(i)Mutex (3) (ii)Semaphore(3) (iii)deadlock(3)
(iv)livelock(2) (v)Named pipes(2) 4
7 i)Explain in detail about spinlock and reader/Writer problem. 8
ii)Explain in detail about barrier. 5
8 i)Define Deadlock and describe it with suitable example.(8) 8 N/D-‘18
ii)Tabulate the difference between deadlock and Livelock.(5) 5
9 Describe in detail about the difference between Message queue and 13
Named pipes.(13)
10 i)Discuss about two threads in a Livelock.(7) 7
ii)Discuss about two threads in a deadlock.(6) 6
11 Explain the following in detail.
i)condition variables.(7) 7
ii)signals and events.(6) 6
12 i)Explain in detail about producer consumer synchronization.(7) 7
ii)Write a simple semaphore to sent a message.(6) 6
13 Summarize the concept of communication between threads.(13) 13