GRD Journals- Global Research and Development Journal for Engineering | Volume 5 | Issue 5 | April 2020

ISSN- 2455-5703

Extraction of Impulse Noise using FPGA

A. V. Kiranmai L. Soniya
Associate Professor UG Student
Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering
Potti Sriramulu Chalavadi Mallikarjunarao College of Potti Sriramulu Chalavadi Mallikarjunarao College of
Engineering and Technology Engineering and Technology

Y. Anudeep V. Venkatesh
UG Student UG Student
Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering
Potti Sriramulu Chalavadi Mallikarjunarao College of Potti Sriramulu Chalavadi Mallikarjunarao College of
Engineering and Technology Engineering and Technology

Abstract
The elimination of noise from images becomes a trending field in image processing. Images may get corrupted by random change
in pixel intensity, illumination, or due to poor contrast and can’t be used directly. Subsidiary information from such images are
extracted by removing the noise, sharpening contrast and detection of the edges by using several filtering techniques. Median
filtering is one such nonlinear based method which removes range isolated noise like salt & pepper noise while preserving the edge
information. Its miles a computationally intensive operation, so it is hard to put into effect it in actual time. This system introduces
a brand-new structure and optimizations for its implementation with FPGAs. The practical consequences show the effectiveness
of our improvements allowing actual-time processing and a minimal use of sources. FPGA result is validated by implementing
the above algorithm in MATLAB when the images are corrupted by noise models.
Keywords- Median Filter, FPGA, Spartan3, Impulse Noise, Xilinx, Matlab

I. INTRODUCTION
Image Processing is used in many fields such as medical imaging, robotics and digital digicam. In lots of these applications due to
imperfection of picture sensors, pix are frequently corrupted by using noise. Impulse noise is most often found sort of noise.
Impulse noise is also caused by malfunctioning pixel in digital camera sensors, defective reminiscence in hardware or mistakes in
information transmission.
There are specially two kinds of impulse noise:-
1) Salt-Pepper Noise (Depth Spike and Speckle Noise):
For images corrupted by salt-pepper noise, the noisy pixel can take most effective maximum and minimum value.
2) Random Valued Shot Noise
In case of random value shot noise noisy pixels have an arbitrary cost. Salt-pepper noise is characterized by way of black and white
spots at the photograph. Median clear out may be very powerful in the removal of salt-pepper noise. Median clear out also preserves
the edges of picture during removal of noise. Photo signal and present noise sorts are typically nonlinear that’s why Median filter
out, being a non-linear clear out, is popularly used. Median filter uses sorting algorithm, wherein processing time is appreciably
excessive. To improve execution speed of sorting technique, we used parallel and pipeline method, which may be done by
implementing the filter on FPGA (discipline Programming Gate Array). Enforcing picture processing algorithms on reconfigurable
tool minimizes the time-to-market cost, enables fast prototyping of complex algorithms and simplifies debugging and verification
additionally, the reprogrammable function of FPGA gadgets provides the person with speedy adaptation of the system to ever-
changing needs.

II. RELATED WORKS

Numerous researchers proposed special strategies for hardware implementation of median filter out to reduce time and to boom
the execution pace. In one in all the initial works to introduce novel styles for median filter [1]
Building on these multi-level median filter styles Miguel A. Vega-Rodríguez, et. al. brought new structure and optimizations for
implementation of Median filter with FPGA for assembly actual-time requirements [2].
M. Jiang and D. Crookes in addition prolonged the systolic array structure based on triple sorting set of rules and proposed
excessive overall performance structure of median clear out for 3D photograph de-speckling [3].
Tripti Jain et. al. proposed a reconfigurable
FPGA based totally filter out that as compared the photo filtering velocity for 3x3, 5x5 and 7x7 window size for numerous picture
sizes [4].

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Yan Lu, et. al. cautioned optimized sorting algorithm for actual time FPGA based median clear out of the human visual gadget [5].
Pingjun Wei, et. al. proposed a fast median filtering set of rules on FPGA that made upgrades to traditional median filtering
algorithm by means of including evaluation threshold to similarly beautify the median clear out traits of maintaining photo element
[6].
Yueli Hu, Huijie Ji et. al. discussed preferred and multi-degree Median Filters and supplied FPGA primarily based solutions for
those [7].
Zdenek Vasicek and Lucas Sekanina proposed a unique hardware implementation for adaptive median clear out [8].
Takeaki Metsubara et. al. presented a unique technique having very low computational complexity however nonetheless presenting
superior fine of effects in phrases of PSNR and image fine for impulse-noise reduction [9].
Carlos R. Castro-Pareja et. al. provided appropriate 3D median filter out architecture for FPGA that consisted of an ordered semi-
systolic array of length equal to the filter window length [10].

III. MEDIAN FILTER

Filters are the operative gear to eliminate the noise. Filters are used to eliminate noise and also used as precursor to in addition
processing. Linear and nonlinear are the two varieties of filters in image processing.
A non-linear filter out is one that can't be performed with convolution or Fourier multiplication. Filters re-compare the
cost of every pixel in an image. For a specific pixel the brand new cost is based on pixel values in a neighborhood location a
window focused on that pixel so one can reduce noise or increase edges. Filters may also either be implemented without delay to
recorded pictures or after transformation of pixel values.
Median filter is non-linear filter which is likewise referred to as rank choice filter and sliding window spatial filter because
it works in spatial area. To reduce the noise it endeavours fee of spike of the noise by using luminance of center pixel with median
of that window. The mathematical expression of median filter out is as follows.
S=s (i, j), in which S taken as filtering image.
S (i, j) is median (k, l) ∈ Wm,n{D(i+k,j+l)}
Where Wm,n is sliding window of mxn pixels sized centered at coordinates( i,j).
Sorting strategies inclusive of bubble sort and quick sort has been the usage of to sort out the pixels to organize the pixel
samples inside the order of upwards or downwards in algorithms which is used for sorting where ns has high price. To attain the
N×N value of the median, the quantity of operations implemented in conventional set of rules is 3/8(n 4 -1) contrast.
The processing time and speed of the facts is not good whilst the quantity of operations encompassed in FPGA. So the
sorting approach, merged insertion kind is proposed that's faster than different sorting strategies. Minimization of comparisons can
be carried out via using this sorting and additionally there is a danger to extend the quantity of comparisons. It reduces the
complexity too.

IV. IMPLEMENTATION OF HARDWARE

To implement the system technically in hardware it must have filters for noise elimination like median filter, UART, PC, memory,
control unit.

A. FPGA
FPGAs, as illustrated in Figure given below include associate degree array of programmable logic blocks of doubtless differing
kinds, together with general logic, memory and number blocks, enclosed by a programmable routing that enables blocks to be
programmable interconnected. The array is enclosed through programmable input/output blocks, tagged I/O within the figure that
connect the chip to the skin world.

Fig. 1: Basic structure of FPGA

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B. Memory
The data of the image processed straightly, it could receive modified with the aid of pixel misplacement i.e. because of the
inequality time of writing and studying. An asynchronous FIFO is inserted among FPGA and FIFO for records buffering. To set
up the cached information, FIFO is taken to organize the structure of pipeline with the aid of ping pong operation. To acquire the
image information which consisting 8bit and sequential flow of show SDRAM is inserted that is having twin ports for reading and
writing the operation. To gather the statistics of the picture write port is used. By using forming a skilled frame buffer with
acceptable timing signal for VGA show read port is employed.

C. Generation of Matrix
Inside the module of the system, for simulating pipeline processing set of rules it is mandatory to swear the range of 25 pixels
inside the window to perform straight away. There’s a need of four shift registers and 25 registers for designing hardware
technically of 5×5 sampling window.

D. UART
The device which transforms the statistics parallel to serial is prevalent asynchronous transmitter receiver (UART). It transmits the
information within the shape of bytes successively a piece at a time from supply but it gets the information in bytes on the cease.
It decodes the records that's sequential having manage bit on the destination. In the entire process the clock signal is not required.
Consequently it classified as asynchronous communication. The speed of the transmission can be calculated inside the form of
baud rate.

E. Control Unit

Fig. 2: Hardware Architecture

In FPGA Control units are used to acquire and process data which is obtained from the sensors. To ensure higher overall
performance and simplicity implementation, there's a requirement of control unit to regulate the data among supply and vacation
spot for transforming.

V. RESULTS

A. Simulation Results
The median filtering algorithm defined above is implemented the usage of MATLAB. The 3x3 filter window is traversed through
the 128x128 image – first along rows and then alongside columns and subsequently along diagonals. Due to the selected filter out
window size, first row & column and closing row & column of the 128x128 photo are not filtered. Those rows & columns can be
overlooked or reproduced in filtered image as it is. The ensuing filtered picture is of size 128x128 pixels. The filtered R, G & B
additives are stacked collectively to reconstruct 128x128x3 RGB filtered image copy of the original picture.

B. FPGA based Median Filter

The impulse noise has been suppressed with the aid of using median filter that is carried out in hardware based on FPGA Spartan
3 kit package inside the bundle of TQ400 with enriched correct results. The practical results of simulation with the aid of the usage
of ISE (VHDL/Verilog) and Xilinx platform studio is used and code has been written in C language.

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Fig. 3: Impulse Noise added image

Fig. 4: Filtered Image using Matlab

Fig. 5: Filtered Image using FPGA

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 Extraction of Impulse Noise using FPGA
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Fig. 6: RTL Schematic of Median Filter

Fig. 7: Graphical design view

VI. CONCLUSION
By analyzing the former experimental results, concludes that this task has been diminishes the vicinity and optimizes the restrictions
like power, area. It fulfils the hardware implementation technically and eradicates the noise to achieve the actual time requirements.
By means of the usage of novel sorting method it minimizes time consumption and will increase the processing speed. Overall
performance has progressed while compare to previous techniques and computational complexity has been decreased.

VII. FUTURE SCOPE

There are numerous strategies in future work like by using imposing different filters to suppress noise in RGB images in another
versions of FPGA and by means of the use of SDRAM for memory for better manner of optimization.

REFERENCES
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[4] Tripti, Bansod, Singh Kushwah and Mewara, “Reconfiguration Hardware for median filtering for image process application”, 3rd International Conf. on
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[10] Castro-Pareja, Jagadeesh, Venugopal, Raj Shekhar, “FPGA primarily based 3D Median Filtering exploitation word-parallel heartbeat arrays”, IEEE ISCAS
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