module testbench;

parameter DATA_WIDTH = 1;

parameter DEPTH = 1;

reg clk;

reg cs;

reg we;

reg oe;

wire data;

reg tb_data;

integer i;

sync_ram #(DATA_WIDTH) u0 ( clk,data,cs,we,oe);

always #10 clk = ~clk;

assign data = !oe ? tb_data : 'hz;

initial begin

{clk, cs, we, tb_data, oe} <= 0;

repeat (2) @ (posedge clk);

for ( i = 0; i < 2; i= i+1)

begin

repeat (1) @(posedge clk)

we <= 1;

cs <=1;

oe <= 0;

tb_data <= $random;

end

for (i = 0; i < 2; i= i+1)

begin

repeat (1) @(posedge clk)

we <= 0;

cs <= 1;

oe <= 1;

end
#20 $finish;

end

initial

begin

$dumpvars;

$dumpfile("dump.vcd");

end

endmodule

design code

module sync_ram

# (parameter DATA_WIDTH = 1,

parameter DEPTH = 1)

(input clk,inout data,input cs,input we,input oe);

reg tmp_data;

reg mem ;

always @ (posedge clk)

begin

if (cs & we)

mem <= data;

end

always @ (posedge clk)

begin

if (cs & !we)

tmp_data <= mem;

end

assign data = cs & oe & !we ? tmp_data : 'hz;

endmodule
module testbench;

reg clk, in, reset;

wire out;

reg [1:0] k;

reg tb_in;

integer loop = 20;

always #10 clk = ~clk;

seq_detect u0 ( clk,reset,in,out );

initial begin

clk <= 0;

reset <= 0;

in <= 0;

repeat (5) @ (posedge clk);

reset <= 1;

`ifndef RANDOM

// Given pattern

@(posedge clk) in <= 1;

@(posedge clk) in <= 1;

@(posedge clk) in <= 1;

@(posedge clk) in <= 1;

@(posedge clk) in <= 1;

@(posedge clk) in <= 0;

@(posedge clk) in <= 1;

@(posedge clk) in <= 1;

@(posedge clk) in <= 0;

@(posedge clk) in <= 1;

@(posedge clk) in <= 1;

@(posedge clk) in <= 0;

 @(posedge clk) in <= 1;

@(posedge clk) in <= 1;

@(posedge clk) in <= 0;

@(posedge clk) in <= 0;

@(posedge clk) in <= 1;

@(posedge clk) in <= 0;

@(posedge clk) in <= 1;

@(posedge clk) in <= 1;

`else

// Using a for loop that drives a random value of input N times

for (int i = 0 ; i < loop; i ++)

begin

k = $random;

repeat (k) @ (posedge clk);

tb_in = $random;

in <= tb_in;

end

`endif

#100 $finish;

end

always @ (posedge clk)

begin

$strobe ("T=%0t in=%0b out=%0b", $time, in, out);

end

initial begin

$dumpvars;

$dumpfile("dump.vcd");

end

endmodule
design code

module seq_detect ( input clk,

input reset,

input in,

output out );

parameter S0 = 0,

S1 = 1,

S2 = 2,

S3 = 3,

S4 = 4;

reg [2:0] pr_state, next_state;

assign out = pr_state == S4 ? 1 : 0;

always @ (posedge clk)

begin

if (!reset)

pr_state <= S0;

else

pr_state <= next_state;

end

always @ (pr_state or in)

begin

case (pr_state)

S0 : begin

if (in)

next_state = S1;

else

next_state = S0;

end

S1: begin
 if (in)

next_state = S2;

else

next_state = S0;

end

S2 : begin

if (in)

next_state = S2;

else

next_state = S3;

end

S3 : begin

if (in)

next_state = S4;

else

next_state = S0;

end

S4: begin

if (in)

next_state = S2;

else

next_state = S0;

end

endcase

end

endmodule