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P-1/41 2019/5/9
教 師 : 蘇 慶 龍
Instructor : Ching-Lung Su
E-mail: kevinsu@yuntech.edu.tw
Chapter 6
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Chapter 6
Registers and Counters
Outline of Chapter 6
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6.1 Registers
6.2 Shift Registers
6.3 Ripple Counters
6.4 Synchronous Counters
6.5 Other Counters
6.6 HDL for Registers and Counters
6.1 Registers
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6.1 Registers
6.2 Shift Registers
6.3 Ripple Counters
6.4 Synchronous Counters
6.5 Other Counters
6.6 HDL for Registers and Counters
6.1 Registers
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◼ Registers
1. A register is a group of flip-flops.
2. An n-bit register consists of a group of n flip-flops
capable of storing n bits of binary information.
3. A counter is essentially a register that goes through a
predetermined sequence of states.
4. The simplest register is one that consists of only flip-
flop without any gates
5. The common clock input triggers all flip-flop on the
positive or negative clock edges.
6. The clear inputs asynchronously goes to the R (reset)
input of all four flip-flops.
7. The R inputs must be maintained at logic 1 during
normal clocked operation.
6.1 Registers
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I0 D A0
CR
I1 D A1
C
R
Clear = 0 ; Ax =0
◼ 4-Bit Registers Clock = ; Ax = Ix
I2 D A2 Normal Operation ; Clear = 1
CR
I3 D A3
Clock CR
Clear
(Active Low)
6.1 Registers
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D A0
I0
C
0/1 D A1
I1
1/0 C
Parallel Load ( )
◼ Register with No Change ( )
Parallel Load D A2
I2
C
D A3
I3
C
Clock
6.2 Shift Registers
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6.1 Registers
6.2 Shift Registers
6.3 Ripple Counters
6.4 Synchronous Counters
6.5 Other Counters
6.6 HDL for Registers and Counters
6.2 Shift Registers
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Serial Serial
D D D D
Input SI SO Output
C C C C
Clock
6.2 Shift Registers
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Timing Diagram
External Clock
Shift Control
Internal Clock
T1 T2 T3 T4
Initial Value 1 0 1 1 Se 0 0 1 0
r
After T1 1 1 0 1 ia 1 0 0 1
Self-copy
l Tr
a
After T2 1 1 1 0 ns
fe 1 1 0 0
r
After T3 0 1 1 1 0 1 1 0
After T4 1 0 1 1 1 0 1 1
6.2 Shift Registers
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◼ Serial Addition:
Slower but requiring less equipment
Q D
CR
Clear
0 00 0 0 0 X
0 01 0 1 0 X
0 10 0 1 0 X
0 11 1 0 1 X
1 00 0 1 X 1
1 01 1 0 X 0
1 10 1 0 X 0
1 11 1 1 X 0
JQ = xy
Simplified Equation KQ = x y = (x+y)
S = x +y + Q
6.2 Shift Registers
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Serial Input y J
Shift Register B Q (Cin/out)
C
K
Clear
6.2 Shift Registers
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Function Table
Mode Control Register C D C D C D C D
S1 S0 Operation Clear
Clock
0 0 No Change
0 1 Shift Right S1 4 1 4 1 4 1 4 1
S0 MUX MUX MUX MUX
1 0 Shift Left
3210 3210 3210 3210
1 1 Parallel Load
I3 I2 I1 I0
Parallel Inputs
6.3 Ripple Counters
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6.1 Registers
6.2 Shift Registers
6.3 Ripple Counters
6.4 Synchronous Counters
6.5 Other Counters
6.6 HDL for Registers and Counters
6.3 Ripple Counters
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◼ Counters
1. Counter: A register that goes through a prescribed
sequence of status upon the application of input
pulses is called a counter.
2. The input pulses may be clock pulse or they may
originate from some external source and may occur
at a fixed interval of time or at random.
3. The sequence of status may follow the binary
sequence is called a binary counter.
4. An n-bit binary counter consists of n flip-flop and can
count in binary from 0 to 2n-1.
6.3 Ripple Counters
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T A0 D A0 Ripple
Propagation
Count Count
CR CR
CR CR 0 0 0 0
0 0 0 1
T
0 0 1 0
0 0 1 1
T A2 D A2 T
0 1 0 0
0 1 0 1
CR CR 0 1 1 0
0 1 1 1
T
1 0 0 0
T A3 D A3
Negative Edge Trigger
CR CR
Reset 1 Reset
6.3 Ripple Counters
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T A0 D A0 Ripple
Propagation
Count Count
CR CR
CR CR 0 0 0 0
0 0 0 1
T
Count Sequence
0 0 1 0
0 0 T 1 1
T A2 D T
A2 0 1 0 0
0 1 0 1
T
CR CR 0 1 1 0
0 1 1 1
T T T
1 0 0 0
T A3 D A3
Positive Edge Trigger
CR CR
Reset 1 Reset
6.3 Ripple Counters
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0 0 0 0
0 0 0 1
T
0 0 1 0
0 0 1 1
1001 1000 0111 0110 0101 T
0 1 T 0 0
0 1 0 1
T
0 1 1 0
Trigger Higher Digit 0 1 1 1
T
If Q8 = 1 then Q2 = 0 1 T 0 0 T 0
2 1 T 0 0 1
J Q8
C
K
1
6.4 Synchronous Counters
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6.1 Registers
6.2 Shift Registers
6.3 Ripple Counters
6.4 Synchronous Counters
6.5 Other Counters
6.6 HDL for Registers and Counters
6.4 Synchronous Counters
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0 0 0 0
0 0 0 T 1
0 0 1 0
0 0 T 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 T 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
6.4 Synchronous Counters
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J A0
C
Count Enable
K
(CE)
◼ 4-Bit Synchronous J A2
Binary Counters C
K
To Next Stage
Clock
6.4 Synchronous Counters
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0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
Count Sequence
0 1 0 1
0 1 1 0
0 1 1 1
1 T 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 T 0 0
1 1 0 1
1 1 1 T 0 A0
1 1 1 1
6.4 Synchronous Counters
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Up
T A0
Down
C
T A1
Function Table
C
◼ 4-bit Binary Up- Up Down Function
Down Counters 0
0
0
1
No Change
Down Count
1 0 Up Count
T A2
1 1 Up Count
T A3
Clock
6.4 Synchronous Counters
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◼ BCD Counters
Excitation Table
Q(t) Q(t+1)
0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 1 0 0 0 0 1 1
TQ1 = 1
0 0 1 0 0 0 1 1 0 0 0 0 1
0 0 1 1 0 1 0 0 0 0 1 1 1 K-Map TQ2 = Q8 Q1
0 1 0 0 0 1 0 1 0 0 0 0 1 TQ4 = Q2Q1
0 1 0 1 0 1 1 0 0 0 0 1 1 TQ8 = Q8Q1+ Q4Q2Q1
0 1 1 0 0 1 1 1 0 0 0 0 1
y = Q8Q1
0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 0 1
1 0 0 1 0 0 0 0 1 1 0 0 1
6.4 Synchronous Counters
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Load
1 0 1
I0 J A0
C
K
I1 J A1 Function Table
C
K Clear Clock Load Count Function
0 X X X Clear to 0
1 1 X load Inputs
I2 J A2 1 0 1 Up Count
C 1 0 0 No Change
K
I3 J A3
C
K
Clear
Clock
Carry-
Output
6.4 Synchronous Counters
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A3 A2 A1 A0 A3 A2 A1 A0
Count=1 Count=1
Counter with Counter with
Clear=1 Load=0
Load Parallel Load Clear Parallel Load
Clock Clock
Inputs=0
Input have no effect
6.5 Other Counters
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6.1 Registers
6.2 Shift Registers
6.3 Ripple Counters
6.4 Synchronous Counters
6.5 Other Counters
6.6 HDL for Registers and Counters
6.5 Other Counters
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Sate Table
Present Next
State Stare Flip-Flop Inputs
ABC ABC JA KA JB KB JC KC Boolean Function
JA=B KA=B
000 001 0 X 0 X 1 X JB=C KB=1
001 010 0 X 1 X X 1
JC=B KC=1
010 100 1 X X 1 0 X
100 101 X 0 0 X 1 X
101 110 X 0 1 X X 1
110 000 X 1 X 1 0 X
6.5 Other Counters
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1 Unused State
J A
111
Complement C
K
1
000
1 1
J B 001 110
Complement
C
1
K 0
010 101
1 100
J C
Reset
0 C
1
1 K
011
Shift
Right T0 T1 T2 T3
Timing Sequence
Clock
Ring Counter with Initial Value = 0
T0 T0 T1 T2 T3
T1
2X4 Decoder
T2
T3
Count
Enable 2-Bit Counter
D A D B D C E
D
E
C C C C
Clock
1 0000 AE
2 1000 AB
3 1100 BC
4 1110 CE
5 1111 AE
6 0111 AB
7 0011 BC
8 0001 CE
6.6 HDL for Registers and Counters
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6.1 Registers
6.2 Shift Registers
6.3 Ripple Counters
6.4 Synchronous Counters
6.5 Other Counters
6.6 HDL for Registers and Counters
6.6 HDL for Registers and Counters
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Referred to TA