CHAPTER 2

LITERATURE SURVEY

1. Preyesh Dalmia et al (2018): One of the primary features that help us

determine the computational power of a processor is the speed of its arithmetic unit.
An important function of an arithmetic block is multiplication because, in most
mathematical computations, it forms the bulk of the execution time. Thus, the
development of a fast multiplier has been a key research area for a long time. The
UT sutra is an ancient Vedic Mathematics sutra that can be used for multiplication of
two numbers in any number system. It is based on “Vertical and Crosswise”
multiplication.
2. Sushma R. et al (2013): With the advent of new technology in the fields of
VLSI and communication, there is also an ever growing demand for high speed
processing and low area design. It is also a well-known fact that the multiplier unit
forms an integral part of processor design. Due to this regard, high speed multiplier
architectures become the need of the day. We introduce a novel architecture to
perform high speed multiplication using ancient Vedic maths techniques. A new high
speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has
also been incorporated in the same and has been explored. Upon comparison, the
compressor based multiplier introduced is almost two times faster than the popular
methods of multiplication.
3. Karanam Deepak et al (2019): This present work deals with a reversible
Vedic type multiplier using the earliest Urdhva Tiryagbhyam sutras of Vedic type
mathematics combine with the QSD adder (Quaternary Signed digit number adder).
The proposed multiplier configuration is contrasted and a reversible Vedic multiplier
consolidates a QSD Quaternary Signed digit number adder viper among a
transformation section for quaternary to paired change. The proposition demonstrates
a most extreme speed enhancement.
4. G.Sameer et al (2015): With the advent of new technology in the fields of VLSI
and communication, there is also an ever growing demand for high speed processing
and low area design. It is also a well-known fact that the multiplier unit forms an
integral part of processor design. Due to this regard, high speed multiplier
architectures become the need of the day. In this paper, we introduce a novel
architecture to perform high speed multiplication using ancient Vedic math’s
techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2
compressors for addition has also been incorporated in the same and has been
explored. Upon comparison, the compressor based multiplier introduced in this
paper, is almost two times faster than the popular methods of multiplication.
5. T. Amy Prasanna et al (2019): The rapid Vedic multiplier dependent on the
Urdhva Tiryagbhyam sutra of Vedic science that consolidates a novel viper
dependent on Quaternary Marked digit number framework. Three tasks are
inalienable in augmentation: fractional items age, incomplete items decrease and
 expansion. A quick viper engineering subsequently significantly upgrades the speed
of the general procedure. A Quaternary rationale viper design is recommended that
chips away at a half breed of parallel and quaternary number frameworks.
6. Ankit trivedi et al (2017): Multipliers are the most important unit in high speed
arithmetic logic units, multiplier and accumulate units, digital signal processing units.
etc. To increase speed many adjustments over the standard modified booth algorithm,
many new techniques are being comes work in action. Amongst these various
multiplier Vedic multipliers based on Vedic mathematics are currently under focus
due to these being one of the super fastest and low power multiplier. There are
sixteen basic sutras in Vedic multiplication in which “Urdhva Tiryakbhyam” has
been found to be the most feasible one in terms of speed.
7. Ila Chaudhary et al (2016): Rapidly growing technology has raised demands
for fast and efficient real time digital signal processing applications. Multiplication is
one of the primary arithmetic operations every application demands. A large number
of multiplier designs have been developed to enhance their speed. Active research
over decades has lead to the emergence of Vedic Multipliers as one of the fastest and
low power multiplier over traditional array and booth multipliers.
8. Poornima M et al (2013): Vedic mathematics is the name given to the ancient
Indian system of mathematics that was rediscovered in the early twentieth century
from ancient Indian sculptures (Vedas). Vedic Mathematics has a unique technique of
calculations based on 16 Sutras. It is the study of high speed 8x8 bit Vedic multiplier
architecture which is quite different from the Conventional method of multiplication
like add and shift. Further, the Verilog HDL coding of Urdhva Tiryakbhyam Sutra for
8x8 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on
Spartan 3 kit have been done and output has been displayed on LED’s of Spartan 3
kit.
9. Harsha R et al (2019): The multiplier is a key building block of all processors,
which improves the speed of Digital Signal Processor (DSP), a special application in
which we need to reduce the time delay. In the proposed method, we design a Vedic
multiplier by using a Vedic Mathematics Sutra called Urdhva Tiryagbhyam, which
means “vertically and crosswise”. Vedic Mathematics is mainly based on 16 Sutras
and was rediscovered in the early 20th century. In ancient times in India, people used
this Sutra for decimal number multiplications effectively. The same basic concept of
the above-mentioned Sutra is extended to the multiplication of binary numbers to
make use in the digital hardware system. The computation of partial products in
parallel in the Urdhva Tiryagbhyam Sutra increases the speed of the computation
process and the processing time is reduced in comparison with the use of inbuilt
MATLAB functions. In our proposed multiplier design, the delay for the 4X4 Vedic
multiplier is reduced and also the number of transistors is reduced by a large amount
compared to the previously proposed design.
10. Nagamani a.n. et al (2011): Arithmetic operations in digital signal processing
applications suffer from problems including propagation delay and circuit
complexity. QSD number representation allows a method of fast addition/subtraction
because the carry propagation chains are eliminated and hence it reduces the
propagation time in comparison with common radix 2 system. Here we propose an
Arithmetic unit based on QSD number system based on quaternary system. The
proposed design is developed using VHDL and implemented on FPGA device and
results are compared with conventional arithmetic unit. The implementation of
quaternary addition and multiplication results in a fix delay independent of the
number of digits. Operations on a large number of digits such as 64, 128, or more,
can be implemented with constant delay and less complexity