Proc. Natl. Acad. Sci., India, Sect. A Phys. Sci.
(April–June 2019) 89(2):257–268
https://doi.org/10.1007/s40010-017-0464-4
RESEARCH ARTICLE
A Delay Efficient Vedic Multiplier
E. Prabhu1 • H. Mangalam2 • P. R. Gokul1
Received: 12 February 2015 / Revised: 25 July 2016 / Accepted: 6 November 2017 / Published online: 9 February 2018
 The National Academy of Sciences, India 2018
Abstract Vedic mathematics is the ancient Indian method
of mathematics based on 16 Sutras applicable to various
branches of mathematics like trigonometry, calculus,
geometry, conics etc. Multiplication is effectively used in
modern communication and Digital Signal Processing
applications. Ordinary multiplication requires propagation
of carry from LSB to MSB while adding binary partial
products, which limits the overall speed of multiplication.
Vedic mathematics helps in generation of partial products
and sums in one step, and ensures reduction in overall
propagation delay. Urdhva Tiryakbhyam Sutra and Nikhi-
lam Sutra are the two multiplication techniques used in
Vedic mathematics. In this paper, an 8 * 8 Nikhilam Sutra
multiplier for three different sets of bases is realized. The
concepts of Urdhva Tiryakbhyam Sutra multiplication are
used for the implementation of the proposed multiplier.
The implementation results are compared with that of a
Modified Booth’s multiplier in terms of delay, area and
power. The design is synthesized in Synopsys Design
Compiler using CMOS 90 nm technology, and results
show that the proposed multiplier using Nikhilam Sutra
& E. Prabhu
e_prabhu@cb.amrita.edu
H. Mangalam
mangalam@skcet.ac.in
P. R. Gokul
gokulpr46@gmail.com
1
Department of Electronics and Communication Engineering,
Amrita School of Engineering, Amrita Vishwa
Vidyapeetham, Coimbatore 641112, India
2 tipliers for high performance systems [5–7]. High speed
Department of Electronics and Communication Engineering,
Sri Krishna College of Engineering and Technology,
Coimbatore 641008, India
with 25 bases is faster than the Modified Booth’s multiplier
by 51.28%.
Keywords Vedic mathematics
Nikhilam Sutra

Booth’s multiplier
Arithmetic operations
1 Introduction
The word Arithmetic is derived from a Greek word
‘arithmos’. Arithmetic is the most elementary branch of
Mathematics which is used by almost everyone in day to
day life for simple tasks ranging from counting to advanced
science and business calculations. As a result, the need for
faster and efficient Arithmetic units in computers has been
a topic of interest over decades. The primary objectives of
this work are, to design a delay efficient 8 * 8 Vedic
multiplier using Nikhilam Sutra of Vedic mathematics, for
different possible decimal bases, to make use of Urdhva
Tiryakbhyam Sutra multiplier in the implementation of the
proposed multiplier and to compare the proposed Nikhilam
Sutra multiplier with a Modified Booth’s multiplier in
terms of power, area and delay.
Digital multipliers [1, 2] form the core components in
most of the Arithmetic and Digital Signal Processors
(DSPs) and the speed of the multiplier [3] decides the
speed of the processor. These multipliers are indispensable
in implementing computational units which realize various
important functions like convolution, compression, multi-
ply accumulate (MAC) [4], FFTs, filtering and in Arith-
metic Logic Unit (ALU) of Microprocessors. Most of the
research works concentrate on designing high speed mul-
multipliers play an important role in the design of any
architecture and vast researches are still going on to
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258 E. Prabhu et al.

increase the speed of operation. Fast bit-parallel multipliers It has a unique technique of calculations based on 16 for-
are embedded in most of the advanced digital processors. mulas (Sutras) and their applications for carrying out
The increased complexity of various applications demands tedious and cumbersome arithmetical operations. The
smarter and efficient multiplier algorithms apart from faster Vedic formulas are applicable to various branches of
multiplier architectures. According to the need of the mathematics like arithmetic, algebra, geometry (plane and
application, the multiplier is implemented and the trade- solid), trigonometry (plane and spherical), conics (geo-
offs are considered. In general, a multiplier is said to be metrical and analytical), astronomy, calculus (differential
efficient based on variation in speed, area and power and integral) etc.
consumption. These Sutras and their Upasutras (Corrolaries), along
The demand for high speed processing has been with their brief meanings are enlisted below alphabetically.
increasing as a result of expanding computer and signal
1. Ekadhikena Purvena—By one more than the previous
processing applications. In many real-time signal and
one
image processing applications, higher throughput arith-
metic operations are of utmost importance to achieve the • Corollary—Anurupyena
desired performance. Multiplication is one of the key
2. Nikhilam Navatascaramam dasatah—All from 9 and
operations in such applications and over decades, the
the last from 10
development of faster multiplication circuits has been a
subject of great interest. Reducing the time delay and • Corollary—Sisyate Sesasamjnah
power consumption is a very essential requirements for
3. Urdhva-Tiryakbhyam—Vertically and Crosswise
many applications. So it is always important to have fast
and efficient mechanisms to implement mathematical • Corollary—Adyamadyenantya-mantyena
functions. Vedic Mathematic techniques are derived from 4. Paravartya Yojayet—Transpose and adjust
ancient Indian mathematics for solving mathematic prob-
lems mentally. Without the use of pen and paper, we can • Corollary—Kevalaih Saptakam Gunyit
transform extremely tedious calculations into simpler and 5. Sunyam Samyasamuccaye—When the sum is the
orally manageable operations, with the help of Vedic same, that sum is zero
mathematics. It provides algorithms to simplify the math-
ematics and hence, is perfect solution for the problem • Corollary—Vestanam
stated. 6. (Anurupye) Shunyamanyat—If one is in ratio, the
Architectures for multiplication using Urdhva Tiryakb- other is zero
hyam (UT) Sutra are reported in [5–7]. The UT multiplier
architecture [7] is used in the implementation of the pro- • Corollary—Yavadunam Tavadunam
posed multiplier. An N 9 N bit parallel hierarchical 7. Sankalana-vyavakalanabhyam—By addition and by
overlay multiplier architecture based on UT multiplier is subtraction
proposed in [8]. A comparative study of Urdhva multipli-
cation and conventional multiplication is done in [9] to • Corollary—Yavadunam Tavadunikrtya Varganca
prove that the number of multiplications required is same Yojeyet
for both normal multiplication and Vedic multiplication 8. Puranapuranabyham—By the completion or non-
method. A hardware architecture for Nikhilam Sutra has completion
been reported for binary radix (base) and exponents, and in
[10] it is used for realizing a complex number multiplier, • Corollary—Antyayordasakepi
and in [11] a transistor level implementation of the mul- 9. Chalana-Kalanabhyam—Differences and Similarities
tiplier is done.
• Corollary—Antyayoreva
10. Yavadunam—Whatever the extend of its deficiency
2 Vedic Mathematics
• Corollary—Samuccayagunitah
Vedic mathematics is the ancient method of calculation 11. Vyastisamastih—Part and Whole
rediscovered by His Holiness Jagadguru Sankaracharya Sri
Bharati Krishna Tirthaji Maharaja in the early twentieth • Corollary—Lopanasthapanabhyam
century from the ancient Indian Vedas [12]. It is a part of 12. Sesanyankena Charamena—The remainders by the
Sthapatya-Veda (book on civil engineering and architec- last digit
ture), which is an upa-veda (supplement) of Atharva Veda.

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A Delay Efficient Vedic Multiplier 259

• Corollary—Vilokanam
1 2
13. Sopantyadvayamantyam—The ultimate and twice the
penultimate
• Corollary—Gunitasamuccayah,
Samuccayagunitah
1 3

14. Ekanyunena Purvena—By one less than the previous (1*1) : ((1*3) + 1*2)) : (2*3)
one
15. Gunitasamuccayah—The product of the sum is equal
to the sum of the product 1 : 3+2 : 6 = 156
16. Gunakasamuccayah—The factors of the sum is equal
Fig. 1 Simple Urdhva Tiryakbhyam Sutra multiplication
to the sum of the factors.
The second and the third Sutras, namely Nikhilam
step1 step2 step3 step4
Navatascaramam Dasatah and Urdhva Tiryakbhyam Sutras
are used for multiplication and division of numbers. Mul-
1100 1100 1100 1100
tiplication using these two Sutras is dealt in detail in this
work. The detailed description of other Sutras is beyond the 1101 1101 1101 1101
scope of this work.
step5 step6 step7
2.1 Urdhva Tiryakbhyam Sutra 1100 1100 1100

Urdhva Tiryakbhyam [12] is a general formula applicable 1101 1101 1101

to all cases of multiplication. It is also useful in the division
of a large number by another large number, which is
beyond the scope of this work. The formula itself is very
short and it literally means ‘‘vertically and crosswise’’.
Traditionally, this Sutra has been used for the multiplica-
tion of numbers in the decimal number system. It is based
on a novel concept through which the generation of all
partial products can be done with the concurrent addition of
these partial products. The algorithm can be generalized for
a n 9 n bit number. A simple example to illustrate this
method to multiply two numbers, for example 12 and 13, is
given in Fig. 1.
If any one of the results has more than one digit, the
extra digit on the left (carry) should be added with the
result obtained in the next step and it goes on. This method
is also applicable to multiplication of binary numbers.
Consider the binary multiplication of the same numbers 12
(1100 in binary) and 13 (1101 in binary). The line diagram
for multiplication is shown in Fig. 2.
2.2 Nilkhilam Navatascaramam Sutra
Nikhilam Sutra [12] simply means ‘‘all from 9 and the last
from 10’’. This technique is applicable to all numbers
which are closer to the base values like 10, 100, 1000 etc.
i.e. increased powers of 10. We can have a theoretical base
and a working base while multiplying using this method.
Theoretical base value can be either of any of the powers of
10 and the working base can be a multiple of 10, 100, 1000
etc. The numbers to be multiplied can be either less or
Fig. 2 Line diagram of Urdhva Tiryakbhyam Sutra multiplication for
binary numbers
more than the base value. This method is efficient for the
multiplication of large integers. Here the complements of
the numbers from their base is found out and are multi-
plied. Hence the multiplication of two large numbers is
reduced to multiplication of their complements. It should
be ensured that the complement values obtained are smaller
than the original numbers. Let us take the multiplication of
9 by 7 and 103 by 102, as examples. The steps for multi-
plication are shown in Figs. 3 and 4 respectively.
Let us take the multiplication of 9 by 7, for example.
The steps for multiplication are as follows.
1. We should choose the base for the numbers to be
multiplied, which is a power of 10. In this particular
case, the base is 10.
2. Place the two numbers 9 and 7 above and below on the
left hand side as shown in the Fig. 3.
3. Find the complement values (1 and 3) of these
numbers from the base (10) and put them on the right
had side of the corresponding numbers with a minus
(-) sign in between them. The minus sign indicates
that the numbers to be multiplied are less than 10.
4. The left hand side of the product can be obtained by,
either subtracting the second complement value (3)
from the first number (9), or subtracting the first
complement value (1) from the second number (7), or

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260 E. Prabhu et al.

9x7 41 x 41
Theoretical Base = 100
Base = 10 Working Base = 50

Column 1 Column 2 Column 1 Column 2

9 - 1 41 - 9

7 - 3 41 - 9

6 | 3 ( 32 / 2 ) | 81

Fig. 3 Multiplication using Nikhilam Sutra for base = 10 = 16 | 81

103 x 102 Fig. 5 Multiplication using Nikhilam Sutra with division on LHS

Base = 100
41 x 41
Column 1 Column 2 Theoretical Base = 10
Working Base = 40
103 + 3
Column 1 Column 2
102 + 2
41 + 1
105 | 06
41 + 1
Fig. 4 Multiplication using Nikhilam Sutra for base = 100
( 42 * 4 ) | 1
subtracting the base (10) from the sum of numbers
(9 ? 7 = 16), or subtracting the sum of complement = 168 | 1
values (1 ? 3 = 4) from the base.
The right hand side of the product can be obtained by Fig. 6 Multiplication using Nikhilam Sutra on LHS
vertically multiplying the two complement values (1 and
3).
Suppose we have to multiply 41 by 41. Both these obtained left hand portion (42) by 4 (42 * 4 = 168) and
numbers are so far away from the base 100. The vertical add it with the carry from the right hand side (if any) to
multiplication of complement values 59 by 59 would prove obtain the actual left hand part. Since 10 * 4 = 40, we
to be too cumbersome to be permissible under the Vedic multiply the left hand portion by 4 to get the actual LHS. It
system and will be positively inadmissible. is shown in Fig. 6.
There are two methods to solve this problem. In the first
method, we choose 50 as the working base. By cross-
subtraction, we get 32 at the left hand side. Since 100 is the 3 Booth’s Multiplication Algorithm
theoretical base and 50 is the working base, and
100/2 = 50, we divide the left hand part by 2 (32/2 = 16) Booth’s multiplication algorithm [13, 14] is a technique
to get the actual left hand side. It is shown in Fig. 5. In the that is used for multiplying two signed binary numbers in
second method, instead of taking 100 as our theoretical two’s complement representation. In the recoding
base and 50 (a sub-multiple or multiple thereof) as our scheme introduced by Booth, the number of partial prod-
working base, we may take 10 as the theoretical base and ucts is reduced by about a factor of two, by grouping the
40 as the working base respectively. Then we multiply the bits of multiplier into pairs. This in turn may improve

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A Delay Efficient Vedic Multiplier
performance and reduce the hardware cost, as the delay and
the amount of hardware requirements are dependent on the
number of partial products to be added. But this method
requires a carry propagate add before the partial products
are generated.
3.1 Modified Booth’s Multiplication
Without requiring the carry propagate add, Modified
Booth’s Algorithm [14, 15] reduces the number of partial
products by about a factor of two. In this method, the
multiplier is partitioned into overlapping groups of three
bits, and each group is decoded to select a single partial
product. While evaluating, each partial product is shifted
two bits with respect to their neighbor’s. In general, for an
n bit multiplication, the number of partial products are
reduced to (n ? 2)/2. The basic steps in Modified Booth’s
algorithm are Booth encoding, Booth decoding, sign
extension of partial products and addition of the partial
products. At first, each partitioned group is Booth encoded
to three individual bits: single, double and neg. The ‘single’
bit corresponds to whether the multiplicand bit should be
multiplied by 1 or not. Similarly ‘double’ bit corresponds
to whether the multiplicand bit is multiplied by 2 or not.
The ‘neg’ bit decides whether the negative of the multi-
plicand is to be taken. Negative of the multiplicand bit is
found out by taking the two’s complement of the corre-
sponding bit. According to these three bits, Booth decoding
is done, i.e., each partial product bits are generated. All the
partial products are sign extended and added to obtain the
final product.
4 Design and Implementation
The design of Vedic multiplier is based on a novel tech-
nique which is quite different from the conventional mul-
tiplier design. The proposed multiplier using Nikhilam
Sutra for different bases is designed using Verilog HDL, as
it gives effective utilization of structural method of mod-
elling. It is simulated using iverilog and functionality of the
designs is verified. The designs are synthesized by
Synopsys Design Compiler using CMOS 90 nm technol-
ogy, and synthesis reports for power, area and delay are
obtained.
4.1 Multiplier Using Nikhilam Sutra
An 8 * 8 Nikhilam Sutra multiplier for different base
values is implemented. The choice of values of the oper-
ands ranges from 0 to 255. So the possible values of the-
oretical bases are 10 and 100, and the maximum value of
261
working base can be 250. If we choose 10 as the theoretical
base, then a maximum of 25 bases can be considered.
4.2 Proposed 8 * 8 Multiplier Using Nikhilam Sutra
with 8 Bases
The challenge with the design of each of these multiplier
variants is how we choose the base values for that partic-
ular multiplier architecture. For this multiplier with 8 base
values, the base values are chosen for a particular range of
random numbers as shown in the Table 1.
The proposed architecture of 8 * 8 multiplier using
Nikhilam Sutra with 8 bases is shown in Fig. 7. It consists
of one 4 bit UT (Urdhva) multiplier, two 8 bit UT multi-
pliers, an adder or a subtractor unit, a 10 bit binary to BCD
converter, a 8 bit adder and a 16 bit adder. The inputs to the
modules are the numbers to be multiplied (a and b), the
base value corresponding to the numbers, the complement
values of the numbers from their base (c1 and c2) and an
index value corresponding to the base.
The complement values c1 and c2 are multiplied using
an 8 bit UT multiplier. The maximum value of this product
contains three group of digits (ones, tens and hundreds), as
the range of complement values is between 0 and 30. Here
we have fixed the theoretical base as 10. Hence the right
hand side of the product must have only a single digit. A
binary to BCD converter is used to convert the product
from the UT multiplier to its equivalent BCD. Here a 10 bit
binary to BCD converter is used since the maximum value
to be converted has 10 bits. The value at one’s place is the
actual RHS of the product. Now, to find the LHS of the
product, first the cross-subtraction or cross-addition of the
numbers and complements is carried out using an Adder or
a Subtractor module. That value is to be multiplied with the
index value (if base is 50, then index value is equal to 5)
using the second 8 bit UT multiplier. The resultant value
should be added with the left over portion from the right
hand side to get the actual LHS. The leftover portion from
Table 1 Base selection for multiplier using Nikhilam Sutra with 8
bases
Range of Numbers Base
0 \ numbers B 15 10
15 \ numbers B 40 30
40 \ numbers B 60 50
60 \ numbers B 80 70
80 \ numbers B 130 100
130 \ numbers B 180 150
180 \ numbers B 220 200
220 \ numbers B 255 240
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262 E. Prabhu et al.

Fig. 7 Proposed architecture of

8 * 8 multiplier using Nikhilam
Sutra with 8 bases a Binary to BCD
Converter (10 bit)
b 4’d 10
a Adder or hundreds
Subtractor tens
base ones
4 bit UT
c1 8 bit UT Multiplier
Multiplier
c2
8 bit UT
index Multiplier 8 bit Adder
value

16 bit Adder

LHS RHS

Table 2 Base selection for multiplier using Nikhilam Sutra with 16 the right is calculated with the help of the 4 bit UT mul-
bases tiplier and the 8 bit adder.
Multiplier or multiplicand bits Base
4.3 Proposed 8 * 8 Multiplier Using Nikhilam Sutra
0000 0000–0000 1111 (0–15) 10 with 16 Bases
0001 0000–0001 1111 (16–31) 20
0010 0000–0010 1111 (32–47) 40 Unlike the previous method, here the way the base values
0011 0000–0011 1111 (48–63) 60 are chosen is different. Here, the base values are chosen by
0100 0000–0100 1111 (64–79) 70 identifying the initial 4 bits of either the multiplier or
0101 0000–0101 1111 (80–95) 90 multiplicand. A total of 16 bases are chosen according to
.. ..
. . the starting four MSB’s of either the multiplicand or
1110 0000–1110 1111 (224–239) 230 multiplier, i.e., from 0000 to 1111 as shown in Table 2.
1111 0000–1111 1111 (240–255) 250 The proposed architecture of 8 * 8 multiplier using
Nikhilam Sutra with 16 bases is shown in Fig. 8.

Fig. 8 Proposed architecture of

8 * 8 multiplier using Nikhilam
Sutra with 16 bases a Binary to BCD
Converter (8 bit)
b 4’d 10
Adder or hundreds
Subtractor tens
base ones
4 bit UT
c1 4 bit UT Multiplier
Multiplier
c2
8 bit UT
index Multiplier 4 bit Adder
value

16 bit Adder

LHS RHS

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A Delay Efficient Vedic Multiplier 263

Table 3 Base selection for multiplier using Nikhilam Sutra with 25 4.4 Proposed 8 * 8 Multiplier Using Nikhilam Sutra
bases with 25 Bases
Range of numbers Base
Similar to the multiplier with 8 bases, here also the base
0–15 10 values are chosen for a random range of numbers. The
16–25 20 advantage of choosing more number of bases is that the
26–35 30 complement values of the numbers from their corre-
36–45 40 sponding bases become lesser in magnitude and a lower
46–55 50 order binary to BCD converter is required for the conver-
.. ..
. . sion of the product of complement values. Here, a total of
236–245 240 25 base values are chosen as shown in the Table 3.
246–255 250 The architecture of proposed 8 * 8 multiplier using
Nikhilam Sutra with 25 bases is shown in the Fig. 9. It
The architecture of this multiplier is same as that of with consists of a 4 bit UT multiplier, an 8 bit UT multiplier, an
8 bases, except few changes. Here the complement values Adder or a Subtractor module, a 5 bit binary to BCD
c1 and c2 are multiplied using a 4 bit UT multiplier and an converter and a 16 bit adder. We can identify the differ-
8 bit binary to BCD converter is used. The procedure for ences of this architecture with the previous ones. Here the
multiplication is same as that of with 8 bases. range of complement values ranges from 0 to 5 as per the

Table 4 Comparison of proposed multiplier using Nikhilam Sutra with Modified Booth’s multiplier
Multiplier Power (lW) Area (lm2) Delay (ns)
Dynamic power(DP)
Leakage power(LP)

8*8 Multiplier using Nikhilam Sutra with 8 bases DP = 1470 10482.022 48.89
LP = 45.4971
8*8 Multiplier using Nikhilam Sutra with 16 bases DP = 650.8425 6521.2309 45.45
LP = 27.9465
8*8 Multiplier using Nikhilam Sutra with 25 bases DP = 649.8292 5389.8529 35.31
LP = 22.7512
8*8 Modified Booth’s multiplier [15] DP = 387.5450 4110.6769 72.48
LP = 18.2304

Fig. 9 Proposed architecture of

8 * 8 multiplier using Nikhilam
a
Sutra with 25 bases Binary to BCD
b Converter (5 bit)
Adder or
base
Sub-tractor
ones
c2 tens
4 bit
UT Multiplier
c1 8 bit UT
Multiplier

Index
value n 16 bit
Adder

LHS RHS

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264 E. Prabhu et al.

table, and hence the input to the binary to BCD converter
has only 5 bits. Therefore the complexity of the binary to
BCD converter is reduced, which in turn reduces the
complexity of the architecture. Moreover, the converter
output consists of only two digits. Hence the design
becomes much simpler by avoiding a 4 bit UT multiplier
and an adder module. The digit at the tens place is added
with the 8 bit UT multiplier output to obtain the actual
LHS. The digit at the units place forms the actual RHS of
the product.
5 Results and Discussion
The power, delay and area reports are generated after
synthesizing the multiplier designs by Synopsys Design
Compiler (Synopsys Design Vision) using CMOS 90 nm
technology. The power, area and delay comparisons for all
the multipliers are shown in the Table 4. The simulated
output wave forms for 4 * 4 UT multiplier, 8 * 8 UT
multiplier, 8 * 8 multiplier using Nikhilam Sutra with 8
bases, 16 bases, 25 bases and 8 * 8 modified booth’s
multiplier are shown in Figs. 10, 12, 14, 16, 18, and 20

Fig. 10 Simulation waveform

of 4 * 4 UT multiplier

Fig. 11 Schematic of 4 * 4 UT
multiplier

Fig. 12 Simulation waveform

of 8 * 8 UT multiplier

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A Delay Efficient Vedic Multiplier 265

respectively. The schematic diagrams for 4 * 4 UT multi-

plier, 8 * 8 UT multiplier, 8 * 8 multiplier using Nikhilam
Sutra with 8 bases, 16 bases, 25 bases and 8 * 8 modified
booth’s multiplier are shown in Figs. 11, 13, 15, 17, 19,
and 21 respectively.
The synthesized report of power, area and delay given in
Table 4 shows that the proposed 8 * 8 multiplier using
Nikhilam Sutra architecture with 25 base values is highly
delay efficient than the Modified Booth multiplier archi-
tecture by 51.28%. The improvement in delay of the
Nikhilam Sutra multipliers with 8 and 16 bases, when
compared to the Booth’s multiplier, are 32.54 and 37.29%
respectively. This can be attributed to the reduction in the
delay of the adder stages due to the elimination of carry
propagation from LSB to MSB. The 8 and 16 bases designs
use an 8 bit binary to BCD converter stage compared to a 5
bit binary to BCD converter stage in the 25 bases multi-
plier. The increase in overhead due to the larger decoder is
responsible for the reduction in speed of the 8 and 16 bases
Fig. 13 Schematic of 8 * 8 UT multiplier
multipliers over the 25 bases multiplier. However, there is

Fig. 14 Simulation waveform of 8 * 8 multiplier using Nikhilam Sutra with 8 bases

Fig. 15 Schematic of 8 * 8
multiplier using Nikhilam Sutra
with 8 bases

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266
a consistent improvement in speed in all the three designs
with an average reduction in delay of 40.37% over the
Booth’s multiplier.
6 Conclusion and Future Work
The proposed 8 * 8 Vedic multiplier shows significant
improvement in delay with an increased cost in terms of
power and area. The multiplier is implemented for three
sets of decimal base values: 8, 16 and 25 bases. This paper
gives an overview of the various Sutras of Vedic
Fig. 16 Simulation waveform of 8 * 8 multiplier using Nikhilam Sutra with 16 bases
Fig. 17 Schematic of 8 * 8
multiplier using Nikhilam Sutra
with 16 bases
123
E. Prabhu et al.
mathematics, and it discusses in detail about the two most
important multiplication techniques, Urdhva Tiryakbhyam
Sutra and Nikhilam Navatascaramam Sutra. The concepts
of Booth encoding and decoding are also discussed in this
work. A comparison of the proposed multiplier using
Nikhilam Sutra architecture is done with a Modified
Booth’s multiplier. The designs of 8 * 8 multiplier using
Nikhilam Sutra for different bases and 8 * 8 Modified
Booth’s multiplier are realized. This finds application in
fields of Digital Signal Processing, High speed low power
VLSI arithmetic systems and algorithms, RSA encryption
system. As an extension, the proposed multiplier could be
A Delay Efficient Vedic Multiplier 267

Fig. 18 Simulation waveform of 8 * 8 multiplier using Nikhilam Sutra with 25 bases

Fig. 19 Schematic of 8 * 8
multiplier using Nikhilam Sutra
with 25 bases

Fig. 20 Simulation waveform of 8 * 8 Modified Booth’s multiplier

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268
Fig. 21 Schematic of 8 * 8
Modified Booth’s multiplier
used for efficient implementation of multiply accumulate
(MAC) units. System level methods based on multiple-
supply voltage (VDD), multiple-threshold voltage (Vth)
and power gating techniques are being suggested to trade
off speed for leakage reduction.
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