Microprocessors and Microsystems 73 (2020) 102961

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Microprocessors and Microsystems

journal homepage: www.elsevier.com/locate/micpro

FPGA implementation of XOR-MUX full adder based DWT for signal

processing applications
P. Radhakrishnan a,∗, G. Themozhi b
a
Dept of ECE, Tagore Engineering College, India
b
Dept of EEE, AMET University, Chennai, India

a r t i c l e i n f o a b s t r a c t

Article history: In the recent past there is a rapid development in the field of digital technology especially in signal
Received 30 September 2019 processing and image processing based applications Excellent performance high speed, compactable in
Revised 12 December 2019
size low power and less delay are the essential needs of the devices used for applications such as signal
Accepted 18 December 2019
processing, audio processing and software define radio and so on. Particularly, digital gadgets are prone
Available online 19 December 2019
to have more critical logic size and power consumption and take large area in VLSI Implementation due
Keywords: to arithmetic operations of adders and multiplier designs. Thus priority architecture of Digital Wavelet
DWT (Discrete Wavelet Transform) Transform (DWT) is affected as it comprises a number of Filter banks in level basics, thus all Filter banks
FPGA(Field Programmable Gate Array) have number of adders and multipliers due to coefficient decompositions of low and high pass filters.
On this n-size repeated filter logic takes more logic size and power consumption. Here, the proposed
work presents a novel approach of DWT by replacing conventional adders and multipliers with XOR-
MUX adders and Truncations multipliers thereby reducing the 2n logic size to n-size logic. Finally, the
proposed DWT architecture designed in VHDL and also implemented in FPGA XC6SLX9-2TQG144 proved
the performance in terms of delay, area and power.
© 2019 Elsevier B.V. All rights reserved.

1. Introduction to priority method of Digital Wavelet Transform (DWT) [7]. This

In the modern digital world there are a range of novelty based
gadgets with lot of application oriented domains such as signal
processing applications, audio, image and video processing appli-
cations, software define radio and so on. In specific, digital gadget
based environment of digital signal processing applications have
more signal noises, signal interference and fluctuation as it con-
sumes more power and area in hardware implementation; as a re-
sult there is a difficulty in the mathematical operations such as
additions, subtractions, divisions and multiplication of designs. The
recent digital signal processing applications concentrate more on
priority in terms of arithmetic operations concerning cryptography
application method, 3G, LTE, Tele-Communication, audio and video
processing and so on. Since, this digital signal processing applica-
tions concerning additions and subtractions are of more priority
to reduce signal noise, fluctuation in all type of gadgets, because
these addition and subtraction process builds multiplication and
division in arithmetic operations. Here, this proposed methodol-
ogy concentrates on resourceful arithmetic operation with regard
∗
Corresponding author.
E-mail addresses: eceradhakrishnan65@yahoo.com (P. Radhakrishnan),
gthemozhivijayakumar@gmail.com (G. Themozhi).
wavelet transform application consists of a number of Filter banks
in level basics, thus all Filter banks have number of adders and
multipliers due to coefficient decompositions of low and high pass
filters, on this n-size repeated filter logic takes more logic size and
power consumption. In this, digital signal processing application
adders are considered to be the most important in all arithmetic
operations as it has many conventional / parallel adders, parallel
pre-fix adders such as Ripple carry adder, Carry look-ahead adder,
Carry Select adder [11,12,21,22], Carry Save adder, Carry By-pass
adder, Kogge stone adder, Brent-Kung adder, Lander-Fischer adder.
Here, the proposed work presents a novel approach of DWT to re-
place conventional adders and multipliers with XOR-MUX adders
and Truncations multipliers, so as to reduce 2n logic size to n-size
logic and while comparing this XOR-MUX adder to parallel adders
of RCA-BEC full adder it is clear that it has more efficiency con-
cerning area, delay and power [10,13]. This XOR-MUX adder is used
to modify the conventional full adders in Truncated Multipliers
[14, 15], XOR-MUX based Full adders are used to reduces the num-
ber of logic gates involved in truncated multiplier reduces output
bits [9], because these truncation multiplier is of the capability to
reduce large area in internal and external architecture of FIR Fil-
ter using round based technique [8], which computes the trun-
cation multiplier by adding the two n-bit partial products, this

https://doi.org/10.1016/j.micpro.2019.102961
0141-9331/© 2019 Elsevier B.V. All rights reserved.
2 P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961
Fig. 1. Proposed XOR-MUX Full adder.
Fig. 2. Conventional RCA-BEC Full adder.
Fig. 3. Block Diagram of Standard 8 × 8 Multiplier.
Fig. 4. Block Diagram of Truncated 8 × 8 Multiplier.
operation of two n-bits, the MSB are the most significant rows and
columns with truncated, deleted, rounded and corrected forms in
variable method. A normal multiplier of n x n bit computes and
gets the weighted sum of output of 2n bits, but a truncation mul-
tiplier computes only n-bits, ant it takes less critical path delay,
propagation delay and high performance in arithmetic operations
[23].
In this paper, our aim is to the design and implement the DWT
by using full adder, Truncation Multiplier, FIR Filter, DWT [18],
and finally provide an architecture design of Modified DWT with
Table 1
Truth table of XOR-MUX full adder.
CIN A B SUM COUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
proven efficiency in terms of area, power and delay comparisons.
Section II presents the details of XOR-MUX Full adder and RCA-
BEC Full adder design. Section III presents the details of Truncation
Multiplier design by using XOR-MUX full adder. Section IV gives
the details about FIR Filter design with Truncation Multiplier and
XOR-MUX full adder. Section V presents the Modified DWT archi-
tecture. Section VI presents the FPGA Implementation of Proposed
DWT architecture. Section VII presents the result implementation
and comparisons of all Adders, Multiplier, FIR and DWT architec-
ture. Section VIII discusses the conclusion of this paper with future
scope and further applications.
2. XOR MUX and RCA-BEC full adder design
In an arithmetic addition, operation of full adders has more
critical paths and data paths on digital signal processing applica-
tions, its core model is used for many arithmetic operations such
as multiplications, division, address computation, cache, memory
accesses in floating point unit and arithmetic logic units. Here, this
paper introduces two successive stages of XOR and Multiplexer
based single bit full adder design with less area and power opti-
mization [1]. While, this XOR and Multiplexer based Full adder de-
sign is compared to parallel adders of RCA-BEC (Ripple Carry Adder
– Binary Excess One Converter) with area, delay and power.
Fig. 1 shows the proposed architecture of XOR MUX Full adder
design while employing the two successive stages of XOR gate for
Sum operations and 2:1 non-inverting multiplexer while using for
Carry operations, it takes totally 2 logic gates and 1 multiplexer.
The truth table of XOR-MUX Full adder design is shown in Table 1.
A Gate level structure of Conventional RCA with BEC adder de-
sign is shown in Fig. 2. Also, in this Fig XOR, AND, OR, NOT gate
based structure are shown, it takes totally 7 logic gate and 1 mul-
tiplexer. The truth table of Conventional RCA Based Carry select
adder is shown in Table 2.
3. Truncation multiplier with XOR MUX full adder design
In Digital signal processing application, the multiplier is of the
highest priority to reduce the signal noise, fluctuation in all type
of gadgets, and it is applied in signal processing, image process-
ing and cryptography method, since all these application methods
are of the highest priority in recent technologies such as 3G, LTE,
Tele-Communication, audio and video processing and so on [17]. In
the recent past, arithmetic operations need more efficient multi-
pliers with accuracy, speed, area and power, in this multiplication
process has three main steps such as partial product generation,
reduction, final addition, for this multiplication procedure n-bit bi-
nary multiplicand by way of an m-bit binary multiplier, m partial
products are generated and results are formed in (n + m) bits long.
In this method concerning types of multipliers, we have pro-
posed a novel XOR MUX based truncation multiplier. The goal of
this proposed multiplier is to reduced the large area in the archi-
tecture of inner and outer architecture using truncated rounded
 P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961 3

Table 2
Truth table for RCA with BEC CSLA.

RCA CIN BEC CIN A B RCA CY RCA SUM BEC CY BEC SUM CARRY SUM

0 1 0 0 0 0 0 1 0 0
0 1 0 1 0 1 1 0 0 1
0 1 1 0 0 1 1 0 0 1
0 1 1 1 1 0 1 1 1 0
0 1 0 0 0 0 0 1 0 1
0 1 0 1 0 1 1 0 1 0
0 1 1 0 0 1 1 0 1 0
0 1 1 1 1 0 1 1 1 1

Fig. 5. Architecture of Truncated 8 × 8 Multiplier.

Fig. 6. FIR Filter Design with MCM Multiplier.

4 P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961

Fig. 7. FIR Filter Design with Truncation Multiplier.

trate on carry operation, such as addition and carry skip opera-

tion, here number of full adders for addition are used, but not im-
plemented in simple and efficient gate level implementation with
carry operation to significantly reduce the area, power and delay.
In this method, truncated multiplier is entirely planned based on
the conventional full adders as shown in Fig. 5, these truncation
multipliers have the potential to replace MCM multipliers in FIR
Filter [2].

4. FIR filter design with truncation multiplier and XOR MUX

full adder

Here, Finite Impulse Response (FIR) is very frequently used to

support the Digital Signal Processing (DSP) application for high and
low sampling range, impulse response and noise reduction with fil-
tering order and cut-off frequency. FIR filter design has a number
of arithmetic operations such as additions, subtractions, multiplica-
tions and delayed elements, all these operations require response
Fig. 8. DWT architecture.
of coefficient decompositions of high pass, low pass, band pass
and band stop filter output. These FIR filters do not compute any
Table 3
Mapping of DWT coefficients to frequency.
rounding error in arithmetic operations and it is inherently sta-
ble to produce significant output and it does take maximum value
DWT coefficient Cut-off frequency (fc) Sampling frequency (fs)
in Nth order impulse response, it can be designed and configured
X1 70 KHz 50 KHz easily with configuration sequence of linear phase coefficient and
X2 10 KHz 50 KHz also application to detect a phase sensitive applications such as
Y1 30 KHz 50 KHz
mastering, seismology, crossover filter design and data communi-
Y2 40 KHz 50 KHz
Y3 60 KHz 50 KHz cation. In this methodology, FIR filter meets the coefficient in as-
Y4 50 KHz 50 KHz sured things, which can be suitable with frequency and time do-
main. The highest disadvantages of FIR filter are large area, and
power consumption mostly due to arithmetic operations such as
multiplication, addition and subtraction in number of Nth order.
For the high performance, Digital signal processing method
base technique, which is compared by summing up the output
is used in Multiple Constant Multiplication(MCM) in all parts of
of 2n-bit partial products, this operation of 2n-bits, the MSB of
arithmetic operations, and it is the same in FIR Filter design which
rows and columns takes place by means of truncated, deleted and
inherently produces a pipelined method of significant computation
rounding to correction in uneven method.
results and this method of MCM based FIR is formed only in trans-
A conventional multiplier of n x n bit computes and gets the
pose form and it is suitable for large order filter implementation
sum of output of 2n bits as shown in Fig. 3 and a truncated mul-
with fixed co-efficient, but it produces large area and power con-
tiplier computes and gets the sum of output of n size bits as
sumptions. In the Fig. 6 architecture is notified for the MCM based
shown in Fig. 4. A truncated multiplier is a logic size and area effi-
FIR Filter with contain number of TAP (Multiplier, Delay, Adder),
cient multiplier [19], it is useful to increase the substitution accu-
these ordinary MCM multipliers provide the 16-bit output for 8-bit
racy and reduce the hardware price, since this truncated multiplier
input, these output are provided to the adder, so the adder design
helps to produce the output of n-bits from n x n bits of multi-
takes 16-bit addition [3].
plication, it is of less significance, and some of the partial prod-
A discrete time filter is implemented in the following equa-
ucts are removed and also replaced using the technique of dele-
tion:
tion, reduction and truncation. In the partial products generation
of conventional method will take more number of columns, that 
n

are eliminated with regard to the area and power utilization, in y[n] = x[n − 1] · h[i]
i=0
this case the delay also decreases while comparing with the con-
ventional operation, but some drawbacks are present in this trun- where, x[n] is the input signal of FIR filter and y[n] is the output
cated multiplication [20], because this multiplier does not concen- signal of FIR filter and h[n] is the impulse response coefficient of
 P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961 5

Fig. 9. Filter design analysis method of X1 Filter – 70 KHz.

Fig. 10. Filter design analysis method of X2 Filter – 10 KHz.

FIR filter design and it is presented in the n form such as H[0],
H[1], H[2],.... H[n], it is derived from MATLAB tool with the help
of FDA (Filter Design Analysis), and it helps to fix the operation of
low pass, high pass, band stop and band pass with the support of
cut-off frequency and sampling frequency and filter order.
In the proposed system, Digital FIR filter design is modified us-
ing XOR MUX adder based Truncated Multiplier, the impulse re-
sponse contains Nth order of 8-TAP and it uses this FIR filter de-
sign, and this multiplier reduces the bit size of adder and de-
lay elements. Fig. 7 shows the FIR Filter Design of Truncation
Multiplier.
5. Modified DWT architecture
The Discrete Wavelet Transform is a technique which is used to
discrete the experimental signals which is the biggest advantage
over other transformations in terms of frequency, time scale and
shift, while implementing as an analog filter bank in audio pro-
cessing, video processing and also in biomedical field, this tech-
nique has a large number of applications in every area i.e. science,
engineering, mathematics, artificial intelligence and many more
[4]. The Discrete Wavelet Transform is a common signal process-
ing method which is used for the multi-resolution analysis of vari-
6 P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961

Fig. 11. Filter design analysis method of Y1 Filter – 30 KHz.

Fig. 12. Filter design analysis method of Y2 Filter – 40 KHz.

ous types of signals. DWT decomposes the input signal into narrow
band of the component frequencies and it is represented in the
form of approximate and detailed coefficients, while the approx-
imate coefficients correspond to the low-frequency/coarser varia-
tion of the signal, the details of coefficients are the higher fre-
quency/finer variations. Since, DWT uses various types of wavelets
and scaling functions as the basis for signal decomposition, it
chooses an appropriate wavelet function which is essential for an
accurate resolution of the signal due to multi-resolution property,
and it helps both spectral and temporal information in the sig-
nal like FFT. In this proposed method of DWT techniques such as
Mallat’s algorithm or lifting facilitates low power design. The pro-
posed system distinguishes and segregates the five acoustic sig-
nals efficiently [16]. The Mallat’s algorithm, is used to implement
the wavelet transform, in lower order filters in combination with
sub sampling operation to resolve the signal into very narrow
 P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961 7

Fig. 13. Filter design analysis method of Y3 Filter – 60 KHz.

Fig. 14. Filter design analysis method of Y4 Filter – 50 KHz.

frequency bands [5]. These are the advantages in implementing the
hardware. However, the wavelet resolved signal is required to be
processed further in order to remove the sporadic spikes and noise,
which might trigger a false detection. The acoustic signals in the
form of wavelet coefficients have certain patterns corresponding to
the symptom to be detected [6]. We know that it is possible to
represent a signal in terms of various types of absolute and statis-
tical parameters, such as average, variance, and so on.
Fig. 8 shows the architecture of Discrete Wavelet Transform, this
architecture is designed using 6 filter structure including low pass
filter and high pass filter, this decision is taken from coefficient de-
composition method using FIR filter design. In this proposed work
of DWT, architecture is integrated using FIR filter through Trun-
cation multiplier and XOR-MUX adder with minimum area, criti-
cal path, delay and power. The wavelet decomposition coefficients
range are shown in Table 3.
These Wavelet Decomposition coefficients are generated from
MATLAB with the help of Filter Design Analysis (FDA) tool, here
the initial two low pass and high pass filter produce X1, X2 out-
puts, these outputs are processed by another four filters Y1, Y2, Y3,
Y4,respectively. Figs. 8–13 shows the filter design analysis of DWT
Coefficients (Fig. 14).
8 P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961

Fig. 15. FPGA Implementation of DWT Architecture.

Fig. 16. UART Interface.

6. FPGA implementation of proposed DWT architecture
In this proposed work DWT is implemented in XILINX FPGA
S6LX9-2TQG144 using VHDL Language and compared in terms of
area, delay and power. Based upon that proposed methodology
XOR-MUX full adder is reduced to more logic size compared to
parallel adder of RCA-BEC full adder design in Truncation Multi-
plier, FIR Filter, and DWT Architecture. Fig. 15 describes the ar-
chitecture of the entire design of Hardware implementation in
FPGA.
Here, the input is given through UART Interface with regard to
switching the input frequency from Digital Control Oscillator with
the support of Dock light UART Interface Tool. Baud Rate 9600,
Data Bits 8, Parity 0, Stop Bits 1 are used to Send as well as Receive
Communications with designed interface code in MAX3232/SO and
communicated with RS232 DB-9 Connector. Fig. 16 shows the
Communication output of UART Interfaces.
Here, the Digital Control Oscillator generates a sine wave signal
at different KHz range, these outputs are given as inputs of Discrete
Wavelet Transform to obtain the output of DATA_HH, DATA_HL,
DATA_LH, DATA_LL, DATA_LOW, DATA_HIGH, these DWT outputs
are given to Switch Control, to configure the DAC Interface with the
help of Controller. Here, MCP4921 12-Bit DAC interface are config-
ured using SPI Interface. In this case the DAC interface output is
checked in Oscilloscope with FPGA Setup. Fig. 17 shows the Hard-
ware Implementation of DWT Interface.
 P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961 9

Table 4
Comparisons of single bit full adder design.

Single bit full adder design

XOR MUX RCA-BEC

Slice registers 0 0
LUT 1 2
Occupied slice 1 1
IOB 5 5
Delay(ns) 6.110 8.025
Power(mW) 14 14

Table 5
Comparisons of truncation multiplier.

Truncation multiplier

XOR MUX RCA-BEC

Slice registers 0 0
LUT 66 109
Occupied slice 26 44
IOB 24 24
Delay(ns) 24.248 39.289
Fig. 17. Hardware Implementation of DAC Interface. Power(mW) 14 14

7. Results and comparisons of adders, multipliers, FIR and DWT

The proposed design of, DWT, FIR Filter, Truncation multiplier,
Adder are synthesized in XILINX FPGA and Simulated in Model-
sim Software. Here the comparisons are made for XOR MUX adder
with parallel adders of RCA-BEC full adder. Fig. 18 shows the RTL
Schematic of XOR-MUX Full adder design, and Fig. 19 shows the
RTL Schematic of RCA-BEC Full adder design. These two single bit
adders are compared in terms of area, power and delay to find the
efficiency and Table 4 shows all the parameters.
Following the adder operation, as a second part Truncation
Multiplier is processed which is one of the major element in the
proposed DWT architecture, this truncation multiplier is designed
using these two adders XOR-MUX based adder and RCA-BEC adder,
the parameters of these multipliers are also compared and hence-
forth proved to be efficient. Fig. 20 shows the RTL Schematic of
Truncation Multiplier design and Table 5 shows the Comparison of
Truncation Multiplier.
Following the design of Adder and Truncation Multiplier, subse-
quent build up of FIR Filter design with these two types of trun-
cation multipliers are done, and finally these parameters are com-
pared to ascertain the efficiency. Fig. 21 shows the RTL Schematic
of FIR Filter design and Table 6 shows the parameter comparisons
of FIR Filter design.
To conclude, a proposed DWT architecture is designed using
XOR MUX based Truncation Multiplier and FIR Filter, this proposed
work is compared with parallel adders method of RCA-BEC based
DWT architecture. The complete architecture is synthesized in Xil-
inx FPGA and Simulated in ModelSim Software’s. Synthesized re-
port of DWT architecture is shown in Fig. 22, and RTL Schematic
is shown in Fig. 23, and Simulation report of proposed DWT archi-

Fig. 18. RTL Schematic of XOR-MUX Full Adder.

10 P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961

Fig. 19. RTL Schematic of XOR-MUX Full Adder.

Fig. 20. RTL Schematic of Truncation Multiplier.

Table 6
Comparison of FIR filter design.

FIR filter

XOR MUX RCA-BEC

Slice registers 147 154

LUT 180 283
Occupied slice 66 91
IOB 18 18
Delay(ns) 5.260 21.079
Power(mW) 14 14
P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961 11

Fig. 21. RTL Schematic of FIR Filter Design.

Fig. 22. Synthesize report of DWT architecture.

12 P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961

Fig. 23. RTL Schematic of Proposed DWT Architecture.

Fig. 24. Simulation output of DWT.

 P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961 13

Table 7 come of this proposed DWT architecture is certain to support

Comparison table of DWT architecture.
all digital processing applications of audio processing, video pro-
DWT cessing with enhanced performance of minimum area, delay and
XOR MUX RCA-BEC
power.

Slice registers 696 1001 References

LUT 1014 1769
Occupied slice 325 592
IOB 58 58
Delay(ns) 8.981 28.453
Power(mW) 14 14
Fig. 25. Comparison chart of XOR MUX DWT and RCA-BEC DWT.
tecture is shown in Fig. 24. Finally comparison of all the terms of
Slice registers, LUT, Occupied Slice, IOB’s, Delay, Power is shown in
Tabel 7, and comparison chart of the proposed DWT architecture
with XOR-MUX DWT and RCA-BEC DWT is shown in Fig. 25. Based
on this comparison, the proposed XOR-MUX Full adder based DWT
architecture is better in all the ways in Digital Signal Processing
applications.
8. Conclusions
A novel approach of this paper is presented to reduce the area,
occupied slice and delay of DWT architecture using XOR MUX
FIR Filter, XOR MUX Truncation Multiplier, XOR-MUX adders. This
method reduces the number of logic gates adder design and adder
based DWT architecture of Digital Signal processing applications.
The proposed method of XOR-MUX Truncation Multiplier has re-
duced the output size 8 × 8 bits giving 8 bit outputs, and it sup-
port to reduce inner and outer architecture of DWT circuits. The
comparisons henceforth prove the efficiency in terms of Slice reg-
isters, LUT, Occupied Slice, IOB’s, Delay. In future, the outcome of
this proposed DWT architecture is certain to support all digital
processing applications of audio processing, video processing with
enhanced performance of minimum area, delay and power.
Declaration of Competing Interest
[1] P. Balasubramanian, Nikos E.,High Speed Gate Level Synchronous Full Adder
Design; Mastorakis, School of Computer Science, University of Manchester,
United Kingdom, Wseas Transactions on Circuits and systes.
[2] S.R. Rijal (Asst. Prof. KITS Ramtek), M. Sharda, G. Mungale, Design and imple-
mentation of 8 ´8 truncated multiplier of FPGA, Int. J. Sci. Res. Publ. 3 (March
(3)) (2013).
[3] U. Penchalaiah, V.G. Siva Kumar, Survey: performance analysis of FIR filter de-
sign using modified truncation multiplier with SQRT based carry select adder,
Int. J. Eng. Technol. SPC 7 (2.32) (2018) 23–34.
[4] S. Saraswat, G. Srivastava, S. Shukla, Decomposition of ECG signals using dis-
crete wavelet transform for wolff Parkinson white syndrome patients, Interna-
tional Conference on Micro Electrions and Telecommunicaiton, 2016.
[5] E.L.M. El Hassan, M. Karim, An FPGA Based Implementation of a Pre-Process-
ing Stages for ECG Signal Analysis Using DWT, University Sidi Mohammed Ben
Abdellah, Fez, Morocco, 2014 IEEE.
[6] S. Saxena, R. Jais, M. Kumar Hota, Removal of power line interference from ECG
signal using FIR, IIR, DWT and NLMS adaptive filter, Internation Conference on
Communication and Signal Processing, April 4–6, 2019.
[7] P. Singh, G. Pradhan, Significance of non-local means estimation in DWT based
ECG signal denoising.
[8] B. Kumar Mohanty Senior Member, IEEE, P. Kumar Meher Senior Member, A
High-Performance FIR Filter Architecture for Fixed and Reconfigurable Appli-
cations, IEEE, 2015 1063-8210 ©.
[9] P. Balasubramanian and N.E. Mastorakis, High Speed Gate Level Synchronous
Full Adder Designs, WSEAS Transactions on Circuits and Systems, Oxford Road,
Manchester M13 9PL, UNITED KINGDOM.
[10] V. Kamalakannan, V. Shilpakala, H.N. Ravi, Design of adder / subtractor circuits
based on reversible gates, Int. J. Adv. Res. Electr. Electron. Instrum. Eng. 2 (Au-
gust (8)) (2013).
[11] Power and area efficient carry select adder, 2015 IEEE Recent Advances in In-
telligent Computational Systems (RAICS) | 10–12 December 2015 | Trivandrum.
[12] I.-C. Wey, C.-C. Ho, Y.-S. Lin, and C.-C. Peng, An area-efficient carry select adder
design by sharing the common boolean logic term, Proceedings of the Interna-
tional Multi Conference of Engineers and Computer Science 2012, Vol II.
[13] H. Thapliyal, A.P. Vinod, Designing Efficient Online Testable Reversible Adders
With New Reversible Gate, School of Computer Engineering, Nanyang Techno-
logical University, Singapore, 2007 IEEE.
[14] A. Prasad, R. Abraham, Variable truncated multiplier with low power, Int. J.
Eng. Comput. Sci. ISSN:2319-7242.
[15] T. Drane, T. Rose, G.A. Constantinides, On The Systematic Creation of Faithfully
Rounded Truncated Multipliers and Arrays, IEEE Transactions on Computers,
2013.
[16] P. Garg, S. Saini, A novel design of compact reversible SG gate and its appli-
cations, 2014 International Symposium on Communications and Information
Technologies (ISCIT).
[17] S.H. Markandeya, K. Roy, Low-Power system for detection of symptomatic pat-
terns in audio biological system, IEEE Trans. Very large Scale Integr. (VLSI) Syst.
24 (August (8)) (2016) 1063–8210.
[18] C. Souani, M. Abid, K. Torki, R. Tourki, VLSI design of 1-D DWT architecture
with parallel filters, Integr. VLSI J. 29 (2) (20 0 0) 181–207.
[19] S.R. Rijal (Asst. Prof. KITS, Ramtek), M. Sharda, G. Mungale (Asst. Prof. PCEA,
Nagpur), Design and implementation of 8 × 8 truncated multiplier of FPGA,
Int. J. Sci. Res. Publ. 3 (March (3)) (2013).
[20] H.-J. Ko, S.-F. Hsiao, Design and application of faithfully rounded and truncated
multipliers with combined deletion, reduction, truncation and rounding, IEEE
Trans. Circt. Syst. 58 (May (5)) (2011) II.Express Briefs.
[21] B Ramkumar, H.M. Kittur, Low power and area efficient carry select adder,
IEEE Transaction on Very Large Scale Integration (VLSI) Systems, May 2011.
[22] U.P. Anagha, P. Pramod, P.G. Scholar, LBS College of Engineering, India, Power
and area efficient carry select adder, 2015, IEEE Recent Advances in Intelligent
Computational Systems, 10-12 December, 2015.
[23] S.K. Soniya, A review of different type of multiplier and multipliers-accumula-
tor unit, Int. J. Emerg. Trends Technol. Comput. Sci. 2 (July–August (4)) (2013).

The comparisons henceforth prove the efficiency in terms of

Slice registers, LUT, Occupied Slice, IOB’s, Delay. In future, the out-
14 P. Radhakrishnan and G. Themozhi / Microprocessors and Microsystems 73 (2020) 102961
P.Radhakrishnan received his B.E degree from Univer-
sity of Madras, Chennai, India in 20 0 0. He received
M.E Degree in Faculty of Information and Communica-
tion Engineering, Anna University, Chennai, India in 2006.
Presently is pursuing Ph.D in Anna University, Chennai.
He is currently working as an Associate professor in
Tagore Engineering College holding an experience of 18
years in teaching. He is a life member of IETE. He has
published seven papers in reputed journals. His research
area is Signal processing, VLSI and Image processing.
G.Themozhi received her M.E degree from University of
Madras, Chennai, India in 2001. She received Ph.D De-
gree in Faculty of Electrical Engineering, Anna University,
Chennai, India in 2013. Presently she is working as Pro-
fessor in the Department of Electrical and Electronics En-
gineering, AMET University, Chennai. She has 26 years of
teaching experience. She is life member of IETE, IE(India)
and ISTE. She has published 20 research papers in reputed
journals. Her research areas are VLSI, Signal Processing
and Power Electronic Converters.